 (at the computer)
 (at the computer)
50 PIN MALE EDGE the computer.
| Pin | Name | Dir | Description | 
|---|---|---|---|
| 1 | +5v |  | Power, 300mA | 
| 2 | /CNTRL2 |  | Game adapter control signal | 
| 3 | +12v |  | Power, 100mA | 
| 4 | -12v |  | Power, 50mA | 
| 5 | /CNTRL1 |  | Game adapter control signal | 
| 6 | /WAIT |  | Z80 WAIT | 
| 7 | /RST |  | Z80 RST | 
| 8 | CPU CLK |  | Buffered 3.58MHz system clock | 
| 9 | A15 |  | Buffered Address bus | 
| 10 | A14 |  | " | 
| 11 | A13 |  | " | 
| 12 | A12 |  | " | 
| 13 | A11 |  | " | 
| 14 | A10 |  | " | 
| 15 | A9 |  | " | 
| 16 | A8 |  | " | 
| 17 | A7 |  | " | 
| 18 | A6 |  | " | 
| 19 | A5 |  | " | 
| 20 | A4 |  | " | 
| 21 | A3 |  | " | 
| 22 | A2 |  | " | 
| 23 | A1 |  | " | 
| 24 | A0 |  | " | 
| 25 | /RFSH |  | RAM expansion refresh | 
| 26 | /EXCSR |  | Video-CPU write select | 
| 27 | /M1 |  | Z80 M1 | 
| 28 | /EXCSW |  | CPU-Video write select | 
| 29 | /WR |  | Z80 WR | 
| 30 | /MREQ |  | Z80 MREQ | 
| 31 | /IORQ |  | Z80 IORQ | 
| 32 | /RD |  | Z80 RD | 
| 33 | D0 | I/O | Buffered Data Bus | 
| 34 | D1 | I/O | " | 
| 35 | D2 | I/O | " | 
| 36 | D3 | I/O | " | 
| 37 | D4 | I/O | " | 
| 38 | D5 | I/O | " | 
| 39 | D6 | I/O | " | 
| 40 | D7 | I/O | " | 
| 41 | CSOUND |  | Audio input signal | 
| 42 | /INT |  | Z80 INT | 
| 43 | /RAMDIS |  | Disable user RAM | 
| 44 | /ROMDIS |  | Disable basic ROM | 
| 45 | /BK32 |  | Enable bank 32 Memory (8000-ffff) | 
| 46 | /BK31 |  | Enable bank 31 Memory (0000-7FFF) | 
| 47 | /BK22 |  | Enable bank 22 Memory (8000-FFFF) | 
| 48 | /BK21 |  | Enable bank 21 Memory (0000-7FFF) | 
| 49 | GND | - | System Ground | 
| 50 | GND | - | System Ground | 
| Contributor: | Rob Gill | 
| Source: | SVI 328 Mk II User Manual | 
  Copyright © The Hardware Book Team 1996-2004.
  May be copied and redistributed, partially or in whole, as appropriate.
  Document last modified: 2002-01-10