core/stdarch/crates/core_arch/src/arm_shared/neon/
generated.rs

1// This code is automatically generated. DO NOT MODIFY.
2//
3// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
4//
5// ```
6// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
7// ```
8#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32 single round checksum for bytes (8 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20#[cfg_attr(test, assert_instr(crc32b))]
21#[cfg_attr(
22    target_arch = "arm",
23    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
24)]
25#[cfg_attr(
26    not(target_arch = "arm"),
27    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
28)]
29pub fn __crc32b(crc: u32, data: u8) -> u32 {
30    unsafe extern "unadjusted" {
31        #[cfg_attr(
32            any(target_arch = "aarch64", target_arch = "arm64ec"),
33            link_name = "llvm.aarch64.crc32b"
34        )]
35        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
36        fn ___crc32b(crc: u32, data: u32) -> u32;
37    }
38    unsafe { ___crc32b(crc, data as u32) }
39}
40#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
41#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
42#[inline]
43#[target_feature(enable = "crc")]
44#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
45#[cfg_attr(test, assert_instr(crc32cb))]
46#[cfg_attr(
47    target_arch = "arm",
48    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
49)]
50#[cfg_attr(
51    not(target_arch = "arm"),
52    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
53)]
54pub fn __crc32cb(crc: u32, data: u8) -> u32 {
55    unsafe extern "unadjusted" {
56        #[cfg_attr(
57            any(target_arch = "aarch64", target_arch = "arm64ec"),
58            link_name = "llvm.aarch64.crc32cb"
59        )]
60        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
61        fn ___crc32cb(crc: u32, data: u32) -> u32;
62    }
63    unsafe { ___crc32cb(crc, data as u32) }
64}
65#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
66#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
67#[inline]
68#[target_feature(enable = "crc")]
69#[cfg(target_arch = "arm")]
70#[cfg_attr(test, assert_instr(crc32cw))]
71#[cfg_attr(
72    target_arch = "arm",
73    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
74)]
75pub fn __crc32cd(crc: u32, data: u64) -> u32 {
76    let b: u32 = (data & 0xFFFFFFFF) as u32;
77    let c: u32 = (data >> 32) as u32;
78    unsafe extern "unadjusted" {
79        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
80        fn ___crc32cw(crc: u32, data: u32) -> u32;
81    }
82    unsafe { ___crc32cw(___crc32cw(crc, b), c) }
83}
84#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
85#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
86#[inline]
87#[target_feature(enable = "crc")]
88#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
89#[cfg_attr(test, assert_instr(crc32ch))]
90#[cfg_attr(
91    target_arch = "arm",
92    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
93)]
94#[cfg_attr(
95    not(target_arch = "arm"),
96    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
97)]
98pub fn __crc32ch(crc: u32, data: u16) -> u32 {
99    unsafe extern "unadjusted" {
100        #[cfg_attr(
101            any(target_arch = "aarch64", target_arch = "arm64ec"),
102            link_name = "llvm.aarch64.crc32ch"
103        )]
104        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
105        fn ___crc32ch(crc: u32, data: u32) -> u32;
106    }
107    unsafe { ___crc32ch(crc, data as u32) }
108}
109#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
111#[inline]
112#[target_feature(enable = "crc")]
113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
114#[cfg_attr(test, assert_instr(crc32cw))]
115#[cfg_attr(
116    target_arch = "arm",
117    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
118)]
119#[cfg_attr(
120    not(target_arch = "arm"),
121    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
122)]
123pub fn __crc32cw(crc: u32, data: u32) -> u32 {
124    unsafe extern "unadjusted" {
125        #[cfg_attr(
126            any(target_arch = "aarch64", target_arch = "arm64ec"),
127            link_name = "llvm.aarch64.crc32cw"
128        )]
129        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
130        fn ___crc32cw(crc: u32, data: u32) -> u32;
131    }
132    unsafe { ___crc32cw(crc, data) }
133}
134#[doc = "CRC32 single round checksum for quad words (64 bits)."]
135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
136#[inline]
137#[target_feature(enable = "crc")]
138#[cfg(target_arch = "arm")]
139#[cfg_attr(test, assert_instr(crc32w))]
140#[cfg_attr(
141    target_arch = "arm",
142    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
143)]
144pub fn __crc32d(crc: u32, data: u64) -> u32 {
145    let b: u32 = (data & 0xFFFFFFFF) as u32;
146    let c: u32 = (data >> 32) as u32;
147    unsafe extern "unadjusted" {
148        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
149        fn ___crc32w(crc: u32, data: u32) -> u32;
150    }
151    unsafe { ___crc32w(___crc32w(crc, b), c) }
152}
153#[doc = "CRC32 single round checksum for bytes (16 bits)."]
154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
155#[inline]
156#[target_feature(enable = "crc")]
157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
158#[cfg_attr(test, assert_instr(crc32h))]
159#[cfg_attr(
160    target_arch = "arm",
161    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
162)]
163#[cfg_attr(
164    not(target_arch = "arm"),
165    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
166)]
167pub fn __crc32h(crc: u32, data: u16) -> u32 {
168    unsafe extern "unadjusted" {
169        #[cfg_attr(
170            any(target_arch = "aarch64", target_arch = "arm64ec"),
171            link_name = "llvm.aarch64.crc32h"
172        )]
173        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
174        fn ___crc32h(crc: u32, data: u32) -> u32;
175    }
176    unsafe { ___crc32h(crc, data as u32) }
177}
178#[doc = "CRC32 single round checksum for bytes (32 bits)."]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
180#[inline]
181#[target_feature(enable = "crc")]
182#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183#[cfg_attr(test, assert_instr(crc32w))]
184#[cfg_attr(
185    target_arch = "arm",
186    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
187)]
188#[cfg_attr(
189    not(target_arch = "arm"),
190    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
191)]
192pub fn __crc32w(crc: u32, data: u32) -> u32 {
193    unsafe extern "unadjusted" {
194        #[cfg_attr(
195            any(target_arch = "aarch64", target_arch = "arm64ec"),
196            link_name = "llvm.aarch64.crc32w"
197        )]
198        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
199        fn ___crc32w(crc: u32, data: u32) -> u32;
200    }
201    unsafe { ___crc32w(crc, data) }
202}
203#[doc = "Signed Add and Accumulate Long Pairwise."]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
209#[cfg_attr(
210    target_arch = "arm",
211    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
212)]
213fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
214    unsafe extern "unadjusted" {
215        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
216        fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
217    }
218    unsafe { _priv_vpadal_s8(a, b) }
219}
220#[doc = "Signed Add and Accumulate Long Pairwise."]
221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
222#[inline]
223#[target_feature(enable = "neon")]
224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
226#[cfg_attr(
227    target_arch = "arm",
228    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
229)]
230fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
231    unsafe extern "unadjusted" {
232        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
233        fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
234    }
235    unsafe { _priv_vpadalq_s8(a, b) }
236}
237#[doc = "Signed Add and Accumulate Long Pairwise."]
238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
239#[inline]
240#[target_feature(enable = "neon")]
241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
243#[cfg_attr(
244    target_arch = "arm",
245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
246)]
247fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
248    unsafe extern "unadjusted" {
249        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
250        fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
251    }
252    unsafe { _priv_vpadal_s16(a, b) }
253}
254#[doc = "Signed Add and Accumulate Long Pairwise."]
255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
256#[inline]
257#[target_feature(enable = "neon")]
258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
260#[cfg_attr(
261    target_arch = "arm",
262    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
263)]
264fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
265    unsafe extern "unadjusted" {
266        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
267        fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
268    }
269    unsafe { _priv_vpadalq_s16(a, b) }
270}
271#[doc = "Signed Add and Accumulate Long Pairwise."]
272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
273#[inline]
274#[target_feature(enable = "neon")]
275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
277#[cfg_attr(
278    target_arch = "arm",
279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
280)]
281fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
282    unsafe extern "unadjusted" {
283        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
284        fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
285    }
286    unsafe { _priv_vpadal_s32(a, b) }
287}
288#[doc = "Signed Add and Accumulate Long Pairwise."]
289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
290#[inline]
291#[target_feature(enable = "neon")]
292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
294#[cfg_attr(
295    target_arch = "arm",
296    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
297)]
298fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
299    unsafe extern "unadjusted" {
300        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
301        fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
302    }
303    unsafe { _priv_vpadalq_s32(a, b) }
304}
305#[doc = "Signed Add and Accumulate Long Pairwise."]
306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
307#[inline]
308#[target_feature(enable = "neon")]
309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
311#[cfg_attr(
312    target_arch = "arm",
313    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
314)]
315fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
316    unsafe extern "unadjusted" {
317        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
318        fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
319    }
320    unsafe { _priv_vpadal_u8(a, b) }
321}
322#[doc = "Signed Add and Accumulate Long Pairwise."]
323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
324#[inline]
325#[target_feature(enable = "neon")]
326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
328#[cfg_attr(
329    target_arch = "arm",
330    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
331)]
332fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
333    unsafe extern "unadjusted" {
334        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
335        fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
336    }
337    unsafe { _priv_vpadalq_u8(a, b) }
338}
339#[doc = "Signed Add and Accumulate Long Pairwise."]
340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
341#[inline]
342#[target_feature(enable = "neon")]
343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
345#[cfg_attr(
346    target_arch = "arm",
347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
348)]
349fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
350    unsafe extern "unadjusted" {
351        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
352        fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
353    }
354    unsafe { _priv_vpadal_u16(a, b) }
355}
356#[doc = "Signed Add and Accumulate Long Pairwise."]
357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
358#[inline]
359#[target_feature(enable = "neon")]
360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
362#[cfg_attr(
363    target_arch = "arm",
364    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
365)]
366fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
367    unsafe extern "unadjusted" {
368        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
369        fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
370    }
371    unsafe { _priv_vpadalq_u16(a, b) }
372}
373#[doc = "Signed Add and Accumulate Long Pairwise."]
374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
375#[inline]
376#[target_feature(enable = "neon")]
377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
379#[cfg_attr(
380    target_arch = "arm",
381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
382)]
383fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
384    unsafe extern "unadjusted" {
385        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
386        fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
387    }
388    unsafe { _priv_vpadal_u32(a, b) }
389}
390#[doc = "Signed Add and Accumulate Long Pairwise."]
391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
392#[inline]
393#[target_feature(enable = "neon")]
394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
395#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
396#[cfg_attr(
397    target_arch = "arm",
398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
399)]
400fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
401    unsafe extern "unadjusted" {
402        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
403        fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
404    }
405    unsafe { _priv_vpadalq_u32(a, b) }
406}
407#[doc = "Absolute difference and accumulate (64-bit)"]
408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
409#[inline]
410#[target_feature(enable = "neon")]
411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
412#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
413#[cfg_attr(
414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
415    assert_instr(saba)
416)]
417#[cfg_attr(
418    not(target_arch = "arm"),
419    stable(feature = "neon_intrinsics", since = "1.59.0")
420)]
421#[cfg_attr(
422    target_arch = "arm",
423    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
424)]
425pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
426    unsafe { simd_add(a, vabd_s16(b, c)) }
427}
428#[doc = "Absolute difference and accumulate (64-bit)"]
429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
430#[inline]
431#[target_feature(enable = "neon")]
432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
433#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
434#[cfg_attr(
435    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
436    assert_instr(saba)
437)]
438#[cfg_attr(
439    not(target_arch = "arm"),
440    stable(feature = "neon_intrinsics", since = "1.59.0")
441)]
442#[cfg_attr(
443    target_arch = "arm",
444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
445)]
446pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
447    unsafe { simd_add(a, vabd_s32(b, c)) }
448}
449#[doc = "Absolute difference and accumulate (64-bit)"]
450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
451#[inline]
452#[target_feature(enable = "neon")]
453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
455#[cfg_attr(
456    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
457    assert_instr(saba)
458)]
459#[cfg_attr(
460    not(target_arch = "arm"),
461    stable(feature = "neon_intrinsics", since = "1.59.0")
462)]
463#[cfg_attr(
464    target_arch = "arm",
465    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
466)]
467pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
468    unsafe { simd_add(a, vabd_s8(b, c)) }
469}
470#[doc = "Absolute difference and accumulate (64-bit)"]
471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
472#[inline]
473#[target_feature(enable = "neon")]
474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
475#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
476#[cfg_attr(
477    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
478    assert_instr(uaba)
479)]
480#[cfg_attr(
481    not(target_arch = "arm"),
482    stable(feature = "neon_intrinsics", since = "1.59.0")
483)]
484#[cfg_attr(
485    target_arch = "arm",
486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
487)]
488pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
489    unsafe { simd_add(a, vabd_u16(b, c)) }
490}
491#[doc = "Absolute difference and accumulate (64-bit)"]
492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
493#[inline]
494#[target_feature(enable = "neon")]
495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
496#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
497#[cfg_attr(
498    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
499    assert_instr(uaba)
500)]
501#[cfg_attr(
502    not(target_arch = "arm"),
503    stable(feature = "neon_intrinsics", since = "1.59.0")
504)]
505#[cfg_attr(
506    target_arch = "arm",
507    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
508)]
509pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
510    unsafe { simd_add(a, vabd_u32(b, c)) }
511}
512#[doc = "Absolute difference and accumulate (64-bit)"]
513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
514#[inline]
515#[target_feature(enable = "neon")]
516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
518#[cfg_attr(
519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
520    assert_instr(uaba)
521)]
522#[cfg_attr(
523    not(target_arch = "arm"),
524    stable(feature = "neon_intrinsics", since = "1.59.0")
525)]
526#[cfg_attr(
527    target_arch = "arm",
528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
529)]
530pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
531    unsafe { simd_add(a, vabd_u8(b, c)) }
532}
533#[doc = "Signed Absolute difference and Accumulate Long"]
534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
535#[inline]
536#[target_feature(enable = "neon")]
537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
539#[cfg_attr(
540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
541    assert_instr(sabal)
542)]
543#[cfg_attr(
544    not(target_arch = "arm"),
545    stable(feature = "neon_intrinsics", since = "1.59.0")
546)]
547#[cfg_attr(
548    target_arch = "arm",
549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
550)]
551pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
552    let d: int8x8_t = vabd_s8(b, c);
553    unsafe {
554        let e: uint8x8_t = simd_cast(d);
555        simd_add(a, simd_cast(e))
556    }
557}
558#[doc = "Signed Absolute difference and Accumulate Long"]
559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
560#[inline]
561#[target_feature(enable = "neon")]
562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
564#[cfg_attr(
565    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
566    assert_instr(sabal)
567)]
568#[cfg_attr(
569    not(target_arch = "arm"),
570    stable(feature = "neon_intrinsics", since = "1.59.0")
571)]
572#[cfg_attr(
573    target_arch = "arm",
574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
575)]
576pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
577    let d: int16x4_t = vabd_s16(b, c);
578    unsafe {
579        let e: uint16x4_t = simd_cast(d);
580        simd_add(a, simd_cast(e))
581    }
582}
583#[doc = "Signed Absolute difference and Accumulate Long"]
584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
585#[inline]
586#[target_feature(enable = "neon")]
587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
588#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
589#[cfg_attr(
590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
591    assert_instr(sabal)
592)]
593#[cfg_attr(
594    not(target_arch = "arm"),
595    stable(feature = "neon_intrinsics", since = "1.59.0")
596)]
597#[cfg_attr(
598    target_arch = "arm",
599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
600)]
601pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
602    let d: int32x2_t = vabd_s32(b, c);
603    unsafe {
604        let e: uint32x2_t = simd_cast(d);
605        simd_add(a, simd_cast(e))
606    }
607}
608#[doc = "Unsigned Absolute difference and Accumulate Long"]
609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
610#[inline]
611#[target_feature(enable = "neon")]
612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
614#[cfg_attr(
615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
616    assert_instr(uabal)
617)]
618#[cfg_attr(
619    not(target_arch = "arm"),
620    stable(feature = "neon_intrinsics", since = "1.59.0")
621)]
622#[cfg_attr(
623    target_arch = "arm",
624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
625)]
626pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
627    let d: uint8x8_t = vabd_u8(b, c);
628    unsafe { simd_add(a, simd_cast(d)) }
629}
630#[doc = "Unsigned Absolute difference and Accumulate Long"]
631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
632#[inline]
633#[target_feature(enable = "neon")]
634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
636#[cfg_attr(
637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
638    assert_instr(uabal)
639)]
640#[cfg_attr(
641    not(target_arch = "arm"),
642    stable(feature = "neon_intrinsics", since = "1.59.0")
643)]
644#[cfg_attr(
645    target_arch = "arm",
646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
647)]
648pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
649    let d: uint16x4_t = vabd_u16(b, c);
650    unsafe { simd_add(a, simd_cast(d)) }
651}
652#[doc = "Unsigned Absolute difference and Accumulate Long"]
653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
654#[inline]
655#[target_feature(enable = "neon")]
656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
658#[cfg_attr(
659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
660    assert_instr(uabal)
661)]
662#[cfg_attr(
663    not(target_arch = "arm"),
664    stable(feature = "neon_intrinsics", since = "1.59.0")
665)]
666#[cfg_attr(
667    target_arch = "arm",
668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
669)]
670pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
671    let d: uint32x2_t = vabd_u32(b, c);
672    unsafe { simd_add(a, simd_cast(d)) }
673}
674#[doc = "Absolute difference and accumulate (128-bit)"]
675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
676#[inline]
677#[target_feature(enable = "neon")]
678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
679#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
680#[cfg_attr(
681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
682    assert_instr(saba)
683)]
684#[cfg_attr(
685    not(target_arch = "arm"),
686    stable(feature = "neon_intrinsics", since = "1.59.0")
687)]
688#[cfg_attr(
689    target_arch = "arm",
690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
691)]
692pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
693    unsafe { simd_add(a, vabdq_s16(b, c)) }
694}
695#[doc = "Absolute difference and accumulate (128-bit)"]
696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
697#[inline]
698#[target_feature(enable = "neon")]
699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
701#[cfg_attr(
702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
703    assert_instr(saba)
704)]
705#[cfg_attr(
706    not(target_arch = "arm"),
707    stable(feature = "neon_intrinsics", since = "1.59.0")
708)]
709#[cfg_attr(
710    target_arch = "arm",
711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
712)]
713pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
714    unsafe { simd_add(a, vabdq_s32(b, c)) }
715}
716#[doc = "Absolute difference and accumulate (128-bit)"]
717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
718#[inline]
719#[target_feature(enable = "neon")]
720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
722#[cfg_attr(
723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
724    assert_instr(saba)
725)]
726#[cfg_attr(
727    not(target_arch = "arm"),
728    stable(feature = "neon_intrinsics", since = "1.59.0")
729)]
730#[cfg_attr(
731    target_arch = "arm",
732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
733)]
734pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
735    unsafe { simd_add(a, vabdq_s8(b, c)) }
736}
737#[doc = "Absolute difference and accumulate (128-bit)"]
738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
739#[inline]
740#[target_feature(enable = "neon")]
741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
743#[cfg_attr(
744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
745    assert_instr(uaba)
746)]
747#[cfg_attr(
748    not(target_arch = "arm"),
749    stable(feature = "neon_intrinsics", since = "1.59.0")
750)]
751#[cfg_attr(
752    target_arch = "arm",
753    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
754)]
755pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
756    unsafe { simd_add(a, vabdq_u16(b, c)) }
757}
758#[doc = "Absolute difference and accumulate (128-bit)"]
759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
760#[inline]
761#[target_feature(enable = "neon")]
762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
763#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
764#[cfg_attr(
765    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
766    assert_instr(uaba)
767)]
768#[cfg_attr(
769    not(target_arch = "arm"),
770    stable(feature = "neon_intrinsics", since = "1.59.0")
771)]
772#[cfg_attr(
773    target_arch = "arm",
774    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
775)]
776pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
777    unsafe { simd_add(a, vabdq_u32(b, c)) }
778}
779#[doc = "Absolute difference and accumulate (128-bit)"]
780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
781#[inline]
782#[target_feature(enable = "neon")]
783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
785#[cfg_attr(
786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
787    assert_instr(uaba)
788)]
789#[cfg_attr(
790    not(target_arch = "arm"),
791    stable(feature = "neon_intrinsics", since = "1.59.0")
792)]
793#[cfg_attr(
794    target_arch = "arm",
795    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
796)]
797pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
798    unsafe { simd_add(a, vabdq_u8(b, c)) }
799}
800#[doc = "Absolute difference between the arguments of Floating"]
801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
802#[inline]
803#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
805#[cfg_attr(
806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
807    assert_instr(fabd)
808)]
809#[target_feature(enable = "neon,fp16")]
810#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
811pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
812    unsafe extern "unadjusted" {
813        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")]
814        #[cfg_attr(
815            any(target_arch = "aarch64", target_arch = "arm64ec"),
816            link_name = "llvm.aarch64.neon.fabd.v4f16"
817        )]
818        fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
819    }
820    unsafe { _vabd_f16(a, b) }
821}
822#[doc = "Absolute difference between the arguments of Floating"]
823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
824#[inline]
825#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
827#[cfg_attr(
828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
829    assert_instr(fabd)
830)]
831#[target_feature(enable = "neon,fp16")]
832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
833pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
834    unsafe extern "unadjusted" {
835        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")]
836        #[cfg_attr(
837            any(target_arch = "aarch64", target_arch = "arm64ec"),
838            link_name = "llvm.aarch64.neon.fabd.v8f16"
839        )]
840        fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
841    }
842    unsafe { _vabdq_f16(a, b) }
843}
844#[doc = "Absolute difference between the arguments of Floating"]
845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
846#[inline]
847#[target_feature(enable = "neon")]
848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
849#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
850#[cfg_attr(
851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
852    assert_instr(fabd)
853)]
854#[cfg_attr(
855    not(target_arch = "arm"),
856    stable(feature = "neon_intrinsics", since = "1.59.0")
857)]
858#[cfg_attr(
859    target_arch = "arm",
860    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
861)]
862pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
863    unsafe extern "unadjusted" {
864        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")]
865        #[cfg_attr(
866            any(target_arch = "aarch64", target_arch = "arm64ec"),
867            link_name = "llvm.aarch64.neon.fabd.v2f32"
868        )]
869        fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
870    }
871    unsafe { _vabd_f32(a, b) }
872}
873#[doc = "Absolute difference between the arguments of Floating"]
874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
875#[inline]
876#[target_feature(enable = "neon")]
877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
878#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
879#[cfg_attr(
880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
881    assert_instr(fabd)
882)]
883#[cfg_attr(
884    not(target_arch = "arm"),
885    stable(feature = "neon_intrinsics", since = "1.59.0")
886)]
887#[cfg_attr(
888    target_arch = "arm",
889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
890)]
891pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
892    unsafe extern "unadjusted" {
893        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")]
894        #[cfg_attr(
895            any(target_arch = "aarch64", target_arch = "arm64ec"),
896            link_name = "llvm.aarch64.neon.fabd.v4f32"
897        )]
898        fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
899    }
900    unsafe { _vabdq_f32(a, b) }
901}
902#[doc = "Absolute difference between the arguments"]
903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
904#[inline]
905#[target_feature(enable = "neon")]
906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
907#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
908#[cfg_attr(
909    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
910    assert_instr(sabd)
911)]
912#[cfg_attr(
913    not(target_arch = "arm"),
914    stable(feature = "neon_intrinsics", since = "1.59.0")
915)]
916#[cfg_attr(
917    target_arch = "arm",
918    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
919)]
920pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
921    unsafe extern "unadjusted" {
922        #[cfg_attr(
923            any(target_arch = "aarch64", target_arch = "arm64ec"),
924            link_name = "llvm.aarch64.neon.sabd.v8i8"
925        )]
926        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")]
927        fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
928    }
929    unsafe { _vabd_s8(a, b) }
930}
931#[doc = "Absolute difference between the arguments"]
932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
933#[inline]
934#[target_feature(enable = "neon")]
935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
937#[cfg_attr(
938    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
939    assert_instr(sabd)
940)]
941#[cfg_attr(
942    not(target_arch = "arm"),
943    stable(feature = "neon_intrinsics", since = "1.59.0")
944)]
945#[cfg_attr(
946    target_arch = "arm",
947    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
948)]
949pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
950    unsafe extern "unadjusted" {
951        #[cfg_attr(
952            any(target_arch = "aarch64", target_arch = "arm64ec"),
953            link_name = "llvm.aarch64.neon.sabd.v16i8"
954        )]
955        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")]
956        fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
957    }
958    unsafe { _vabdq_s8(a, b) }
959}
960#[doc = "Absolute difference between the arguments"]
961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
962#[inline]
963#[target_feature(enable = "neon")]
964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
966#[cfg_attr(
967    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
968    assert_instr(sabd)
969)]
970#[cfg_attr(
971    not(target_arch = "arm"),
972    stable(feature = "neon_intrinsics", since = "1.59.0")
973)]
974#[cfg_attr(
975    target_arch = "arm",
976    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
977)]
978pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
979    unsafe extern "unadjusted" {
980        #[cfg_attr(
981            any(target_arch = "aarch64", target_arch = "arm64ec"),
982            link_name = "llvm.aarch64.neon.sabd.v4i16"
983        )]
984        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")]
985        fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
986    }
987    unsafe { _vabd_s16(a, b) }
988}
989#[doc = "Absolute difference between the arguments"]
990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
991#[inline]
992#[target_feature(enable = "neon")]
993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
994#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
995#[cfg_attr(
996    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
997    assert_instr(sabd)
998)]
999#[cfg_attr(
1000    not(target_arch = "arm"),
1001    stable(feature = "neon_intrinsics", since = "1.59.0")
1002)]
1003#[cfg_attr(
1004    target_arch = "arm",
1005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1006)]
1007pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1008    unsafe extern "unadjusted" {
1009        #[cfg_attr(
1010            any(target_arch = "aarch64", target_arch = "arm64ec"),
1011            link_name = "llvm.aarch64.neon.sabd.v8i16"
1012        )]
1013        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")]
1014        fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
1015    }
1016    unsafe { _vabdq_s16(a, b) }
1017}
1018#[doc = "Absolute difference between the arguments"]
1019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
1020#[inline]
1021#[target_feature(enable = "neon")]
1022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1024#[cfg_attr(
1025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1026    assert_instr(sabd)
1027)]
1028#[cfg_attr(
1029    not(target_arch = "arm"),
1030    stable(feature = "neon_intrinsics", since = "1.59.0")
1031)]
1032#[cfg_attr(
1033    target_arch = "arm",
1034    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1035)]
1036pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1037    unsafe extern "unadjusted" {
1038        #[cfg_attr(
1039            any(target_arch = "aarch64", target_arch = "arm64ec"),
1040            link_name = "llvm.aarch64.neon.sabd.v2i32"
1041        )]
1042        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")]
1043        fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
1044    }
1045    unsafe { _vabd_s32(a, b) }
1046}
1047#[doc = "Absolute difference between the arguments"]
1048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
1049#[inline]
1050#[target_feature(enable = "neon")]
1051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1052#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1053#[cfg_attr(
1054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1055    assert_instr(sabd)
1056)]
1057#[cfg_attr(
1058    not(target_arch = "arm"),
1059    stable(feature = "neon_intrinsics", since = "1.59.0")
1060)]
1061#[cfg_attr(
1062    target_arch = "arm",
1063    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1064)]
1065pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1066    unsafe extern "unadjusted" {
1067        #[cfg_attr(
1068            any(target_arch = "aarch64", target_arch = "arm64ec"),
1069            link_name = "llvm.aarch64.neon.sabd.v4i32"
1070        )]
1071        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")]
1072        fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
1073    }
1074    unsafe { _vabdq_s32(a, b) }
1075}
1076#[doc = "Absolute difference between the arguments"]
1077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
1078#[inline]
1079#[target_feature(enable = "neon")]
1080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1082#[cfg_attr(
1083    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1084    assert_instr(uabd)
1085)]
1086#[cfg_attr(
1087    not(target_arch = "arm"),
1088    stable(feature = "neon_intrinsics", since = "1.59.0")
1089)]
1090#[cfg_attr(
1091    target_arch = "arm",
1092    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1093)]
1094pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1095    unsafe extern "unadjusted" {
1096        #[cfg_attr(
1097            any(target_arch = "aarch64", target_arch = "arm64ec"),
1098            link_name = "llvm.aarch64.neon.uabd.v8i8"
1099        )]
1100        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")]
1101        fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
1102    }
1103    unsafe { _vabd_u8(a, b) }
1104}
1105#[doc = "Absolute difference between the arguments"]
1106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
1107#[inline]
1108#[target_feature(enable = "neon")]
1109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1111#[cfg_attr(
1112    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1113    assert_instr(uabd)
1114)]
1115#[cfg_attr(
1116    not(target_arch = "arm"),
1117    stable(feature = "neon_intrinsics", since = "1.59.0")
1118)]
1119#[cfg_attr(
1120    target_arch = "arm",
1121    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1122)]
1123pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1124    unsafe extern "unadjusted" {
1125        #[cfg_attr(
1126            any(target_arch = "aarch64", target_arch = "arm64ec"),
1127            link_name = "llvm.aarch64.neon.uabd.v16i8"
1128        )]
1129        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")]
1130        fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
1131    }
1132    unsafe { _vabdq_u8(a, b) }
1133}
1134#[doc = "Absolute difference between the arguments"]
1135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
1136#[inline]
1137#[target_feature(enable = "neon")]
1138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1139#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1140#[cfg_attr(
1141    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1142    assert_instr(uabd)
1143)]
1144#[cfg_attr(
1145    not(target_arch = "arm"),
1146    stable(feature = "neon_intrinsics", since = "1.59.0")
1147)]
1148#[cfg_attr(
1149    target_arch = "arm",
1150    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1151)]
1152pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1153    unsafe extern "unadjusted" {
1154        #[cfg_attr(
1155            any(target_arch = "aarch64", target_arch = "arm64ec"),
1156            link_name = "llvm.aarch64.neon.uabd.v4i16"
1157        )]
1158        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")]
1159        fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
1160    }
1161    unsafe { _vabd_u16(a, b) }
1162}
1163#[doc = "Absolute difference between the arguments"]
1164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
1165#[inline]
1166#[target_feature(enable = "neon")]
1167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1169#[cfg_attr(
1170    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1171    assert_instr(uabd)
1172)]
1173#[cfg_attr(
1174    not(target_arch = "arm"),
1175    stable(feature = "neon_intrinsics", since = "1.59.0")
1176)]
1177#[cfg_attr(
1178    target_arch = "arm",
1179    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1180)]
1181pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1182    unsafe extern "unadjusted" {
1183        #[cfg_attr(
1184            any(target_arch = "aarch64", target_arch = "arm64ec"),
1185            link_name = "llvm.aarch64.neon.uabd.v8i16"
1186        )]
1187        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")]
1188        fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
1189    }
1190    unsafe { _vabdq_u16(a, b) }
1191}
1192#[doc = "Absolute difference between the arguments"]
1193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
1194#[inline]
1195#[target_feature(enable = "neon")]
1196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1198#[cfg_attr(
1199    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1200    assert_instr(uabd)
1201)]
1202#[cfg_attr(
1203    not(target_arch = "arm"),
1204    stable(feature = "neon_intrinsics", since = "1.59.0")
1205)]
1206#[cfg_attr(
1207    target_arch = "arm",
1208    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1209)]
1210pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1211    unsafe extern "unadjusted" {
1212        #[cfg_attr(
1213            any(target_arch = "aarch64", target_arch = "arm64ec"),
1214            link_name = "llvm.aarch64.neon.uabd.v2i32"
1215        )]
1216        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")]
1217        fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
1218    }
1219    unsafe { _vabd_u32(a, b) }
1220}
1221#[doc = "Absolute difference between the arguments"]
1222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
1223#[inline]
1224#[target_feature(enable = "neon")]
1225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1227#[cfg_attr(
1228    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1229    assert_instr(uabd)
1230)]
1231#[cfg_attr(
1232    not(target_arch = "arm"),
1233    stable(feature = "neon_intrinsics", since = "1.59.0")
1234)]
1235#[cfg_attr(
1236    target_arch = "arm",
1237    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1238)]
1239pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1240    unsafe extern "unadjusted" {
1241        #[cfg_attr(
1242            any(target_arch = "aarch64", target_arch = "arm64ec"),
1243            link_name = "llvm.aarch64.neon.uabd.v4i32"
1244        )]
1245        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")]
1246        fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
1247    }
1248    unsafe { _vabdq_u32(a, b) }
1249}
1250#[doc = "Signed Absolute difference Long"]
1251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
1252#[inline]
1253#[target_feature(enable = "neon")]
1254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
1256#[cfg_attr(
1257    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1258    assert_instr(sabdl)
1259)]
1260#[cfg_attr(
1261    not(target_arch = "arm"),
1262    stable(feature = "neon_intrinsics", since = "1.59.0")
1263)]
1264#[cfg_attr(
1265    target_arch = "arm",
1266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1267)]
1268pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
1269    unsafe {
1270        let c: uint8x8_t = simd_cast(vabd_s8(a, b));
1271        simd_cast(c)
1272    }
1273}
1274#[doc = "Signed Absolute difference Long"]
1275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
1276#[inline]
1277#[target_feature(enable = "neon")]
1278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
1280#[cfg_attr(
1281    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1282    assert_instr(sabdl)
1283)]
1284#[cfg_attr(
1285    not(target_arch = "arm"),
1286    stable(feature = "neon_intrinsics", since = "1.59.0")
1287)]
1288#[cfg_attr(
1289    target_arch = "arm",
1290    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1291)]
1292pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
1293    unsafe {
1294        let c: uint16x4_t = simd_cast(vabd_s16(a, b));
1295        simd_cast(c)
1296    }
1297}
1298#[doc = "Signed Absolute difference Long"]
1299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
1300#[inline]
1301#[target_feature(enable = "neon")]
1302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
1304#[cfg_attr(
1305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1306    assert_instr(sabdl)
1307)]
1308#[cfg_attr(
1309    not(target_arch = "arm"),
1310    stable(feature = "neon_intrinsics", since = "1.59.0")
1311)]
1312#[cfg_attr(
1313    target_arch = "arm",
1314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1315)]
1316pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
1317    unsafe {
1318        let c: uint32x2_t = simd_cast(vabd_s32(a, b));
1319        simd_cast(c)
1320    }
1321}
1322#[doc = "Unsigned Absolute difference Long"]
1323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
1324#[inline]
1325#[target_feature(enable = "neon")]
1326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
1328#[cfg_attr(
1329    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1330    assert_instr(uabdl)
1331)]
1332#[cfg_attr(
1333    not(target_arch = "arm"),
1334    stable(feature = "neon_intrinsics", since = "1.59.0")
1335)]
1336#[cfg_attr(
1337    target_arch = "arm",
1338    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1339)]
1340pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
1341    unsafe { simd_cast(vabd_u8(a, b)) }
1342}
1343#[doc = "Unsigned Absolute difference Long"]
1344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
1345#[inline]
1346#[target_feature(enable = "neon")]
1347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1348#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
1349#[cfg_attr(
1350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1351    assert_instr(uabdl)
1352)]
1353#[cfg_attr(
1354    not(target_arch = "arm"),
1355    stable(feature = "neon_intrinsics", since = "1.59.0")
1356)]
1357#[cfg_attr(
1358    target_arch = "arm",
1359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1360)]
1361pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
1362    unsafe { simd_cast(vabd_u16(a, b)) }
1363}
1364#[doc = "Unsigned Absolute difference Long"]
1365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
1366#[inline]
1367#[target_feature(enable = "neon")]
1368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
1370#[cfg_attr(
1371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1372    assert_instr(uabdl)
1373)]
1374#[cfg_attr(
1375    not(target_arch = "arm"),
1376    stable(feature = "neon_intrinsics", since = "1.59.0")
1377)]
1378#[cfg_attr(
1379    target_arch = "arm",
1380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1381)]
1382pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
1383    unsafe { simd_cast(vabd_u32(a, b)) }
1384}
1385#[doc = "Floating-point absolute value"]
1386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
1387#[inline]
1388#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1390#[cfg_attr(
1391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1392    assert_instr(fabs)
1393)]
1394#[target_feature(enable = "neon,fp16")]
1395#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1396pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
1397    unsafe { simd_fabs(a) }
1398}
1399#[doc = "Floating-point absolute value"]
1400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
1401#[inline]
1402#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1404#[cfg_attr(
1405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1406    assert_instr(fabs)
1407)]
1408#[target_feature(enable = "neon,fp16")]
1409#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1410pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
1411    unsafe { simd_fabs(a) }
1412}
1413#[doc = "Floating-point absolute value"]
1414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
1415#[inline]
1416#[target_feature(enable = "neon")]
1417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1419#[cfg_attr(
1420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1421    assert_instr(fabs)
1422)]
1423#[cfg_attr(
1424    not(target_arch = "arm"),
1425    stable(feature = "neon_intrinsics", since = "1.59.0")
1426)]
1427#[cfg_attr(
1428    target_arch = "arm",
1429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1430)]
1431pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
1432    unsafe { simd_fabs(a) }
1433}
1434#[doc = "Floating-point absolute value"]
1435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
1436#[inline]
1437#[target_feature(enable = "neon")]
1438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1440#[cfg_attr(
1441    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1442    assert_instr(fabs)
1443)]
1444#[cfg_attr(
1445    not(target_arch = "arm"),
1446    stable(feature = "neon_intrinsics", since = "1.59.0")
1447)]
1448#[cfg_attr(
1449    target_arch = "arm",
1450    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1451)]
1452pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
1453    unsafe { simd_fabs(a) }
1454}
1455#[doc = "Absolute value (wrapping)."]
1456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
1457#[inline]
1458#[target_feature(enable = "neon")]
1459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1461#[cfg_attr(
1462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1463    assert_instr(abs)
1464)]
1465#[cfg_attr(
1466    not(target_arch = "arm"),
1467    stable(feature = "neon_intrinsics", since = "1.59.0")
1468)]
1469#[cfg_attr(
1470    target_arch = "arm",
1471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1472)]
1473pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
1474    unsafe extern "unadjusted" {
1475        #[cfg_attr(
1476            any(target_arch = "aarch64", target_arch = "arm64ec"),
1477            link_name = "llvm.aarch64.neon.abs.v8i8"
1478        )]
1479        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
1480        fn _vabs_s8(a: int8x8_t) -> int8x8_t;
1481    }
1482    unsafe { _vabs_s8(a) }
1483}
1484#[doc = "Absolute value (wrapping)."]
1485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
1486#[inline]
1487#[target_feature(enable = "neon")]
1488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1490#[cfg_attr(
1491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1492    assert_instr(abs)
1493)]
1494#[cfg_attr(
1495    not(target_arch = "arm"),
1496    stable(feature = "neon_intrinsics", since = "1.59.0")
1497)]
1498#[cfg_attr(
1499    target_arch = "arm",
1500    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1501)]
1502pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
1503    unsafe extern "unadjusted" {
1504        #[cfg_attr(
1505            any(target_arch = "aarch64", target_arch = "arm64ec"),
1506            link_name = "llvm.aarch64.neon.abs.v16i8"
1507        )]
1508        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
1509        fn _vabsq_s8(a: int8x16_t) -> int8x16_t;
1510    }
1511    unsafe { _vabsq_s8(a) }
1512}
1513#[doc = "Absolute value (wrapping)."]
1514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
1515#[inline]
1516#[target_feature(enable = "neon")]
1517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1518#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1519#[cfg_attr(
1520    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1521    assert_instr(abs)
1522)]
1523#[cfg_attr(
1524    not(target_arch = "arm"),
1525    stable(feature = "neon_intrinsics", since = "1.59.0")
1526)]
1527#[cfg_attr(
1528    target_arch = "arm",
1529    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1530)]
1531pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
1532    unsafe extern "unadjusted" {
1533        #[cfg_attr(
1534            any(target_arch = "aarch64", target_arch = "arm64ec"),
1535            link_name = "llvm.aarch64.neon.abs.v4i16"
1536        )]
1537        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
1538        fn _vabs_s16(a: int16x4_t) -> int16x4_t;
1539    }
1540    unsafe { _vabs_s16(a) }
1541}
1542#[doc = "Absolute value (wrapping)."]
1543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
1544#[inline]
1545#[target_feature(enable = "neon")]
1546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1548#[cfg_attr(
1549    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1550    assert_instr(abs)
1551)]
1552#[cfg_attr(
1553    not(target_arch = "arm"),
1554    stable(feature = "neon_intrinsics", since = "1.59.0")
1555)]
1556#[cfg_attr(
1557    target_arch = "arm",
1558    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1559)]
1560pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
1561    unsafe extern "unadjusted" {
1562        #[cfg_attr(
1563            any(target_arch = "aarch64", target_arch = "arm64ec"),
1564            link_name = "llvm.aarch64.neon.abs.v8i16"
1565        )]
1566        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
1567        fn _vabsq_s16(a: int16x8_t) -> int16x8_t;
1568    }
1569    unsafe { _vabsq_s16(a) }
1570}
1571#[doc = "Absolute value (wrapping)."]
1572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
1573#[inline]
1574#[target_feature(enable = "neon")]
1575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1577#[cfg_attr(
1578    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1579    assert_instr(abs)
1580)]
1581#[cfg_attr(
1582    not(target_arch = "arm"),
1583    stable(feature = "neon_intrinsics", since = "1.59.0")
1584)]
1585#[cfg_attr(
1586    target_arch = "arm",
1587    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1588)]
1589pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
1590    unsafe extern "unadjusted" {
1591        #[cfg_attr(
1592            any(target_arch = "aarch64", target_arch = "arm64ec"),
1593            link_name = "llvm.aarch64.neon.abs.v2i32"
1594        )]
1595        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
1596        fn _vabs_s32(a: int32x2_t) -> int32x2_t;
1597    }
1598    unsafe { _vabs_s32(a) }
1599}
1600#[doc = "Absolute value (wrapping)."]
1601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
1602#[inline]
1603#[target_feature(enable = "neon")]
1604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1606#[cfg_attr(
1607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1608    assert_instr(abs)
1609)]
1610#[cfg_attr(
1611    not(target_arch = "arm"),
1612    stable(feature = "neon_intrinsics", since = "1.59.0")
1613)]
1614#[cfg_attr(
1615    target_arch = "arm",
1616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1617)]
1618pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
1619    unsafe extern "unadjusted" {
1620        #[cfg_attr(
1621            any(target_arch = "aarch64", target_arch = "arm64ec"),
1622            link_name = "llvm.aarch64.neon.abs.v4i32"
1623        )]
1624        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
1625        fn _vabsq_s32(a: int32x4_t) -> int32x4_t;
1626    }
1627    unsafe { _vabsq_s32(a) }
1628}
1629#[doc = "Floating-point absolute value"]
1630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
1631#[inline]
1632#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1634#[cfg_attr(
1635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1636    assert_instr(fabs)
1637)]
1638#[target_feature(enable = "neon,fp16")]
1639#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1640pub fn vabsh_f16(a: f16) -> f16 {
1641    unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
1642}
1643#[doc = "Floating-point Add (vector)."]
1644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
1645#[inline]
1646#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1648#[cfg_attr(
1649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1650    assert_instr(fadd)
1651)]
1652#[target_feature(enable = "neon,fp16")]
1653#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1654pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1655    unsafe { simd_add(a, b) }
1656}
1657#[doc = "Floating-point Add (vector)."]
1658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
1659#[inline]
1660#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1662#[cfg_attr(
1663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1664    assert_instr(fadd)
1665)]
1666#[target_feature(enable = "neon,fp16")]
1667#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1668pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1669    unsafe { simd_add(a, b) }
1670}
1671#[doc = "Vector add."]
1672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
1673#[inline]
1674#[target_feature(enable = "neon")]
1675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1677#[cfg_attr(
1678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1679    assert_instr(fadd)
1680)]
1681#[cfg_attr(
1682    not(target_arch = "arm"),
1683    stable(feature = "neon_intrinsics", since = "1.59.0")
1684)]
1685#[cfg_attr(
1686    target_arch = "arm",
1687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1688)]
1689pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1690    unsafe { simd_add(a, b) }
1691}
1692#[doc = "Vector add."]
1693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
1694#[inline]
1695#[target_feature(enable = "neon")]
1696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1698#[cfg_attr(
1699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1700    assert_instr(add)
1701)]
1702#[cfg_attr(
1703    not(target_arch = "arm"),
1704    stable(feature = "neon_intrinsics", since = "1.59.0")
1705)]
1706#[cfg_attr(
1707    target_arch = "arm",
1708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1709)]
1710pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
1711    unsafe { simd_add(a, b) }
1712}
1713#[doc = "Vector add."]
1714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
1715#[inline]
1716#[target_feature(enable = "neon")]
1717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1719#[cfg_attr(
1720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1721    assert_instr(add)
1722)]
1723#[cfg_attr(
1724    not(target_arch = "arm"),
1725    stable(feature = "neon_intrinsics", since = "1.59.0")
1726)]
1727#[cfg_attr(
1728    target_arch = "arm",
1729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1730)]
1731pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1732    unsafe { simd_add(a, b) }
1733}
1734#[doc = "Vector add."]
1735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
1736#[inline]
1737#[target_feature(enable = "neon")]
1738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1740#[cfg_attr(
1741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1742    assert_instr(add)
1743)]
1744#[cfg_attr(
1745    not(target_arch = "arm"),
1746    stable(feature = "neon_intrinsics", since = "1.59.0")
1747)]
1748#[cfg_attr(
1749    target_arch = "arm",
1750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1751)]
1752pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
1753    unsafe { simd_add(a, b) }
1754}
1755#[doc = "Vector add."]
1756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
1757#[inline]
1758#[target_feature(enable = "neon")]
1759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1761#[cfg_attr(
1762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1763    assert_instr(add)
1764)]
1765#[cfg_attr(
1766    not(target_arch = "arm"),
1767    stable(feature = "neon_intrinsics", since = "1.59.0")
1768)]
1769#[cfg_attr(
1770    target_arch = "arm",
1771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1772)]
1773pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1774    unsafe { simd_add(a, b) }
1775}
1776#[doc = "Vector add."]
1777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
1778#[inline]
1779#[target_feature(enable = "neon")]
1780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1782#[cfg_attr(
1783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1784    assert_instr(add)
1785)]
1786#[cfg_attr(
1787    not(target_arch = "arm"),
1788    stable(feature = "neon_intrinsics", since = "1.59.0")
1789)]
1790#[cfg_attr(
1791    target_arch = "arm",
1792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1793)]
1794pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1795    unsafe { simd_add(a, b) }
1796}
1797#[doc = "Vector add."]
1798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
1799#[inline]
1800#[target_feature(enable = "neon")]
1801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1803#[cfg_attr(
1804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1805    assert_instr(add)
1806)]
1807#[cfg_attr(
1808    not(target_arch = "arm"),
1809    stable(feature = "neon_intrinsics", since = "1.59.0")
1810)]
1811#[cfg_attr(
1812    target_arch = "arm",
1813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1814)]
1815pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1816    unsafe { simd_add(a, b) }
1817}
1818#[doc = "Vector add."]
1819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
1820#[inline]
1821#[target_feature(enable = "neon")]
1822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1824#[cfg_attr(
1825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1826    assert_instr(fadd)
1827)]
1828#[cfg_attr(
1829    not(target_arch = "arm"),
1830    stable(feature = "neon_intrinsics", since = "1.59.0")
1831)]
1832#[cfg_attr(
1833    target_arch = "arm",
1834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1835)]
1836pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1837    unsafe { simd_add(a, b) }
1838}
1839#[doc = "Vector add."]
1840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
1841#[inline]
1842#[target_feature(enable = "neon")]
1843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1845#[cfg_attr(
1846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1847    assert_instr(add)
1848)]
1849#[cfg_attr(
1850    not(target_arch = "arm"),
1851    stable(feature = "neon_intrinsics", since = "1.59.0")
1852)]
1853#[cfg_attr(
1854    target_arch = "arm",
1855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1856)]
1857pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1858    unsafe { simd_add(a, b) }
1859}
1860#[doc = "Vector add."]
1861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
1862#[inline]
1863#[target_feature(enable = "neon")]
1864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1866#[cfg_attr(
1867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1868    assert_instr(add)
1869)]
1870#[cfg_attr(
1871    not(target_arch = "arm"),
1872    stable(feature = "neon_intrinsics", since = "1.59.0")
1873)]
1874#[cfg_attr(
1875    target_arch = "arm",
1876    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1877)]
1878pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1879    unsafe { simd_add(a, b) }
1880}
1881#[doc = "Vector add."]
1882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
1883#[inline]
1884#[target_feature(enable = "neon")]
1885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1887#[cfg_attr(
1888    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1889    assert_instr(add)
1890)]
1891#[cfg_attr(
1892    not(target_arch = "arm"),
1893    stable(feature = "neon_intrinsics", since = "1.59.0")
1894)]
1895#[cfg_attr(
1896    target_arch = "arm",
1897    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1898)]
1899pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
1900    unsafe { simd_add(a, b) }
1901}
1902#[doc = "Vector add."]
1903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
1904#[inline]
1905#[target_feature(enable = "neon")]
1906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1908#[cfg_attr(
1909    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1910    assert_instr(add)
1911)]
1912#[cfg_attr(
1913    not(target_arch = "arm"),
1914    stable(feature = "neon_intrinsics", since = "1.59.0")
1915)]
1916#[cfg_attr(
1917    target_arch = "arm",
1918    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1919)]
1920pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
1921    unsafe { simd_add(a, b) }
1922}
1923#[doc = "Vector add."]
1924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
1925#[inline]
1926#[target_feature(enable = "neon")]
1927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1929#[cfg_attr(
1930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1931    assert_instr(add)
1932)]
1933#[cfg_attr(
1934    not(target_arch = "arm"),
1935    stable(feature = "neon_intrinsics", since = "1.59.0")
1936)]
1937#[cfg_attr(
1938    target_arch = "arm",
1939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1940)]
1941pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1942    unsafe { simd_add(a, b) }
1943}
1944#[doc = "Vector add."]
1945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
1946#[inline]
1947#[target_feature(enable = "neon")]
1948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1950#[cfg_attr(
1951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1952    assert_instr(add)
1953)]
1954#[cfg_attr(
1955    not(target_arch = "arm"),
1956    stable(feature = "neon_intrinsics", since = "1.59.0")
1957)]
1958#[cfg_attr(
1959    target_arch = "arm",
1960    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1961)]
1962pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1963    unsafe { simd_add(a, b) }
1964}
1965#[doc = "Vector add."]
1966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
1967#[inline]
1968#[target_feature(enable = "neon")]
1969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1971#[cfg_attr(
1972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1973    assert_instr(add)
1974)]
1975#[cfg_attr(
1976    not(target_arch = "arm"),
1977    stable(feature = "neon_intrinsics", since = "1.59.0")
1978)]
1979#[cfg_attr(
1980    target_arch = "arm",
1981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1982)]
1983pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
1984    unsafe { simd_add(a, b) }
1985}
1986#[doc = "Vector add."]
1987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
1988#[inline]
1989#[target_feature(enable = "neon")]
1990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1991#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1992#[cfg_attr(
1993    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1994    assert_instr(add)
1995)]
1996#[cfg_attr(
1997    not(target_arch = "arm"),
1998    stable(feature = "neon_intrinsics", since = "1.59.0")
1999)]
2000#[cfg_attr(
2001    target_arch = "arm",
2002    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2003)]
2004pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
2005    unsafe { simd_add(a, b) }
2006}
2007#[doc = "Bitwise exclusive OR"]
2008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
2009#[inline]
2010#[target_feature(enable = "neon")]
2011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2013#[cfg_attr(
2014    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2015    assert_instr(nop)
2016)]
2017#[cfg_attr(
2018    not(target_arch = "arm"),
2019    stable(feature = "neon_intrinsics", since = "1.59.0")
2020)]
2021#[cfg_attr(
2022    target_arch = "arm",
2023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2024)]
2025pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
2026    unsafe { simd_xor(a, b) }
2027}
2028#[doc = "Bitwise exclusive OR"]
2029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
2030#[inline]
2031#[target_feature(enable = "neon")]
2032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2034#[cfg_attr(
2035    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2036    assert_instr(nop)
2037)]
2038#[cfg_attr(
2039    not(target_arch = "arm"),
2040    stable(feature = "neon_intrinsics", since = "1.59.0")
2041)]
2042#[cfg_attr(
2043    target_arch = "arm",
2044    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2045)]
2046pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
2047    unsafe { simd_xor(a, b) }
2048}
2049#[doc = "Bitwise exclusive OR"]
2050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
2051#[inline]
2052#[target_feature(enable = "neon")]
2053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2055#[cfg_attr(
2056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2057    assert_instr(nop)
2058)]
2059#[cfg_attr(
2060    not(target_arch = "arm"),
2061    stable(feature = "neon_intrinsics", since = "1.59.0")
2062)]
2063#[cfg_attr(
2064    target_arch = "arm",
2065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2066)]
2067pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
2068    unsafe { simd_xor(a, b) }
2069}
2070#[doc = "Bitwise exclusive OR"]
2071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
2072#[inline]
2073#[target_feature(enable = "neon")]
2074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2076#[cfg_attr(
2077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2078    assert_instr(nop)
2079)]
2080#[cfg_attr(
2081    not(target_arch = "arm"),
2082    stable(feature = "neon_intrinsics", since = "1.59.0")
2083)]
2084#[cfg_attr(
2085    target_arch = "arm",
2086    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2087)]
2088pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
2089    unsafe { simd_xor(a, b) }
2090}
2091#[doc = "Bitwise exclusive OR"]
2092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
2093#[inline]
2094#[target_feature(enable = "neon")]
2095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2097#[cfg_attr(
2098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2099    assert_instr(nop)
2100)]
2101#[cfg_attr(
2102    not(target_arch = "arm"),
2103    stable(feature = "neon_intrinsics", since = "1.59.0")
2104)]
2105#[cfg_attr(
2106    target_arch = "arm",
2107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2108)]
2109pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
2110    unsafe { simd_xor(a, b) }
2111}
2112#[doc = "Bitwise exclusive OR"]
2113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
2114#[inline]
2115#[target_feature(enable = "neon")]
2116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2118#[cfg_attr(
2119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2120    assert_instr(nop)
2121)]
2122#[cfg_attr(
2123    not(target_arch = "arm"),
2124    stable(feature = "neon_intrinsics", since = "1.59.0")
2125)]
2126#[cfg_attr(
2127    target_arch = "arm",
2128    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2129)]
2130pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
2131    unsafe { simd_xor(a, b) }
2132}
2133#[doc = "Add"]
2134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
2135#[inline]
2136#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2137#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
2138#[cfg_attr(
2139    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2140    assert_instr(fadd)
2141)]
2142#[target_feature(enable = "neon,fp16")]
2143#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2144pub fn vaddh_f16(a: f16, b: f16) -> f16 {
2145    a + b
2146}
2147#[doc = "Add returning High Narrow (high half)."]
2148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
2149#[inline]
2150#[target_feature(enable = "neon")]
2151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2153#[cfg_attr(
2154    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2155    assert_instr(addhn2)
2156)]
2157#[cfg_attr(
2158    not(target_arch = "arm"),
2159    stable(feature = "neon_intrinsics", since = "1.59.0")
2160)]
2161#[cfg_attr(
2162    target_arch = "arm",
2163    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2164)]
2165pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
2166    unsafe {
2167        let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8)));
2168        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2169    }
2170}
2171#[doc = "Add returning High Narrow (high half)."]
2172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
2173#[inline]
2174#[target_feature(enable = "neon")]
2175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2177#[cfg_attr(
2178    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2179    assert_instr(addhn2)
2180)]
2181#[cfg_attr(
2182    not(target_arch = "arm"),
2183    stable(feature = "neon_intrinsics", since = "1.59.0")
2184)]
2185#[cfg_attr(
2186    target_arch = "arm",
2187    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2188)]
2189pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
2190    unsafe {
2191        let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16)));
2192        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2193    }
2194}
2195#[doc = "Add returning High Narrow (high half)."]
2196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
2197#[inline]
2198#[target_feature(enable = "neon")]
2199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2201#[cfg_attr(
2202    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2203    assert_instr(addhn2)
2204)]
2205#[cfg_attr(
2206    not(target_arch = "arm"),
2207    stable(feature = "neon_intrinsics", since = "1.59.0")
2208)]
2209#[cfg_attr(
2210    target_arch = "arm",
2211    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2212)]
2213pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
2214    unsafe {
2215        let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32)));
2216        simd_shuffle!(r, x, [0, 1, 2, 3])
2217    }
2218}
2219#[doc = "Add returning High Narrow (high half)."]
2220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
2221#[inline]
2222#[target_feature(enable = "neon")]
2223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2225#[cfg_attr(
2226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2227    assert_instr(addhn2)
2228)]
2229#[cfg_attr(
2230    not(target_arch = "arm"),
2231    stable(feature = "neon_intrinsics", since = "1.59.0")
2232)]
2233#[cfg_attr(
2234    target_arch = "arm",
2235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2236)]
2237pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t {
2238    unsafe {
2239        let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8)));
2240        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2241    }
2242}
2243#[doc = "Add returning High Narrow (high half)."]
2244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
2245#[inline]
2246#[target_feature(enable = "neon")]
2247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2249#[cfg_attr(
2250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2251    assert_instr(addhn2)
2252)]
2253#[cfg_attr(
2254    not(target_arch = "arm"),
2255    stable(feature = "neon_intrinsics", since = "1.59.0")
2256)]
2257#[cfg_attr(
2258    target_arch = "arm",
2259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2260)]
2261pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t {
2262    unsafe {
2263        let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16)));
2264        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2265    }
2266}
2267#[doc = "Add returning High Narrow (high half)."]
2268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
2269#[inline]
2270#[target_feature(enable = "neon")]
2271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2273#[cfg_attr(
2274    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2275    assert_instr(addhn2)
2276)]
2277#[cfg_attr(
2278    not(target_arch = "arm"),
2279    stable(feature = "neon_intrinsics", since = "1.59.0")
2280)]
2281#[cfg_attr(
2282    target_arch = "arm",
2283    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2284)]
2285pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t {
2286    unsafe {
2287        let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32)));
2288        simd_shuffle!(r, x, [0, 1, 2, 3])
2289    }
2290}
2291#[doc = "Add returning High Narrow."]
2292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
2293#[inline]
2294#[target_feature(enable = "neon")]
2295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2297#[cfg_attr(
2298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2299    assert_instr(addhn)
2300)]
2301#[cfg_attr(
2302    not(target_arch = "arm"),
2303    stable(feature = "neon_intrinsics", since = "1.59.0")
2304)]
2305#[cfg_attr(
2306    target_arch = "arm",
2307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2308)]
2309pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
2310    unsafe { simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) }
2311}
2312#[doc = "Add returning High Narrow."]
2313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
2314#[inline]
2315#[target_feature(enable = "neon")]
2316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2318#[cfg_attr(
2319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2320    assert_instr(addhn)
2321)]
2322#[cfg_attr(
2323    not(target_arch = "arm"),
2324    stable(feature = "neon_intrinsics", since = "1.59.0")
2325)]
2326#[cfg_attr(
2327    target_arch = "arm",
2328    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2329)]
2330pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
2331    unsafe { simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) }
2332}
2333#[doc = "Add returning High Narrow."]
2334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
2335#[inline]
2336#[target_feature(enable = "neon")]
2337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2339#[cfg_attr(
2340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2341    assert_instr(addhn)
2342)]
2343#[cfg_attr(
2344    not(target_arch = "arm"),
2345    stable(feature = "neon_intrinsics", since = "1.59.0")
2346)]
2347#[cfg_attr(
2348    target_arch = "arm",
2349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2350)]
2351pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
2352    unsafe { simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) }
2353}
2354#[doc = "Add returning High Narrow."]
2355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
2356#[inline]
2357#[target_feature(enable = "neon")]
2358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2360#[cfg_attr(
2361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2362    assert_instr(addhn)
2363)]
2364#[cfg_attr(
2365    not(target_arch = "arm"),
2366    stable(feature = "neon_intrinsics", since = "1.59.0")
2367)]
2368#[cfg_attr(
2369    target_arch = "arm",
2370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2371)]
2372pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
2373    unsafe { simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) }
2374}
2375#[doc = "Add returning High Narrow."]
2376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
2377#[inline]
2378#[target_feature(enable = "neon")]
2379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2381#[cfg_attr(
2382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2383    assert_instr(addhn)
2384)]
2385#[cfg_attr(
2386    not(target_arch = "arm"),
2387    stable(feature = "neon_intrinsics", since = "1.59.0")
2388)]
2389#[cfg_attr(
2390    target_arch = "arm",
2391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2392)]
2393pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
2394    unsafe { simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) }
2395}
2396#[doc = "Add returning High Narrow."]
2397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
2398#[inline]
2399#[target_feature(enable = "neon")]
2400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2402#[cfg_attr(
2403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2404    assert_instr(addhn)
2405)]
2406#[cfg_attr(
2407    not(target_arch = "arm"),
2408    stable(feature = "neon_intrinsics", since = "1.59.0")
2409)]
2410#[cfg_attr(
2411    target_arch = "arm",
2412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2413)]
2414pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
2415    unsafe { simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) }
2416}
2417#[doc = "Signed Add Long (vector, high half)."]
2418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
2419#[inline]
2420#[target_feature(enable = "neon")]
2421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2423#[cfg_attr(
2424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2425    assert_instr(saddl2)
2426)]
2427#[cfg_attr(
2428    not(target_arch = "arm"),
2429    stable(feature = "neon_intrinsics", since = "1.59.0")
2430)]
2431#[cfg_attr(
2432    target_arch = "arm",
2433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2434)]
2435pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
2436    unsafe {
2437        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2438        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2439        let a: int32x4_t = simd_cast(a);
2440        let b: int32x4_t = simd_cast(b);
2441        simd_add(a, b)
2442    }
2443}
2444#[doc = "Signed Add Long (vector, high half)."]
2445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
2446#[inline]
2447#[target_feature(enable = "neon")]
2448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2450#[cfg_attr(
2451    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2452    assert_instr(saddl2)
2453)]
2454#[cfg_attr(
2455    not(target_arch = "arm"),
2456    stable(feature = "neon_intrinsics", since = "1.59.0")
2457)]
2458#[cfg_attr(
2459    target_arch = "arm",
2460    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2461)]
2462pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
2463    unsafe {
2464        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
2465        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2466        let a: int64x2_t = simd_cast(a);
2467        let b: int64x2_t = simd_cast(b);
2468        simd_add(a, b)
2469    }
2470}
2471#[doc = "Signed Add Long (vector, high half)."]
2472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
2473#[inline]
2474#[target_feature(enable = "neon")]
2475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2477#[cfg_attr(
2478    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2479    assert_instr(saddl2)
2480)]
2481#[cfg_attr(
2482    not(target_arch = "arm"),
2483    stable(feature = "neon_intrinsics", since = "1.59.0")
2484)]
2485#[cfg_attr(
2486    target_arch = "arm",
2487    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2488)]
2489pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
2490    unsafe {
2491        let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2492        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2493        let a: int16x8_t = simd_cast(a);
2494        let b: int16x8_t = simd_cast(b);
2495        simd_add(a, b)
2496    }
2497}
2498#[doc = "Signed Add Long (vector, high half)."]
2499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
2500#[inline]
2501#[target_feature(enable = "neon")]
2502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2504#[cfg_attr(
2505    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2506    assert_instr(uaddl2)
2507)]
2508#[cfg_attr(
2509    not(target_arch = "arm"),
2510    stable(feature = "neon_intrinsics", since = "1.59.0")
2511)]
2512#[cfg_attr(
2513    target_arch = "arm",
2514    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2515)]
2516pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
2517    unsafe {
2518        let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2519        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2520        let a: uint32x4_t = simd_cast(a);
2521        let b: uint32x4_t = simd_cast(b);
2522        simd_add(a, b)
2523    }
2524}
2525#[doc = "Signed Add Long (vector, high half)."]
2526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
2527#[inline]
2528#[target_feature(enable = "neon")]
2529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2531#[cfg_attr(
2532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2533    assert_instr(uaddl2)
2534)]
2535#[cfg_attr(
2536    not(target_arch = "arm"),
2537    stable(feature = "neon_intrinsics", since = "1.59.0")
2538)]
2539#[cfg_attr(
2540    target_arch = "arm",
2541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2542)]
2543pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
2544    unsafe {
2545        let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
2546        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2547        let a: uint64x2_t = simd_cast(a);
2548        let b: uint64x2_t = simd_cast(b);
2549        simd_add(a, b)
2550    }
2551}
2552#[doc = "Signed Add Long (vector, high half)."]
2553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
2554#[inline]
2555#[target_feature(enable = "neon")]
2556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2558#[cfg_attr(
2559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2560    assert_instr(uaddl2)
2561)]
2562#[cfg_attr(
2563    not(target_arch = "arm"),
2564    stable(feature = "neon_intrinsics", since = "1.59.0")
2565)]
2566#[cfg_attr(
2567    target_arch = "arm",
2568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2569)]
2570pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
2571    unsafe {
2572        let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2573        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2574        let a: uint16x8_t = simd_cast(a);
2575        let b: uint16x8_t = simd_cast(b);
2576        simd_add(a, b)
2577    }
2578}
2579#[doc = "Add Long (vector)."]
2580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
2581#[inline]
2582#[target_feature(enable = "neon")]
2583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2585#[cfg_attr(
2586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2587    assert_instr(saddl)
2588)]
2589#[cfg_attr(
2590    not(target_arch = "arm"),
2591    stable(feature = "neon_intrinsics", since = "1.59.0")
2592)]
2593#[cfg_attr(
2594    target_arch = "arm",
2595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2596)]
2597pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
2598    unsafe {
2599        let a: int32x4_t = simd_cast(a);
2600        let b: int32x4_t = simd_cast(b);
2601        simd_add(a, b)
2602    }
2603}
2604#[doc = "Add Long (vector)."]
2605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
2606#[inline]
2607#[target_feature(enable = "neon")]
2608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2610#[cfg_attr(
2611    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2612    assert_instr(saddl)
2613)]
2614#[cfg_attr(
2615    not(target_arch = "arm"),
2616    stable(feature = "neon_intrinsics", since = "1.59.0")
2617)]
2618#[cfg_attr(
2619    target_arch = "arm",
2620    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2621)]
2622pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
2623    unsafe {
2624        let a: int64x2_t = simd_cast(a);
2625        let b: int64x2_t = simd_cast(b);
2626        simd_add(a, b)
2627    }
2628}
2629#[doc = "Add Long (vector)."]
2630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
2631#[inline]
2632#[target_feature(enable = "neon")]
2633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2635#[cfg_attr(
2636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2637    assert_instr(saddl)
2638)]
2639#[cfg_attr(
2640    not(target_arch = "arm"),
2641    stable(feature = "neon_intrinsics", since = "1.59.0")
2642)]
2643#[cfg_attr(
2644    target_arch = "arm",
2645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2646)]
2647pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
2648    unsafe {
2649        let a: int16x8_t = simd_cast(a);
2650        let b: int16x8_t = simd_cast(b);
2651        simd_add(a, b)
2652    }
2653}
2654#[doc = "Add Long (vector)."]
2655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
2656#[inline]
2657#[target_feature(enable = "neon")]
2658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2660#[cfg_attr(
2661    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2662    assert_instr(uaddl)
2663)]
2664#[cfg_attr(
2665    not(target_arch = "arm"),
2666    stable(feature = "neon_intrinsics", since = "1.59.0")
2667)]
2668#[cfg_attr(
2669    target_arch = "arm",
2670    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2671)]
2672pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
2673    unsafe {
2674        let a: uint32x4_t = simd_cast(a);
2675        let b: uint32x4_t = simd_cast(b);
2676        simd_add(a, b)
2677    }
2678}
2679#[doc = "Add Long (vector)."]
2680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
2681#[inline]
2682#[target_feature(enable = "neon")]
2683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2685#[cfg_attr(
2686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2687    assert_instr(uaddl)
2688)]
2689#[cfg_attr(
2690    not(target_arch = "arm"),
2691    stable(feature = "neon_intrinsics", since = "1.59.0")
2692)]
2693#[cfg_attr(
2694    target_arch = "arm",
2695    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2696)]
2697pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
2698    unsafe {
2699        let a: uint64x2_t = simd_cast(a);
2700        let b: uint64x2_t = simd_cast(b);
2701        simd_add(a, b)
2702    }
2703}
2704#[doc = "Add Long (vector)."]
2705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
2706#[inline]
2707#[target_feature(enable = "neon")]
2708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2710#[cfg_attr(
2711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2712    assert_instr(uaddl)
2713)]
2714#[cfg_attr(
2715    not(target_arch = "arm"),
2716    stable(feature = "neon_intrinsics", since = "1.59.0")
2717)]
2718#[cfg_attr(
2719    target_arch = "arm",
2720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2721)]
2722pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
2723    unsafe {
2724        let a: uint16x8_t = simd_cast(a);
2725        let b: uint16x8_t = simd_cast(b);
2726        simd_add(a, b)
2727    }
2728}
2729#[doc = "Bitwise exclusive OR"]
2730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
2731#[inline]
2732#[target_feature(enable = "neon")]
2733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2735#[cfg_attr(
2736    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2737    assert_instr(nop)
2738)]
2739#[cfg_attr(
2740    not(target_arch = "arm"),
2741    stable(feature = "neon_intrinsics", since = "1.59.0")
2742)]
2743#[cfg_attr(
2744    target_arch = "arm",
2745    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2746)]
2747pub fn vaddq_p128(a: p128, b: p128) -> p128 {
2748    a ^ b
2749}
2750#[doc = "Add Wide (high half)."]
2751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
2752#[inline]
2753#[target_feature(enable = "neon")]
2754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2756#[cfg_attr(
2757    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2758    assert_instr(saddw2)
2759)]
2760#[cfg_attr(
2761    not(target_arch = "arm"),
2762    stable(feature = "neon_intrinsics", since = "1.59.0")
2763)]
2764#[cfg_attr(
2765    target_arch = "arm",
2766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2767)]
2768pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
2769    unsafe {
2770        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2771        let b: int32x4_t = simd_cast(b);
2772        simd_add(a, b)
2773    }
2774}
2775#[doc = "Add Wide (high half)."]
2776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
2777#[inline]
2778#[target_feature(enable = "neon")]
2779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2781#[cfg_attr(
2782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2783    assert_instr(saddw2)
2784)]
2785#[cfg_attr(
2786    not(target_arch = "arm"),
2787    stable(feature = "neon_intrinsics", since = "1.59.0")
2788)]
2789#[cfg_attr(
2790    target_arch = "arm",
2791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2792)]
2793pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
2794    unsafe {
2795        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2796        let b: int64x2_t = simd_cast(b);
2797        simd_add(a, b)
2798    }
2799}
2800#[doc = "Add Wide (high half)."]
2801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
2802#[inline]
2803#[target_feature(enable = "neon")]
2804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2806#[cfg_attr(
2807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2808    assert_instr(saddw2)
2809)]
2810#[cfg_attr(
2811    not(target_arch = "arm"),
2812    stable(feature = "neon_intrinsics", since = "1.59.0")
2813)]
2814#[cfg_attr(
2815    target_arch = "arm",
2816    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2817)]
2818pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
2819    unsafe {
2820        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2821        let b: int16x8_t = simd_cast(b);
2822        simd_add(a, b)
2823    }
2824}
2825#[doc = "Add Wide (high half)."]
2826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
2827#[inline]
2828#[target_feature(enable = "neon")]
2829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2831#[cfg_attr(
2832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2833    assert_instr(uaddw2)
2834)]
2835#[cfg_attr(
2836    not(target_arch = "arm"),
2837    stable(feature = "neon_intrinsics", since = "1.59.0")
2838)]
2839#[cfg_attr(
2840    target_arch = "arm",
2841    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2842)]
2843pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
2844    unsafe {
2845        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2846        let b: uint32x4_t = simd_cast(b);
2847        simd_add(a, b)
2848    }
2849}
2850#[doc = "Add Wide (high half)."]
2851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
2852#[inline]
2853#[target_feature(enable = "neon")]
2854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2856#[cfg_attr(
2857    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2858    assert_instr(uaddw2)
2859)]
2860#[cfg_attr(
2861    not(target_arch = "arm"),
2862    stable(feature = "neon_intrinsics", since = "1.59.0")
2863)]
2864#[cfg_attr(
2865    target_arch = "arm",
2866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2867)]
2868pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
2869    unsafe {
2870        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2871        let b: uint64x2_t = simd_cast(b);
2872        simd_add(a, b)
2873    }
2874}
2875#[doc = "Add Wide (high half)."]
2876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
2877#[inline]
2878#[target_feature(enable = "neon")]
2879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2881#[cfg_attr(
2882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2883    assert_instr(uaddw2)
2884)]
2885#[cfg_attr(
2886    not(target_arch = "arm"),
2887    stable(feature = "neon_intrinsics", since = "1.59.0")
2888)]
2889#[cfg_attr(
2890    target_arch = "arm",
2891    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2892)]
2893pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
2894    unsafe {
2895        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2896        let b: uint16x8_t = simd_cast(b);
2897        simd_add(a, b)
2898    }
2899}
2900#[doc = "Add Wide"]
2901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
2902#[inline]
2903#[target_feature(enable = "neon")]
2904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2906#[cfg_attr(
2907    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2908    assert_instr(saddw)
2909)]
2910#[cfg_attr(
2911    not(target_arch = "arm"),
2912    stable(feature = "neon_intrinsics", since = "1.59.0")
2913)]
2914#[cfg_attr(
2915    target_arch = "arm",
2916    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2917)]
2918pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
2919    unsafe {
2920        let b: int32x4_t = simd_cast(b);
2921        simd_add(a, b)
2922    }
2923}
2924#[doc = "Add Wide"]
2925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
2926#[inline]
2927#[target_feature(enable = "neon")]
2928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2930#[cfg_attr(
2931    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2932    assert_instr(saddw)
2933)]
2934#[cfg_attr(
2935    not(target_arch = "arm"),
2936    stable(feature = "neon_intrinsics", since = "1.59.0")
2937)]
2938#[cfg_attr(
2939    target_arch = "arm",
2940    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2941)]
2942pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
2943    unsafe {
2944        let b: int64x2_t = simd_cast(b);
2945        simd_add(a, b)
2946    }
2947}
2948#[doc = "Add Wide"]
2949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
2950#[inline]
2951#[target_feature(enable = "neon")]
2952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2954#[cfg_attr(
2955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2956    assert_instr(saddw)
2957)]
2958#[cfg_attr(
2959    not(target_arch = "arm"),
2960    stable(feature = "neon_intrinsics", since = "1.59.0")
2961)]
2962#[cfg_attr(
2963    target_arch = "arm",
2964    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2965)]
2966pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
2967    unsafe {
2968        let b: int16x8_t = simd_cast(b);
2969        simd_add(a, b)
2970    }
2971}
2972#[doc = "Add Wide"]
2973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
2974#[inline]
2975#[target_feature(enable = "neon")]
2976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2978#[cfg_attr(
2979    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2980    assert_instr(uaddw)
2981)]
2982#[cfg_attr(
2983    not(target_arch = "arm"),
2984    stable(feature = "neon_intrinsics", since = "1.59.0")
2985)]
2986#[cfg_attr(
2987    target_arch = "arm",
2988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2989)]
2990pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
2991    unsafe {
2992        let b: uint32x4_t = simd_cast(b);
2993        simd_add(a, b)
2994    }
2995}
2996#[doc = "Add Wide"]
2997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
2998#[inline]
2999#[target_feature(enable = "neon")]
3000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3002#[cfg_attr(
3003    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3004    assert_instr(uaddw)
3005)]
3006#[cfg_attr(
3007    not(target_arch = "arm"),
3008    stable(feature = "neon_intrinsics", since = "1.59.0")
3009)]
3010#[cfg_attr(
3011    target_arch = "arm",
3012    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3013)]
3014pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
3015    unsafe {
3016        let b: uint64x2_t = simd_cast(b);
3017        simd_add(a, b)
3018    }
3019}
3020#[doc = "Add Wide"]
3021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
3022#[inline]
3023#[target_feature(enable = "neon")]
3024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3026#[cfg_attr(
3027    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3028    assert_instr(uaddw)
3029)]
3030#[cfg_attr(
3031    not(target_arch = "arm"),
3032    stable(feature = "neon_intrinsics", since = "1.59.0")
3033)]
3034#[cfg_attr(
3035    target_arch = "arm",
3036    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3037)]
3038pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
3039    unsafe {
3040        let b: uint16x8_t = simd_cast(b);
3041        simd_add(a, b)
3042    }
3043}
3044#[doc = "AES single round encryption."]
3045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
3046#[inline]
3047#[target_feature(enable = "aes")]
3048#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3049#[cfg_attr(test, assert_instr(aesd))]
3050#[cfg_attr(
3051    target_arch = "arm",
3052    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3053)]
3054#[cfg_attr(
3055    not(target_arch = "arm"),
3056    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3057)]
3058pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3059    unsafe extern "unadjusted" {
3060        #[cfg_attr(
3061            any(target_arch = "aarch64", target_arch = "arm64ec"),
3062            link_name = "llvm.aarch64.crypto.aesd"
3063        )]
3064        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
3065        fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3066    }
3067    unsafe { _vaesdq_u8(data, key) }
3068}
3069#[doc = "AES single round encryption."]
3070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
3071#[inline]
3072#[target_feature(enable = "aes")]
3073#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3074#[cfg_attr(test, assert_instr(aese))]
3075#[cfg_attr(
3076    target_arch = "arm",
3077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3078)]
3079#[cfg_attr(
3080    not(target_arch = "arm"),
3081    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3082)]
3083pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3084    unsafe extern "unadjusted" {
3085        #[cfg_attr(
3086            any(target_arch = "aarch64", target_arch = "arm64ec"),
3087            link_name = "llvm.aarch64.crypto.aese"
3088        )]
3089        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
3090        fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3091    }
3092    unsafe { _vaeseq_u8(data, key) }
3093}
3094#[doc = "AES inverse mix columns."]
3095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
3096#[inline]
3097#[target_feature(enable = "aes")]
3098#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3099#[cfg_attr(test, assert_instr(aesimc))]
3100#[cfg_attr(
3101    target_arch = "arm",
3102    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3103)]
3104#[cfg_attr(
3105    not(target_arch = "arm"),
3106    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3107)]
3108pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
3109    unsafe extern "unadjusted" {
3110        #[cfg_attr(
3111            any(target_arch = "aarch64", target_arch = "arm64ec"),
3112            link_name = "llvm.aarch64.crypto.aesimc"
3113        )]
3114        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
3115        fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t;
3116    }
3117    unsafe { _vaesimcq_u8(data) }
3118}
3119#[doc = "AES mix columns."]
3120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
3121#[inline]
3122#[target_feature(enable = "aes")]
3123#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3124#[cfg_attr(test, assert_instr(aesmc))]
3125#[cfg_attr(
3126    target_arch = "arm",
3127    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3128)]
3129#[cfg_attr(
3130    not(target_arch = "arm"),
3131    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3132)]
3133pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
3134    unsafe extern "unadjusted" {
3135        #[cfg_attr(
3136            any(target_arch = "aarch64", target_arch = "arm64ec"),
3137            link_name = "llvm.aarch64.crypto.aesmc"
3138        )]
3139        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
3140        fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t;
3141    }
3142    unsafe { _vaesmcq_u8(data) }
3143}
3144#[doc = "Vector bitwise and"]
3145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
3146#[inline]
3147#[target_feature(enable = "neon")]
3148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3149#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3150#[cfg_attr(
3151    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3152    assert_instr(and)
3153)]
3154#[cfg_attr(
3155    not(target_arch = "arm"),
3156    stable(feature = "neon_intrinsics", since = "1.59.0")
3157)]
3158#[cfg_attr(
3159    target_arch = "arm",
3160    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3161)]
3162pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3163    unsafe { simd_and(a, b) }
3164}
3165#[doc = "Vector bitwise and"]
3166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
3167#[inline]
3168#[target_feature(enable = "neon")]
3169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3171#[cfg_attr(
3172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3173    assert_instr(and)
3174)]
3175#[cfg_attr(
3176    not(target_arch = "arm"),
3177    stable(feature = "neon_intrinsics", since = "1.59.0")
3178)]
3179#[cfg_attr(
3180    target_arch = "arm",
3181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3182)]
3183pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3184    unsafe { simd_and(a, b) }
3185}
3186#[doc = "Vector bitwise and"]
3187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
3188#[inline]
3189#[target_feature(enable = "neon")]
3190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3192#[cfg_attr(
3193    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3194    assert_instr(and)
3195)]
3196#[cfg_attr(
3197    not(target_arch = "arm"),
3198    stable(feature = "neon_intrinsics", since = "1.59.0")
3199)]
3200#[cfg_attr(
3201    target_arch = "arm",
3202    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3203)]
3204pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3205    unsafe { simd_and(a, b) }
3206}
3207#[doc = "Vector bitwise and"]
3208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
3209#[inline]
3210#[target_feature(enable = "neon")]
3211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3213#[cfg_attr(
3214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3215    assert_instr(and)
3216)]
3217#[cfg_attr(
3218    not(target_arch = "arm"),
3219    stable(feature = "neon_intrinsics", since = "1.59.0")
3220)]
3221#[cfg_attr(
3222    target_arch = "arm",
3223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3224)]
3225pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3226    unsafe { simd_and(a, b) }
3227}
3228#[doc = "Vector bitwise and"]
3229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
3230#[inline]
3231#[target_feature(enable = "neon")]
3232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3234#[cfg_attr(
3235    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3236    assert_instr(and)
3237)]
3238#[cfg_attr(
3239    not(target_arch = "arm"),
3240    stable(feature = "neon_intrinsics", since = "1.59.0")
3241)]
3242#[cfg_attr(
3243    target_arch = "arm",
3244    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3245)]
3246pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3247    unsafe { simd_and(a, b) }
3248}
3249#[doc = "Vector bitwise and"]
3250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
3251#[inline]
3252#[target_feature(enable = "neon")]
3253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3255#[cfg_attr(
3256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3257    assert_instr(and)
3258)]
3259#[cfg_attr(
3260    not(target_arch = "arm"),
3261    stable(feature = "neon_intrinsics", since = "1.59.0")
3262)]
3263#[cfg_attr(
3264    target_arch = "arm",
3265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3266)]
3267pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3268    unsafe { simd_and(a, b) }
3269}
3270#[doc = "Vector bitwise and"]
3271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
3272#[inline]
3273#[target_feature(enable = "neon")]
3274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3276#[cfg_attr(
3277    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3278    assert_instr(and)
3279)]
3280#[cfg_attr(
3281    not(target_arch = "arm"),
3282    stable(feature = "neon_intrinsics", since = "1.59.0")
3283)]
3284#[cfg_attr(
3285    target_arch = "arm",
3286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3287)]
3288pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3289    unsafe { simd_and(a, b) }
3290}
3291#[doc = "Vector bitwise and"]
3292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
3293#[inline]
3294#[target_feature(enable = "neon")]
3295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3297#[cfg_attr(
3298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3299    assert_instr(and)
3300)]
3301#[cfg_attr(
3302    not(target_arch = "arm"),
3303    stable(feature = "neon_intrinsics", since = "1.59.0")
3304)]
3305#[cfg_attr(
3306    target_arch = "arm",
3307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3308)]
3309pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3310    unsafe { simd_and(a, b) }
3311}
3312#[doc = "Vector bitwise and"]
3313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
3314#[inline]
3315#[target_feature(enable = "neon")]
3316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3318#[cfg_attr(
3319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3320    assert_instr(and)
3321)]
3322#[cfg_attr(
3323    not(target_arch = "arm"),
3324    stable(feature = "neon_intrinsics", since = "1.59.0")
3325)]
3326#[cfg_attr(
3327    target_arch = "arm",
3328    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3329)]
3330pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3331    unsafe { simd_and(a, b) }
3332}
3333#[doc = "Vector bitwise and"]
3334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
3335#[inline]
3336#[target_feature(enable = "neon")]
3337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3339#[cfg_attr(
3340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3341    assert_instr(and)
3342)]
3343#[cfg_attr(
3344    not(target_arch = "arm"),
3345    stable(feature = "neon_intrinsics", since = "1.59.0")
3346)]
3347#[cfg_attr(
3348    target_arch = "arm",
3349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3350)]
3351pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3352    unsafe { simd_and(a, b) }
3353}
3354#[doc = "Vector bitwise and"]
3355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
3356#[inline]
3357#[target_feature(enable = "neon")]
3358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3360#[cfg_attr(
3361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3362    assert_instr(and)
3363)]
3364#[cfg_attr(
3365    not(target_arch = "arm"),
3366    stable(feature = "neon_intrinsics", since = "1.59.0")
3367)]
3368#[cfg_attr(
3369    target_arch = "arm",
3370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3371)]
3372pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3373    unsafe { simd_and(a, b) }
3374}
3375#[doc = "Vector bitwise and"]
3376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
3377#[inline]
3378#[target_feature(enable = "neon")]
3379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3381#[cfg_attr(
3382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3383    assert_instr(and)
3384)]
3385#[cfg_attr(
3386    not(target_arch = "arm"),
3387    stable(feature = "neon_intrinsics", since = "1.59.0")
3388)]
3389#[cfg_attr(
3390    target_arch = "arm",
3391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3392)]
3393pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3394    unsafe { simd_and(a, b) }
3395}
3396#[doc = "Vector bitwise and"]
3397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
3398#[inline]
3399#[target_feature(enable = "neon")]
3400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3402#[cfg_attr(
3403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3404    assert_instr(and)
3405)]
3406#[cfg_attr(
3407    not(target_arch = "arm"),
3408    stable(feature = "neon_intrinsics", since = "1.59.0")
3409)]
3410#[cfg_attr(
3411    target_arch = "arm",
3412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3413)]
3414pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3415    unsafe { simd_and(a, b) }
3416}
3417#[doc = "Vector bitwise and"]
3418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
3419#[inline]
3420#[target_feature(enable = "neon")]
3421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3423#[cfg_attr(
3424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3425    assert_instr(and)
3426)]
3427#[cfg_attr(
3428    not(target_arch = "arm"),
3429    stable(feature = "neon_intrinsics", since = "1.59.0")
3430)]
3431#[cfg_attr(
3432    target_arch = "arm",
3433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3434)]
3435pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3436    unsafe { simd_and(a, b) }
3437}
3438#[doc = "Vector bitwise and"]
3439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
3440#[inline]
3441#[target_feature(enable = "neon")]
3442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3444#[cfg_attr(
3445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3446    assert_instr(and)
3447)]
3448#[cfg_attr(
3449    not(target_arch = "arm"),
3450    stable(feature = "neon_intrinsics", since = "1.59.0")
3451)]
3452#[cfg_attr(
3453    target_arch = "arm",
3454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3455)]
3456pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3457    unsafe { simd_and(a, b) }
3458}
3459#[doc = "Vector bitwise and"]
3460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
3461#[inline]
3462#[target_feature(enable = "neon")]
3463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3465#[cfg_attr(
3466    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3467    assert_instr(and)
3468)]
3469#[cfg_attr(
3470    not(target_arch = "arm"),
3471    stable(feature = "neon_intrinsics", since = "1.59.0")
3472)]
3473#[cfg_attr(
3474    target_arch = "arm",
3475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3476)]
3477pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3478    unsafe { simd_and(a, b) }
3479}
3480#[doc = "Vector bitwise bit clear."]
3481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
3482#[inline]
3483#[target_feature(enable = "neon")]
3484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3486#[cfg_attr(
3487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3488    assert_instr(bic)
3489)]
3490#[cfg_attr(
3491    not(target_arch = "arm"),
3492    stable(feature = "neon_intrinsics", since = "1.59.0")
3493)]
3494#[cfg_attr(
3495    target_arch = "arm",
3496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3497)]
3498pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3499    let c = int16x4_t::splat(-1);
3500    unsafe { simd_and(simd_xor(b, c), a) }
3501}
3502#[doc = "Vector bitwise bit clear."]
3503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
3504#[inline]
3505#[target_feature(enable = "neon")]
3506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3508#[cfg_attr(
3509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3510    assert_instr(bic)
3511)]
3512#[cfg_attr(
3513    not(target_arch = "arm"),
3514    stable(feature = "neon_intrinsics", since = "1.59.0")
3515)]
3516#[cfg_attr(
3517    target_arch = "arm",
3518    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3519)]
3520pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3521    let c = int32x2_t::splat(-1);
3522    unsafe { simd_and(simd_xor(b, c), a) }
3523}
3524#[doc = "Vector bitwise bit clear."]
3525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
3526#[inline]
3527#[target_feature(enable = "neon")]
3528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3530#[cfg_attr(
3531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3532    assert_instr(bic)
3533)]
3534#[cfg_attr(
3535    not(target_arch = "arm"),
3536    stable(feature = "neon_intrinsics", since = "1.59.0")
3537)]
3538#[cfg_attr(
3539    target_arch = "arm",
3540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3541)]
3542pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3543    let c = int64x1_t::splat(-1);
3544    unsafe { simd_and(simd_xor(b, c), a) }
3545}
3546#[doc = "Vector bitwise bit clear."]
3547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
3548#[inline]
3549#[target_feature(enable = "neon")]
3550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3552#[cfg_attr(
3553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3554    assert_instr(bic)
3555)]
3556#[cfg_attr(
3557    not(target_arch = "arm"),
3558    stable(feature = "neon_intrinsics", since = "1.59.0")
3559)]
3560#[cfg_attr(
3561    target_arch = "arm",
3562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3563)]
3564pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3565    let c = int8x8_t::splat(-1);
3566    unsafe { simd_and(simd_xor(b, c), a) }
3567}
3568#[doc = "Vector bitwise bit clear."]
3569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
3570#[inline]
3571#[target_feature(enable = "neon")]
3572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3574#[cfg_attr(
3575    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3576    assert_instr(bic)
3577)]
3578#[cfg_attr(
3579    not(target_arch = "arm"),
3580    stable(feature = "neon_intrinsics", since = "1.59.0")
3581)]
3582#[cfg_attr(
3583    target_arch = "arm",
3584    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3585)]
3586pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3587    let c = int16x8_t::splat(-1);
3588    unsafe { simd_and(simd_xor(b, c), a) }
3589}
3590#[doc = "Vector bitwise bit clear."]
3591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
3592#[inline]
3593#[target_feature(enable = "neon")]
3594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3596#[cfg_attr(
3597    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3598    assert_instr(bic)
3599)]
3600#[cfg_attr(
3601    not(target_arch = "arm"),
3602    stable(feature = "neon_intrinsics", since = "1.59.0")
3603)]
3604#[cfg_attr(
3605    target_arch = "arm",
3606    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3607)]
3608pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3609    let c = int32x4_t::splat(-1);
3610    unsafe { simd_and(simd_xor(b, c), a) }
3611}
3612#[doc = "Vector bitwise bit clear."]
3613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
3614#[inline]
3615#[target_feature(enable = "neon")]
3616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3618#[cfg_attr(
3619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3620    assert_instr(bic)
3621)]
3622#[cfg_attr(
3623    not(target_arch = "arm"),
3624    stable(feature = "neon_intrinsics", since = "1.59.0")
3625)]
3626#[cfg_attr(
3627    target_arch = "arm",
3628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3629)]
3630pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3631    let c = int64x2_t::splat(-1);
3632    unsafe { simd_and(simd_xor(b, c), a) }
3633}
3634#[doc = "Vector bitwise bit clear."]
3635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
3636#[inline]
3637#[target_feature(enable = "neon")]
3638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3640#[cfg_attr(
3641    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3642    assert_instr(bic)
3643)]
3644#[cfg_attr(
3645    not(target_arch = "arm"),
3646    stable(feature = "neon_intrinsics", since = "1.59.0")
3647)]
3648#[cfg_attr(
3649    target_arch = "arm",
3650    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3651)]
3652pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3653    let c = int8x16_t::splat(-1);
3654    unsafe { simd_and(simd_xor(b, c), a) }
3655}
3656#[doc = "Vector bitwise bit clear."]
3657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
3658#[inline]
3659#[target_feature(enable = "neon")]
3660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3662#[cfg_attr(
3663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3664    assert_instr(bic)
3665)]
3666#[cfg_attr(
3667    not(target_arch = "arm"),
3668    stable(feature = "neon_intrinsics", since = "1.59.0")
3669)]
3670#[cfg_attr(
3671    target_arch = "arm",
3672    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3673)]
3674pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3675    let c = int16x4_t::splat(-1);
3676    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3677}
3678#[doc = "Vector bitwise bit clear."]
3679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
3680#[inline]
3681#[target_feature(enable = "neon")]
3682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3684#[cfg_attr(
3685    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3686    assert_instr(bic)
3687)]
3688#[cfg_attr(
3689    not(target_arch = "arm"),
3690    stable(feature = "neon_intrinsics", since = "1.59.0")
3691)]
3692#[cfg_attr(
3693    target_arch = "arm",
3694    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3695)]
3696pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3697    let c = int32x2_t::splat(-1);
3698    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3699}
3700#[doc = "Vector bitwise bit clear."]
3701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
3702#[inline]
3703#[target_feature(enable = "neon")]
3704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3706#[cfg_attr(
3707    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3708    assert_instr(bic)
3709)]
3710#[cfg_attr(
3711    not(target_arch = "arm"),
3712    stable(feature = "neon_intrinsics", since = "1.59.0")
3713)]
3714#[cfg_attr(
3715    target_arch = "arm",
3716    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3717)]
3718pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3719    let c = int64x1_t::splat(-1);
3720    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3721}
3722#[doc = "Vector bitwise bit clear."]
3723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
3724#[inline]
3725#[target_feature(enable = "neon")]
3726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3728#[cfg_attr(
3729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3730    assert_instr(bic)
3731)]
3732#[cfg_attr(
3733    not(target_arch = "arm"),
3734    stable(feature = "neon_intrinsics", since = "1.59.0")
3735)]
3736#[cfg_attr(
3737    target_arch = "arm",
3738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3739)]
3740pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3741    let c = int8x8_t::splat(-1);
3742    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3743}
3744#[doc = "Vector bitwise bit clear."]
3745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
3746#[inline]
3747#[target_feature(enable = "neon")]
3748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3750#[cfg_attr(
3751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3752    assert_instr(bic)
3753)]
3754#[cfg_attr(
3755    not(target_arch = "arm"),
3756    stable(feature = "neon_intrinsics", since = "1.59.0")
3757)]
3758#[cfg_attr(
3759    target_arch = "arm",
3760    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3761)]
3762pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3763    let c = int16x8_t::splat(-1);
3764    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3765}
3766#[doc = "Vector bitwise bit clear."]
3767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
3768#[inline]
3769#[target_feature(enable = "neon")]
3770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3772#[cfg_attr(
3773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3774    assert_instr(bic)
3775)]
3776#[cfg_attr(
3777    not(target_arch = "arm"),
3778    stable(feature = "neon_intrinsics", since = "1.59.0")
3779)]
3780#[cfg_attr(
3781    target_arch = "arm",
3782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3783)]
3784pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3785    let c = int32x4_t::splat(-1);
3786    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3787}
3788#[doc = "Vector bitwise bit clear."]
3789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
3790#[inline]
3791#[target_feature(enable = "neon")]
3792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3794#[cfg_attr(
3795    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3796    assert_instr(bic)
3797)]
3798#[cfg_attr(
3799    not(target_arch = "arm"),
3800    stable(feature = "neon_intrinsics", since = "1.59.0")
3801)]
3802#[cfg_attr(
3803    target_arch = "arm",
3804    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3805)]
3806pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3807    let c = int64x2_t::splat(-1);
3808    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3809}
3810#[doc = "Vector bitwise bit clear."]
3811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
3812#[inline]
3813#[target_feature(enable = "neon")]
3814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3816#[cfg_attr(
3817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3818    assert_instr(bic)
3819)]
3820#[cfg_attr(
3821    not(target_arch = "arm"),
3822    stable(feature = "neon_intrinsics", since = "1.59.0")
3823)]
3824#[cfg_attr(
3825    target_arch = "arm",
3826    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3827)]
3828pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3829    let c = int8x16_t::splat(-1);
3830    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3831}
3832#[doc = "Bitwise Select."]
3833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
3834#[inline]
3835#[target_feature(enable = "neon,fp16")]
3836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3838#[cfg_attr(
3839    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3840    assert_instr(bsl)
3841)]
3842#[cfg_attr(
3843    not(target_arch = "arm"),
3844    stable(feature = "neon_intrinsics", since = "1.59.0")
3845)]
3846#[cfg_attr(
3847    target_arch = "arm",
3848    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3849)]
3850pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3851    let not = int16x4_t::splat(-1);
3852    unsafe {
3853        transmute(simd_or(
3854            simd_and(a, transmute(b)),
3855            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3856        ))
3857    }
3858}
3859#[doc = "Bitwise Select."]
3860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
3861#[inline]
3862#[target_feature(enable = "neon,fp16")]
3863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3865#[cfg_attr(
3866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3867    assert_instr(bsl)
3868)]
3869#[cfg_attr(
3870    not(target_arch = "arm"),
3871    stable(feature = "neon_intrinsics", since = "1.59.0")
3872)]
3873#[cfg_attr(
3874    target_arch = "arm",
3875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3876)]
3877pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3878    let not = int16x8_t::splat(-1);
3879    unsafe {
3880        transmute(simd_or(
3881            simd_and(a, transmute(b)),
3882            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3883        ))
3884    }
3885}
3886#[doc = "Bitwise Select."]
3887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
3888#[inline]
3889#[target_feature(enable = "neon")]
3890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3892#[cfg_attr(
3893    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3894    assert_instr(bsl)
3895)]
3896#[cfg_attr(
3897    not(target_arch = "arm"),
3898    stable(feature = "neon_intrinsics", since = "1.59.0")
3899)]
3900#[cfg_attr(
3901    target_arch = "arm",
3902    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3903)]
3904pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3905    let not = int32x2_t::splat(-1);
3906    unsafe {
3907        transmute(simd_or(
3908            simd_and(a, transmute(b)),
3909            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3910        ))
3911    }
3912}
3913#[doc = "Bitwise Select."]
3914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
3915#[inline]
3916#[target_feature(enable = "neon")]
3917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3919#[cfg_attr(
3920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3921    assert_instr(bsl)
3922)]
3923#[cfg_attr(
3924    not(target_arch = "arm"),
3925    stable(feature = "neon_intrinsics", since = "1.59.0")
3926)]
3927#[cfg_attr(
3928    target_arch = "arm",
3929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3930)]
3931pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
3932    let not = int16x4_t::splat(-1);
3933    unsafe {
3934        transmute(simd_or(
3935            simd_and(a, transmute(b)),
3936            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3937        ))
3938    }
3939}
3940#[doc = "Bitwise Select."]
3941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
3942#[inline]
3943#[target_feature(enable = "neon")]
3944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3946#[cfg_attr(
3947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3948    assert_instr(bsl)
3949)]
3950#[cfg_attr(
3951    not(target_arch = "arm"),
3952    stable(feature = "neon_intrinsics", since = "1.59.0")
3953)]
3954#[cfg_attr(
3955    target_arch = "arm",
3956    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3957)]
3958pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
3959    let not = int8x8_t::splat(-1);
3960    unsafe {
3961        transmute(simd_or(
3962            simd_and(a, transmute(b)),
3963            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3964        ))
3965    }
3966}
3967#[doc = "Bitwise Select."]
3968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
3969#[inline]
3970#[target_feature(enable = "neon")]
3971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3973#[cfg_attr(
3974    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3975    assert_instr(bsl)
3976)]
3977#[cfg_attr(
3978    not(target_arch = "arm"),
3979    stable(feature = "neon_intrinsics", since = "1.59.0")
3980)]
3981#[cfg_attr(
3982    target_arch = "arm",
3983    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3984)]
3985pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
3986    let not = int16x4_t::splat(-1);
3987    unsafe {
3988        transmute(simd_or(
3989            simd_and(a, transmute(b)),
3990            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3991        ))
3992    }
3993}
3994#[doc = "Bitwise Select."]
3995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
3996#[inline]
3997#[target_feature(enable = "neon")]
3998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4000#[cfg_attr(
4001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4002    assert_instr(bsl)
4003)]
4004#[cfg_attr(
4005    not(target_arch = "arm"),
4006    stable(feature = "neon_intrinsics", since = "1.59.0")
4007)]
4008#[cfg_attr(
4009    target_arch = "arm",
4010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4011)]
4012pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
4013    let not = int32x2_t::splat(-1);
4014    unsafe {
4015        transmute(simd_or(
4016            simd_and(a, transmute(b)),
4017            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4018        ))
4019    }
4020}
4021#[doc = "Bitwise Select."]
4022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
4023#[inline]
4024#[target_feature(enable = "neon")]
4025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4027#[cfg_attr(
4028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4029    assert_instr(bsl)
4030)]
4031#[cfg_attr(
4032    not(target_arch = "arm"),
4033    stable(feature = "neon_intrinsics", since = "1.59.0")
4034)]
4035#[cfg_attr(
4036    target_arch = "arm",
4037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4038)]
4039pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
4040    let not = int64x1_t::splat(-1);
4041    unsafe {
4042        transmute(simd_or(
4043            simd_and(a, transmute(b)),
4044            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4045        ))
4046    }
4047}
4048#[doc = "Bitwise Select."]
4049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
4050#[inline]
4051#[target_feature(enable = "neon")]
4052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4054#[cfg_attr(
4055    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4056    assert_instr(bsl)
4057)]
4058#[cfg_attr(
4059    not(target_arch = "arm"),
4060    stable(feature = "neon_intrinsics", since = "1.59.0")
4061)]
4062#[cfg_attr(
4063    target_arch = "arm",
4064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4065)]
4066pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
4067    let not = int8x8_t::splat(-1);
4068    unsafe {
4069        transmute(simd_or(
4070            simd_and(a, transmute(b)),
4071            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4072        ))
4073    }
4074}
4075#[doc = "Bitwise Select."]
4076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
4077#[inline]
4078#[target_feature(enable = "neon")]
4079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4081#[cfg_attr(
4082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4083    assert_instr(bsl)
4084)]
4085#[cfg_attr(
4086    not(target_arch = "arm"),
4087    stable(feature = "neon_intrinsics", since = "1.59.0")
4088)]
4089#[cfg_attr(
4090    target_arch = "arm",
4091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4092)]
4093pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4094    let not = int32x4_t::splat(-1);
4095    unsafe {
4096        transmute(simd_or(
4097            simd_and(a, transmute(b)),
4098            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4099        ))
4100    }
4101}
4102#[doc = "Bitwise Select."]
4103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
4104#[inline]
4105#[target_feature(enable = "neon")]
4106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4108#[cfg_attr(
4109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4110    assert_instr(bsl)
4111)]
4112#[cfg_attr(
4113    not(target_arch = "arm"),
4114    stable(feature = "neon_intrinsics", since = "1.59.0")
4115)]
4116#[cfg_attr(
4117    target_arch = "arm",
4118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4119)]
4120pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
4121    let not = int16x8_t::splat(-1);
4122    unsafe {
4123        transmute(simd_or(
4124            simd_and(a, transmute(b)),
4125            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4126        ))
4127    }
4128}
4129#[doc = "Bitwise Select."]
4130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
4131#[inline]
4132#[target_feature(enable = "neon")]
4133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4135#[cfg_attr(
4136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4137    assert_instr(bsl)
4138)]
4139#[cfg_attr(
4140    not(target_arch = "arm"),
4141    stable(feature = "neon_intrinsics", since = "1.59.0")
4142)]
4143#[cfg_attr(
4144    target_arch = "arm",
4145    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4146)]
4147pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
4148    let not = int8x16_t::splat(-1);
4149    unsafe {
4150        transmute(simd_or(
4151            simd_and(a, transmute(b)),
4152            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4153        ))
4154    }
4155}
4156#[doc = "Bitwise Select."]
4157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
4158#[inline]
4159#[target_feature(enable = "neon")]
4160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4162#[cfg_attr(
4163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4164    assert_instr(bsl)
4165)]
4166#[cfg_attr(
4167    not(target_arch = "arm"),
4168    stable(feature = "neon_intrinsics", since = "1.59.0")
4169)]
4170#[cfg_attr(
4171    target_arch = "arm",
4172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4173)]
4174pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
4175    let not = int16x8_t::splat(-1);
4176    unsafe {
4177        transmute(simd_or(
4178            simd_and(a, transmute(b)),
4179            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4180        ))
4181    }
4182}
4183#[doc = "Bitwise Select."]
4184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
4185#[inline]
4186#[target_feature(enable = "neon")]
4187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4189#[cfg_attr(
4190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4191    assert_instr(bsl)
4192)]
4193#[cfg_attr(
4194    not(target_arch = "arm"),
4195    stable(feature = "neon_intrinsics", since = "1.59.0")
4196)]
4197#[cfg_attr(
4198    target_arch = "arm",
4199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4200)]
4201pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
4202    let not = int32x4_t::splat(-1);
4203    unsafe {
4204        transmute(simd_or(
4205            simd_and(a, transmute(b)),
4206            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4207        ))
4208    }
4209}
4210#[doc = "Bitwise Select."]
4211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
4212#[inline]
4213#[target_feature(enable = "neon")]
4214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4216#[cfg_attr(
4217    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4218    assert_instr(bsl)
4219)]
4220#[cfg_attr(
4221    not(target_arch = "arm"),
4222    stable(feature = "neon_intrinsics", since = "1.59.0")
4223)]
4224#[cfg_attr(
4225    target_arch = "arm",
4226    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4227)]
4228pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
4229    let not = int64x2_t::splat(-1);
4230    unsafe {
4231        transmute(simd_or(
4232            simd_and(a, transmute(b)),
4233            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4234        ))
4235    }
4236}
4237#[doc = "Bitwise Select."]
4238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
4239#[inline]
4240#[target_feature(enable = "neon")]
4241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4243#[cfg_attr(
4244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4245    assert_instr(bsl)
4246)]
4247#[cfg_attr(
4248    not(target_arch = "arm"),
4249    stable(feature = "neon_intrinsics", since = "1.59.0")
4250)]
4251#[cfg_attr(
4252    target_arch = "arm",
4253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4254)]
4255pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
4256    let not = int8x16_t::splat(-1);
4257    unsafe {
4258        transmute(simd_or(
4259            simd_and(a, transmute(b)),
4260            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4261        ))
4262    }
4263}
4264#[doc = "Bitwise Select."]
4265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
4266#[inline]
4267#[target_feature(enable = "neon")]
4268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4270#[cfg_attr(
4271    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4272    assert_instr(bsl)
4273)]
4274#[cfg_attr(
4275    not(target_arch = "arm"),
4276    stable(feature = "neon_intrinsics", since = "1.59.0")
4277)]
4278#[cfg_attr(
4279    target_arch = "arm",
4280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4281)]
4282pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
4283    let not = int16x4_t::splat(-1);
4284    unsafe {
4285        transmute(simd_or(
4286            simd_and(a, b),
4287            simd_and(simd_xor(a, transmute(not)), c),
4288        ))
4289    }
4290}
4291#[doc = "Bitwise Select."]
4292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
4293#[inline]
4294#[target_feature(enable = "neon")]
4295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4297#[cfg_attr(
4298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4299    assert_instr(bsl)
4300)]
4301#[cfg_attr(
4302    not(target_arch = "arm"),
4303    stable(feature = "neon_intrinsics", since = "1.59.0")
4304)]
4305#[cfg_attr(
4306    target_arch = "arm",
4307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4308)]
4309pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
4310    let not = int32x2_t::splat(-1);
4311    unsafe {
4312        transmute(simd_or(
4313            simd_and(a, b),
4314            simd_and(simd_xor(a, transmute(not)), c),
4315        ))
4316    }
4317}
4318#[doc = "Bitwise Select."]
4319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
4320#[inline]
4321#[target_feature(enable = "neon")]
4322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4324#[cfg_attr(
4325    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4326    assert_instr(bsl)
4327)]
4328#[cfg_attr(
4329    not(target_arch = "arm"),
4330    stable(feature = "neon_intrinsics", since = "1.59.0")
4331)]
4332#[cfg_attr(
4333    target_arch = "arm",
4334    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4335)]
4336pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
4337    let not = int64x1_t::splat(-1);
4338    unsafe {
4339        transmute(simd_or(
4340            simd_and(a, b),
4341            simd_and(simd_xor(a, transmute(not)), c),
4342        ))
4343    }
4344}
4345#[doc = "Bitwise Select."]
4346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
4347#[inline]
4348#[target_feature(enable = "neon")]
4349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4351#[cfg_attr(
4352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4353    assert_instr(bsl)
4354)]
4355#[cfg_attr(
4356    not(target_arch = "arm"),
4357    stable(feature = "neon_intrinsics", since = "1.59.0")
4358)]
4359#[cfg_attr(
4360    target_arch = "arm",
4361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4362)]
4363pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
4364    let not = int8x8_t::splat(-1);
4365    unsafe {
4366        transmute(simd_or(
4367            simd_and(a, b),
4368            simd_and(simd_xor(a, transmute(not)), c),
4369        ))
4370    }
4371}
4372#[doc = "Bitwise Select."]
4373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
4374#[inline]
4375#[target_feature(enable = "neon")]
4376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4378#[cfg_attr(
4379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4380    assert_instr(bsl)
4381)]
4382#[cfg_attr(
4383    not(target_arch = "arm"),
4384    stable(feature = "neon_intrinsics", since = "1.59.0")
4385)]
4386#[cfg_attr(
4387    target_arch = "arm",
4388    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4389)]
4390pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
4391    let not = int16x8_t::splat(-1);
4392    unsafe {
4393        transmute(simd_or(
4394            simd_and(a, b),
4395            simd_and(simd_xor(a, transmute(not)), c),
4396        ))
4397    }
4398}
4399#[doc = "Bitwise Select."]
4400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
4401#[inline]
4402#[target_feature(enable = "neon")]
4403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4405#[cfg_attr(
4406    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4407    assert_instr(bsl)
4408)]
4409#[cfg_attr(
4410    not(target_arch = "arm"),
4411    stable(feature = "neon_intrinsics", since = "1.59.0")
4412)]
4413#[cfg_attr(
4414    target_arch = "arm",
4415    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4416)]
4417pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
4418    let not = int32x4_t::splat(-1);
4419    unsafe {
4420        transmute(simd_or(
4421            simd_and(a, b),
4422            simd_and(simd_xor(a, transmute(not)), c),
4423        ))
4424    }
4425}
4426#[doc = "Bitwise Select."]
4427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
4428#[inline]
4429#[target_feature(enable = "neon")]
4430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4432#[cfg_attr(
4433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4434    assert_instr(bsl)
4435)]
4436#[cfg_attr(
4437    not(target_arch = "arm"),
4438    stable(feature = "neon_intrinsics", since = "1.59.0")
4439)]
4440#[cfg_attr(
4441    target_arch = "arm",
4442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4443)]
4444pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
4445    let not = int64x2_t::splat(-1);
4446    unsafe {
4447        transmute(simd_or(
4448            simd_and(a, b),
4449            simd_and(simd_xor(a, transmute(not)), c),
4450        ))
4451    }
4452}
4453#[doc = "Bitwise Select."]
4454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
4455#[inline]
4456#[target_feature(enable = "neon")]
4457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4459#[cfg_attr(
4460    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4461    assert_instr(bsl)
4462)]
4463#[cfg_attr(
4464    not(target_arch = "arm"),
4465    stable(feature = "neon_intrinsics", since = "1.59.0")
4466)]
4467#[cfg_attr(
4468    target_arch = "arm",
4469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4470)]
4471pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
4472    let not = int8x16_t::splat(-1);
4473    unsafe {
4474        transmute(simd_or(
4475            simd_and(a, b),
4476            simd_and(simd_xor(a, transmute(not)), c),
4477        ))
4478    }
4479}
4480#[doc = "Floating-point absolute compare greater than or equal"]
4481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
4482#[inline]
4483#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4485#[cfg_attr(
4486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4487    assert_instr(facge)
4488)]
4489#[target_feature(enable = "neon,fp16")]
4490#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4491pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4492    unsafe extern "unadjusted" {
4493        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")]
4494        #[cfg_attr(
4495            any(target_arch = "aarch64", target_arch = "arm64ec"),
4496            link_name = "llvm.aarch64.neon.facge.v4i16.v4f16"
4497        )]
4498        fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4499    }
4500    unsafe { _vcage_f16(a, b) }
4501}
4502#[doc = "Floating-point absolute compare greater than or equal"]
4503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
4504#[inline]
4505#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4506#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4507#[cfg_attr(
4508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4509    assert_instr(facge)
4510)]
4511#[target_feature(enable = "neon,fp16")]
4512#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4513pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4514    unsafe extern "unadjusted" {
4515        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")]
4516        #[cfg_attr(
4517            any(target_arch = "aarch64", target_arch = "arm64ec"),
4518            link_name = "llvm.aarch64.neon.facge.v8i16.v8f16"
4519        )]
4520        fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4521    }
4522    unsafe { _vcageq_f16(a, b) }
4523}
4524#[doc = "Floating-point absolute compare greater than or equal"]
4525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
4526#[inline]
4527#[target_feature(enable = "neon")]
4528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4530#[cfg_attr(
4531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4532    assert_instr(facge)
4533)]
4534#[cfg_attr(
4535    not(target_arch = "arm"),
4536    stable(feature = "neon_intrinsics", since = "1.59.0")
4537)]
4538#[cfg_attr(
4539    target_arch = "arm",
4540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4541)]
4542pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4543    unsafe extern "unadjusted" {
4544        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")]
4545        #[cfg_attr(
4546            any(target_arch = "aarch64", target_arch = "arm64ec"),
4547            link_name = "llvm.aarch64.neon.facge.v2i32.v2f32"
4548        )]
4549        fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4550    }
4551    unsafe { _vcage_f32(a, b) }
4552}
4553#[doc = "Floating-point absolute compare greater than or equal"]
4554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
4555#[inline]
4556#[target_feature(enable = "neon")]
4557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4558#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4559#[cfg_attr(
4560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4561    assert_instr(facge)
4562)]
4563#[cfg_attr(
4564    not(target_arch = "arm"),
4565    stable(feature = "neon_intrinsics", since = "1.59.0")
4566)]
4567#[cfg_attr(
4568    target_arch = "arm",
4569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4570)]
4571pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4572    unsafe extern "unadjusted" {
4573        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")]
4574        #[cfg_attr(
4575            any(target_arch = "aarch64", target_arch = "arm64ec"),
4576            link_name = "llvm.aarch64.neon.facge.v4i32.v4f32"
4577        )]
4578        fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4579    }
4580    unsafe { _vcageq_f32(a, b) }
4581}
4582#[doc = "Floating-point absolute compare greater than"]
4583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
4584#[inline]
4585#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4586#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4587#[cfg_attr(
4588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4589    assert_instr(facgt)
4590)]
4591#[target_feature(enable = "neon,fp16")]
4592#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4593pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4594    unsafe extern "unadjusted" {
4595        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")]
4596        #[cfg_attr(
4597            any(target_arch = "aarch64", target_arch = "arm64ec"),
4598            link_name = "llvm.aarch64.neon.facgt.v4i16.v4f16"
4599        )]
4600        fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4601    }
4602    unsafe { _vcagt_f16(a, b) }
4603}
4604#[doc = "Floating-point absolute compare greater than"]
4605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
4606#[inline]
4607#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4609#[cfg_attr(
4610    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4611    assert_instr(facgt)
4612)]
4613#[target_feature(enable = "neon,fp16")]
4614#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4615pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4616    unsafe extern "unadjusted" {
4617        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")]
4618        #[cfg_attr(
4619            any(target_arch = "aarch64", target_arch = "arm64ec"),
4620            link_name = "llvm.aarch64.neon.facgt.v8i16.v8f16"
4621        )]
4622        fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4623    }
4624    unsafe { _vcagtq_f16(a, b) }
4625}
4626#[doc = "Floating-point absolute compare greater than"]
4627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
4628#[inline]
4629#[target_feature(enable = "neon")]
4630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4631#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4632#[cfg_attr(
4633    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4634    assert_instr(facgt)
4635)]
4636#[cfg_attr(
4637    not(target_arch = "arm"),
4638    stable(feature = "neon_intrinsics", since = "1.59.0")
4639)]
4640#[cfg_attr(
4641    target_arch = "arm",
4642    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4643)]
4644pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4645    unsafe extern "unadjusted" {
4646        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")]
4647        #[cfg_attr(
4648            any(target_arch = "aarch64", target_arch = "arm64ec"),
4649            link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32"
4650        )]
4651        fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4652    }
4653    unsafe { _vcagt_f32(a, b) }
4654}
4655#[doc = "Floating-point absolute compare greater than"]
4656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
4657#[inline]
4658#[target_feature(enable = "neon")]
4659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4661#[cfg_attr(
4662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4663    assert_instr(facgt)
4664)]
4665#[cfg_attr(
4666    not(target_arch = "arm"),
4667    stable(feature = "neon_intrinsics", since = "1.59.0")
4668)]
4669#[cfg_attr(
4670    target_arch = "arm",
4671    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4672)]
4673pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4674    unsafe extern "unadjusted" {
4675        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")]
4676        #[cfg_attr(
4677            any(target_arch = "aarch64", target_arch = "arm64ec"),
4678            link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32"
4679        )]
4680        fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4681    }
4682    unsafe { _vcagtq_f32(a, b) }
4683}
4684#[doc = "Floating-point absolute compare less than or equal"]
4685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
4686#[inline]
4687#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4689#[cfg_attr(
4690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4691    assert_instr(facge)
4692)]
4693#[target_feature(enable = "neon,fp16")]
4694#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4695pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4696    vcage_f16(b, a)
4697}
4698#[doc = "Floating-point absolute compare less than or equal"]
4699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
4700#[inline]
4701#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4702#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4703#[cfg_attr(
4704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4705    assert_instr(facge)
4706)]
4707#[target_feature(enable = "neon,fp16")]
4708#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4709pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4710    vcageq_f16(b, a)
4711}
4712#[doc = "Floating-point absolute compare less than or equal"]
4713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
4714#[inline]
4715#[target_feature(enable = "neon")]
4716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4717#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4718#[cfg_attr(
4719    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4720    assert_instr(facge)
4721)]
4722#[cfg_attr(
4723    not(target_arch = "arm"),
4724    stable(feature = "neon_intrinsics", since = "1.59.0")
4725)]
4726#[cfg_attr(
4727    target_arch = "arm",
4728    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4729)]
4730pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4731    vcage_f32(b, a)
4732}
4733#[doc = "Floating-point absolute compare less than or equal"]
4734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
4735#[inline]
4736#[target_feature(enable = "neon")]
4737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4739#[cfg_attr(
4740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4741    assert_instr(facge)
4742)]
4743#[cfg_attr(
4744    not(target_arch = "arm"),
4745    stable(feature = "neon_intrinsics", since = "1.59.0")
4746)]
4747#[cfg_attr(
4748    target_arch = "arm",
4749    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4750)]
4751pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4752    vcageq_f32(b, a)
4753}
4754#[doc = "Floating-point absolute compare less than"]
4755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
4756#[inline]
4757#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4759#[cfg_attr(
4760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4761    assert_instr(facgt)
4762)]
4763#[target_feature(enable = "neon,fp16")]
4764#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4765pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4766    vcagt_f16(b, a)
4767}
4768#[doc = "Floating-point absolute compare less than"]
4769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
4770#[inline]
4771#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4772#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4773#[cfg_attr(
4774    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4775    assert_instr(facgt)
4776)]
4777#[target_feature(enable = "neon,fp16")]
4778#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4779pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4780    vcagtq_f16(b, a)
4781}
4782#[doc = "Floating-point absolute compare less than"]
4783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
4784#[inline]
4785#[target_feature(enable = "neon")]
4786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4788#[cfg_attr(
4789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4790    assert_instr(facgt)
4791)]
4792#[cfg_attr(
4793    not(target_arch = "arm"),
4794    stable(feature = "neon_intrinsics", since = "1.59.0")
4795)]
4796#[cfg_attr(
4797    target_arch = "arm",
4798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4799)]
4800pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4801    vcagt_f32(b, a)
4802}
4803#[doc = "Floating-point absolute compare less than"]
4804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
4805#[inline]
4806#[target_feature(enable = "neon")]
4807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4809#[cfg_attr(
4810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4811    assert_instr(facgt)
4812)]
4813#[cfg_attr(
4814    not(target_arch = "arm"),
4815    stable(feature = "neon_intrinsics", since = "1.59.0")
4816)]
4817#[cfg_attr(
4818    target_arch = "arm",
4819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4820)]
4821pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4822    vcagtq_f32(b, a)
4823}
4824#[doc = "Floating-point compare equal"]
4825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
4826#[inline]
4827#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4828#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4829#[cfg_attr(
4830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4831    assert_instr(fcmeq)
4832)]
4833#[target_feature(enable = "neon,fp16")]
4834#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4835pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4836    unsafe { simd_eq(a, b) }
4837}
4838#[doc = "Floating-point compare equal"]
4839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
4840#[inline]
4841#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4842#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4843#[cfg_attr(
4844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4845    assert_instr(fcmeq)
4846)]
4847#[target_feature(enable = "neon,fp16")]
4848#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4849pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4850    unsafe { simd_eq(a, b) }
4851}
4852#[doc = "Floating-point compare equal"]
4853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
4854#[inline]
4855#[target_feature(enable = "neon")]
4856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4857#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4858#[cfg_attr(
4859    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4860    assert_instr(fcmeq)
4861)]
4862#[cfg_attr(
4863    not(target_arch = "arm"),
4864    stable(feature = "neon_intrinsics", since = "1.59.0")
4865)]
4866#[cfg_attr(
4867    target_arch = "arm",
4868    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4869)]
4870pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4871    unsafe { simd_eq(a, b) }
4872}
4873#[doc = "Floating-point compare equal"]
4874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
4875#[inline]
4876#[target_feature(enable = "neon")]
4877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4878#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4879#[cfg_attr(
4880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4881    assert_instr(fcmeq)
4882)]
4883#[cfg_attr(
4884    not(target_arch = "arm"),
4885    stable(feature = "neon_intrinsics", since = "1.59.0")
4886)]
4887#[cfg_attr(
4888    target_arch = "arm",
4889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4890)]
4891pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4892    unsafe { simd_eq(a, b) }
4893}
4894#[doc = "Compare bitwise Equal (vector)"]
4895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
4896#[inline]
4897#[target_feature(enable = "neon")]
4898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4899#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4900#[cfg_attr(
4901    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4902    assert_instr(cmeq)
4903)]
4904#[cfg_attr(
4905    not(target_arch = "arm"),
4906    stable(feature = "neon_intrinsics", since = "1.59.0")
4907)]
4908#[cfg_attr(
4909    target_arch = "arm",
4910    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4911)]
4912pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
4913    unsafe { simd_eq(a, b) }
4914}
4915#[doc = "Compare bitwise Equal (vector)"]
4916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
4917#[inline]
4918#[target_feature(enable = "neon")]
4919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4921#[cfg_attr(
4922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4923    assert_instr(cmeq)
4924)]
4925#[cfg_attr(
4926    not(target_arch = "arm"),
4927    stable(feature = "neon_intrinsics", since = "1.59.0")
4928)]
4929#[cfg_attr(
4930    target_arch = "arm",
4931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4932)]
4933pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
4934    unsafe { simd_eq(a, b) }
4935}
4936#[doc = "Compare bitwise Equal (vector)"]
4937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
4938#[inline]
4939#[target_feature(enable = "neon")]
4940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4942#[cfg_attr(
4943    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4944    assert_instr(cmeq)
4945)]
4946#[cfg_attr(
4947    not(target_arch = "arm"),
4948    stable(feature = "neon_intrinsics", since = "1.59.0")
4949)]
4950#[cfg_attr(
4951    target_arch = "arm",
4952    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4953)]
4954pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
4955    unsafe { simd_eq(a, b) }
4956}
4957#[doc = "Compare bitwise Equal (vector)"]
4958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
4959#[inline]
4960#[target_feature(enable = "neon")]
4961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4962#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4963#[cfg_attr(
4964    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4965    assert_instr(cmeq)
4966)]
4967#[cfg_attr(
4968    not(target_arch = "arm"),
4969    stable(feature = "neon_intrinsics", since = "1.59.0")
4970)]
4971#[cfg_attr(
4972    target_arch = "arm",
4973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4974)]
4975pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
4976    unsafe { simd_eq(a, b) }
4977}
4978#[doc = "Compare bitwise Equal (vector)"]
4979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
4980#[inline]
4981#[target_feature(enable = "neon")]
4982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4983#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4984#[cfg_attr(
4985    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4986    assert_instr(cmeq)
4987)]
4988#[cfg_attr(
4989    not(target_arch = "arm"),
4990    stable(feature = "neon_intrinsics", since = "1.59.0")
4991)]
4992#[cfg_attr(
4993    target_arch = "arm",
4994    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4995)]
4996pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
4997    unsafe { simd_eq(a, b) }
4998}
4999#[doc = "Compare bitwise Equal (vector)"]
5000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
5001#[inline]
5002#[target_feature(enable = "neon")]
5003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5005#[cfg_attr(
5006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5007    assert_instr(cmeq)
5008)]
5009#[cfg_attr(
5010    not(target_arch = "arm"),
5011    stable(feature = "neon_intrinsics", since = "1.59.0")
5012)]
5013#[cfg_attr(
5014    target_arch = "arm",
5015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5016)]
5017pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5018    unsafe { simd_eq(a, b) }
5019}
5020#[doc = "Compare bitwise Equal (vector)"]
5021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
5022#[inline]
5023#[target_feature(enable = "neon")]
5024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5025#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5026#[cfg_attr(
5027    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5028    assert_instr(cmeq)
5029)]
5030#[cfg_attr(
5031    not(target_arch = "arm"),
5032    stable(feature = "neon_intrinsics", since = "1.59.0")
5033)]
5034#[cfg_attr(
5035    target_arch = "arm",
5036    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5037)]
5038pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5039    unsafe { simd_eq(a, b) }
5040}
5041#[doc = "Compare bitwise Equal (vector)"]
5042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
5043#[inline]
5044#[target_feature(enable = "neon")]
5045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5046#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5047#[cfg_attr(
5048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5049    assert_instr(cmeq)
5050)]
5051#[cfg_attr(
5052    not(target_arch = "arm"),
5053    stable(feature = "neon_intrinsics", since = "1.59.0")
5054)]
5055#[cfg_attr(
5056    target_arch = "arm",
5057    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5058)]
5059pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5060    unsafe { simd_eq(a, b) }
5061}
5062#[doc = "Compare bitwise Equal (vector)"]
5063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
5064#[inline]
5065#[target_feature(enable = "neon")]
5066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5067#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5068#[cfg_attr(
5069    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5070    assert_instr(cmeq)
5071)]
5072#[cfg_attr(
5073    not(target_arch = "arm"),
5074    stable(feature = "neon_intrinsics", since = "1.59.0")
5075)]
5076#[cfg_attr(
5077    target_arch = "arm",
5078    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5079)]
5080pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5081    unsafe { simd_eq(a, b) }
5082}
5083#[doc = "Compare bitwise Equal (vector)"]
5084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
5085#[inline]
5086#[target_feature(enable = "neon")]
5087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5088#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5089#[cfg_attr(
5090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5091    assert_instr(cmeq)
5092)]
5093#[cfg_attr(
5094    not(target_arch = "arm"),
5095    stable(feature = "neon_intrinsics", since = "1.59.0")
5096)]
5097#[cfg_attr(
5098    target_arch = "arm",
5099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5100)]
5101pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5102    unsafe { simd_eq(a, b) }
5103}
5104#[doc = "Compare bitwise Equal (vector)"]
5105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
5106#[inline]
5107#[target_feature(enable = "neon")]
5108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5110#[cfg_attr(
5111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5112    assert_instr(cmeq)
5113)]
5114#[cfg_attr(
5115    not(target_arch = "arm"),
5116    stable(feature = "neon_intrinsics", since = "1.59.0")
5117)]
5118#[cfg_attr(
5119    target_arch = "arm",
5120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5121)]
5122pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5123    unsafe { simd_eq(a, b) }
5124}
5125#[doc = "Compare bitwise Equal (vector)"]
5126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
5127#[inline]
5128#[target_feature(enable = "neon")]
5129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5130#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5131#[cfg_attr(
5132    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5133    assert_instr(cmeq)
5134)]
5135#[cfg_attr(
5136    not(target_arch = "arm"),
5137    stable(feature = "neon_intrinsics", since = "1.59.0")
5138)]
5139#[cfg_attr(
5140    target_arch = "arm",
5141    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5142)]
5143pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5144    unsafe { simd_eq(a, b) }
5145}
5146#[doc = "Compare bitwise Equal (vector)"]
5147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
5148#[inline]
5149#[target_feature(enable = "neon")]
5150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5152#[cfg_attr(
5153    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5154    assert_instr(cmeq)
5155)]
5156#[cfg_attr(
5157    not(target_arch = "arm"),
5158    stable(feature = "neon_intrinsics", since = "1.59.0")
5159)]
5160#[cfg_attr(
5161    target_arch = "arm",
5162    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5163)]
5164pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
5165    unsafe { simd_eq(a, b) }
5166}
5167#[doc = "Compare bitwise Equal (vector)"]
5168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
5169#[inline]
5170#[target_feature(enable = "neon")]
5171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5172#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5173#[cfg_attr(
5174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5175    assert_instr(cmeq)
5176)]
5177#[cfg_attr(
5178    not(target_arch = "arm"),
5179    stable(feature = "neon_intrinsics", since = "1.59.0")
5180)]
5181#[cfg_attr(
5182    target_arch = "arm",
5183    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5184)]
5185pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
5186    unsafe { simd_eq(a, b) }
5187}
5188#[doc = "Floating-point compare greater than or equal"]
5189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
5190#[inline]
5191#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5193#[cfg_attr(
5194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5195    assert_instr(fcmge)
5196)]
5197#[target_feature(enable = "neon,fp16")]
5198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5199pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5200    unsafe { simd_ge(a, b) }
5201}
5202#[doc = "Floating-point compare greater than or equal"]
5203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
5204#[inline]
5205#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5206#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5207#[cfg_attr(
5208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5209    assert_instr(fcmge)
5210)]
5211#[target_feature(enable = "neon,fp16")]
5212#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5213pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5214    unsafe { simd_ge(a, b) }
5215}
5216#[doc = "Floating-point compare greater than or equal"]
5217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
5218#[inline]
5219#[target_feature(enable = "neon")]
5220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5221#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5222#[cfg_attr(
5223    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5224    assert_instr(fcmge)
5225)]
5226#[cfg_attr(
5227    not(target_arch = "arm"),
5228    stable(feature = "neon_intrinsics", since = "1.59.0")
5229)]
5230#[cfg_attr(
5231    target_arch = "arm",
5232    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5233)]
5234pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5235    unsafe { simd_ge(a, b) }
5236}
5237#[doc = "Floating-point compare greater than or equal"]
5238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
5239#[inline]
5240#[target_feature(enable = "neon")]
5241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5243#[cfg_attr(
5244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5245    assert_instr(fcmge)
5246)]
5247#[cfg_attr(
5248    not(target_arch = "arm"),
5249    stable(feature = "neon_intrinsics", since = "1.59.0")
5250)]
5251#[cfg_attr(
5252    target_arch = "arm",
5253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5254)]
5255pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5256    unsafe { simd_ge(a, b) }
5257}
5258#[doc = "Compare signed greater than or equal"]
5259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
5260#[inline]
5261#[target_feature(enable = "neon")]
5262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5263#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5264#[cfg_attr(
5265    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5266    assert_instr(cmge)
5267)]
5268#[cfg_attr(
5269    not(target_arch = "arm"),
5270    stable(feature = "neon_intrinsics", since = "1.59.0")
5271)]
5272#[cfg_attr(
5273    target_arch = "arm",
5274    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5275)]
5276pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5277    unsafe { simd_ge(a, b) }
5278}
5279#[doc = "Compare signed greater than or equal"]
5280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
5281#[inline]
5282#[target_feature(enable = "neon")]
5283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5284#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5285#[cfg_attr(
5286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5287    assert_instr(cmge)
5288)]
5289#[cfg_attr(
5290    not(target_arch = "arm"),
5291    stable(feature = "neon_intrinsics", since = "1.59.0")
5292)]
5293#[cfg_attr(
5294    target_arch = "arm",
5295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5296)]
5297pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5298    unsafe { simd_ge(a, b) }
5299}
5300#[doc = "Compare signed greater than or equal"]
5301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
5302#[inline]
5303#[target_feature(enable = "neon")]
5304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5305#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5306#[cfg_attr(
5307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5308    assert_instr(cmge)
5309)]
5310#[cfg_attr(
5311    not(target_arch = "arm"),
5312    stable(feature = "neon_intrinsics", since = "1.59.0")
5313)]
5314#[cfg_attr(
5315    target_arch = "arm",
5316    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5317)]
5318pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5319    unsafe { simd_ge(a, b) }
5320}
5321#[doc = "Compare signed greater than or equal"]
5322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
5323#[inline]
5324#[target_feature(enable = "neon")]
5325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5327#[cfg_attr(
5328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5329    assert_instr(cmge)
5330)]
5331#[cfg_attr(
5332    not(target_arch = "arm"),
5333    stable(feature = "neon_intrinsics", since = "1.59.0")
5334)]
5335#[cfg_attr(
5336    target_arch = "arm",
5337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5338)]
5339pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5340    unsafe { simd_ge(a, b) }
5341}
5342#[doc = "Compare signed greater than or equal"]
5343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
5344#[inline]
5345#[target_feature(enable = "neon")]
5346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5347#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5348#[cfg_attr(
5349    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5350    assert_instr(cmge)
5351)]
5352#[cfg_attr(
5353    not(target_arch = "arm"),
5354    stable(feature = "neon_intrinsics", since = "1.59.0")
5355)]
5356#[cfg_attr(
5357    target_arch = "arm",
5358    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5359)]
5360pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5361    unsafe { simd_ge(a, b) }
5362}
5363#[doc = "Compare signed greater than or equal"]
5364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
5365#[inline]
5366#[target_feature(enable = "neon")]
5367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5368#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5369#[cfg_attr(
5370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5371    assert_instr(cmge)
5372)]
5373#[cfg_attr(
5374    not(target_arch = "arm"),
5375    stable(feature = "neon_intrinsics", since = "1.59.0")
5376)]
5377#[cfg_attr(
5378    target_arch = "arm",
5379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5380)]
5381pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5382    unsafe { simd_ge(a, b) }
5383}
5384#[doc = "Compare unsigned greater than or equal"]
5385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
5386#[inline]
5387#[target_feature(enable = "neon")]
5388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5389#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5390#[cfg_attr(
5391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5392    assert_instr(cmhs)
5393)]
5394#[cfg_attr(
5395    not(target_arch = "arm"),
5396    stable(feature = "neon_intrinsics", since = "1.59.0")
5397)]
5398#[cfg_attr(
5399    target_arch = "arm",
5400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5401)]
5402pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5403    unsafe { simd_ge(a, b) }
5404}
5405#[doc = "Compare unsigned greater than or equal"]
5406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
5407#[inline]
5408#[target_feature(enable = "neon")]
5409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5410#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5411#[cfg_attr(
5412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5413    assert_instr(cmhs)
5414)]
5415#[cfg_attr(
5416    not(target_arch = "arm"),
5417    stable(feature = "neon_intrinsics", since = "1.59.0")
5418)]
5419#[cfg_attr(
5420    target_arch = "arm",
5421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5422)]
5423pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5424    unsafe { simd_ge(a, b) }
5425}
5426#[doc = "Compare unsigned greater than or equal"]
5427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
5428#[inline]
5429#[target_feature(enable = "neon")]
5430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5431#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5432#[cfg_attr(
5433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5434    assert_instr(cmhs)
5435)]
5436#[cfg_attr(
5437    not(target_arch = "arm"),
5438    stable(feature = "neon_intrinsics", since = "1.59.0")
5439)]
5440#[cfg_attr(
5441    target_arch = "arm",
5442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5443)]
5444pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5445    unsafe { simd_ge(a, b) }
5446}
5447#[doc = "Compare unsigned greater than or equal"]
5448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
5449#[inline]
5450#[target_feature(enable = "neon")]
5451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5453#[cfg_attr(
5454    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5455    assert_instr(cmhs)
5456)]
5457#[cfg_attr(
5458    not(target_arch = "arm"),
5459    stable(feature = "neon_intrinsics", since = "1.59.0")
5460)]
5461#[cfg_attr(
5462    target_arch = "arm",
5463    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5464)]
5465pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5466    unsafe { simd_ge(a, b) }
5467}
5468#[doc = "Compare unsigned greater than or equal"]
5469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
5470#[inline]
5471#[target_feature(enable = "neon")]
5472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5473#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5474#[cfg_attr(
5475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5476    assert_instr(cmhs)
5477)]
5478#[cfg_attr(
5479    not(target_arch = "arm"),
5480    stable(feature = "neon_intrinsics", since = "1.59.0")
5481)]
5482#[cfg_attr(
5483    target_arch = "arm",
5484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5485)]
5486pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5487    unsafe { simd_ge(a, b) }
5488}
5489#[doc = "Compare unsigned greater than or equal"]
5490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
5491#[inline]
5492#[target_feature(enable = "neon")]
5493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5494#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5495#[cfg_attr(
5496    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5497    assert_instr(cmhs)
5498)]
5499#[cfg_attr(
5500    not(target_arch = "arm"),
5501    stable(feature = "neon_intrinsics", since = "1.59.0")
5502)]
5503#[cfg_attr(
5504    target_arch = "arm",
5505    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5506)]
5507pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5508    unsafe { simd_ge(a, b) }
5509}
5510#[doc = "Floating-point compare greater than or equal to zero"]
5511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
5512#[inline]
5513#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5515#[cfg_attr(
5516    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5517    assert_instr(fcmge)
5518)]
5519#[target_feature(enable = "neon,fp16")]
5520#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5521pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
5522    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5523    unsafe { simd_ge(a, transmute(b)) }
5524}
5525#[doc = "Floating-point compare greater than or equal to zero"]
5526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
5527#[inline]
5528#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5530#[cfg_attr(
5531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5532    assert_instr(fcmge)
5533)]
5534#[target_feature(enable = "neon,fp16")]
5535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5536pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
5537    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5538    unsafe { simd_ge(a, transmute(b)) }
5539}
5540#[doc = "Floating-point compare greater than"]
5541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
5542#[inline]
5543#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5544#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5545#[cfg_attr(
5546    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5547    assert_instr(fcmgt)
5548)]
5549#[target_feature(enable = "neon,fp16")]
5550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5551pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5552    unsafe { simd_gt(a, b) }
5553}
5554#[doc = "Floating-point compare greater than"]
5555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
5556#[inline]
5557#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5558#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5559#[cfg_attr(
5560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5561    assert_instr(fcmgt)
5562)]
5563#[target_feature(enable = "neon,fp16")]
5564#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5565pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5566    unsafe { simd_gt(a, b) }
5567}
5568#[doc = "Floating-point compare greater than"]
5569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
5570#[inline]
5571#[target_feature(enable = "neon")]
5572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5574#[cfg_attr(
5575    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5576    assert_instr(fcmgt)
5577)]
5578#[cfg_attr(
5579    not(target_arch = "arm"),
5580    stable(feature = "neon_intrinsics", since = "1.59.0")
5581)]
5582#[cfg_attr(
5583    target_arch = "arm",
5584    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5585)]
5586pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5587    unsafe { simd_gt(a, b) }
5588}
5589#[doc = "Floating-point compare greater than"]
5590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
5591#[inline]
5592#[target_feature(enable = "neon")]
5593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5595#[cfg_attr(
5596    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5597    assert_instr(fcmgt)
5598)]
5599#[cfg_attr(
5600    not(target_arch = "arm"),
5601    stable(feature = "neon_intrinsics", since = "1.59.0")
5602)]
5603#[cfg_attr(
5604    target_arch = "arm",
5605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5606)]
5607pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5608    unsafe { simd_gt(a, b) }
5609}
5610#[doc = "Compare signed greater than"]
5611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
5612#[inline]
5613#[target_feature(enable = "neon")]
5614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5615#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5616#[cfg_attr(
5617    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5618    assert_instr(cmgt)
5619)]
5620#[cfg_attr(
5621    not(target_arch = "arm"),
5622    stable(feature = "neon_intrinsics", since = "1.59.0")
5623)]
5624#[cfg_attr(
5625    target_arch = "arm",
5626    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5627)]
5628pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5629    unsafe { simd_gt(a, b) }
5630}
5631#[doc = "Compare signed greater than"]
5632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
5633#[inline]
5634#[target_feature(enable = "neon")]
5635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5636#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5637#[cfg_attr(
5638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5639    assert_instr(cmgt)
5640)]
5641#[cfg_attr(
5642    not(target_arch = "arm"),
5643    stable(feature = "neon_intrinsics", since = "1.59.0")
5644)]
5645#[cfg_attr(
5646    target_arch = "arm",
5647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5648)]
5649pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5650    unsafe { simd_gt(a, b) }
5651}
5652#[doc = "Compare signed greater than"]
5653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
5654#[inline]
5655#[target_feature(enable = "neon")]
5656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5658#[cfg_attr(
5659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5660    assert_instr(cmgt)
5661)]
5662#[cfg_attr(
5663    not(target_arch = "arm"),
5664    stable(feature = "neon_intrinsics", since = "1.59.0")
5665)]
5666#[cfg_attr(
5667    target_arch = "arm",
5668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5669)]
5670pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5671    unsafe { simd_gt(a, b) }
5672}
5673#[doc = "Compare signed greater than"]
5674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
5675#[inline]
5676#[target_feature(enable = "neon")]
5677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5679#[cfg_attr(
5680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5681    assert_instr(cmgt)
5682)]
5683#[cfg_attr(
5684    not(target_arch = "arm"),
5685    stable(feature = "neon_intrinsics", since = "1.59.0")
5686)]
5687#[cfg_attr(
5688    target_arch = "arm",
5689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5690)]
5691pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5692    unsafe { simd_gt(a, b) }
5693}
5694#[doc = "Compare signed greater than"]
5695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
5696#[inline]
5697#[target_feature(enable = "neon")]
5698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5700#[cfg_attr(
5701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5702    assert_instr(cmgt)
5703)]
5704#[cfg_attr(
5705    not(target_arch = "arm"),
5706    stable(feature = "neon_intrinsics", since = "1.59.0")
5707)]
5708#[cfg_attr(
5709    target_arch = "arm",
5710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5711)]
5712pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5713    unsafe { simd_gt(a, b) }
5714}
5715#[doc = "Compare signed greater than"]
5716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
5717#[inline]
5718#[target_feature(enable = "neon")]
5719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5721#[cfg_attr(
5722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5723    assert_instr(cmgt)
5724)]
5725#[cfg_attr(
5726    not(target_arch = "arm"),
5727    stable(feature = "neon_intrinsics", since = "1.59.0")
5728)]
5729#[cfg_attr(
5730    target_arch = "arm",
5731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5732)]
5733pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5734    unsafe { simd_gt(a, b) }
5735}
5736#[doc = "Compare unsigned greater than"]
5737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
5738#[inline]
5739#[target_feature(enable = "neon")]
5740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5742#[cfg_attr(
5743    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5744    assert_instr(cmhi)
5745)]
5746#[cfg_attr(
5747    not(target_arch = "arm"),
5748    stable(feature = "neon_intrinsics", since = "1.59.0")
5749)]
5750#[cfg_attr(
5751    target_arch = "arm",
5752    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5753)]
5754pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5755    unsafe { simd_gt(a, b) }
5756}
5757#[doc = "Compare unsigned greater than"]
5758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
5759#[inline]
5760#[target_feature(enable = "neon")]
5761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5762#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5763#[cfg_attr(
5764    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5765    assert_instr(cmhi)
5766)]
5767#[cfg_attr(
5768    not(target_arch = "arm"),
5769    stable(feature = "neon_intrinsics", since = "1.59.0")
5770)]
5771#[cfg_attr(
5772    target_arch = "arm",
5773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5774)]
5775pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5776    unsafe { simd_gt(a, b) }
5777}
5778#[doc = "Compare unsigned greater than"]
5779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
5780#[inline]
5781#[target_feature(enable = "neon")]
5782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5783#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5784#[cfg_attr(
5785    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5786    assert_instr(cmhi)
5787)]
5788#[cfg_attr(
5789    not(target_arch = "arm"),
5790    stable(feature = "neon_intrinsics", since = "1.59.0")
5791)]
5792#[cfg_attr(
5793    target_arch = "arm",
5794    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5795)]
5796pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5797    unsafe { simd_gt(a, b) }
5798}
5799#[doc = "Compare unsigned greater than"]
5800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
5801#[inline]
5802#[target_feature(enable = "neon")]
5803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5805#[cfg_attr(
5806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5807    assert_instr(cmhi)
5808)]
5809#[cfg_attr(
5810    not(target_arch = "arm"),
5811    stable(feature = "neon_intrinsics", since = "1.59.0")
5812)]
5813#[cfg_attr(
5814    target_arch = "arm",
5815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5816)]
5817pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5818    unsafe { simd_gt(a, b) }
5819}
5820#[doc = "Compare unsigned greater than"]
5821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
5822#[inline]
5823#[target_feature(enable = "neon")]
5824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5826#[cfg_attr(
5827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5828    assert_instr(cmhi)
5829)]
5830#[cfg_attr(
5831    not(target_arch = "arm"),
5832    stable(feature = "neon_intrinsics", since = "1.59.0")
5833)]
5834#[cfg_attr(
5835    target_arch = "arm",
5836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5837)]
5838pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5839    unsafe { simd_gt(a, b) }
5840}
5841#[doc = "Compare unsigned greater than"]
5842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
5843#[inline]
5844#[target_feature(enable = "neon")]
5845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5847#[cfg_attr(
5848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5849    assert_instr(cmhi)
5850)]
5851#[cfg_attr(
5852    not(target_arch = "arm"),
5853    stable(feature = "neon_intrinsics", since = "1.59.0")
5854)]
5855#[cfg_attr(
5856    target_arch = "arm",
5857    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5858)]
5859pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5860    unsafe { simd_gt(a, b) }
5861}
5862#[doc = "Floating-point compare greater than zero"]
5863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
5864#[inline]
5865#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5866#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5867#[cfg_attr(
5868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5869    assert_instr(fcmgt)
5870)]
5871#[target_feature(enable = "neon,fp16")]
5872#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5873pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
5874    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5875    unsafe { simd_gt(a, transmute(b)) }
5876}
5877#[doc = "Floating-point compare greater than zero"]
5878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
5879#[inline]
5880#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5882#[cfg_attr(
5883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5884    assert_instr(fcmgt)
5885)]
5886#[target_feature(enable = "neon,fp16")]
5887#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5888pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
5889    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5890    unsafe { simd_gt(a, transmute(b)) }
5891}
5892#[doc = "Floating-point compare less than or equal"]
5893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
5894#[inline]
5895#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5896#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5897#[cfg_attr(
5898    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5899    assert_instr(fcmge)
5900)]
5901#[target_feature(enable = "neon,fp16")]
5902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5903pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5904    unsafe { simd_le(a, b) }
5905}
5906#[doc = "Floating-point compare less than or equal"]
5907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
5908#[inline]
5909#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5910#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5911#[cfg_attr(
5912    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5913    assert_instr(fcmge)
5914)]
5915#[target_feature(enable = "neon,fp16")]
5916#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5917pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5918    unsafe { simd_le(a, b) }
5919}
5920#[doc = "Floating-point compare less than or equal"]
5921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
5922#[inline]
5923#[target_feature(enable = "neon")]
5924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5925#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5926#[cfg_attr(
5927    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5928    assert_instr(fcmge)
5929)]
5930#[cfg_attr(
5931    not(target_arch = "arm"),
5932    stable(feature = "neon_intrinsics", since = "1.59.0")
5933)]
5934#[cfg_attr(
5935    target_arch = "arm",
5936    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5937)]
5938pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5939    unsafe { simd_le(a, b) }
5940}
5941#[doc = "Floating-point compare less than or equal"]
5942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
5943#[inline]
5944#[target_feature(enable = "neon")]
5945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5946#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5947#[cfg_attr(
5948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5949    assert_instr(fcmge)
5950)]
5951#[cfg_attr(
5952    not(target_arch = "arm"),
5953    stable(feature = "neon_intrinsics", since = "1.59.0")
5954)]
5955#[cfg_attr(
5956    target_arch = "arm",
5957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5958)]
5959pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5960    unsafe { simd_le(a, b) }
5961}
5962#[doc = "Compare signed less than or equal"]
5963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
5964#[inline]
5965#[target_feature(enable = "neon")]
5966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5967#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5968#[cfg_attr(
5969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5970    assert_instr(cmge)
5971)]
5972#[cfg_attr(
5973    not(target_arch = "arm"),
5974    stable(feature = "neon_intrinsics", since = "1.59.0")
5975)]
5976#[cfg_attr(
5977    target_arch = "arm",
5978    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5979)]
5980pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5981    unsafe { simd_le(a, b) }
5982}
5983#[doc = "Compare signed less than or equal"]
5984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
5985#[inline]
5986#[target_feature(enable = "neon")]
5987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5989#[cfg_attr(
5990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5991    assert_instr(cmge)
5992)]
5993#[cfg_attr(
5994    not(target_arch = "arm"),
5995    stable(feature = "neon_intrinsics", since = "1.59.0")
5996)]
5997#[cfg_attr(
5998    target_arch = "arm",
5999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6000)]
6001pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6002    unsafe { simd_le(a, b) }
6003}
6004#[doc = "Compare signed less than or equal"]
6005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
6006#[inline]
6007#[target_feature(enable = "neon")]
6008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6010#[cfg_attr(
6011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6012    assert_instr(cmge)
6013)]
6014#[cfg_attr(
6015    not(target_arch = "arm"),
6016    stable(feature = "neon_intrinsics", since = "1.59.0")
6017)]
6018#[cfg_attr(
6019    target_arch = "arm",
6020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6021)]
6022pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6023    unsafe { simd_le(a, b) }
6024}
6025#[doc = "Compare signed less than or equal"]
6026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
6027#[inline]
6028#[target_feature(enable = "neon")]
6029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6030#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6031#[cfg_attr(
6032    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6033    assert_instr(cmge)
6034)]
6035#[cfg_attr(
6036    not(target_arch = "arm"),
6037    stable(feature = "neon_intrinsics", since = "1.59.0")
6038)]
6039#[cfg_attr(
6040    target_arch = "arm",
6041    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6042)]
6043pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6044    unsafe { simd_le(a, b) }
6045}
6046#[doc = "Compare signed less than or equal"]
6047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
6048#[inline]
6049#[target_feature(enable = "neon")]
6050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6051#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6052#[cfg_attr(
6053    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6054    assert_instr(cmge)
6055)]
6056#[cfg_attr(
6057    not(target_arch = "arm"),
6058    stable(feature = "neon_intrinsics", since = "1.59.0")
6059)]
6060#[cfg_attr(
6061    target_arch = "arm",
6062    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6063)]
6064pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6065    unsafe { simd_le(a, b) }
6066}
6067#[doc = "Compare signed less than or equal"]
6068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
6069#[inline]
6070#[target_feature(enable = "neon")]
6071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6073#[cfg_attr(
6074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6075    assert_instr(cmge)
6076)]
6077#[cfg_attr(
6078    not(target_arch = "arm"),
6079    stable(feature = "neon_intrinsics", since = "1.59.0")
6080)]
6081#[cfg_attr(
6082    target_arch = "arm",
6083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6084)]
6085pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6086    unsafe { simd_le(a, b) }
6087}
6088#[doc = "Compare unsigned less than or equal"]
6089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
6090#[inline]
6091#[target_feature(enable = "neon")]
6092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6093#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6094#[cfg_attr(
6095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6096    assert_instr(cmhs)
6097)]
6098#[cfg_attr(
6099    not(target_arch = "arm"),
6100    stable(feature = "neon_intrinsics", since = "1.59.0")
6101)]
6102#[cfg_attr(
6103    target_arch = "arm",
6104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6105)]
6106pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6107    unsafe { simd_le(a, b) }
6108}
6109#[doc = "Compare unsigned less than or equal"]
6110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
6111#[inline]
6112#[target_feature(enable = "neon")]
6113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6114#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6115#[cfg_attr(
6116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6117    assert_instr(cmhs)
6118)]
6119#[cfg_attr(
6120    not(target_arch = "arm"),
6121    stable(feature = "neon_intrinsics", since = "1.59.0")
6122)]
6123#[cfg_attr(
6124    target_arch = "arm",
6125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6126)]
6127pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6128    unsafe { simd_le(a, b) }
6129}
6130#[doc = "Compare unsigned less than or equal"]
6131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
6132#[inline]
6133#[target_feature(enable = "neon")]
6134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6136#[cfg_attr(
6137    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6138    assert_instr(cmhs)
6139)]
6140#[cfg_attr(
6141    not(target_arch = "arm"),
6142    stable(feature = "neon_intrinsics", since = "1.59.0")
6143)]
6144#[cfg_attr(
6145    target_arch = "arm",
6146    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6147)]
6148pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6149    unsafe { simd_le(a, b) }
6150}
6151#[doc = "Compare unsigned less than or equal"]
6152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
6153#[inline]
6154#[target_feature(enable = "neon")]
6155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6157#[cfg_attr(
6158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6159    assert_instr(cmhs)
6160)]
6161#[cfg_attr(
6162    not(target_arch = "arm"),
6163    stable(feature = "neon_intrinsics", since = "1.59.0")
6164)]
6165#[cfg_attr(
6166    target_arch = "arm",
6167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6168)]
6169pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6170    unsafe { simd_le(a, b) }
6171}
6172#[doc = "Compare unsigned less than or equal"]
6173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
6174#[inline]
6175#[target_feature(enable = "neon")]
6176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6177#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6178#[cfg_attr(
6179    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6180    assert_instr(cmhs)
6181)]
6182#[cfg_attr(
6183    not(target_arch = "arm"),
6184    stable(feature = "neon_intrinsics", since = "1.59.0")
6185)]
6186#[cfg_attr(
6187    target_arch = "arm",
6188    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6189)]
6190pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6191    unsafe { simd_le(a, b) }
6192}
6193#[doc = "Compare unsigned less than or equal"]
6194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
6195#[inline]
6196#[target_feature(enable = "neon")]
6197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6199#[cfg_attr(
6200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6201    assert_instr(cmhs)
6202)]
6203#[cfg_attr(
6204    not(target_arch = "arm"),
6205    stable(feature = "neon_intrinsics", since = "1.59.0")
6206)]
6207#[cfg_attr(
6208    target_arch = "arm",
6209    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6210)]
6211pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6212    unsafe { simd_le(a, b) }
6213}
6214#[doc = "Floating-point compare less than or equal to zero"]
6215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
6216#[inline]
6217#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6219#[cfg_attr(
6220    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6221    assert_instr(fcmle)
6222)]
6223#[target_feature(enable = "neon,fp16")]
6224#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6225pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
6226    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6227    unsafe { simd_le(a, transmute(b)) }
6228}
6229#[doc = "Floating-point compare less than or equal to zero"]
6230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
6231#[inline]
6232#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6233#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6234#[cfg_attr(
6235    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6236    assert_instr(fcmle)
6237)]
6238#[target_feature(enable = "neon,fp16")]
6239#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6240pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
6241    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6242    unsafe { simd_le(a, transmute(b)) }
6243}
6244#[doc = "Count leading sign bits"]
6245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
6246#[inline]
6247#[target_feature(enable = "neon")]
6248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6249#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6250#[cfg_attr(
6251    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6252    assert_instr(cls)
6253)]
6254#[cfg_attr(
6255    not(target_arch = "arm"),
6256    stable(feature = "neon_intrinsics", since = "1.59.0")
6257)]
6258#[cfg_attr(
6259    target_arch = "arm",
6260    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6261)]
6262pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
6263    unsafe extern "unadjusted" {
6264        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")]
6265        #[cfg_attr(
6266            any(target_arch = "aarch64", target_arch = "arm64ec"),
6267            link_name = "llvm.aarch64.neon.cls.v8i8"
6268        )]
6269        fn _vcls_s8(a: int8x8_t) -> int8x8_t;
6270    }
6271    unsafe { _vcls_s8(a) }
6272}
6273#[doc = "Count leading sign bits"]
6274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
6275#[inline]
6276#[target_feature(enable = "neon")]
6277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6278#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6279#[cfg_attr(
6280    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6281    assert_instr(cls)
6282)]
6283#[cfg_attr(
6284    not(target_arch = "arm"),
6285    stable(feature = "neon_intrinsics", since = "1.59.0")
6286)]
6287#[cfg_attr(
6288    target_arch = "arm",
6289    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6290)]
6291pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
6292    unsafe extern "unadjusted" {
6293        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")]
6294        #[cfg_attr(
6295            any(target_arch = "aarch64", target_arch = "arm64ec"),
6296            link_name = "llvm.aarch64.neon.cls.v16i8"
6297        )]
6298        fn _vclsq_s8(a: int8x16_t) -> int8x16_t;
6299    }
6300    unsafe { _vclsq_s8(a) }
6301}
6302#[doc = "Count leading sign bits"]
6303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
6304#[inline]
6305#[target_feature(enable = "neon")]
6306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6307#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6308#[cfg_attr(
6309    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6310    assert_instr(cls)
6311)]
6312#[cfg_attr(
6313    not(target_arch = "arm"),
6314    stable(feature = "neon_intrinsics", since = "1.59.0")
6315)]
6316#[cfg_attr(
6317    target_arch = "arm",
6318    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6319)]
6320pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
6321    unsafe extern "unadjusted" {
6322        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")]
6323        #[cfg_attr(
6324            any(target_arch = "aarch64", target_arch = "arm64ec"),
6325            link_name = "llvm.aarch64.neon.cls.v4i16"
6326        )]
6327        fn _vcls_s16(a: int16x4_t) -> int16x4_t;
6328    }
6329    unsafe { _vcls_s16(a) }
6330}
6331#[doc = "Count leading sign bits"]
6332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
6333#[inline]
6334#[target_feature(enable = "neon")]
6335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6336#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6337#[cfg_attr(
6338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6339    assert_instr(cls)
6340)]
6341#[cfg_attr(
6342    not(target_arch = "arm"),
6343    stable(feature = "neon_intrinsics", since = "1.59.0")
6344)]
6345#[cfg_attr(
6346    target_arch = "arm",
6347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6348)]
6349pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
6350    unsafe extern "unadjusted" {
6351        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")]
6352        #[cfg_attr(
6353            any(target_arch = "aarch64", target_arch = "arm64ec"),
6354            link_name = "llvm.aarch64.neon.cls.v8i16"
6355        )]
6356        fn _vclsq_s16(a: int16x8_t) -> int16x8_t;
6357    }
6358    unsafe { _vclsq_s16(a) }
6359}
6360#[doc = "Count leading sign bits"]
6361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
6362#[inline]
6363#[target_feature(enable = "neon")]
6364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6365#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6366#[cfg_attr(
6367    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6368    assert_instr(cls)
6369)]
6370#[cfg_attr(
6371    not(target_arch = "arm"),
6372    stable(feature = "neon_intrinsics", since = "1.59.0")
6373)]
6374#[cfg_attr(
6375    target_arch = "arm",
6376    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6377)]
6378pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
6379    unsafe extern "unadjusted" {
6380        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")]
6381        #[cfg_attr(
6382            any(target_arch = "aarch64", target_arch = "arm64ec"),
6383            link_name = "llvm.aarch64.neon.cls.v2i32"
6384        )]
6385        fn _vcls_s32(a: int32x2_t) -> int32x2_t;
6386    }
6387    unsafe { _vcls_s32(a) }
6388}
6389#[doc = "Count leading sign bits"]
6390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
6391#[inline]
6392#[target_feature(enable = "neon")]
6393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6394#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6395#[cfg_attr(
6396    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6397    assert_instr(cls)
6398)]
6399#[cfg_attr(
6400    not(target_arch = "arm"),
6401    stable(feature = "neon_intrinsics", since = "1.59.0")
6402)]
6403#[cfg_attr(
6404    target_arch = "arm",
6405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6406)]
6407pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
6408    unsafe extern "unadjusted" {
6409        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")]
6410        #[cfg_attr(
6411            any(target_arch = "aarch64", target_arch = "arm64ec"),
6412            link_name = "llvm.aarch64.neon.cls.v4i32"
6413        )]
6414        fn _vclsq_s32(a: int32x4_t) -> int32x4_t;
6415    }
6416    unsafe { _vclsq_s32(a) }
6417}
6418#[doc = "Count leading sign bits"]
6419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
6420#[inline]
6421#[target_feature(enable = "neon")]
6422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6424#[cfg_attr(
6425    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6426    assert_instr(cls)
6427)]
6428#[cfg_attr(
6429    not(target_arch = "arm"),
6430    stable(feature = "neon_intrinsics", since = "1.59.0")
6431)]
6432#[cfg_attr(
6433    target_arch = "arm",
6434    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6435)]
6436pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
6437    unsafe { vcls_s8(transmute(a)) }
6438}
6439#[doc = "Count leading sign bits"]
6440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
6441#[inline]
6442#[target_feature(enable = "neon")]
6443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6445#[cfg_attr(
6446    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6447    assert_instr(cls)
6448)]
6449#[cfg_attr(
6450    not(target_arch = "arm"),
6451    stable(feature = "neon_intrinsics", since = "1.59.0")
6452)]
6453#[cfg_attr(
6454    target_arch = "arm",
6455    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6456)]
6457pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
6458    unsafe { vclsq_s8(transmute(a)) }
6459}
6460#[doc = "Count leading sign bits"]
6461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
6462#[inline]
6463#[target_feature(enable = "neon")]
6464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6466#[cfg_attr(
6467    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6468    assert_instr(cls)
6469)]
6470#[cfg_attr(
6471    not(target_arch = "arm"),
6472    stable(feature = "neon_intrinsics", since = "1.59.0")
6473)]
6474#[cfg_attr(
6475    target_arch = "arm",
6476    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6477)]
6478pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
6479    unsafe { vcls_s16(transmute(a)) }
6480}
6481#[doc = "Count leading sign bits"]
6482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
6483#[inline]
6484#[target_feature(enable = "neon")]
6485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6487#[cfg_attr(
6488    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6489    assert_instr(cls)
6490)]
6491#[cfg_attr(
6492    not(target_arch = "arm"),
6493    stable(feature = "neon_intrinsics", since = "1.59.0")
6494)]
6495#[cfg_attr(
6496    target_arch = "arm",
6497    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6498)]
6499pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
6500    unsafe { vclsq_s16(transmute(a)) }
6501}
6502#[doc = "Count leading sign bits"]
6503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
6504#[inline]
6505#[target_feature(enable = "neon")]
6506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6508#[cfg_attr(
6509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6510    assert_instr(cls)
6511)]
6512#[cfg_attr(
6513    not(target_arch = "arm"),
6514    stable(feature = "neon_intrinsics", since = "1.59.0")
6515)]
6516#[cfg_attr(
6517    target_arch = "arm",
6518    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6519)]
6520pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
6521    unsafe { vcls_s32(transmute(a)) }
6522}
6523#[doc = "Count leading sign bits"]
6524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
6525#[inline]
6526#[target_feature(enable = "neon")]
6527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6529#[cfg_attr(
6530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6531    assert_instr(cls)
6532)]
6533#[cfg_attr(
6534    not(target_arch = "arm"),
6535    stable(feature = "neon_intrinsics", since = "1.59.0")
6536)]
6537#[cfg_attr(
6538    target_arch = "arm",
6539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6540)]
6541pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
6542    unsafe { vclsq_s32(transmute(a)) }
6543}
6544#[doc = "Floating-point compare less than"]
6545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
6546#[inline]
6547#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6548#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6549#[cfg_attr(
6550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6551    assert_instr(fcmgt)
6552)]
6553#[target_feature(enable = "neon,fp16")]
6554#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6555pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
6556    unsafe { simd_lt(a, b) }
6557}
6558#[doc = "Floating-point compare less than"]
6559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
6560#[inline]
6561#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6562#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6563#[cfg_attr(
6564    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6565    assert_instr(fcmgt)
6566)]
6567#[target_feature(enable = "neon,fp16")]
6568#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6569pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
6570    unsafe { simd_lt(a, b) }
6571}
6572#[doc = "Floating-point compare less than"]
6573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
6574#[inline]
6575#[target_feature(enable = "neon")]
6576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6577#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6578#[cfg_attr(
6579    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6580    assert_instr(fcmgt)
6581)]
6582#[cfg_attr(
6583    not(target_arch = "arm"),
6584    stable(feature = "neon_intrinsics", since = "1.59.0")
6585)]
6586#[cfg_attr(
6587    target_arch = "arm",
6588    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6589)]
6590pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
6591    unsafe { simd_lt(a, b) }
6592}
6593#[doc = "Floating-point compare less than"]
6594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
6595#[inline]
6596#[target_feature(enable = "neon")]
6597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6599#[cfg_attr(
6600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6601    assert_instr(fcmgt)
6602)]
6603#[cfg_attr(
6604    not(target_arch = "arm"),
6605    stable(feature = "neon_intrinsics", since = "1.59.0")
6606)]
6607#[cfg_attr(
6608    target_arch = "arm",
6609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6610)]
6611pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
6612    unsafe { simd_lt(a, b) }
6613}
6614#[doc = "Compare signed less than"]
6615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
6616#[inline]
6617#[target_feature(enable = "neon")]
6618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6619#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6620#[cfg_attr(
6621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6622    assert_instr(cmgt)
6623)]
6624#[cfg_attr(
6625    not(target_arch = "arm"),
6626    stable(feature = "neon_intrinsics", since = "1.59.0")
6627)]
6628#[cfg_attr(
6629    target_arch = "arm",
6630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6631)]
6632pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
6633    unsafe { simd_lt(a, b) }
6634}
6635#[doc = "Compare signed less than"]
6636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
6637#[inline]
6638#[target_feature(enable = "neon")]
6639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6641#[cfg_attr(
6642    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6643    assert_instr(cmgt)
6644)]
6645#[cfg_attr(
6646    not(target_arch = "arm"),
6647    stable(feature = "neon_intrinsics", since = "1.59.0")
6648)]
6649#[cfg_attr(
6650    target_arch = "arm",
6651    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6652)]
6653pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6654    unsafe { simd_lt(a, b) }
6655}
6656#[doc = "Compare signed less than"]
6657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
6658#[inline]
6659#[target_feature(enable = "neon")]
6660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6662#[cfg_attr(
6663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6664    assert_instr(cmgt)
6665)]
6666#[cfg_attr(
6667    not(target_arch = "arm"),
6668    stable(feature = "neon_intrinsics", since = "1.59.0")
6669)]
6670#[cfg_attr(
6671    target_arch = "arm",
6672    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6673)]
6674pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6675    unsafe { simd_lt(a, b) }
6676}
6677#[doc = "Compare signed less than"]
6678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
6679#[inline]
6680#[target_feature(enable = "neon")]
6681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6683#[cfg_attr(
6684    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6685    assert_instr(cmgt)
6686)]
6687#[cfg_attr(
6688    not(target_arch = "arm"),
6689    stable(feature = "neon_intrinsics", since = "1.59.0")
6690)]
6691#[cfg_attr(
6692    target_arch = "arm",
6693    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6694)]
6695pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6696    unsafe { simd_lt(a, b) }
6697}
6698#[doc = "Compare signed less than"]
6699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
6700#[inline]
6701#[target_feature(enable = "neon")]
6702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6703#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6704#[cfg_attr(
6705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6706    assert_instr(cmgt)
6707)]
6708#[cfg_attr(
6709    not(target_arch = "arm"),
6710    stable(feature = "neon_intrinsics", since = "1.59.0")
6711)]
6712#[cfg_attr(
6713    target_arch = "arm",
6714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6715)]
6716pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6717    unsafe { simd_lt(a, b) }
6718}
6719#[doc = "Compare signed less than"]
6720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
6721#[inline]
6722#[target_feature(enable = "neon")]
6723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6725#[cfg_attr(
6726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6727    assert_instr(cmgt)
6728)]
6729#[cfg_attr(
6730    not(target_arch = "arm"),
6731    stable(feature = "neon_intrinsics", since = "1.59.0")
6732)]
6733#[cfg_attr(
6734    target_arch = "arm",
6735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6736)]
6737pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6738    unsafe { simd_lt(a, b) }
6739}
6740#[doc = "Compare unsigned less than"]
6741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
6742#[inline]
6743#[target_feature(enable = "neon")]
6744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6746#[cfg_attr(
6747    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6748    assert_instr(cmhi)
6749)]
6750#[cfg_attr(
6751    not(target_arch = "arm"),
6752    stable(feature = "neon_intrinsics", since = "1.59.0")
6753)]
6754#[cfg_attr(
6755    target_arch = "arm",
6756    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6757)]
6758pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6759    unsafe { simd_lt(a, b) }
6760}
6761#[doc = "Compare unsigned less than"]
6762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
6763#[inline]
6764#[target_feature(enable = "neon")]
6765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6767#[cfg_attr(
6768    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6769    assert_instr(cmhi)
6770)]
6771#[cfg_attr(
6772    not(target_arch = "arm"),
6773    stable(feature = "neon_intrinsics", since = "1.59.0")
6774)]
6775#[cfg_attr(
6776    target_arch = "arm",
6777    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6778)]
6779pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6780    unsafe { simd_lt(a, b) }
6781}
6782#[doc = "Compare unsigned less than"]
6783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
6784#[inline]
6785#[target_feature(enable = "neon")]
6786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6788#[cfg_attr(
6789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6790    assert_instr(cmhi)
6791)]
6792#[cfg_attr(
6793    not(target_arch = "arm"),
6794    stable(feature = "neon_intrinsics", since = "1.59.0")
6795)]
6796#[cfg_attr(
6797    target_arch = "arm",
6798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6799)]
6800pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6801    unsafe { simd_lt(a, b) }
6802}
6803#[doc = "Compare unsigned less than"]
6804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
6805#[inline]
6806#[target_feature(enable = "neon")]
6807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6809#[cfg_attr(
6810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6811    assert_instr(cmhi)
6812)]
6813#[cfg_attr(
6814    not(target_arch = "arm"),
6815    stable(feature = "neon_intrinsics", since = "1.59.0")
6816)]
6817#[cfg_attr(
6818    target_arch = "arm",
6819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6820)]
6821pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6822    unsafe { simd_lt(a, b) }
6823}
6824#[doc = "Compare unsigned less than"]
6825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
6826#[inline]
6827#[target_feature(enable = "neon")]
6828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6830#[cfg_attr(
6831    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6832    assert_instr(cmhi)
6833)]
6834#[cfg_attr(
6835    not(target_arch = "arm"),
6836    stable(feature = "neon_intrinsics", since = "1.59.0")
6837)]
6838#[cfg_attr(
6839    target_arch = "arm",
6840    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6841)]
6842pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6843    unsafe { simd_lt(a, b) }
6844}
6845#[doc = "Compare unsigned less than"]
6846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
6847#[inline]
6848#[target_feature(enable = "neon")]
6849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6851#[cfg_attr(
6852    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6853    assert_instr(cmhi)
6854)]
6855#[cfg_attr(
6856    not(target_arch = "arm"),
6857    stable(feature = "neon_intrinsics", since = "1.59.0")
6858)]
6859#[cfg_attr(
6860    target_arch = "arm",
6861    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6862)]
6863pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6864    unsafe { simd_lt(a, b) }
6865}
6866#[doc = "Floating-point compare less than"]
6867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
6868#[inline]
6869#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6870#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6871#[cfg_attr(
6872    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6873    assert_instr(fcmlt)
6874)]
6875#[target_feature(enable = "neon,fp16")]
6876#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6877pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
6878    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6879    unsafe { simd_lt(a, transmute(b)) }
6880}
6881#[doc = "Floating-point compare less than"]
6882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
6883#[inline]
6884#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6886#[cfg_attr(
6887    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6888    assert_instr(fcmlt)
6889)]
6890#[target_feature(enable = "neon,fp16")]
6891#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6892pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
6893    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6894    unsafe { simd_lt(a, transmute(b)) }
6895}
6896#[doc = "Count leading zero bits"]
6897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
6898#[inline]
6899#[target_feature(enable = "neon")]
6900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6901#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6902#[cfg_attr(
6903    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6904    assert_instr(clz)
6905)]
6906#[cfg_attr(
6907    not(target_arch = "arm"),
6908    stable(feature = "neon_intrinsics", since = "1.59.0")
6909)]
6910#[cfg_attr(
6911    target_arch = "arm",
6912    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6913)]
6914pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
6915    unsafe extern "unadjusted" {
6916        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i8")]
6917        #[cfg_attr(
6918            any(target_arch = "aarch64", target_arch = "arm64ec"),
6919            link_name = "llvm.ctlz.v8i8"
6920        )]
6921        fn _vclz_s8(a: int8x8_t) -> int8x8_t;
6922    }
6923    unsafe { _vclz_s8(a) }
6924}
6925#[doc = "Count leading zero bits"]
6926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
6927#[inline]
6928#[target_feature(enable = "neon")]
6929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6930#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6931#[cfg_attr(
6932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6933    assert_instr(clz)
6934)]
6935#[cfg_attr(
6936    not(target_arch = "arm"),
6937    stable(feature = "neon_intrinsics", since = "1.59.0")
6938)]
6939#[cfg_attr(
6940    target_arch = "arm",
6941    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6942)]
6943pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
6944    unsafe extern "unadjusted" {
6945        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v16i8")]
6946        #[cfg_attr(
6947            any(target_arch = "aarch64", target_arch = "arm64ec"),
6948            link_name = "llvm.ctlz.v16i8"
6949        )]
6950        fn _vclzq_s8(a: int8x16_t) -> int8x16_t;
6951    }
6952    unsafe { _vclzq_s8(a) }
6953}
6954#[doc = "Count leading zero bits"]
6955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
6956#[inline]
6957#[target_feature(enable = "neon")]
6958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6960#[cfg_attr(
6961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6962    assert_instr(clz)
6963)]
6964#[cfg_attr(
6965    not(target_arch = "arm"),
6966    stable(feature = "neon_intrinsics", since = "1.59.0")
6967)]
6968#[cfg_attr(
6969    target_arch = "arm",
6970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6971)]
6972pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
6973    unsafe extern "unadjusted" {
6974        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i16")]
6975        #[cfg_attr(
6976            any(target_arch = "aarch64", target_arch = "arm64ec"),
6977            link_name = "llvm.ctlz.v4i16"
6978        )]
6979        fn _vclz_s16(a: int16x4_t) -> int16x4_t;
6980    }
6981    unsafe { _vclz_s16(a) }
6982}
6983#[doc = "Count leading zero bits"]
6984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
6985#[inline]
6986#[target_feature(enable = "neon")]
6987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6989#[cfg_attr(
6990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6991    assert_instr(clz)
6992)]
6993#[cfg_attr(
6994    not(target_arch = "arm"),
6995    stable(feature = "neon_intrinsics", since = "1.59.0")
6996)]
6997#[cfg_attr(
6998    target_arch = "arm",
6999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7000)]
7001pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
7002    unsafe extern "unadjusted" {
7003        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i16")]
7004        #[cfg_attr(
7005            any(target_arch = "aarch64", target_arch = "arm64ec"),
7006            link_name = "llvm.ctlz.v8i16"
7007        )]
7008        fn _vclzq_s16(a: int16x8_t) -> int16x8_t;
7009    }
7010    unsafe { _vclzq_s16(a) }
7011}
7012#[doc = "Count leading zero bits"]
7013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
7014#[inline]
7015#[target_feature(enable = "neon")]
7016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7018#[cfg_attr(
7019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7020    assert_instr(clz)
7021)]
7022#[cfg_attr(
7023    not(target_arch = "arm"),
7024    stable(feature = "neon_intrinsics", since = "1.59.0")
7025)]
7026#[cfg_attr(
7027    target_arch = "arm",
7028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7029)]
7030pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
7031    unsafe extern "unadjusted" {
7032        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v2i32")]
7033        #[cfg_attr(
7034            any(target_arch = "aarch64", target_arch = "arm64ec"),
7035            link_name = "llvm.ctlz.v2i32"
7036        )]
7037        fn _vclz_s32(a: int32x2_t) -> int32x2_t;
7038    }
7039    unsafe { _vclz_s32(a) }
7040}
7041#[doc = "Count leading zero bits"]
7042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
7043#[inline]
7044#[target_feature(enable = "neon")]
7045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7046#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7047#[cfg_attr(
7048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7049    assert_instr(clz)
7050)]
7051#[cfg_attr(
7052    not(target_arch = "arm"),
7053    stable(feature = "neon_intrinsics", since = "1.59.0")
7054)]
7055#[cfg_attr(
7056    target_arch = "arm",
7057    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7058)]
7059pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
7060    unsafe extern "unadjusted" {
7061        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i32")]
7062        #[cfg_attr(
7063            any(target_arch = "aarch64", target_arch = "arm64ec"),
7064            link_name = "llvm.ctlz.v4i32"
7065        )]
7066        fn _vclzq_s32(a: int32x4_t) -> int32x4_t;
7067    }
7068    unsafe { _vclzq_s32(a) }
7069}
7070#[doc = "Count leading zero bits"]
7071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7072#[inline]
7073#[cfg(target_endian = "little")]
7074#[target_feature(enable = "neon")]
7075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7076#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7077#[cfg_attr(
7078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7079    assert_instr(clz)
7080)]
7081#[cfg_attr(
7082    not(target_arch = "arm"),
7083    stable(feature = "neon_intrinsics", since = "1.59.0")
7084)]
7085#[cfg_attr(
7086    target_arch = "arm",
7087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7088)]
7089pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7090    unsafe { transmute(vclz_s16(transmute(a))) }
7091}
7092#[doc = "Count leading zero bits"]
7093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7094#[inline]
7095#[cfg(target_endian = "big")]
7096#[target_feature(enable = "neon")]
7097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7099#[cfg_attr(
7100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7101    assert_instr(clz)
7102)]
7103#[cfg_attr(
7104    not(target_arch = "arm"),
7105    stable(feature = "neon_intrinsics", since = "1.59.0")
7106)]
7107#[cfg_attr(
7108    target_arch = "arm",
7109    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7110)]
7111pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7112    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7113    unsafe {
7114        let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
7115        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7116    }
7117}
7118#[doc = "Count leading zero bits"]
7119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7120#[inline]
7121#[cfg(target_endian = "little")]
7122#[target_feature(enable = "neon")]
7123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7124#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7125#[cfg_attr(
7126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7127    assert_instr(clz)
7128)]
7129#[cfg_attr(
7130    not(target_arch = "arm"),
7131    stable(feature = "neon_intrinsics", since = "1.59.0")
7132)]
7133#[cfg_attr(
7134    target_arch = "arm",
7135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7136)]
7137pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7138    unsafe { transmute(vclzq_s16(transmute(a))) }
7139}
7140#[doc = "Count leading zero bits"]
7141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7142#[inline]
7143#[cfg(target_endian = "big")]
7144#[target_feature(enable = "neon")]
7145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7146#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7147#[cfg_attr(
7148    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7149    assert_instr(clz)
7150)]
7151#[cfg_attr(
7152    not(target_arch = "arm"),
7153    stable(feature = "neon_intrinsics", since = "1.59.0")
7154)]
7155#[cfg_attr(
7156    target_arch = "arm",
7157    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7158)]
7159pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7160    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7161    unsafe {
7162        let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
7163        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7164    }
7165}
7166#[doc = "Count leading zero bits"]
7167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7168#[inline]
7169#[cfg(target_endian = "little")]
7170#[target_feature(enable = "neon")]
7171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7172#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7173#[cfg_attr(
7174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7175    assert_instr(clz)
7176)]
7177#[cfg_attr(
7178    not(target_arch = "arm"),
7179    stable(feature = "neon_intrinsics", since = "1.59.0")
7180)]
7181#[cfg_attr(
7182    target_arch = "arm",
7183    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7184)]
7185pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7186    unsafe { transmute(vclz_s32(transmute(a))) }
7187}
7188#[doc = "Count leading zero bits"]
7189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7190#[inline]
7191#[cfg(target_endian = "big")]
7192#[target_feature(enable = "neon")]
7193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7194#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7195#[cfg_attr(
7196    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7197    assert_instr(clz)
7198)]
7199#[cfg_attr(
7200    not(target_arch = "arm"),
7201    stable(feature = "neon_intrinsics", since = "1.59.0")
7202)]
7203#[cfg_attr(
7204    target_arch = "arm",
7205    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7206)]
7207pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7208    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
7209    unsafe {
7210        let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
7211        simd_shuffle!(ret_val, ret_val, [1, 0])
7212    }
7213}
7214#[doc = "Count leading zero bits"]
7215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7216#[inline]
7217#[cfg(target_endian = "little")]
7218#[target_feature(enable = "neon")]
7219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7220#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7221#[cfg_attr(
7222    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7223    assert_instr(clz)
7224)]
7225#[cfg_attr(
7226    not(target_arch = "arm"),
7227    stable(feature = "neon_intrinsics", since = "1.59.0")
7228)]
7229#[cfg_attr(
7230    target_arch = "arm",
7231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7232)]
7233pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7234    unsafe { transmute(vclzq_s32(transmute(a))) }
7235}
7236#[doc = "Count leading zero bits"]
7237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7238#[inline]
7239#[cfg(target_endian = "big")]
7240#[target_feature(enable = "neon")]
7241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7243#[cfg_attr(
7244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7245    assert_instr(clz)
7246)]
7247#[cfg_attr(
7248    not(target_arch = "arm"),
7249    stable(feature = "neon_intrinsics", since = "1.59.0")
7250)]
7251#[cfg_attr(
7252    target_arch = "arm",
7253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7254)]
7255pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7256    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7257    unsafe {
7258        let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
7259        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7260    }
7261}
7262#[doc = "Count leading zero bits"]
7263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7264#[inline]
7265#[cfg(target_endian = "little")]
7266#[target_feature(enable = "neon")]
7267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7269#[cfg_attr(
7270    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7271    assert_instr(clz)
7272)]
7273#[cfg_attr(
7274    not(target_arch = "arm"),
7275    stable(feature = "neon_intrinsics", since = "1.59.0")
7276)]
7277#[cfg_attr(
7278    target_arch = "arm",
7279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7280)]
7281pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7282    unsafe { transmute(vclz_s8(transmute(a))) }
7283}
7284#[doc = "Count leading zero bits"]
7285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7286#[inline]
7287#[cfg(target_endian = "big")]
7288#[target_feature(enable = "neon")]
7289#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7290#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7291#[cfg_attr(
7292    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7293    assert_instr(clz)
7294)]
7295#[cfg_attr(
7296    not(target_arch = "arm"),
7297    stable(feature = "neon_intrinsics", since = "1.59.0")
7298)]
7299#[cfg_attr(
7300    target_arch = "arm",
7301    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7302)]
7303pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7304    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7305    unsafe {
7306        let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
7307        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7308    }
7309}
7310#[doc = "Count leading zero bits"]
7311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7312#[inline]
7313#[cfg(target_endian = "little")]
7314#[target_feature(enable = "neon")]
7315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7316#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7317#[cfg_attr(
7318    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7319    assert_instr(clz)
7320)]
7321#[cfg_attr(
7322    not(target_arch = "arm"),
7323    stable(feature = "neon_intrinsics", since = "1.59.0")
7324)]
7325#[cfg_attr(
7326    target_arch = "arm",
7327    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7328)]
7329pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7330    unsafe { transmute(vclzq_s8(transmute(a))) }
7331}
7332#[doc = "Count leading zero bits"]
7333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7334#[inline]
7335#[cfg(target_endian = "big")]
7336#[target_feature(enable = "neon")]
7337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7338#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7339#[cfg_attr(
7340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7341    assert_instr(clz)
7342)]
7343#[cfg_attr(
7344    not(target_arch = "arm"),
7345    stable(feature = "neon_intrinsics", since = "1.59.0")
7346)]
7347#[cfg_attr(
7348    target_arch = "arm",
7349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7350)]
7351pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7352    let a: uint8x16_t =
7353        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7354    unsafe {
7355        let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
7356        simd_shuffle!(
7357            ret_val,
7358            ret_val,
7359            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7360        )
7361    }
7362}
7363#[doc = "Population count per byte."]
7364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
7365#[inline]
7366#[target_feature(enable = "neon")]
7367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7369#[cfg_attr(
7370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7371    assert_instr(cnt)
7372)]
7373#[cfg_attr(
7374    not(target_arch = "arm"),
7375    stable(feature = "neon_intrinsics", since = "1.59.0")
7376)]
7377#[cfg_attr(
7378    target_arch = "arm",
7379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7380)]
7381pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
7382    unsafe extern "unadjusted" {
7383        #[cfg_attr(
7384            any(target_arch = "aarch64", target_arch = "arm64ec"),
7385            link_name = "llvm.ctpop.v8i8"
7386        )]
7387        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v8i8")]
7388        fn _vcnt_s8(a: int8x8_t) -> int8x8_t;
7389    }
7390    unsafe { _vcnt_s8(a) }
7391}
7392#[doc = "Population count per byte."]
7393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
7394#[inline]
7395#[target_feature(enable = "neon")]
7396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7398#[cfg_attr(
7399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7400    assert_instr(cnt)
7401)]
7402#[cfg_attr(
7403    not(target_arch = "arm"),
7404    stable(feature = "neon_intrinsics", since = "1.59.0")
7405)]
7406#[cfg_attr(
7407    target_arch = "arm",
7408    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7409)]
7410pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
7411    unsafe extern "unadjusted" {
7412        #[cfg_attr(
7413            any(target_arch = "aarch64", target_arch = "arm64ec"),
7414            link_name = "llvm.ctpop.v16i8"
7415        )]
7416        #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v16i8")]
7417        fn _vcntq_s8(a: int8x16_t) -> int8x16_t;
7418    }
7419    unsafe { _vcntq_s8(a) }
7420}
7421#[doc = "Population count per byte."]
7422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7423#[inline]
7424#[cfg(target_endian = "little")]
7425#[target_feature(enable = "neon")]
7426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7427#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7428#[cfg_attr(
7429    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7430    assert_instr(cnt)
7431)]
7432#[cfg_attr(
7433    not(target_arch = "arm"),
7434    stable(feature = "neon_intrinsics", since = "1.59.0")
7435)]
7436#[cfg_attr(
7437    target_arch = "arm",
7438    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7439)]
7440pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7441    unsafe { transmute(vcnt_s8(transmute(a))) }
7442}
7443#[doc = "Population count per byte."]
7444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7445#[inline]
7446#[cfg(target_endian = "big")]
7447#[target_feature(enable = "neon")]
7448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7450#[cfg_attr(
7451    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7452    assert_instr(cnt)
7453)]
7454#[cfg_attr(
7455    not(target_arch = "arm"),
7456    stable(feature = "neon_intrinsics", since = "1.59.0")
7457)]
7458#[cfg_attr(
7459    target_arch = "arm",
7460    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7461)]
7462pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7463    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7464    unsafe {
7465        let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
7466        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7467    }
7468}
7469#[doc = "Population count per byte."]
7470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7471#[inline]
7472#[cfg(target_endian = "little")]
7473#[target_feature(enable = "neon")]
7474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7476#[cfg_attr(
7477    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7478    assert_instr(cnt)
7479)]
7480#[cfg_attr(
7481    not(target_arch = "arm"),
7482    stable(feature = "neon_intrinsics", since = "1.59.0")
7483)]
7484#[cfg_attr(
7485    target_arch = "arm",
7486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7487)]
7488pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7489    unsafe { transmute(vcntq_s8(transmute(a))) }
7490}
7491#[doc = "Population count per byte."]
7492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7493#[inline]
7494#[cfg(target_endian = "big")]
7495#[target_feature(enable = "neon")]
7496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7498#[cfg_attr(
7499    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7500    assert_instr(cnt)
7501)]
7502#[cfg_attr(
7503    not(target_arch = "arm"),
7504    stable(feature = "neon_intrinsics", since = "1.59.0")
7505)]
7506#[cfg_attr(
7507    target_arch = "arm",
7508    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7509)]
7510pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7511    let a: uint8x16_t =
7512        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7513    unsafe {
7514        let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
7515        simd_shuffle!(
7516            ret_val,
7517            ret_val,
7518            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7519        )
7520    }
7521}
7522#[doc = "Population count per byte."]
7523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7524#[inline]
7525#[cfg(target_endian = "little")]
7526#[target_feature(enable = "neon")]
7527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7529#[cfg_attr(
7530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7531    assert_instr(cnt)
7532)]
7533#[cfg_attr(
7534    not(target_arch = "arm"),
7535    stable(feature = "neon_intrinsics", since = "1.59.0")
7536)]
7537#[cfg_attr(
7538    target_arch = "arm",
7539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7540)]
7541pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7542    unsafe { transmute(vcnt_s8(transmute(a))) }
7543}
7544#[doc = "Population count per byte."]
7545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7546#[inline]
7547#[cfg(target_endian = "big")]
7548#[target_feature(enable = "neon")]
7549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7551#[cfg_attr(
7552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7553    assert_instr(cnt)
7554)]
7555#[cfg_attr(
7556    not(target_arch = "arm"),
7557    stable(feature = "neon_intrinsics", since = "1.59.0")
7558)]
7559#[cfg_attr(
7560    target_arch = "arm",
7561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7562)]
7563pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7564    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7565    unsafe {
7566        let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
7567        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7568    }
7569}
7570#[doc = "Population count per byte."]
7571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7572#[inline]
7573#[cfg(target_endian = "little")]
7574#[target_feature(enable = "neon")]
7575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7577#[cfg_attr(
7578    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7579    assert_instr(cnt)
7580)]
7581#[cfg_attr(
7582    not(target_arch = "arm"),
7583    stable(feature = "neon_intrinsics", since = "1.59.0")
7584)]
7585#[cfg_attr(
7586    target_arch = "arm",
7587    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7588)]
7589pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7590    unsafe { transmute(vcntq_s8(transmute(a))) }
7591}
7592#[doc = "Population count per byte."]
7593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7594#[inline]
7595#[cfg(target_endian = "big")]
7596#[target_feature(enable = "neon")]
7597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7599#[cfg_attr(
7600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7601    assert_instr(cnt)
7602)]
7603#[cfg_attr(
7604    not(target_arch = "arm"),
7605    stable(feature = "neon_intrinsics", since = "1.59.0")
7606)]
7607#[cfg_attr(
7608    target_arch = "arm",
7609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7610)]
7611pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7612    let a: poly8x16_t =
7613        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7614    unsafe {
7615        let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
7616        simd_shuffle!(
7617            ret_val,
7618            ret_val,
7619            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7620        )
7621    }
7622}
7623#[doc = "Join two smaller vectors into a single larger vector"]
7624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
7625#[inline]
7626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7627#[target_feature(enable = "neon,fp16")]
7628#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7629#[cfg_attr(test, assert_instr(nop))]
7630pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
7631    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7632}
7633#[doc = "Join two smaller vectors into a single larger vector"]
7634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
7635#[inline]
7636#[target_feature(enable = "neon")]
7637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7639#[cfg_attr(
7640    not(target_arch = "arm"),
7641    stable(feature = "neon_intrinsics", since = "1.59.0")
7642)]
7643#[cfg_attr(
7644    target_arch = "arm",
7645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7646)]
7647pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
7648    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7649}
7650#[doc = "Join two smaller vectors into a single larger vector"]
7651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
7652#[inline]
7653#[target_feature(enable = "neon")]
7654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7656#[cfg_attr(
7657    not(target_arch = "arm"),
7658    stable(feature = "neon_intrinsics", since = "1.59.0")
7659)]
7660#[cfg_attr(
7661    target_arch = "arm",
7662    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7663)]
7664pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
7665    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7666}
7667#[doc = "Join two smaller vectors into a single larger vector"]
7668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
7669#[inline]
7670#[target_feature(enable = "neon")]
7671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7673#[cfg_attr(
7674    not(target_arch = "arm"),
7675    stable(feature = "neon_intrinsics", since = "1.59.0")
7676)]
7677#[cfg_attr(
7678    target_arch = "arm",
7679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7680)]
7681pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
7682    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7683}
7684#[doc = "Join two smaller vectors into a single larger vector"]
7685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
7686#[inline]
7687#[target_feature(enable = "neon")]
7688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7690#[cfg_attr(
7691    not(target_arch = "arm"),
7692    stable(feature = "neon_intrinsics", since = "1.59.0")
7693)]
7694#[cfg_attr(
7695    target_arch = "arm",
7696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7697)]
7698pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
7699    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7700}
7701#[doc = "Join two smaller vectors into a single larger vector"]
7702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
7703#[inline]
7704#[target_feature(enable = "neon")]
7705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7707#[cfg_attr(
7708    not(target_arch = "arm"),
7709    stable(feature = "neon_intrinsics", since = "1.59.0")
7710)]
7711#[cfg_attr(
7712    target_arch = "arm",
7713    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7714)]
7715pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
7716    unsafe { simd_shuffle!(a, b, [0, 1]) }
7717}
7718#[doc = "Join two smaller vectors into a single larger vector"]
7719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
7720#[inline]
7721#[target_feature(enable = "neon")]
7722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7724#[cfg_attr(
7725    not(target_arch = "arm"),
7726    stable(feature = "neon_intrinsics", since = "1.59.0")
7727)]
7728#[cfg_attr(
7729    target_arch = "arm",
7730    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7731)]
7732pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
7733    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7734}
7735#[doc = "Join two smaller vectors into a single larger vector"]
7736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
7737#[inline]
7738#[target_feature(enable = "neon")]
7739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7741#[cfg_attr(
7742    not(target_arch = "arm"),
7743    stable(feature = "neon_intrinsics", since = "1.59.0")
7744)]
7745#[cfg_attr(
7746    target_arch = "arm",
7747    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7748)]
7749pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
7750    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7751}
7752#[doc = "Join two smaller vectors into a single larger vector"]
7753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
7754#[inline]
7755#[target_feature(enable = "neon")]
7756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7758#[cfg_attr(
7759    not(target_arch = "arm"),
7760    stable(feature = "neon_intrinsics", since = "1.59.0")
7761)]
7762#[cfg_attr(
7763    target_arch = "arm",
7764    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7765)]
7766pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
7767    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7768}
7769#[doc = "Join two smaller vectors into a single larger vector"]
7770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
7771#[inline]
7772#[target_feature(enable = "neon")]
7773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7775#[cfg_attr(
7776    not(target_arch = "arm"),
7777    stable(feature = "neon_intrinsics", since = "1.59.0")
7778)]
7779#[cfg_attr(
7780    target_arch = "arm",
7781    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7782)]
7783pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
7784    unsafe { simd_shuffle!(a, b, [0, 1]) }
7785}
7786#[doc = "Join two smaller vectors into a single larger vector"]
7787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
7788#[inline]
7789#[target_feature(enable = "neon")]
7790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7792#[cfg_attr(
7793    not(target_arch = "arm"),
7794    stable(feature = "neon_intrinsics", since = "1.59.0")
7795)]
7796#[cfg_attr(
7797    target_arch = "arm",
7798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7799)]
7800pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
7801    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7802}
7803#[doc = "Join two smaller vectors into a single larger vector"]
7804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
7805#[inline]
7806#[target_feature(enable = "neon")]
7807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7809#[cfg_attr(
7810    not(target_arch = "arm"),
7811    stable(feature = "neon_intrinsics", since = "1.59.0")
7812)]
7813#[cfg_attr(
7814    target_arch = "arm",
7815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7816)]
7817pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
7818    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7819}
7820#[doc = "Join two smaller vectors into a single larger vector"]
7821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
7822#[inline]
7823#[target_feature(enable = "neon")]
7824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7826#[cfg_attr(
7827    not(target_arch = "arm"),
7828    stable(feature = "neon_intrinsics", since = "1.59.0")
7829)]
7830#[cfg_attr(
7831    target_arch = "arm",
7832    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7833)]
7834pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
7835    unsafe { simd_shuffle!(a, b, [0, 1]) }
7836}
7837#[doc = "Insert vector element from another vector element"]
7838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7839#[inline]
7840#[cfg(target_endian = "little")]
7841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7843#[cfg_attr(
7844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7845    assert_instr(nop)
7846)]
7847#[target_feature(enable = "neon,fp16")]
7848#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7849pub fn vcreate_f16(a: u64) -> float16x4_t {
7850    unsafe { transmute(a) }
7851}
7852#[doc = "Insert vector element from another vector element"]
7853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7854#[inline]
7855#[cfg(target_endian = "big")]
7856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7858#[cfg_attr(
7859    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7860    assert_instr(nop)
7861)]
7862#[target_feature(enable = "neon,fp16")]
7863#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7864pub fn vcreate_f16(a: u64) -> float16x4_t {
7865    unsafe {
7866        let ret_val: float16x4_t = transmute(a);
7867        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7868    }
7869}
7870#[doc = "Insert vector element from another vector element"]
7871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7872#[inline]
7873#[cfg(target_endian = "little")]
7874#[target_feature(enable = "neon")]
7875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7877#[cfg_attr(
7878    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7879    assert_instr(nop)
7880)]
7881#[cfg_attr(
7882    not(target_arch = "arm"),
7883    stable(feature = "neon_intrinsics", since = "1.59.0")
7884)]
7885#[cfg_attr(
7886    target_arch = "arm",
7887    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7888)]
7889pub fn vcreate_f32(a: u64) -> float32x2_t {
7890    unsafe { transmute(a) }
7891}
7892#[doc = "Insert vector element from another vector element"]
7893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7894#[inline]
7895#[cfg(target_endian = "big")]
7896#[target_feature(enable = "neon")]
7897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7899#[cfg_attr(
7900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7901    assert_instr(nop)
7902)]
7903#[cfg_attr(
7904    not(target_arch = "arm"),
7905    stable(feature = "neon_intrinsics", since = "1.59.0")
7906)]
7907#[cfg_attr(
7908    target_arch = "arm",
7909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7910)]
7911pub fn vcreate_f32(a: u64) -> float32x2_t {
7912    unsafe {
7913        let ret_val: float32x2_t = transmute(a);
7914        simd_shuffle!(ret_val, ret_val, [1, 0])
7915    }
7916}
7917#[doc = "Insert vector element from another vector element"]
7918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7919#[inline]
7920#[cfg(target_endian = "little")]
7921#[target_feature(enable = "neon")]
7922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7924#[cfg_attr(
7925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7926    assert_instr(nop)
7927)]
7928#[cfg_attr(
7929    not(target_arch = "arm"),
7930    stable(feature = "neon_intrinsics", since = "1.59.0")
7931)]
7932#[cfg_attr(
7933    target_arch = "arm",
7934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7935)]
7936pub fn vcreate_s8(a: u64) -> int8x8_t {
7937    unsafe { transmute(a) }
7938}
7939#[doc = "Insert vector element from another vector element"]
7940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7941#[inline]
7942#[cfg(target_endian = "big")]
7943#[target_feature(enable = "neon")]
7944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7946#[cfg_attr(
7947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7948    assert_instr(nop)
7949)]
7950#[cfg_attr(
7951    not(target_arch = "arm"),
7952    stable(feature = "neon_intrinsics", since = "1.59.0")
7953)]
7954#[cfg_attr(
7955    target_arch = "arm",
7956    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7957)]
7958pub fn vcreate_s8(a: u64) -> int8x8_t {
7959    unsafe {
7960        let ret_val: int8x8_t = transmute(a);
7961        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7962    }
7963}
7964#[doc = "Insert vector element from another vector element"]
7965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7966#[inline]
7967#[cfg(target_endian = "little")]
7968#[target_feature(enable = "neon")]
7969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7971#[cfg_attr(
7972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7973    assert_instr(nop)
7974)]
7975#[cfg_attr(
7976    not(target_arch = "arm"),
7977    stable(feature = "neon_intrinsics", since = "1.59.0")
7978)]
7979#[cfg_attr(
7980    target_arch = "arm",
7981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7982)]
7983pub fn vcreate_s16(a: u64) -> int16x4_t {
7984    unsafe { transmute(a) }
7985}
7986#[doc = "Insert vector element from another vector element"]
7987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7988#[inline]
7989#[cfg(target_endian = "big")]
7990#[target_feature(enable = "neon")]
7991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7993#[cfg_attr(
7994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7995    assert_instr(nop)
7996)]
7997#[cfg_attr(
7998    not(target_arch = "arm"),
7999    stable(feature = "neon_intrinsics", since = "1.59.0")
8000)]
8001#[cfg_attr(
8002    target_arch = "arm",
8003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8004)]
8005pub fn vcreate_s16(a: u64) -> int16x4_t {
8006    unsafe {
8007        let ret_val: int16x4_t = transmute(a);
8008        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8009    }
8010}
8011#[doc = "Insert vector element from another vector element"]
8012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
8013#[inline]
8014#[cfg(target_endian = "little")]
8015#[target_feature(enable = "neon")]
8016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8018#[cfg_attr(
8019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8020    assert_instr(nop)
8021)]
8022#[cfg_attr(
8023    not(target_arch = "arm"),
8024    stable(feature = "neon_intrinsics", since = "1.59.0")
8025)]
8026#[cfg_attr(
8027    target_arch = "arm",
8028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8029)]
8030pub fn vcreate_s32(a: u64) -> int32x2_t {
8031    unsafe { transmute(a) }
8032}
8033#[doc = "Insert vector element from another vector element"]
8034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
8035#[inline]
8036#[cfg(target_endian = "big")]
8037#[target_feature(enable = "neon")]
8038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8040#[cfg_attr(
8041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8042    assert_instr(nop)
8043)]
8044#[cfg_attr(
8045    not(target_arch = "arm"),
8046    stable(feature = "neon_intrinsics", since = "1.59.0")
8047)]
8048#[cfg_attr(
8049    target_arch = "arm",
8050    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8051)]
8052pub fn vcreate_s32(a: u64) -> int32x2_t {
8053    unsafe {
8054        let ret_val: int32x2_t = transmute(a);
8055        simd_shuffle!(ret_val, ret_val, [1, 0])
8056    }
8057}
8058#[doc = "Insert vector element from another vector element"]
8059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
8060#[inline]
8061#[target_feature(enable = "neon")]
8062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8064#[cfg_attr(
8065    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8066    assert_instr(nop)
8067)]
8068#[cfg_attr(
8069    not(target_arch = "arm"),
8070    stable(feature = "neon_intrinsics", since = "1.59.0")
8071)]
8072#[cfg_attr(
8073    target_arch = "arm",
8074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8075)]
8076pub fn vcreate_s64(a: u64) -> int64x1_t {
8077    unsafe { transmute(a) }
8078}
8079#[doc = "Insert vector element from another vector element"]
8080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8081#[inline]
8082#[cfg(target_endian = "little")]
8083#[target_feature(enable = "neon")]
8084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8086#[cfg_attr(
8087    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8088    assert_instr(nop)
8089)]
8090#[cfg_attr(
8091    not(target_arch = "arm"),
8092    stable(feature = "neon_intrinsics", since = "1.59.0")
8093)]
8094#[cfg_attr(
8095    target_arch = "arm",
8096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8097)]
8098pub fn vcreate_u8(a: u64) -> uint8x8_t {
8099    unsafe { transmute(a) }
8100}
8101#[doc = "Insert vector element from another vector element"]
8102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8103#[inline]
8104#[cfg(target_endian = "big")]
8105#[target_feature(enable = "neon")]
8106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8108#[cfg_attr(
8109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8110    assert_instr(nop)
8111)]
8112#[cfg_attr(
8113    not(target_arch = "arm"),
8114    stable(feature = "neon_intrinsics", since = "1.59.0")
8115)]
8116#[cfg_attr(
8117    target_arch = "arm",
8118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8119)]
8120pub fn vcreate_u8(a: u64) -> uint8x8_t {
8121    unsafe {
8122        let ret_val: uint8x8_t = transmute(a);
8123        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8124    }
8125}
8126#[doc = "Insert vector element from another vector element"]
8127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8128#[inline]
8129#[cfg(target_endian = "little")]
8130#[target_feature(enable = "neon")]
8131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8133#[cfg_attr(
8134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8135    assert_instr(nop)
8136)]
8137#[cfg_attr(
8138    not(target_arch = "arm"),
8139    stable(feature = "neon_intrinsics", since = "1.59.0")
8140)]
8141#[cfg_attr(
8142    target_arch = "arm",
8143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8144)]
8145pub fn vcreate_u16(a: u64) -> uint16x4_t {
8146    unsafe { transmute(a) }
8147}
8148#[doc = "Insert vector element from another vector element"]
8149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8150#[inline]
8151#[cfg(target_endian = "big")]
8152#[target_feature(enable = "neon")]
8153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8155#[cfg_attr(
8156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8157    assert_instr(nop)
8158)]
8159#[cfg_attr(
8160    not(target_arch = "arm"),
8161    stable(feature = "neon_intrinsics", since = "1.59.0")
8162)]
8163#[cfg_attr(
8164    target_arch = "arm",
8165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8166)]
8167pub fn vcreate_u16(a: u64) -> uint16x4_t {
8168    unsafe {
8169        let ret_val: uint16x4_t = transmute(a);
8170        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8171    }
8172}
8173#[doc = "Insert vector element from another vector element"]
8174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8175#[inline]
8176#[cfg(target_endian = "little")]
8177#[target_feature(enable = "neon")]
8178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8180#[cfg_attr(
8181    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8182    assert_instr(nop)
8183)]
8184#[cfg_attr(
8185    not(target_arch = "arm"),
8186    stable(feature = "neon_intrinsics", since = "1.59.0")
8187)]
8188#[cfg_attr(
8189    target_arch = "arm",
8190    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8191)]
8192pub fn vcreate_u32(a: u64) -> uint32x2_t {
8193    unsafe { transmute(a) }
8194}
8195#[doc = "Insert vector element from another vector element"]
8196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8197#[inline]
8198#[cfg(target_endian = "big")]
8199#[target_feature(enable = "neon")]
8200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8201#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8202#[cfg_attr(
8203    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8204    assert_instr(nop)
8205)]
8206#[cfg_attr(
8207    not(target_arch = "arm"),
8208    stable(feature = "neon_intrinsics", since = "1.59.0")
8209)]
8210#[cfg_attr(
8211    target_arch = "arm",
8212    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8213)]
8214pub fn vcreate_u32(a: u64) -> uint32x2_t {
8215    unsafe {
8216        let ret_val: uint32x2_t = transmute(a);
8217        simd_shuffle!(ret_val, ret_val, [1, 0])
8218    }
8219}
8220#[doc = "Insert vector element from another vector element"]
8221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
8222#[inline]
8223#[target_feature(enable = "neon")]
8224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8226#[cfg_attr(
8227    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8228    assert_instr(nop)
8229)]
8230#[cfg_attr(
8231    not(target_arch = "arm"),
8232    stable(feature = "neon_intrinsics", since = "1.59.0")
8233)]
8234#[cfg_attr(
8235    target_arch = "arm",
8236    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8237)]
8238pub fn vcreate_u64(a: u64) -> uint64x1_t {
8239    unsafe { transmute(a) }
8240}
8241#[doc = "Insert vector element from another vector element"]
8242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8243#[inline]
8244#[cfg(target_endian = "little")]
8245#[target_feature(enable = "neon")]
8246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8248#[cfg_attr(
8249    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8250    assert_instr(nop)
8251)]
8252#[cfg_attr(
8253    not(target_arch = "arm"),
8254    stable(feature = "neon_intrinsics", since = "1.59.0")
8255)]
8256#[cfg_attr(
8257    target_arch = "arm",
8258    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8259)]
8260pub fn vcreate_p8(a: u64) -> poly8x8_t {
8261    unsafe { transmute(a) }
8262}
8263#[doc = "Insert vector element from another vector element"]
8264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8265#[inline]
8266#[cfg(target_endian = "big")]
8267#[target_feature(enable = "neon")]
8268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8270#[cfg_attr(
8271    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8272    assert_instr(nop)
8273)]
8274#[cfg_attr(
8275    not(target_arch = "arm"),
8276    stable(feature = "neon_intrinsics", since = "1.59.0")
8277)]
8278#[cfg_attr(
8279    target_arch = "arm",
8280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8281)]
8282pub fn vcreate_p8(a: u64) -> poly8x8_t {
8283    unsafe {
8284        let ret_val: poly8x8_t = transmute(a);
8285        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8286    }
8287}
8288#[doc = "Insert vector element from another vector element"]
8289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8290#[inline]
8291#[cfg(target_endian = "little")]
8292#[target_feature(enable = "neon")]
8293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8295#[cfg_attr(
8296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8297    assert_instr(nop)
8298)]
8299#[cfg_attr(
8300    not(target_arch = "arm"),
8301    stable(feature = "neon_intrinsics", since = "1.59.0")
8302)]
8303#[cfg_attr(
8304    target_arch = "arm",
8305    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8306)]
8307pub fn vcreate_p16(a: u64) -> poly16x4_t {
8308    unsafe { transmute(a) }
8309}
8310#[doc = "Insert vector element from another vector element"]
8311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8312#[inline]
8313#[cfg(target_endian = "big")]
8314#[target_feature(enable = "neon")]
8315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8317#[cfg_attr(
8318    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8319    assert_instr(nop)
8320)]
8321#[cfg_attr(
8322    not(target_arch = "arm"),
8323    stable(feature = "neon_intrinsics", since = "1.59.0")
8324)]
8325#[cfg_attr(
8326    target_arch = "arm",
8327    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8328)]
8329pub fn vcreate_p16(a: u64) -> poly16x4_t {
8330    unsafe {
8331        let ret_val: poly16x4_t = transmute(a);
8332        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8333    }
8334}
8335#[doc = "Insert vector element from another vector element"]
8336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
8337#[inline]
8338#[target_feature(enable = "neon,aes")]
8339#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8341#[cfg_attr(
8342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8343    assert_instr(nop)
8344)]
8345#[cfg_attr(
8346    not(target_arch = "arm"),
8347    stable(feature = "neon_intrinsics", since = "1.59.0")
8348)]
8349#[cfg_attr(
8350    target_arch = "arm",
8351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8352)]
8353pub fn vcreate_p64(a: u64) -> poly64x1_t {
8354    unsafe { transmute(a) }
8355}
8356#[doc = "Floating-point convert to lower precision narrow"]
8357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
8358#[inline]
8359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8360# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
8361#[cfg_attr(
8362    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8363    assert_instr(fcvtn)
8364)]
8365#[target_feature(enable = "neon,fp16")]
8366#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8367pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
8368    unsafe { simd_cast(a) }
8369}
8370#[doc = "Fixed-point convert to floating-point"]
8371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
8372#[inline]
8373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8375#[cfg_attr(
8376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8377    assert_instr(scvtf)
8378)]
8379#[target_feature(enable = "neon,fp16")]
8380#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8381pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
8382    unsafe { simd_cast(a) }
8383}
8384#[doc = "Fixed-point convert to floating-point"]
8385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
8386#[inline]
8387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8389#[cfg_attr(
8390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8391    assert_instr(scvtf)
8392)]
8393#[target_feature(enable = "neon,fp16")]
8394#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8395pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
8396    unsafe { simd_cast(a) }
8397}
8398#[doc = "Fixed-point convert to floating-point"]
8399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
8400#[inline]
8401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8403#[cfg_attr(
8404    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8405    assert_instr(ucvtf)
8406)]
8407#[target_feature(enable = "neon,fp16")]
8408#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8409pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
8410    unsafe { simd_cast(a) }
8411}
8412#[doc = "Fixed-point convert to floating-point"]
8413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
8414#[inline]
8415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8417#[cfg_attr(
8418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8419    assert_instr(ucvtf)
8420)]
8421#[target_feature(enable = "neon,fp16")]
8422#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8423pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
8424    unsafe { simd_cast(a) }
8425}
8426#[doc = "Floating-point convert to higher precision long"]
8427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
8428#[inline]
8429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8431#[cfg_attr(
8432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8433    assert_instr(fcvtl)
8434)]
8435#[target_feature(enable = "neon,fp16")]
8436#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8437pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
8438    unsafe { simd_cast(a) }
8439}
8440#[doc = "Fixed-point convert to floating-point"]
8441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
8442#[inline]
8443#[target_feature(enable = "neon")]
8444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8446#[cfg_attr(
8447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8448    assert_instr(scvtf)
8449)]
8450#[cfg_attr(
8451    not(target_arch = "arm"),
8452    stable(feature = "neon_intrinsics", since = "1.59.0")
8453)]
8454#[cfg_attr(
8455    target_arch = "arm",
8456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8457)]
8458pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
8459    unsafe { simd_cast(a) }
8460}
8461#[doc = "Fixed-point convert to floating-point"]
8462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
8463#[inline]
8464#[target_feature(enable = "neon")]
8465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8467#[cfg_attr(
8468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8469    assert_instr(scvtf)
8470)]
8471#[cfg_attr(
8472    not(target_arch = "arm"),
8473    stable(feature = "neon_intrinsics", since = "1.59.0")
8474)]
8475#[cfg_attr(
8476    target_arch = "arm",
8477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8478)]
8479pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
8480    unsafe { simd_cast(a) }
8481}
8482#[doc = "Fixed-point convert to floating-point"]
8483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
8484#[inline]
8485#[target_feature(enable = "neon")]
8486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8488#[cfg_attr(
8489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8490    assert_instr(ucvtf)
8491)]
8492#[cfg_attr(
8493    not(target_arch = "arm"),
8494    stable(feature = "neon_intrinsics", since = "1.59.0")
8495)]
8496#[cfg_attr(
8497    target_arch = "arm",
8498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8499)]
8500pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
8501    unsafe { simd_cast(a) }
8502}
8503#[doc = "Fixed-point convert to floating-point"]
8504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
8505#[inline]
8506#[target_feature(enable = "neon")]
8507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8509#[cfg_attr(
8510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8511    assert_instr(ucvtf)
8512)]
8513#[cfg_attr(
8514    not(target_arch = "arm"),
8515    stable(feature = "neon_intrinsics", since = "1.59.0")
8516)]
8517#[cfg_attr(
8518    target_arch = "arm",
8519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8520)]
8521pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
8522    unsafe { simd_cast(a) }
8523}
8524#[doc = "Fixed-point convert to floating-point"]
8525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
8526#[inline]
8527#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8529#[cfg_attr(
8530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8531    assert_instr(scvtf, N = 1)
8532)]
8533#[rustc_legacy_const_generics(1)]
8534#[target_feature(enable = "neon,fp16")]
8535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8536pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
8537    static_assert!(N >= 1 && N <= 16);
8538    unsafe extern "unadjusted" {
8539        #[cfg_attr(
8540            target_arch = "arm",
8541            link_name = "llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16"
8542        )]
8543        #[cfg_attr(
8544            any(target_arch = "aarch64", target_arch = "arm64ec"),
8545            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16"
8546        )]
8547        fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t;
8548    }
8549    unsafe { _vcvt_n_f16_s16(a, N) }
8550}
8551#[doc = "Fixed-point convert to floating-point"]
8552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
8553#[inline]
8554#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8556#[cfg_attr(
8557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8558    assert_instr(scvtf, N = 1)
8559)]
8560#[rustc_legacy_const_generics(1)]
8561#[target_feature(enable = "neon,fp16")]
8562#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8563pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
8564    static_assert!(N >= 1 && N <= 16);
8565    unsafe extern "unadjusted" {
8566        #[cfg_attr(
8567            target_arch = "arm",
8568            link_name = "llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16"
8569        )]
8570        #[cfg_attr(
8571            any(target_arch = "aarch64", target_arch = "arm64ec"),
8572            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16"
8573        )]
8574        fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t;
8575    }
8576    unsafe { _vcvtq_n_f16_s16(a, N) }
8577}
8578#[doc = "Fixed-point convert to floating-point"]
8579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
8580#[inline]
8581#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8583#[cfg_attr(
8584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8585    assert_instr(ucvtf, N = 1)
8586)]
8587#[rustc_legacy_const_generics(1)]
8588#[target_feature(enable = "neon,fp16")]
8589#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8590pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
8591    static_assert!(N >= 1 && N <= 16);
8592    unsafe extern "unadjusted" {
8593        #[cfg_attr(
8594            target_arch = "arm",
8595            link_name = "llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16"
8596        )]
8597        #[cfg_attr(
8598            any(target_arch = "aarch64", target_arch = "arm64ec"),
8599            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16"
8600        )]
8601        fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t;
8602    }
8603    unsafe { _vcvt_n_f16_u16(a, N) }
8604}
8605#[doc = "Fixed-point convert to floating-point"]
8606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
8607#[inline]
8608#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8609#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8610#[cfg_attr(
8611    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8612    assert_instr(ucvtf, N = 1)
8613)]
8614#[rustc_legacy_const_generics(1)]
8615#[target_feature(enable = "neon,fp16")]
8616#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8617pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
8618    static_assert!(N >= 1 && N <= 16);
8619    unsafe extern "unadjusted" {
8620        #[cfg_attr(
8621            target_arch = "arm",
8622            link_name = "llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16"
8623        )]
8624        #[cfg_attr(
8625            any(target_arch = "aarch64", target_arch = "arm64ec"),
8626            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16"
8627        )]
8628        fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t;
8629    }
8630    unsafe { _vcvtq_n_f16_u16(a, N) }
8631}
8632#[doc = "Fixed-point convert to floating-point"]
8633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8634#[inline]
8635#[cfg(target_arch = "arm")]
8636#[target_feature(enable = "neon,v7")]
8637#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8638#[rustc_legacy_const_generics(1)]
8639#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8640pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8641    static_assert!(N >= 1 && N <= 32);
8642    unsafe extern "unadjusted" {
8643        #[cfg_attr(
8644            target_arch = "arm",
8645            link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32"
8646        )]
8647        fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8648    }
8649    unsafe { _vcvt_n_f32_s32(a, N) }
8650}
8651#[doc = "Fixed-point convert to floating-point"]
8652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8653#[inline]
8654#[cfg(target_arch = "arm")]
8655#[target_feature(enable = "neon,v7")]
8656#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8657#[rustc_legacy_const_generics(1)]
8658#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8659pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8660    static_assert!(N >= 1 && N <= 32);
8661    unsafe extern "unadjusted" {
8662        #[cfg_attr(
8663            target_arch = "arm",
8664            link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32"
8665        )]
8666        fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8667    }
8668    unsafe { _vcvtq_n_f32_s32(a, N) }
8669}
8670#[doc = "Fixed-point convert to floating-point"]
8671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8672#[inline]
8673#[target_feature(enable = "neon")]
8674#[cfg(not(target_arch = "arm"))]
8675#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8676#[rustc_legacy_const_generics(1)]
8677#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8678pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8679    static_assert!(N >= 1 && N <= 32);
8680    unsafe extern "unadjusted" {
8681        #[cfg_attr(
8682            any(target_arch = "aarch64", target_arch = "arm64ec"),
8683            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32"
8684        )]
8685        fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8686    }
8687    unsafe { _vcvt_n_f32_s32(a, N) }
8688}
8689#[doc = "Fixed-point convert to floating-point"]
8690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8691#[inline]
8692#[target_feature(enable = "neon")]
8693#[cfg(not(target_arch = "arm"))]
8694#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8695#[rustc_legacy_const_generics(1)]
8696#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8697pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8698    static_assert!(N >= 1 && N <= 32);
8699    unsafe extern "unadjusted" {
8700        #[cfg_attr(
8701            any(target_arch = "aarch64", target_arch = "arm64ec"),
8702            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32"
8703        )]
8704        fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8705    }
8706    unsafe { _vcvtq_n_f32_s32(a, N) }
8707}
8708#[doc = "Fixed-point convert to floating-point"]
8709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8710#[inline]
8711#[cfg(target_arch = "arm")]
8712#[target_feature(enable = "neon,v7")]
8713#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8714#[rustc_legacy_const_generics(1)]
8715#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8716pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8717    static_assert!(N >= 1 && N <= 32);
8718    unsafe extern "unadjusted" {
8719        #[cfg_attr(
8720            target_arch = "arm",
8721            link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32"
8722        )]
8723        fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8724    }
8725    unsafe { _vcvt_n_f32_u32(a, N) }
8726}
8727#[doc = "Fixed-point convert to floating-point"]
8728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8729#[inline]
8730#[cfg(target_arch = "arm")]
8731#[target_feature(enable = "neon,v7")]
8732#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8733#[rustc_legacy_const_generics(1)]
8734#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8735pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8736    static_assert!(N >= 1 && N <= 32);
8737    unsafe extern "unadjusted" {
8738        #[cfg_attr(
8739            target_arch = "arm",
8740            link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32"
8741        )]
8742        fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8743    }
8744    unsafe { _vcvtq_n_f32_u32(a, N) }
8745}
8746#[doc = "Fixed-point convert to floating-point"]
8747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8748#[inline]
8749#[target_feature(enable = "neon")]
8750#[cfg(not(target_arch = "arm"))]
8751#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8752#[rustc_legacy_const_generics(1)]
8753#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8754pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8755    static_assert!(N >= 1 && N <= 32);
8756    unsafe extern "unadjusted" {
8757        #[cfg_attr(
8758            any(target_arch = "aarch64", target_arch = "arm64ec"),
8759            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32"
8760        )]
8761        fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8762    }
8763    unsafe { _vcvt_n_f32_u32(a, N) }
8764}
8765#[doc = "Fixed-point convert to floating-point"]
8766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8767#[inline]
8768#[target_feature(enable = "neon")]
8769#[cfg(not(target_arch = "arm"))]
8770#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8771#[rustc_legacy_const_generics(1)]
8772#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8773pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8774    static_assert!(N >= 1 && N <= 32);
8775    unsafe extern "unadjusted" {
8776        #[cfg_attr(
8777            any(target_arch = "aarch64", target_arch = "arm64ec"),
8778            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32"
8779        )]
8780        fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8781    }
8782    unsafe { _vcvtq_n_f32_u32(a, N) }
8783}
8784#[doc = "Floating-point convert to signed fixed-point"]
8785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
8786#[inline]
8787#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8788#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8789#[cfg_attr(
8790    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8791    assert_instr(fcvtzs, N = 1)
8792)]
8793#[rustc_legacy_const_generics(1)]
8794#[target_feature(enable = "neon,fp16")]
8795#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8796pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
8797    static_assert!(N >= 1 && N <= 16);
8798    unsafe extern "unadjusted" {
8799        #[cfg_attr(
8800            target_arch = "arm",
8801            link_name = "llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16"
8802        )]
8803        #[cfg_attr(
8804            any(target_arch = "aarch64", target_arch = "arm64ec"),
8805            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16"
8806        )]
8807        fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t;
8808    }
8809    unsafe { _vcvt_n_s16_f16(a, N) }
8810}
8811#[doc = "Floating-point convert to signed fixed-point"]
8812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
8813#[inline]
8814#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8816#[cfg_attr(
8817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8818    assert_instr(fcvtzs, N = 1)
8819)]
8820#[rustc_legacy_const_generics(1)]
8821#[target_feature(enable = "neon,fp16")]
8822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8823pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
8824    static_assert!(N >= 1 && N <= 16);
8825    unsafe extern "unadjusted" {
8826        #[cfg_attr(
8827            target_arch = "arm",
8828            link_name = "llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16"
8829        )]
8830        #[cfg_attr(
8831            any(target_arch = "aarch64", target_arch = "arm64ec"),
8832            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16"
8833        )]
8834        fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t;
8835    }
8836    unsafe { _vcvtq_n_s16_f16(a, N) }
8837}
8838#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8840#[inline]
8841#[cfg(target_arch = "arm")]
8842#[target_feature(enable = "neon,v7")]
8843#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8844#[rustc_legacy_const_generics(1)]
8845#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8846pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8847    static_assert!(N >= 1 && N <= 32);
8848    unsafe extern "unadjusted" {
8849        #[cfg_attr(
8850            target_arch = "arm",
8851            link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32"
8852        )]
8853        fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8854    }
8855    unsafe { _vcvt_n_s32_f32(a, N) }
8856}
8857#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8859#[inline]
8860#[cfg(target_arch = "arm")]
8861#[target_feature(enable = "neon,v7")]
8862#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8863#[rustc_legacy_const_generics(1)]
8864#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8865pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8866    static_assert!(N >= 1 && N <= 32);
8867    unsafe extern "unadjusted" {
8868        #[cfg_attr(
8869            target_arch = "arm",
8870            link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32"
8871        )]
8872        fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8873    }
8874    unsafe { _vcvtq_n_s32_f32(a, N) }
8875}
8876#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8878#[inline]
8879#[target_feature(enable = "neon")]
8880#[cfg(not(target_arch = "arm"))]
8881#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8882#[rustc_legacy_const_generics(1)]
8883#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8884pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8885    static_assert!(N >= 1 && N <= 32);
8886    unsafe extern "unadjusted" {
8887        #[cfg_attr(
8888            any(target_arch = "aarch64", target_arch = "arm64ec"),
8889            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32"
8890        )]
8891        fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8892    }
8893    unsafe { _vcvt_n_s32_f32(a, N) }
8894}
8895#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8897#[inline]
8898#[target_feature(enable = "neon")]
8899#[cfg(not(target_arch = "arm"))]
8900#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8901#[rustc_legacy_const_generics(1)]
8902#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8903pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8904    static_assert!(N >= 1 && N <= 32);
8905    unsafe extern "unadjusted" {
8906        #[cfg_attr(
8907            any(target_arch = "aarch64", target_arch = "arm64ec"),
8908            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32"
8909        )]
8910        fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8911    }
8912    unsafe { _vcvtq_n_s32_f32(a, N) }
8913}
8914#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
8916#[inline]
8917#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8918#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8919#[cfg_attr(
8920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8921    assert_instr(fcvtzu, N = 1)
8922)]
8923#[rustc_legacy_const_generics(1)]
8924#[target_feature(enable = "neon,fp16")]
8925#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8926pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
8927    static_assert!(N >= 1 && N <= 16);
8928    unsafe extern "unadjusted" {
8929        #[cfg_attr(
8930            target_arch = "arm",
8931            link_name = "llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16"
8932        )]
8933        #[cfg_attr(
8934            any(target_arch = "aarch64", target_arch = "arm64ec"),
8935            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16"
8936        )]
8937        fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t;
8938    }
8939    unsafe { _vcvt_n_u16_f16(a, N) }
8940}
8941#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
8943#[inline]
8944#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8945#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8946#[cfg_attr(
8947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8948    assert_instr(fcvtzu, N = 1)
8949)]
8950#[rustc_legacy_const_generics(1)]
8951#[target_feature(enable = "neon,fp16")]
8952#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8953pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
8954    static_assert!(N >= 1 && N <= 16);
8955    unsafe extern "unadjusted" {
8956        #[cfg_attr(
8957            target_arch = "arm",
8958            link_name = "llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16"
8959        )]
8960        #[cfg_attr(
8961            any(target_arch = "aarch64", target_arch = "arm64ec"),
8962            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16"
8963        )]
8964        fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t;
8965    }
8966    unsafe { _vcvtq_n_u16_f16(a, N) }
8967}
8968#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8970#[inline]
8971#[cfg(target_arch = "arm")]
8972#[target_feature(enable = "neon,v7")]
8973#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8974#[rustc_legacy_const_generics(1)]
8975#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8976pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8977    static_assert!(N >= 1 && N <= 32);
8978    unsafe extern "unadjusted" {
8979        #[cfg_attr(
8980            target_arch = "arm",
8981            link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32"
8982        )]
8983        fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8984    }
8985    unsafe { _vcvt_n_u32_f32(a, N) }
8986}
8987#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8989#[inline]
8990#[cfg(target_arch = "arm")]
8991#[target_feature(enable = "neon,v7")]
8992#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8993#[rustc_legacy_const_generics(1)]
8994#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8995pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8996    static_assert!(N >= 1 && N <= 32);
8997    unsafe extern "unadjusted" {
8998        #[cfg_attr(
8999            target_arch = "arm",
9000            link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32"
9001        )]
9002        fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
9003    }
9004    unsafe { _vcvtq_n_u32_f32(a, N) }
9005}
9006#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
9007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
9008#[inline]
9009#[target_feature(enable = "neon")]
9010#[cfg(not(target_arch = "arm"))]
9011#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
9012#[rustc_legacy_const_generics(1)]
9013#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9014pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
9015    static_assert!(N >= 1 && N <= 32);
9016    unsafe extern "unadjusted" {
9017        #[cfg_attr(
9018            any(target_arch = "aarch64", target_arch = "arm64ec"),
9019            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32"
9020        )]
9021        fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
9022    }
9023    unsafe { _vcvt_n_u32_f32(a, N) }
9024}
9025#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
9026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
9027#[inline]
9028#[target_feature(enable = "neon")]
9029#[cfg(not(target_arch = "arm"))]
9030#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
9031#[rustc_legacy_const_generics(1)]
9032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9033pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
9034    static_assert!(N >= 1 && N <= 32);
9035    unsafe extern "unadjusted" {
9036        #[cfg_attr(
9037            any(target_arch = "aarch64", target_arch = "arm64ec"),
9038            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32"
9039        )]
9040        fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
9041    }
9042    unsafe { _vcvtq_n_u32_f32(a, N) }
9043}
9044#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
9046#[inline]
9047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9049#[cfg_attr(
9050    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9051    assert_instr(fcvtzs)
9052)]
9053#[target_feature(enable = "neon,fp16")]
9054#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9055pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
9056    unsafe { simd_cast(a) }
9057}
9058#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
9060#[inline]
9061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9063#[cfg_attr(
9064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9065    assert_instr(fcvtzs)
9066)]
9067#[target_feature(enable = "neon,fp16")]
9068#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9069pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
9070    unsafe { simd_cast(a) }
9071}
9072#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
9074#[inline]
9075#[target_feature(enable = "neon")]
9076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9078#[cfg_attr(
9079    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9080    assert_instr(fcvtzs)
9081)]
9082#[cfg_attr(
9083    not(target_arch = "arm"),
9084    stable(feature = "neon_intrinsics", since = "1.59.0")
9085)]
9086#[cfg_attr(
9087    target_arch = "arm",
9088    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9089)]
9090pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
9091    unsafe extern "unadjusted" {
9092        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")]
9093        #[cfg_attr(
9094            any(target_arch = "aarch64", target_arch = "arm64ec"),
9095            link_name = "llvm.fptosi.sat.v2i32.v2f32"
9096        )]
9097        fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t;
9098    }
9099    unsafe { _vcvt_s32_f32(a) }
9100}
9101#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
9103#[inline]
9104#[target_feature(enable = "neon")]
9105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9107#[cfg_attr(
9108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9109    assert_instr(fcvtzs)
9110)]
9111#[cfg_attr(
9112    not(target_arch = "arm"),
9113    stable(feature = "neon_intrinsics", since = "1.59.0")
9114)]
9115#[cfg_attr(
9116    target_arch = "arm",
9117    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9118)]
9119pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
9120    unsafe extern "unadjusted" {
9121        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")]
9122        #[cfg_attr(
9123            any(target_arch = "aarch64", target_arch = "arm64ec"),
9124            link_name = "llvm.fptosi.sat.v4i32.v4f32"
9125        )]
9126        fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t;
9127    }
9128    unsafe { _vcvtq_s32_f32(a) }
9129}
9130#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
9132#[inline]
9133#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9135#[cfg_attr(
9136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9137    assert_instr(fcvtzu)
9138)]
9139#[target_feature(enable = "neon,fp16")]
9140#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9141pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
9142    unsafe { simd_cast(a) }
9143}
9144#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
9146#[inline]
9147#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9149#[cfg_attr(
9150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9151    assert_instr(fcvtzu)
9152)]
9153#[target_feature(enable = "neon,fp16")]
9154#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9155pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
9156    unsafe { simd_cast(a) }
9157}
9158#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
9160#[inline]
9161#[target_feature(enable = "neon")]
9162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9164#[cfg_attr(
9165    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9166    assert_instr(fcvtzu)
9167)]
9168#[cfg_attr(
9169    not(target_arch = "arm"),
9170    stable(feature = "neon_intrinsics", since = "1.59.0")
9171)]
9172#[cfg_attr(
9173    target_arch = "arm",
9174    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9175)]
9176pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
9177    unsafe extern "unadjusted" {
9178        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")]
9179        #[cfg_attr(
9180            any(target_arch = "aarch64", target_arch = "arm64ec"),
9181            link_name = "llvm.fptoui.sat.v2i32.v2f32"
9182        )]
9183        fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t;
9184    }
9185    unsafe { _vcvt_u32_f32(a) }
9186}
9187#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
9189#[inline]
9190#[target_feature(enable = "neon")]
9191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9193#[cfg_attr(
9194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9195    assert_instr(fcvtzu)
9196)]
9197#[cfg_attr(
9198    not(target_arch = "arm"),
9199    stable(feature = "neon_intrinsics", since = "1.59.0")
9200)]
9201#[cfg_attr(
9202    target_arch = "arm",
9203    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9204)]
9205pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
9206    unsafe extern "unadjusted" {
9207        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")]
9208        #[cfg_attr(
9209            any(target_arch = "aarch64", target_arch = "arm64ec"),
9210            link_name = "llvm.fptoui.sat.v4i32.v4f32"
9211        )]
9212        fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t;
9213    }
9214    unsafe { _vcvtq_u32_f32(a) }
9215}
9216#[doc = "Dot product arithmetic (indexed)"]
9217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
9218#[inline]
9219#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9220#[target_feature(enable = "neon,dotprod")]
9221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9222#[cfg_attr(
9223    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9224    assert_instr(sdot, LANE = 0)
9225)]
9226#[rustc_legacy_const_generics(3)]
9227#[cfg_attr(
9228    not(target_arch = "arm"),
9229    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9230)]
9231#[cfg_attr(
9232    target_arch = "arm",
9233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9234)]
9235pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9236    static_assert_uimm_bits!(LANE, 1);
9237    unsafe {
9238        let c: int32x2_t = transmute(c);
9239        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9240        vdot_s32(a, b, transmute(c))
9241    }
9242}
9243#[doc = "Dot product arithmetic (indexed)"]
9244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
9245#[inline]
9246#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9247#[target_feature(enable = "neon,dotprod")]
9248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9249#[cfg_attr(
9250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9251    assert_instr(sdot, LANE = 0)
9252)]
9253#[rustc_legacy_const_generics(3)]
9254#[cfg_attr(
9255    not(target_arch = "arm"),
9256    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9257)]
9258#[cfg_attr(
9259    target_arch = "arm",
9260    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9261)]
9262pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
9263    static_assert_uimm_bits!(LANE, 1);
9264    unsafe {
9265        let c: int32x2_t = transmute(c);
9266        let c: int32x4_t =
9267            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9268        vdotq_s32(a, b, transmute(c))
9269    }
9270}
9271#[doc = "Dot product arithmetic (indexed)"]
9272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
9273#[inline]
9274#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9275#[target_feature(enable = "neon,dotprod")]
9276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9277#[cfg_attr(
9278    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9279    assert_instr(udot, LANE = 0)
9280)]
9281#[rustc_legacy_const_generics(3)]
9282#[cfg_attr(
9283    not(target_arch = "arm"),
9284    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9285)]
9286#[cfg_attr(
9287    target_arch = "arm",
9288    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9289)]
9290pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9291    static_assert_uimm_bits!(LANE, 1);
9292    unsafe {
9293        let c: uint32x2_t = transmute(c);
9294        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9295        vdot_u32(a, b, transmute(c))
9296    }
9297}
9298#[doc = "Dot product arithmetic (indexed)"]
9299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
9300#[inline]
9301#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9302#[target_feature(enable = "neon,dotprod")]
9303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9304#[cfg_attr(
9305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9306    assert_instr(udot, LANE = 0)
9307)]
9308#[rustc_legacy_const_generics(3)]
9309#[cfg_attr(
9310    not(target_arch = "arm"),
9311    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9312)]
9313#[cfg_attr(
9314    target_arch = "arm",
9315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9316)]
9317pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
9318    static_assert_uimm_bits!(LANE, 1);
9319    unsafe {
9320        let c: uint32x2_t = transmute(c);
9321        let c: uint32x4_t =
9322            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9323        vdotq_u32(a, b, transmute(c))
9324    }
9325}
9326#[doc = "Dot product arithmetic (vector)"]
9327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
9328#[inline]
9329#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9330#[target_feature(enable = "neon,dotprod")]
9331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9332#[cfg_attr(
9333    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9334    assert_instr(sdot)
9335)]
9336#[cfg_attr(
9337    not(target_arch = "arm"),
9338    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9339)]
9340#[cfg_attr(
9341    target_arch = "arm",
9342    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9343)]
9344pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9345    unsafe extern "unadjusted" {
9346        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")]
9347        #[cfg_attr(
9348            any(target_arch = "aarch64", target_arch = "arm64ec"),
9349            link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8"
9350        )]
9351        fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t;
9352    }
9353    unsafe { _vdot_s32(a, b, c) }
9354}
9355#[doc = "Dot product arithmetic (vector)"]
9356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
9357#[inline]
9358#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9359#[target_feature(enable = "neon,dotprod")]
9360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9361#[cfg_attr(
9362    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9363    assert_instr(sdot)
9364)]
9365#[cfg_attr(
9366    not(target_arch = "arm"),
9367    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9368)]
9369#[cfg_attr(
9370    target_arch = "arm",
9371    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9372)]
9373pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
9374    unsafe extern "unadjusted" {
9375        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")]
9376        #[cfg_attr(
9377            any(target_arch = "aarch64", target_arch = "arm64ec"),
9378            link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8"
9379        )]
9380        fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
9381    }
9382    unsafe { _vdotq_s32(a, b, c) }
9383}
9384#[doc = "Dot product arithmetic (vector)"]
9385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
9386#[inline]
9387#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9388#[target_feature(enable = "neon,dotprod")]
9389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9390#[cfg_attr(
9391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9392    assert_instr(udot)
9393)]
9394#[cfg_attr(
9395    not(target_arch = "arm"),
9396    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9397)]
9398#[cfg_attr(
9399    target_arch = "arm",
9400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9401)]
9402pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9403    unsafe extern "unadjusted" {
9404        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")]
9405        #[cfg_attr(
9406            any(target_arch = "aarch64", target_arch = "arm64ec"),
9407            link_name = "llvm.aarch64.neon.udot.v2i32.v8i8"
9408        )]
9409        fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t;
9410    }
9411    unsafe { _vdot_u32(a, b, c) }
9412}
9413#[doc = "Dot product arithmetic (vector)"]
9414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
9415#[inline]
9416#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9417#[target_feature(enable = "neon,dotprod")]
9418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9419#[cfg_attr(
9420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9421    assert_instr(udot)
9422)]
9423#[cfg_attr(
9424    not(target_arch = "arm"),
9425    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9426)]
9427#[cfg_attr(
9428    target_arch = "arm",
9429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9430)]
9431pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
9432    unsafe extern "unadjusted" {
9433        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")]
9434        #[cfg_attr(
9435            any(target_arch = "aarch64", target_arch = "arm64ec"),
9436            link_name = "llvm.aarch64.neon.udot.v4i32.v16i8"
9437        )]
9438        fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
9439    }
9440    unsafe { _vdotq_u32(a, b, c) }
9441}
9442#[doc = "Set all vector lanes to the same value"]
9443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
9444#[inline]
9445#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9446#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9447#[cfg_attr(
9448    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9449    assert_instr(dup, N = 2)
9450)]
9451#[rustc_legacy_const_generics(1)]
9452#[target_feature(enable = "neon,fp16")]
9453#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9454pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
9455    static_assert_uimm_bits!(N, 2);
9456    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9457}
9458#[doc = "Set all vector lanes to the same value"]
9459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
9460#[inline]
9461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9463#[cfg_attr(
9464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9465    assert_instr(dup, N = 2)
9466)]
9467#[rustc_legacy_const_generics(1)]
9468#[target_feature(enable = "neon,fp16")]
9469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9470pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
9471    static_assert_uimm_bits!(N, 2);
9472    unsafe {
9473        simd_shuffle!(
9474            a,
9475            a,
9476            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9477        )
9478    }
9479}
9480#[doc = "Set all vector lanes to the same value"]
9481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
9482#[inline]
9483#[target_feature(enable = "neon")]
9484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9486#[cfg_attr(
9487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9488    assert_instr(dup, N = 1)
9489)]
9490#[rustc_legacy_const_generics(1)]
9491#[cfg_attr(
9492    not(target_arch = "arm"),
9493    stable(feature = "neon_intrinsics", since = "1.59.0")
9494)]
9495#[cfg_attr(
9496    target_arch = "arm",
9497    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9498)]
9499pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
9500    static_assert_uimm_bits!(N, 1);
9501    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9502}
9503#[doc = "Set all vector lanes to the same value"]
9504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
9505#[inline]
9506#[target_feature(enable = "neon")]
9507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9509#[cfg_attr(
9510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9511    assert_instr(dup, N = 1)
9512)]
9513#[rustc_legacy_const_generics(1)]
9514#[cfg_attr(
9515    not(target_arch = "arm"),
9516    stable(feature = "neon_intrinsics", since = "1.59.0")
9517)]
9518#[cfg_attr(
9519    target_arch = "arm",
9520    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9521)]
9522pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
9523    static_assert_uimm_bits!(N, 1);
9524    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9525}
9526#[doc = "Set all vector lanes to the same value"]
9527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
9528#[inline]
9529#[target_feature(enable = "neon")]
9530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9531#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9532#[cfg_attr(
9533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9534    assert_instr(dup, N = 1)
9535)]
9536#[rustc_legacy_const_generics(1)]
9537#[cfg_attr(
9538    not(target_arch = "arm"),
9539    stable(feature = "neon_intrinsics", since = "1.59.0")
9540)]
9541#[cfg_attr(
9542    target_arch = "arm",
9543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9544)]
9545pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
9546    static_assert_uimm_bits!(N, 1);
9547    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9548}
9549#[doc = "Set all vector lanes to the same value"]
9550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
9551#[inline]
9552#[target_feature(enable = "neon")]
9553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9554#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9555#[cfg_attr(
9556    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9557    assert_instr(dup, N = 1)
9558)]
9559#[rustc_legacy_const_generics(1)]
9560#[cfg_attr(
9561    not(target_arch = "arm"),
9562    stable(feature = "neon_intrinsics", since = "1.59.0")
9563)]
9564#[cfg_attr(
9565    target_arch = "arm",
9566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9567)]
9568pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
9569    static_assert_uimm_bits!(N, 1);
9570    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9571}
9572#[doc = "Set all vector lanes to the same value"]
9573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
9574#[inline]
9575#[target_feature(enable = "neon")]
9576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9577#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9578#[cfg_attr(
9579    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9580    assert_instr(dup, N = 1)
9581)]
9582#[rustc_legacy_const_generics(1)]
9583#[cfg_attr(
9584    not(target_arch = "arm"),
9585    stable(feature = "neon_intrinsics", since = "1.59.0")
9586)]
9587#[cfg_attr(
9588    target_arch = "arm",
9589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9590)]
9591pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
9592    static_assert_uimm_bits!(N, 1);
9593    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9594}
9595#[doc = "Set all vector lanes to the same value"]
9596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
9597#[inline]
9598#[target_feature(enable = "neon")]
9599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9601#[cfg_attr(
9602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9603    assert_instr(dup, N = 1)
9604)]
9605#[rustc_legacy_const_generics(1)]
9606#[cfg_attr(
9607    not(target_arch = "arm"),
9608    stable(feature = "neon_intrinsics", since = "1.59.0")
9609)]
9610#[cfg_attr(
9611    target_arch = "arm",
9612    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9613)]
9614pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
9615    static_assert_uimm_bits!(N, 1);
9616    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9617}
9618#[doc = "Set all vector lanes to the same value"]
9619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
9620#[inline]
9621#[target_feature(enable = "neon")]
9622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9623#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9624#[cfg_attr(
9625    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9626    assert_instr(dup, N = 2)
9627)]
9628#[rustc_legacy_const_generics(1)]
9629#[cfg_attr(
9630    not(target_arch = "arm"),
9631    stable(feature = "neon_intrinsics", since = "1.59.0")
9632)]
9633#[cfg_attr(
9634    target_arch = "arm",
9635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9636)]
9637pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
9638    static_assert_uimm_bits!(N, 2);
9639    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9640}
9641#[doc = "Set all vector lanes to the same value"]
9642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
9643#[inline]
9644#[target_feature(enable = "neon")]
9645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9646#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9647#[cfg_attr(
9648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9649    assert_instr(dup, N = 2)
9650)]
9651#[rustc_legacy_const_generics(1)]
9652#[cfg_attr(
9653    not(target_arch = "arm"),
9654    stable(feature = "neon_intrinsics", since = "1.59.0")
9655)]
9656#[cfg_attr(
9657    target_arch = "arm",
9658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9659)]
9660pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
9661    static_assert_uimm_bits!(N, 2);
9662    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9663}
9664#[doc = "Set all vector lanes to the same value"]
9665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
9666#[inline]
9667#[target_feature(enable = "neon")]
9668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9670#[cfg_attr(
9671    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9672    assert_instr(dup, N = 2)
9673)]
9674#[rustc_legacy_const_generics(1)]
9675#[cfg_attr(
9676    not(target_arch = "arm"),
9677    stable(feature = "neon_intrinsics", since = "1.59.0")
9678)]
9679#[cfg_attr(
9680    target_arch = "arm",
9681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9682)]
9683pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
9684    static_assert_uimm_bits!(N, 2);
9685    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9686}
9687#[doc = "Set all vector lanes to the same value"]
9688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
9689#[inline]
9690#[target_feature(enable = "neon")]
9691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9693#[cfg_attr(
9694    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9695    assert_instr(dup, N = 2)
9696)]
9697#[rustc_legacy_const_generics(1)]
9698#[cfg_attr(
9699    not(target_arch = "arm"),
9700    stable(feature = "neon_intrinsics", since = "1.59.0")
9701)]
9702#[cfg_attr(
9703    target_arch = "arm",
9704    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9705)]
9706pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
9707    static_assert_uimm_bits!(N, 2);
9708    unsafe {
9709        simd_shuffle!(
9710            a,
9711            a,
9712            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9713        )
9714    }
9715}
9716#[doc = "Set all vector lanes to the same value"]
9717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
9718#[inline]
9719#[target_feature(enable = "neon")]
9720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9722#[cfg_attr(
9723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9724    assert_instr(dup, N = 2)
9725)]
9726#[rustc_legacy_const_generics(1)]
9727#[cfg_attr(
9728    not(target_arch = "arm"),
9729    stable(feature = "neon_intrinsics", since = "1.59.0")
9730)]
9731#[cfg_attr(
9732    target_arch = "arm",
9733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9734)]
9735pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
9736    static_assert_uimm_bits!(N, 2);
9737    unsafe {
9738        simd_shuffle!(
9739            a,
9740            a,
9741            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9742        )
9743    }
9744}
9745#[doc = "Set all vector lanes to the same value"]
9746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
9747#[inline]
9748#[target_feature(enable = "neon")]
9749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9750#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9751#[cfg_attr(
9752    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9753    assert_instr(dup, N = 2)
9754)]
9755#[rustc_legacy_const_generics(1)]
9756#[cfg_attr(
9757    not(target_arch = "arm"),
9758    stable(feature = "neon_intrinsics", since = "1.59.0")
9759)]
9760#[cfg_attr(
9761    target_arch = "arm",
9762    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9763)]
9764pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
9765    static_assert_uimm_bits!(N, 2);
9766    unsafe {
9767        simd_shuffle!(
9768            a,
9769            a,
9770            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9771        )
9772    }
9773}
9774#[doc = "Set all vector lanes to the same value"]
9775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
9776#[inline]
9777#[target_feature(enable = "neon")]
9778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9780#[cfg_attr(
9781    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9782    assert_instr(dup, N = 4)
9783)]
9784#[rustc_legacy_const_generics(1)]
9785#[cfg_attr(
9786    not(target_arch = "arm"),
9787    stable(feature = "neon_intrinsics", since = "1.59.0")
9788)]
9789#[cfg_attr(
9790    target_arch = "arm",
9791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9792)]
9793pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
9794    static_assert_uimm_bits!(N, 3);
9795    unsafe {
9796        simd_shuffle!(
9797            a,
9798            a,
9799            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9800        )
9801    }
9802}
9803#[doc = "Set all vector lanes to the same value"]
9804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
9805#[inline]
9806#[target_feature(enable = "neon")]
9807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9809#[cfg_attr(
9810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9811    assert_instr(dup, N = 4)
9812)]
9813#[rustc_legacy_const_generics(1)]
9814#[cfg_attr(
9815    not(target_arch = "arm"),
9816    stable(feature = "neon_intrinsics", since = "1.59.0")
9817)]
9818#[cfg_attr(
9819    target_arch = "arm",
9820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9821)]
9822pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
9823    static_assert_uimm_bits!(N, 3);
9824    unsafe {
9825        simd_shuffle!(
9826            a,
9827            a,
9828            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9829        )
9830    }
9831}
9832#[doc = "Set all vector lanes to the same value"]
9833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
9834#[inline]
9835#[target_feature(enable = "neon")]
9836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9837#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9838#[cfg_attr(
9839    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9840    assert_instr(dup, N = 4)
9841)]
9842#[rustc_legacy_const_generics(1)]
9843#[cfg_attr(
9844    not(target_arch = "arm"),
9845    stable(feature = "neon_intrinsics", since = "1.59.0")
9846)]
9847#[cfg_attr(
9848    target_arch = "arm",
9849    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9850)]
9851pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
9852    static_assert_uimm_bits!(N, 3);
9853    unsafe {
9854        simd_shuffle!(
9855            a,
9856            a,
9857            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9858        )
9859    }
9860}
9861#[doc = "Set all vector lanes to the same value"]
9862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
9863#[inline]
9864#[target_feature(enable = "neon")]
9865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9866#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9867#[cfg_attr(
9868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9869    assert_instr(dup, N = 4)
9870)]
9871#[rustc_legacy_const_generics(1)]
9872#[cfg_attr(
9873    not(target_arch = "arm"),
9874    stable(feature = "neon_intrinsics", since = "1.59.0")
9875)]
9876#[cfg_attr(
9877    target_arch = "arm",
9878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9879)]
9880pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
9881    static_assert_uimm_bits!(N, 3);
9882    unsafe {
9883        simd_shuffle!(
9884            a,
9885            a,
9886            [
9887                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9888                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9889            ]
9890        )
9891    }
9892}
9893#[doc = "Set all vector lanes to the same value"]
9894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
9895#[inline]
9896#[target_feature(enable = "neon")]
9897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9899#[cfg_attr(
9900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9901    assert_instr(dup, N = 4)
9902)]
9903#[rustc_legacy_const_generics(1)]
9904#[cfg_attr(
9905    not(target_arch = "arm"),
9906    stable(feature = "neon_intrinsics", since = "1.59.0")
9907)]
9908#[cfg_attr(
9909    target_arch = "arm",
9910    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9911)]
9912pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
9913    static_assert_uimm_bits!(N, 3);
9914    unsafe {
9915        simd_shuffle!(
9916            a,
9917            a,
9918            [
9919                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9920                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9921            ]
9922        )
9923    }
9924}
9925#[doc = "Set all vector lanes to the same value"]
9926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
9927#[inline]
9928#[target_feature(enable = "neon")]
9929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9930#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9931#[cfg_attr(
9932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9933    assert_instr(dup, N = 4)
9934)]
9935#[rustc_legacy_const_generics(1)]
9936#[cfg_attr(
9937    not(target_arch = "arm"),
9938    stable(feature = "neon_intrinsics", since = "1.59.0")
9939)]
9940#[cfg_attr(
9941    target_arch = "arm",
9942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9943)]
9944pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
9945    static_assert_uimm_bits!(N, 3);
9946    unsafe {
9947        simd_shuffle!(
9948            a,
9949            a,
9950            [
9951                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9952                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9953            ]
9954        )
9955    }
9956}
9957#[doc = "Set all vector lanes to the same value"]
9958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
9959#[inline]
9960#[target_feature(enable = "neon")]
9961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9963#[cfg_attr(
9964    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9965    assert_instr(nop, N = 0)
9966)]
9967#[rustc_legacy_const_generics(1)]
9968#[cfg_attr(
9969    not(target_arch = "arm"),
9970    stable(feature = "neon_intrinsics", since = "1.59.0")
9971)]
9972#[cfg_attr(
9973    target_arch = "arm",
9974    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9975)]
9976pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
9977    static_assert!(N == 0);
9978    a
9979}
9980#[doc = "Set all vector lanes to the same value"]
9981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
9982#[inline]
9983#[target_feature(enable = "neon")]
9984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9986#[cfg_attr(
9987    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9988    assert_instr(nop, N = 0)
9989)]
9990#[rustc_legacy_const_generics(1)]
9991#[cfg_attr(
9992    not(target_arch = "arm"),
9993    stable(feature = "neon_intrinsics", since = "1.59.0")
9994)]
9995#[cfg_attr(
9996    target_arch = "arm",
9997    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9998)]
9999pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
10000    static_assert!(N == 0);
10001    a
10002}
10003#[doc = "Set all vector lanes to the same value"]
10004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
10005#[inline]
10006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10008#[cfg_attr(
10009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10010    assert_instr(dup, N = 4)
10011)]
10012#[rustc_legacy_const_generics(1)]
10013#[target_feature(enable = "neon,fp16")]
10014#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10015pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
10016    static_assert_uimm_bits!(N, 3);
10017    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10018}
10019#[doc = "Set all vector lanes to the same value"]
10020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
10021#[inline]
10022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10024#[cfg_attr(
10025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10026    assert_instr(dup, N = 4)
10027)]
10028#[rustc_legacy_const_generics(1)]
10029#[target_feature(enable = "neon,fp16")]
10030#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10031pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
10032    static_assert_uimm_bits!(N, 3);
10033    unsafe {
10034        simd_shuffle!(
10035            a,
10036            a,
10037            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10038        )
10039    }
10040}
10041#[doc = "Set all vector lanes to the same value"]
10042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
10043#[inline]
10044#[target_feature(enable = "neon")]
10045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10046#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10047#[cfg_attr(
10048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10049    assert_instr(dup, N = 2)
10050)]
10051#[rustc_legacy_const_generics(1)]
10052#[cfg_attr(
10053    not(target_arch = "arm"),
10054    stable(feature = "neon_intrinsics", since = "1.59.0")
10055)]
10056#[cfg_attr(
10057    target_arch = "arm",
10058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10059)]
10060pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
10061    static_assert_uimm_bits!(N, 2);
10062    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10063}
10064#[doc = "Set all vector lanes to the same value"]
10065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
10066#[inline]
10067#[target_feature(enable = "neon")]
10068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10069#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10070#[cfg_attr(
10071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10072    assert_instr(dup, N = 2)
10073)]
10074#[rustc_legacy_const_generics(1)]
10075#[cfg_attr(
10076    not(target_arch = "arm"),
10077    stable(feature = "neon_intrinsics", since = "1.59.0")
10078)]
10079#[cfg_attr(
10080    target_arch = "arm",
10081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10082)]
10083pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
10084    static_assert_uimm_bits!(N, 2);
10085    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10086}
10087#[doc = "Set all vector lanes to the same value"]
10088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
10089#[inline]
10090#[target_feature(enable = "neon")]
10091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10092#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10093#[cfg_attr(
10094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10095    assert_instr(dup, N = 2)
10096)]
10097#[rustc_legacy_const_generics(1)]
10098#[cfg_attr(
10099    not(target_arch = "arm"),
10100    stable(feature = "neon_intrinsics", since = "1.59.0")
10101)]
10102#[cfg_attr(
10103    target_arch = "arm",
10104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10105)]
10106pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
10107    static_assert_uimm_bits!(N, 2);
10108    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10109}
10110#[doc = "Set all vector lanes to the same value"]
10111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
10112#[inline]
10113#[target_feature(enable = "neon")]
10114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10115#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10116#[cfg_attr(
10117    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10118    assert_instr(dup, N = 2)
10119)]
10120#[rustc_legacy_const_generics(1)]
10121#[cfg_attr(
10122    not(target_arch = "arm"),
10123    stable(feature = "neon_intrinsics", since = "1.59.0")
10124)]
10125#[cfg_attr(
10126    target_arch = "arm",
10127    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10128)]
10129pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
10130    static_assert_uimm_bits!(N, 2);
10131    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10132}
10133#[doc = "Set all vector lanes to the same value"]
10134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
10135#[inline]
10136#[target_feature(enable = "neon")]
10137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10138#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10139#[cfg_attr(
10140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10141    assert_instr(dup, N = 2)
10142)]
10143#[rustc_legacy_const_generics(1)]
10144#[cfg_attr(
10145    not(target_arch = "arm"),
10146    stable(feature = "neon_intrinsics", since = "1.59.0")
10147)]
10148#[cfg_attr(
10149    target_arch = "arm",
10150    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10151)]
10152pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
10153    static_assert_uimm_bits!(N, 2);
10154    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10155}
10156#[doc = "Set all vector lanes to the same value"]
10157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
10158#[inline]
10159#[target_feature(enable = "neon")]
10160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10161#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10162#[cfg_attr(
10163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10164    assert_instr(dup, N = 2)
10165)]
10166#[rustc_legacy_const_generics(1)]
10167#[cfg_attr(
10168    not(target_arch = "arm"),
10169    stable(feature = "neon_intrinsics", since = "1.59.0")
10170)]
10171#[cfg_attr(
10172    target_arch = "arm",
10173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10174)]
10175pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
10176    static_assert_uimm_bits!(N, 2);
10177    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10178}
10179#[doc = "Set all vector lanes to the same value"]
10180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
10181#[inline]
10182#[target_feature(enable = "neon")]
10183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10184#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10185#[cfg_attr(
10186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10187    assert_instr(dup, N = 4)
10188)]
10189#[rustc_legacy_const_generics(1)]
10190#[cfg_attr(
10191    not(target_arch = "arm"),
10192    stable(feature = "neon_intrinsics", since = "1.59.0")
10193)]
10194#[cfg_attr(
10195    target_arch = "arm",
10196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10197)]
10198pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
10199    static_assert_uimm_bits!(N, 3);
10200    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10201}
10202#[doc = "Set all vector lanes to the same value"]
10203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
10204#[inline]
10205#[target_feature(enable = "neon")]
10206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10207#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10208#[cfg_attr(
10209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10210    assert_instr(dup, N = 4)
10211)]
10212#[rustc_legacy_const_generics(1)]
10213#[cfg_attr(
10214    not(target_arch = "arm"),
10215    stable(feature = "neon_intrinsics", since = "1.59.0")
10216)]
10217#[cfg_attr(
10218    target_arch = "arm",
10219    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10220)]
10221pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
10222    static_assert_uimm_bits!(N, 3);
10223    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10224}
10225#[doc = "Set all vector lanes to the same value"]
10226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
10227#[inline]
10228#[target_feature(enable = "neon")]
10229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10230#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10231#[cfg_attr(
10232    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10233    assert_instr(dup, N = 4)
10234)]
10235#[rustc_legacy_const_generics(1)]
10236#[cfg_attr(
10237    not(target_arch = "arm"),
10238    stable(feature = "neon_intrinsics", since = "1.59.0")
10239)]
10240#[cfg_attr(
10241    target_arch = "arm",
10242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10243)]
10244pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
10245    static_assert_uimm_bits!(N, 3);
10246    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10247}
10248#[doc = "Set all vector lanes to the same value"]
10249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
10250#[inline]
10251#[target_feature(enable = "neon")]
10252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10253#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10254#[cfg_attr(
10255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10256    assert_instr(dup, N = 4)
10257)]
10258#[rustc_legacy_const_generics(1)]
10259#[cfg_attr(
10260    not(target_arch = "arm"),
10261    stable(feature = "neon_intrinsics", since = "1.59.0")
10262)]
10263#[cfg_attr(
10264    target_arch = "arm",
10265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10266)]
10267pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
10268    static_assert_uimm_bits!(N, 3);
10269    unsafe {
10270        simd_shuffle!(
10271            a,
10272            a,
10273            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10274        )
10275    }
10276}
10277#[doc = "Set all vector lanes to the same value"]
10278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
10279#[inline]
10280#[target_feature(enable = "neon")]
10281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10283#[cfg_attr(
10284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10285    assert_instr(dup, N = 4)
10286)]
10287#[rustc_legacy_const_generics(1)]
10288#[cfg_attr(
10289    not(target_arch = "arm"),
10290    stable(feature = "neon_intrinsics", since = "1.59.0")
10291)]
10292#[cfg_attr(
10293    target_arch = "arm",
10294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10295)]
10296pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
10297    static_assert_uimm_bits!(N, 3);
10298    unsafe {
10299        simd_shuffle!(
10300            a,
10301            a,
10302            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10303        )
10304    }
10305}
10306#[doc = "Set all vector lanes to the same value"]
10307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
10308#[inline]
10309#[target_feature(enable = "neon")]
10310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10312#[cfg_attr(
10313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10314    assert_instr(dup, N = 4)
10315)]
10316#[rustc_legacy_const_generics(1)]
10317#[cfg_attr(
10318    not(target_arch = "arm"),
10319    stable(feature = "neon_intrinsics", since = "1.59.0")
10320)]
10321#[cfg_attr(
10322    target_arch = "arm",
10323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10324)]
10325pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
10326    static_assert_uimm_bits!(N, 3);
10327    unsafe {
10328        simd_shuffle!(
10329            a,
10330            a,
10331            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10332        )
10333    }
10334}
10335#[doc = "Set all vector lanes to the same value"]
10336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
10337#[inline]
10338#[target_feature(enable = "neon")]
10339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10341#[cfg_attr(
10342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10343    assert_instr(dup, N = 8)
10344)]
10345#[rustc_legacy_const_generics(1)]
10346#[cfg_attr(
10347    not(target_arch = "arm"),
10348    stable(feature = "neon_intrinsics", since = "1.59.0")
10349)]
10350#[cfg_attr(
10351    target_arch = "arm",
10352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10353)]
10354pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
10355    static_assert_uimm_bits!(N, 4);
10356    unsafe {
10357        simd_shuffle!(
10358            a,
10359            a,
10360            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10361        )
10362    }
10363}
10364#[doc = "Set all vector lanes to the same value"]
10365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
10366#[inline]
10367#[target_feature(enable = "neon")]
10368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10370#[cfg_attr(
10371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10372    assert_instr(dup, N = 8)
10373)]
10374#[rustc_legacy_const_generics(1)]
10375#[cfg_attr(
10376    not(target_arch = "arm"),
10377    stable(feature = "neon_intrinsics", since = "1.59.0")
10378)]
10379#[cfg_attr(
10380    target_arch = "arm",
10381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10382)]
10383pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
10384    static_assert_uimm_bits!(N, 4);
10385    unsafe {
10386        simd_shuffle!(
10387            a,
10388            a,
10389            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10390        )
10391    }
10392}
10393#[doc = "Set all vector lanes to the same value"]
10394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
10395#[inline]
10396#[target_feature(enable = "neon")]
10397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10398#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10399#[cfg_attr(
10400    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10401    assert_instr(dup, N = 8)
10402)]
10403#[rustc_legacy_const_generics(1)]
10404#[cfg_attr(
10405    not(target_arch = "arm"),
10406    stable(feature = "neon_intrinsics", since = "1.59.0")
10407)]
10408#[cfg_attr(
10409    target_arch = "arm",
10410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10411)]
10412pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
10413    static_assert_uimm_bits!(N, 4);
10414    unsafe {
10415        simd_shuffle!(
10416            a,
10417            a,
10418            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10419        )
10420    }
10421}
10422#[doc = "Set all vector lanes to the same value"]
10423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
10424#[inline]
10425#[target_feature(enable = "neon")]
10426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10427#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10428#[cfg_attr(
10429    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10430    assert_instr(dup, N = 8)
10431)]
10432#[rustc_legacy_const_generics(1)]
10433#[cfg_attr(
10434    not(target_arch = "arm"),
10435    stable(feature = "neon_intrinsics", since = "1.59.0")
10436)]
10437#[cfg_attr(
10438    target_arch = "arm",
10439    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10440)]
10441pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
10442    static_assert_uimm_bits!(N, 4);
10443    unsafe {
10444        simd_shuffle!(
10445            a,
10446            a,
10447            [
10448                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10449                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10450            ]
10451        )
10452    }
10453}
10454#[doc = "Set all vector lanes to the same value"]
10455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
10456#[inline]
10457#[target_feature(enable = "neon")]
10458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10460#[cfg_attr(
10461    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10462    assert_instr(dup, N = 8)
10463)]
10464#[rustc_legacy_const_generics(1)]
10465#[cfg_attr(
10466    not(target_arch = "arm"),
10467    stable(feature = "neon_intrinsics", since = "1.59.0")
10468)]
10469#[cfg_attr(
10470    target_arch = "arm",
10471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10472)]
10473pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
10474    static_assert_uimm_bits!(N, 4);
10475    unsafe {
10476        simd_shuffle!(
10477            a,
10478            a,
10479            [
10480                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10481                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10482            ]
10483        )
10484    }
10485}
10486#[doc = "Set all vector lanes to the same value"]
10487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
10488#[inline]
10489#[target_feature(enable = "neon")]
10490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10491#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10492#[cfg_attr(
10493    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10494    assert_instr(dup, N = 8)
10495)]
10496#[rustc_legacy_const_generics(1)]
10497#[cfg_attr(
10498    not(target_arch = "arm"),
10499    stable(feature = "neon_intrinsics", since = "1.59.0")
10500)]
10501#[cfg_attr(
10502    target_arch = "arm",
10503    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10504)]
10505pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
10506    static_assert_uimm_bits!(N, 4);
10507    unsafe {
10508        simd_shuffle!(
10509            a,
10510            a,
10511            [
10512                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10513                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10514            ]
10515        )
10516    }
10517}
10518#[doc = "Set all vector lanes to the same value"]
10519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
10520#[inline]
10521#[target_feature(enable = "neon")]
10522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10524#[cfg_attr(
10525    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10526    assert_instr(nop, N = 1)
10527)]
10528#[rustc_legacy_const_generics(1)]
10529#[cfg_attr(
10530    not(target_arch = "arm"),
10531    stable(feature = "neon_intrinsics", since = "1.59.0")
10532)]
10533#[cfg_attr(
10534    target_arch = "arm",
10535    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10536)]
10537pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
10538    static_assert_uimm_bits!(N, 1);
10539    unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
10540}
10541#[doc = "Set all vector lanes to the same value"]
10542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
10543#[inline]
10544#[target_feature(enable = "neon")]
10545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10547#[cfg_attr(
10548    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10549    assert_instr(nop, N = 1)
10550)]
10551#[rustc_legacy_const_generics(1)]
10552#[cfg_attr(
10553    not(target_arch = "arm"),
10554    stable(feature = "neon_intrinsics", since = "1.59.0")
10555)]
10556#[cfg_attr(
10557    target_arch = "arm",
10558    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10559)]
10560pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
10561    static_assert_uimm_bits!(N, 1);
10562    unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
10563}
10564#[doc = "Create a new vector with all lanes set to a value"]
10565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
10566#[inline]
10567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10569#[cfg_attr(
10570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10571    assert_instr(dup)
10572)]
10573#[target_feature(enable = "neon,fp16")]
10574#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10575pub fn vdup_n_f16(a: f16) -> float16x4_t {
10576    float16x4_t::splat(a)
10577}
10578#[doc = "Create a new vector with all lanes set to a value"]
10579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
10580#[inline]
10581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10583#[cfg_attr(
10584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10585    assert_instr(dup)
10586)]
10587#[target_feature(enable = "neon,fp16")]
10588#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10589pub fn vdupq_n_f16(a: f16) -> float16x8_t {
10590    float16x8_t::splat(a)
10591}
10592#[doc = "Duplicate vector element to vector or scalar"]
10593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
10594#[inline]
10595#[target_feature(enable = "neon")]
10596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10597#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10598#[cfg_attr(
10599    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10600    assert_instr(dup)
10601)]
10602#[cfg_attr(
10603    not(target_arch = "arm"),
10604    stable(feature = "neon_intrinsics", since = "1.59.0")
10605)]
10606#[cfg_attr(
10607    target_arch = "arm",
10608    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10609)]
10610pub fn vdup_n_f32(value: f32) -> float32x2_t {
10611    float32x2_t::splat(value)
10612}
10613#[doc = "Duplicate vector element to vector or scalar"]
10614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
10615#[inline]
10616#[target_feature(enable = "neon")]
10617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10618#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10619#[cfg_attr(
10620    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10621    assert_instr(dup)
10622)]
10623#[cfg_attr(
10624    not(target_arch = "arm"),
10625    stable(feature = "neon_intrinsics", since = "1.59.0")
10626)]
10627#[cfg_attr(
10628    target_arch = "arm",
10629    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10630)]
10631pub fn vdup_n_p16(value: p16) -> poly16x4_t {
10632    poly16x4_t::splat(value)
10633}
10634#[doc = "Duplicate vector element to vector or scalar"]
10635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
10636#[inline]
10637#[target_feature(enable = "neon")]
10638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10639#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10640#[cfg_attr(
10641    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10642    assert_instr(dup)
10643)]
10644#[cfg_attr(
10645    not(target_arch = "arm"),
10646    stable(feature = "neon_intrinsics", since = "1.59.0")
10647)]
10648#[cfg_attr(
10649    target_arch = "arm",
10650    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10651)]
10652pub fn vdup_n_p8(value: p8) -> poly8x8_t {
10653    poly8x8_t::splat(value)
10654}
10655#[doc = "Duplicate vector element to vector or scalar"]
10656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
10657#[inline]
10658#[target_feature(enable = "neon")]
10659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10661#[cfg_attr(
10662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10663    assert_instr(dup)
10664)]
10665#[cfg_attr(
10666    not(target_arch = "arm"),
10667    stable(feature = "neon_intrinsics", since = "1.59.0")
10668)]
10669#[cfg_attr(
10670    target_arch = "arm",
10671    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10672)]
10673pub fn vdup_n_s16(value: i16) -> int16x4_t {
10674    int16x4_t::splat(value)
10675}
10676#[doc = "Duplicate vector element to vector or scalar"]
10677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
10678#[inline]
10679#[target_feature(enable = "neon")]
10680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10681#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10682#[cfg_attr(
10683    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10684    assert_instr(dup)
10685)]
10686#[cfg_attr(
10687    not(target_arch = "arm"),
10688    stable(feature = "neon_intrinsics", since = "1.59.0")
10689)]
10690#[cfg_attr(
10691    target_arch = "arm",
10692    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10693)]
10694pub fn vdup_n_s32(value: i32) -> int32x2_t {
10695    int32x2_t::splat(value)
10696}
10697#[doc = "Duplicate vector element to vector or scalar"]
10698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
10699#[inline]
10700#[target_feature(enable = "neon")]
10701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10702#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10703#[cfg_attr(
10704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10705    assert_instr(fmov)
10706)]
10707#[cfg_attr(
10708    not(target_arch = "arm"),
10709    stable(feature = "neon_intrinsics", since = "1.59.0")
10710)]
10711#[cfg_attr(
10712    target_arch = "arm",
10713    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10714)]
10715pub fn vdup_n_s64(value: i64) -> int64x1_t {
10716    int64x1_t::splat(value)
10717}
10718#[doc = "Duplicate vector element to vector or scalar"]
10719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
10720#[inline]
10721#[target_feature(enable = "neon")]
10722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10723#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10724#[cfg_attr(
10725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10726    assert_instr(dup)
10727)]
10728#[cfg_attr(
10729    not(target_arch = "arm"),
10730    stable(feature = "neon_intrinsics", since = "1.59.0")
10731)]
10732#[cfg_attr(
10733    target_arch = "arm",
10734    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10735)]
10736pub fn vdup_n_s8(value: i8) -> int8x8_t {
10737    int8x8_t::splat(value)
10738}
10739#[doc = "Duplicate vector element to vector or scalar"]
10740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
10741#[inline]
10742#[target_feature(enable = "neon")]
10743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10745#[cfg_attr(
10746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10747    assert_instr(dup)
10748)]
10749#[cfg_attr(
10750    not(target_arch = "arm"),
10751    stable(feature = "neon_intrinsics", since = "1.59.0")
10752)]
10753#[cfg_attr(
10754    target_arch = "arm",
10755    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10756)]
10757pub fn vdup_n_u16(value: u16) -> uint16x4_t {
10758    uint16x4_t::splat(value)
10759}
10760#[doc = "Duplicate vector element to vector or scalar"]
10761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
10762#[inline]
10763#[target_feature(enable = "neon")]
10764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10765#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10766#[cfg_attr(
10767    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10768    assert_instr(dup)
10769)]
10770#[cfg_attr(
10771    not(target_arch = "arm"),
10772    stable(feature = "neon_intrinsics", since = "1.59.0")
10773)]
10774#[cfg_attr(
10775    target_arch = "arm",
10776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10777)]
10778pub fn vdup_n_u32(value: u32) -> uint32x2_t {
10779    uint32x2_t::splat(value)
10780}
10781#[doc = "Duplicate vector element to vector or scalar"]
10782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
10783#[inline]
10784#[target_feature(enable = "neon")]
10785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10786#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10787#[cfg_attr(
10788    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10789    assert_instr(fmov)
10790)]
10791#[cfg_attr(
10792    not(target_arch = "arm"),
10793    stable(feature = "neon_intrinsics", since = "1.59.0")
10794)]
10795#[cfg_attr(
10796    target_arch = "arm",
10797    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10798)]
10799pub fn vdup_n_u64(value: u64) -> uint64x1_t {
10800    uint64x1_t::splat(value)
10801}
10802#[doc = "Duplicate vector element to vector or scalar"]
10803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
10804#[inline]
10805#[target_feature(enable = "neon")]
10806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10807#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10808#[cfg_attr(
10809    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10810    assert_instr(dup)
10811)]
10812#[cfg_attr(
10813    not(target_arch = "arm"),
10814    stable(feature = "neon_intrinsics", since = "1.59.0")
10815)]
10816#[cfg_attr(
10817    target_arch = "arm",
10818    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10819)]
10820pub fn vdup_n_u8(value: u8) -> uint8x8_t {
10821    uint8x8_t::splat(value)
10822}
10823#[doc = "Duplicate vector element to vector or scalar"]
10824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
10825#[inline]
10826#[target_feature(enable = "neon")]
10827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10828#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10829#[cfg_attr(
10830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10831    assert_instr(dup)
10832)]
10833#[cfg_attr(
10834    not(target_arch = "arm"),
10835    stable(feature = "neon_intrinsics", since = "1.59.0")
10836)]
10837#[cfg_attr(
10838    target_arch = "arm",
10839    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10840)]
10841pub fn vdupq_n_f32(value: f32) -> float32x4_t {
10842    float32x4_t::splat(value)
10843}
10844#[doc = "Duplicate vector element to vector or scalar"]
10845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
10846#[inline]
10847#[target_feature(enable = "neon")]
10848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10849#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10850#[cfg_attr(
10851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10852    assert_instr(dup)
10853)]
10854#[cfg_attr(
10855    not(target_arch = "arm"),
10856    stable(feature = "neon_intrinsics", since = "1.59.0")
10857)]
10858#[cfg_attr(
10859    target_arch = "arm",
10860    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10861)]
10862pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
10863    poly16x8_t::splat(value)
10864}
10865#[doc = "Duplicate vector element to vector or scalar"]
10866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
10867#[inline]
10868#[target_feature(enable = "neon")]
10869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10870#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10871#[cfg_attr(
10872    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10873    assert_instr(dup)
10874)]
10875#[cfg_attr(
10876    not(target_arch = "arm"),
10877    stable(feature = "neon_intrinsics", since = "1.59.0")
10878)]
10879#[cfg_attr(
10880    target_arch = "arm",
10881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10882)]
10883pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
10884    poly8x16_t::splat(value)
10885}
10886#[doc = "Duplicate vector element to vector or scalar"]
10887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
10888#[inline]
10889#[target_feature(enable = "neon")]
10890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10891#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10892#[cfg_attr(
10893    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10894    assert_instr(dup)
10895)]
10896#[cfg_attr(
10897    not(target_arch = "arm"),
10898    stable(feature = "neon_intrinsics", since = "1.59.0")
10899)]
10900#[cfg_attr(
10901    target_arch = "arm",
10902    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10903)]
10904pub fn vdupq_n_s16(value: i16) -> int16x8_t {
10905    int16x8_t::splat(value)
10906}
10907#[doc = "Duplicate vector element to vector or scalar"]
10908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
10909#[inline]
10910#[target_feature(enable = "neon")]
10911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10912#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10913#[cfg_attr(
10914    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10915    assert_instr(dup)
10916)]
10917#[cfg_attr(
10918    not(target_arch = "arm"),
10919    stable(feature = "neon_intrinsics", since = "1.59.0")
10920)]
10921#[cfg_attr(
10922    target_arch = "arm",
10923    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10924)]
10925pub fn vdupq_n_s32(value: i32) -> int32x4_t {
10926    int32x4_t::splat(value)
10927}
10928#[doc = "Duplicate vector element to vector or scalar"]
10929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
10930#[inline]
10931#[target_feature(enable = "neon")]
10932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10933#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10934#[cfg_attr(
10935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10936    assert_instr(dup)
10937)]
10938#[cfg_attr(
10939    not(target_arch = "arm"),
10940    stable(feature = "neon_intrinsics", since = "1.59.0")
10941)]
10942#[cfg_attr(
10943    target_arch = "arm",
10944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10945)]
10946pub fn vdupq_n_s64(value: i64) -> int64x2_t {
10947    int64x2_t::splat(value)
10948}
10949#[doc = "Duplicate vector element to vector or scalar"]
10950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
10951#[inline]
10952#[target_feature(enable = "neon")]
10953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10954#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10955#[cfg_attr(
10956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10957    assert_instr(dup)
10958)]
10959#[cfg_attr(
10960    not(target_arch = "arm"),
10961    stable(feature = "neon_intrinsics", since = "1.59.0")
10962)]
10963#[cfg_attr(
10964    target_arch = "arm",
10965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10966)]
10967pub fn vdupq_n_s8(value: i8) -> int8x16_t {
10968    int8x16_t::splat(value)
10969}
10970#[doc = "Duplicate vector element to vector or scalar"]
10971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
10972#[inline]
10973#[target_feature(enable = "neon")]
10974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10975#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10976#[cfg_attr(
10977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10978    assert_instr(dup)
10979)]
10980#[cfg_attr(
10981    not(target_arch = "arm"),
10982    stable(feature = "neon_intrinsics", since = "1.59.0")
10983)]
10984#[cfg_attr(
10985    target_arch = "arm",
10986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10987)]
10988pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
10989    uint16x8_t::splat(value)
10990}
10991#[doc = "Duplicate vector element to vector or scalar"]
10992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
10993#[inline]
10994#[target_feature(enable = "neon")]
10995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10996#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10997#[cfg_attr(
10998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10999    assert_instr(dup)
11000)]
11001#[cfg_attr(
11002    not(target_arch = "arm"),
11003    stable(feature = "neon_intrinsics", since = "1.59.0")
11004)]
11005#[cfg_attr(
11006    target_arch = "arm",
11007    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11008)]
11009pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
11010    uint32x4_t::splat(value)
11011}
11012#[doc = "Duplicate vector element to vector or scalar"]
11013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
11014#[inline]
11015#[target_feature(enable = "neon")]
11016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
11018#[cfg_attr(
11019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11020    assert_instr(dup)
11021)]
11022#[cfg_attr(
11023    not(target_arch = "arm"),
11024    stable(feature = "neon_intrinsics", since = "1.59.0")
11025)]
11026#[cfg_attr(
11027    target_arch = "arm",
11028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11029)]
11030pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
11031    uint64x2_t::splat(value)
11032}
11033#[doc = "Duplicate vector element to vector or scalar"]
11034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
11035#[inline]
11036#[target_feature(enable = "neon")]
11037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11038#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
11039#[cfg_attr(
11040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11041    assert_instr(dup)
11042)]
11043#[cfg_attr(
11044    not(target_arch = "arm"),
11045    stable(feature = "neon_intrinsics", since = "1.59.0")
11046)]
11047#[cfg_attr(
11048    target_arch = "arm",
11049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11050)]
11051pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
11052    uint8x16_t::splat(value)
11053}
11054#[doc = "Duplicate vector element to vector or scalar"]
11055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
11056#[inline]
11057#[target_feature(enable = "neon")]
11058#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
11059#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
11060#[cfg_attr(
11061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11062    assert_instr(dup)
11063)]
11064#[cfg_attr(
11065    not(target_arch = "arm"),
11066    stable(feature = "neon_intrinsics", since = "1.59.0")
11067)]
11068#[cfg_attr(
11069    target_arch = "arm",
11070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11071)]
11072fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
11073    float32x2_t::splat(value)
11074}
11075#[doc = "Duplicate vector element to vector or scalar"]
11076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
11077#[inline]
11078#[target_feature(enable = "neon")]
11079#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
11080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
11081#[cfg_attr(
11082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11083    assert_instr(dup)
11084)]
11085#[cfg_attr(
11086    not(target_arch = "arm"),
11087    stable(feature = "neon_intrinsics", since = "1.59.0")
11088)]
11089#[cfg_attr(
11090    target_arch = "arm",
11091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11092)]
11093fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
11094    float32x4_t::splat(value)
11095}
11096#[doc = "Set all vector lanes to the same value"]
11097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
11098#[inline]
11099#[target_feature(enable = "neon")]
11100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11102#[cfg_attr(
11103    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11104    assert_instr(dup, N = 0)
11105)]
11106#[rustc_legacy_const_generics(1)]
11107#[cfg_attr(
11108    not(target_arch = "arm"),
11109    stable(feature = "neon_intrinsics", since = "1.59.0")
11110)]
11111#[cfg_attr(
11112    target_arch = "arm",
11113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11114)]
11115pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
11116    static_assert!(N == 0);
11117    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11118}
11119#[doc = "Set all vector lanes to the same value"]
11120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
11121#[inline]
11122#[target_feature(enable = "neon")]
11123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11125#[cfg_attr(
11126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11127    assert_instr(dup, N = 0)
11128)]
11129#[rustc_legacy_const_generics(1)]
11130#[cfg_attr(
11131    not(target_arch = "arm"),
11132    stable(feature = "neon_intrinsics", since = "1.59.0")
11133)]
11134#[cfg_attr(
11135    target_arch = "arm",
11136    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11137)]
11138pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
11139    static_assert!(N == 0);
11140    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11141}
11142#[doc = "Set all vector lanes to the same value"]
11143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
11144#[inline]
11145#[target_feature(enable = "neon")]
11146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11148#[cfg_attr(
11149    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11150    assert_instr(dup, N = 1)
11151)]
11152#[rustc_legacy_const_generics(1)]
11153#[cfg_attr(
11154    not(target_arch = "arm"),
11155    stable(feature = "neon_intrinsics", since = "1.59.0")
11156)]
11157#[cfg_attr(
11158    target_arch = "arm",
11159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11160)]
11161pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
11162    static_assert_uimm_bits!(N, 1);
11163    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11164}
11165#[doc = "Set all vector lanes to the same value"]
11166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
11167#[inline]
11168#[target_feature(enable = "neon")]
11169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11171#[cfg_attr(
11172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11173    assert_instr(dup, N = 1)
11174)]
11175#[rustc_legacy_const_generics(1)]
11176#[cfg_attr(
11177    not(target_arch = "arm"),
11178    stable(feature = "neon_intrinsics", since = "1.59.0")
11179)]
11180#[cfg_attr(
11181    target_arch = "arm",
11182    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11183)]
11184pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
11185    static_assert_uimm_bits!(N, 1);
11186    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11187}
11188#[doc = "Vector bitwise exclusive or (vector)"]
11189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
11190#[inline]
11191#[target_feature(enable = "neon")]
11192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11194#[cfg_attr(
11195    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11196    assert_instr(eor)
11197)]
11198#[cfg_attr(
11199    not(target_arch = "arm"),
11200    stable(feature = "neon_intrinsics", since = "1.59.0")
11201)]
11202#[cfg_attr(
11203    target_arch = "arm",
11204    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11205)]
11206pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11207    unsafe { simd_xor(a, b) }
11208}
11209#[doc = "Vector bitwise exclusive or (vector)"]
11210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
11211#[inline]
11212#[target_feature(enable = "neon")]
11213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11215#[cfg_attr(
11216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11217    assert_instr(eor)
11218)]
11219#[cfg_attr(
11220    not(target_arch = "arm"),
11221    stable(feature = "neon_intrinsics", since = "1.59.0")
11222)]
11223#[cfg_attr(
11224    target_arch = "arm",
11225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11226)]
11227pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
11228    unsafe { simd_xor(a, b) }
11229}
11230#[doc = "Vector bitwise exclusive or (vector)"]
11231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
11232#[inline]
11233#[target_feature(enable = "neon")]
11234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11236#[cfg_attr(
11237    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11238    assert_instr(eor)
11239)]
11240#[cfg_attr(
11241    not(target_arch = "arm"),
11242    stable(feature = "neon_intrinsics", since = "1.59.0")
11243)]
11244#[cfg_attr(
11245    target_arch = "arm",
11246    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11247)]
11248pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11249    unsafe { simd_xor(a, b) }
11250}
11251#[doc = "Vector bitwise exclusive or (vector)"]
11252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
11253#[inline]
11254#[target_feature(enable = "neon")]
11255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11257#[cfg_attr(
11258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11259    assert_instr(eor)
11260)]
11261#[cfg_attr(
11262    not(target_arch = "arm"),
11263    stable(feature = "neon_intrinsics", since = "1.59.0")
11264)]
11265#[cfg_attr(
11266    target_arch = "arm",
11267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11268)]
11269pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11270    unsafe { simd_xor(a, b) }
11271}
11272#[doc = "Vector bitwise exclusive or (vector)"]
11273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
11274#[inline]
11275#[target_feature(enable = "neon")]
11276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11278#[cfg_attr(
11279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11280    assert_instr(eor)
11281)]
11282#[cfg_attr(
11283    not(target_arch = "arm"),
11284    stable(feature = "neon_intrinsics", since = "1.59.0")
11285)]
11286#[cfg_attr(
11287    target_arch = "arm",
11288    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11289)]
11290pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11291    unsafe { simd_xor(a, b) }
11292}
11293#[doc = "Vector bitwise exclusive or (vector)"]
11294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
11295#[inline]
11296#[target_feature(enable = "neon")]
11297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11299#[cfg_attr(
11300    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11301    assert_instr(eor)
11302)]
11303#[cfg_attr(
11304    not(target_arch = "arm"),
11305    stable(feature = "neon_intrinsics", since = "1.59.0")
11306)]
11307#[cfg_attr(
11308    target_arch = "arm",
11309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11310)]
11311pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11312    unsafe { simd_xor(a, b) }
11313}
11314#[doc = "Vector bitwise exclusive or (vector)"]
11315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
11316#[inline]
11317#[target_feature(enable = "neon")]
11318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11320#[cfg_attr(
11321    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11322    assert_instr(eor)
11323)]
11324#[cfg_attr(
11325    not(target_arch = "arm"),
11326    stable(feature = "neon_intrinsics", since = "1.59.0")
11327)]
11328#[cfg_attr(
11329    target_arch = "arm",
11330    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11331)]
11332pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
11333    unsafe { simd_xor(a, b) }
11334}
11335#[doc = "Vector bitwise exclusive or (vector)"]
11336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
11337#[inline]
11338#[target_feature(enable = "neon")]
11339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11341#[cfg_attr(
11342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11343    assert_instr(eor)
11344)]
11345#[cfg_attr(
11346    not(target_arch = "arm"),
11347    stable(feature = "neon_intrinsics", since = "1.59.0")
11348)]
11349#[cfg_attr(
11350    target_arch = "arm",
11351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11352)]
11353pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
11354    unsafe { simd_xor(a, b) }
11355}
11356#[doc = "Vector bitwise exclusive or (vector)"]
11357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
11358#[inline]
11359#[target_feature(enable = "neon")]
11360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11362#[cfg_attr(
11363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11364    assert_instr(eor)
11365)]
11366#[cfg_attr(
11367    not(target_arch = "arm"),
11368    stable(feature = "neon_intrinsics", since = "1.59.0")
11369)]
11370#[cfg_attr(
11371    target_arch = "arm",
11372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11373)]
11374pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11375    unsafe { simd_xor(a, b) }
11376}
11377#[doc = "Vector bitwise exclusive or (vector)"]
11378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
11379#[inline]
11380#[target_feature(enable = "neon")]
11381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11383#[cfg_attr(
11384    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11385    assert_instr(eor)
11386)]
11387#[cfg_attr(
11388    not(target_arch = "arm"),
11389    stable(feature = "neon_intrinsics", since = "1.59.0")
11390)]
11391#[cfg_attr(
11392    target_arch = "arm",
11393    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11394)]
11395pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
11396    unsafe { simd_xor(a, b) }
11397}
11398#[doc = "Vector bitwise exclusive or (vector)"]
11399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
11400#[inline]
11401#[target_feature(enable = "neon")]
11402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11404#[cfg_attr(
11405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11406    assert_instr(eor)
11407)]
11408#[cfg_attr(
11409    not(target_arch = "arm"),
11410    stable(feature = "neon_intrinsics", since = "1.59.0")
11411)]
11412#[cfg_attr(
11413    target_arch = "arm",
11414    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11415)]
11416pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11417    unsafe { simd_xor(a, b) }
11418}
11419#[doc = "Vector bitwise exclusive or (vector)"]
11420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
11421#[inline]
11422#[target_feature(enable = "neon")]
11423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11425#[cfg_attr(
11426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11427    assert_instr(eor)
11428)]
11429#[cfg_attr(
11430    not(target_arch = "arm"),
11431    stable(feature = "neon_intrinsics", since = "1.59.0")
11432)]
11433#[cfg_attr(
11434    target_arch = "arm",
11435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11436)]
11437pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11438    unsafe { simd_xor(a, b) }
11439}
11440#[doc = "Vector bitwise exclusive or (vector)"]
11441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
11442#[inline]
11443#[target_feature(enable = "neon")]
11444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11446#[cfg_attr(
11447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11448    assert_instr(eor)
11449)]
11450#[cfg_attr(
11451    not(target_arch = "arm"),
11452    stable(feature = "neon_intrinsics", since = "1.59.0")
11453)]
11454#[cfg_attr(
11455    target_arch = "arm",
11456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11457)]
11458pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11459    unsafe { simd_xor(a, b) }
11460}
11461#[doc = "Vector bitwise exclusive or (vector)"]
11462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
11463#[inline]
11464#[target_feature(enable = "neon")]
11465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11467#[cfg_attr(
11468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11469    assert_instr(eor)
11470)]
11471#[cfg_attr(
11472    not(target_arch = "arm"),
11473    stable(feature = "neon_intrinsics", since = "1.59.0")
11474)]
11475#[cfg_attr(
11476    target_arch = "arm",
11477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11478)]
11479pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
11480    unsafe { simd_xor(a, b) }
11481}
11482#[doc = "Vector bitwise exclusive or (vector)"]
11483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
11484#[inline]
11485#[target_feature(enable = "neon")]
11486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11488#[cfg_attr(
11489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11490    assert_instr(eor)
11491)]
11492#[cfg_attr(
11493    not(target_arch = "arm"),
11494    stable(feature = "neon_intrinsics", since = "1.59.0")
11495)]
11496#[cfg_attr(
11497    target_arch = "arm",
11498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11499)]
11500pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
11501    unsafe { simd_xor(a, b) }
11502}
11503#[doc = "Vector bitwise exclusive or (vector)"]
11504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
11505#[inline]
11506#[target_feature(enable = "neon")]
11507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11509#[cfg_attr(
11510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11511    assert_instr(eor)
11512)]
11513#[cfg_attr(
11514    not(target_arch = "arm"),
11515    stable(feature = "neon_intrinsics", since = "1.59.0")
11516)]
11517#[cfg_attr(
11518    target_arch = "arm",
11519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11520)]
11521pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
11522    unsafe { simd_xor(a, b) }
11523}
11524#[doc = "Extract vector from pair of vectors"]
11525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
11526#[inline]
11527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11529#[cfg_attr(
11530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11531    assert_instr(ext, N = 3)
11532)]
11533#[rustc_legacy_const_generics(2)]
11534#[target_feature(enable = "neon,fp16")]
11535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11536pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
11537    static_assert_uimm_bits!(N, 2);
11538    unsafe {
11539        match N & 0b11 {
11540            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11541            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11542            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11543            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11544            _ => unreachable_unchecked(),
11545        }
11546    }
11547}
11548#[doc = "Extract vector from pair of vectors"]
11549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
11550#[inline]
11551#[target_feature(enable = "neon")]
11552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11553#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11554#[cfg_attr(
11555    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11556    assert_instr(ext, N = 1)
11557)]
11558#[rustc_legacy_const_generics(2)]
11559#[cfg_attr(
11560    not(target_arch = "arm"),
11561    stable(feature = "neon_intrinsics", since = "1.59.0")
11562)]
11563#[cfg_attr(
11564    target_arch = "arm",
11565    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11566)]
11567pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
11568    static_assert_uimm_bits!(N, 1);
11569    unsafe {
11570        match N & 0b1 {
11571            0 => simd_shuffle!(a, b, [0, 1]),
11572            1 => simd_shuffle!(a, b, [1, 2]),
11573            _ => unreachable_unchecked(),
11574        }
11575    }
11576}
11577#[doc = "Extract vector from pair of vectors"]
11578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
11579#[inline]
11580#[target_feature(enable = "neon")]
11581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11583#[cfg_attr(
11584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11585    assert_instr(ext, N = 1)
11586)]
11587#[rustc_legacy_const_generics(2)]
11588#[cfg_attr(
11589    not(target_arch = "arm"),
11590    stable(feature = "neon_intrinsics", since = "1.59.0")
11591)]
11592#[cfg_attr(
11593    target_arch = "arm",
11594    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11595)]
11596pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11597    static_assert_uimm_bits!(N, 1);
11598    unsafe {
11599        match N & 0b1 {
11600            0 => simd_shuffle!(a, b, [0, 1]),
11601            1 => simd_shuffle!(a, b, [1, 2]),
11602            _ => unreachable_unchecked(),
11603        }
11604    }
11605}
11606#[doc = "Extract vector from pair of vectors"]
11607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
11608#[inline]
11609#[target_feature(enable = "neon")]
11610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11611#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11612#[cfg_attr(
11613    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11614    assert_instr(ext, N = 1)
11615)]
11616#[rustc_legacy_const_generics(2)]
11617#[cfg_attr(
11618    not(target_arch = "arm"),
11619    stable(feature = "neon_intrinsics", since = "1.59.0")
11620)]
11621#[cfg_attr(
11622    target_arch = "arm",
11623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11624)]
11625pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11626    static_assert_uimm_bits!(N, 1);
11627    unsafe {
11628        match N & 0b1 {
11629            0 => simd_shuffle!(a, b, [0, 1]),
11630            1 => simd_shuffle!(a, b, [1, 2]),
11631            _ => unreachable_unchecked(),
11632        }
11633    }
11634}
11635#[doc = "Extract vector from pair of vectors"]
11636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
11637#[doc = "## Safety"]
11638#[doc = "  * Neon instrinsic unsafe"]
11639#[inline]
11640#[target_feature(enable = "neon")]
11641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11643#[cfg_attr(
11644    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11645    assert_instr(nop, N = 0)
11646)]
11647#[rustc_legacy_const_generics(2)]
11648#[cfg_attr(
11649    not(target_arch = "arm"),
11650    stable(feature = "neon_intrinsics", since = "1.59.0")
11651)]
11652#[cfg_attr(
11653    target_arch = "arm",
11654    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11655)]
11656pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
11657    static_assert!(N == 0);
11658    a
11659}
11660#[doc = "Extract vector from pair of vectors"]
11661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
11662#[doc = "## Safety"]
11663#[doc = "  * Neon instrinsic unsafe"]
11664#[inline]
11665#[target_feature(enable = "neon")]
11666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11668#[cfg_attr(
11669    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11670    assert_instr(nop, N = 0)
11671)]
11672#[rustc_legacy_const_generics(2)]
11673#[cfg_attr(
11674    not(target_arch = "arm"),
11675    stable(feature = "neon_intrinsics", since = "1.59.0")
11676)]
11677#[cfg_attr(
11678    target_arch = "arm",
11679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11680)]
11681pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t {
11682    static_assert!(N == 0);
11683    a
11684}
11685#[doc = "Extract vector from pair of vectors"]
11686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
11687#[inline]
11688#[target_feature(enable = "neon")]
11689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11690#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11691#[cfg_attr(
11692    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11693    assert_instr(ext, N = 7)
11694)]
11695#[rustc_legacy_const_generics(2)]
11696#[cfg_attr(
11697    not(target_arch = "arm"),
11698    stable(feature = "neon_intrinsics", since = "1.59.0")
11699)]
11700#[cfg_attr(
11701    target_arch = "arm",
11702    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11703)]
11704pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11705    static_assert_uimm_bits!(N, 3);
11706    unsafe {
11707        match N & 0b111 {
11708            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11709            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11710            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11711            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11712            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11713            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11714            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11715            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11716            _ => unreachable_unchecked(),
11717        }
11718    }
11719}
11720#[doc = "Extract vector from pair of vectors"]
11721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
11722#[inline]
11723#[target_feature(enable = "neon")]
11724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11725#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11726#[cfg_attr(
11727    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11728    assert_instr(ext, N = 7)
11729)]
11730#[rustc_legacy_const_generics(2)]
11731#[cfg_attr(
11732    not(target_arch = "arm"),
11733    stable(feature = "neon_intrinsics", since = "1.59.0")
11734)]
11735#[cfg_attr(
11736    target_arch = "arm",
11737    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11738)]
11739pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11740    static_assert_uimm_bits!(N, 3);
11741    unsafe {
11742        match N & 0b111 {
11743            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11744            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11745            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11746            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11747            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11748            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11749            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11750            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11751            _ => unreachable_unchecked(),
11752        }
11753    }
11754}
11755#[doc = "Extract vector from pair of vectors"]
11756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
11757#[inline]
11758#[target_feature(enable = "neon")]
11759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11760#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11761#[cfg_attr(
11762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11763    assert_instr(ext, N = 7)
11764)]
11765#[rustc_legacy_const_generics(2)]
11766#[cfg_attr(
11767    not(target_arch = "arm"),
11768    stable(feature = "neon_intrinsics", since = "1.59.0")
11769)]
11770#[cfg_attr(
11771    target_arch = "arm",
11772    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11773)]
11774pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11775    static_assert_uimm_bits!(N, 3);
11776    unsafe {
11777        match N & 0b111 {
11778            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11779            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11780            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11781            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11782            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11783            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11784            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11785            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11786            _ => unreachable_unchecked(),
11787        }
11788    }
11789}
11790#[doc = "Extract vector from pair of vectors"]
11791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
11792#[inline]
11793#[target_feature(enable = "neon")]
11794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11795#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11796#[cfg_attr(
11797    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11798    assert_instr(ext, N = 7)
11799)]
11800#[rustc_legacy_const_generics(2)]
11801#[cfg_attr(
11802    not(target_arch = "arm"),
11803    stable(feature = "neon_intrinsics", since = "1.59.0")
11804)]
11805#[cfg_attr(
11806    target_arch = "arm",
11807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11808)]
11809pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11810    static_assert_uimm_bits!(N, 3);
11811    unsafe {
11812        match N & 0b111 {
11813            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11814            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11815            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11816            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11817            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11818            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11819            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11820            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11821            _ => unreachable_unchecked(),
11822        }
11823    }
11824}
11825#[doc = "Extract vector from pair of vectors"]
11826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
11827#[inline]
11828#[target_feature(enable = "neon")]
11829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11830#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11831#[cfg_attr(
11832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11833    assert_instr(ext, N = 7)
11834)]
11835#[rustc_legacy_const_generics(2)]
11836#[cfg_attr(
11837    not(target_arch = "arm"),
11838    stable(feature = "neon_intrinsics", since = "1.59.0")
11839)]
11840#[cfg_attr(
11841    target_arch = "arm",
11842    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11843)]
11844pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
11845    static_assert_uimm_bits!(N, 3);
11846    unsafe {
11847        match N & 0b111 {
11848            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11849            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11850            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11851            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11852            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11853            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11854            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11855            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11856            _ => unreachable_unchecked(),
11857        }
11858    }
11859}
11860#[doc = "Extract vector from pair of vectors"]
11861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
11862#[inline]
11863#[target_feature(enable = "neon")]
11864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11865#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11866#[cfg_attr(
11867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11868    assert_instr(ext, N = 7)
11869)]
11870#[rustc_legacy_const_generics(2)]
11871#[cfg_attr(
11872    not(target_arch = "arm"),
11873    stable(feature = "neon_intrinsics", since = "1.59.0")
11874)]
11875#[cfg_attr(
11876    target_arch = "arm",
11877    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11878)]
11879pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
11880    static_assert_uimm_bits!(N, 3);
11881    unsafe {
11882        match N & 0b111 {
11883            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11884            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11885            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11886            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11887            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11888            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11889            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11890            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11891            _ => unreachable_unchecked(),
11892        }
11893    }
11894}
11895#[doc = "Extract vector from pair of vectors"]
11896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
11897#[inline]
11898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11899#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11900#[cfg_attr(
11901    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11902    assert_instr(ext, N = 7)
11903)]
11904#[rustc_legacy_const_generics(2)]
11905#[target_feature(enable = "neon,fp16")]
11906#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11907pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
11908    static_assert_uimm_bits!(N, 3);
11909    unsafe {
11910        match N & 0b111 {
11911            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11912            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11913            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11914            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11915            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11916            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11917            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11918            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11919            _ => unreachable_unchecked(),
11920        }
11921    }
11922}
11923#[doc = "Extract vector from pair of vectors"]
11924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
11925#[inline]
11926#[target_feature(enable = "neon")]
11927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11928#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11929#[cfg_attr(
11930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11931    assert_instr(ext, N = 3)
11932)]
11933#[rustc_legacy_const_generics(2)]
11934#[cfg_attr(
11935    not(target_arch = "arm"),
11936    stable(feature = "neon_intrinsics", since = "1.59.0")
11937)]
11938#[cfg_attr(
11939    target_arch = "arm",
11940    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11941)]
11942pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
11943    static_assert_uimm_bits!(N, 2);
11944    unsafe {
11945        match N & 0b11 {
11946            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11947            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11948            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11949            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11950            _ => unreachable_unchecked(),
11951        }
11952    }
11953}
11954#[doc = "Extract vector from pair of vectors"]
11955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
11956#[inline]
11957#[target_feature(enable = "neon")]
11958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11960#[cfg_attr(
11961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11962    assert_instr(ext, N = 3)
11963)]
11964#[rustc_legacy_const_generics(2)]
11965#[cfg_attr(
11966    not(target_arch = "arm"),
11967    stable(feature = "neon_intrinsics", since = "1.59.0")
11968)]
11969#[cfg_attr(
11970    target_arch = "arm",
11971    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11972)]
11973pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11974    static_assert_uimm_bits!(N, 2);
11975    unsafe {
11976        match N & 0b11 {
11977            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11978            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11979            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11980            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11981            _ => unreachable_unchecked(),
11982        }
11983    }
11984}
11985#[doc = "Extract vector from pair of vectors"]
11986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
11987#[inline]
11988#[target_feature(enable = "neon")]
11989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11990#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11991#[cfg_attr(
11992    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11993    assert_instr(ext, N = 3)
11994)]
11995#[rustc_legacy_const_generics(2)]
11996#[cfg_attr(
11997    not(target_arch = "arm"),
11998    stable(feature = "neon_intrinsics", since = "1.59.0")
11999)]
12000#[cfg_attr(
12001    target_arch = "arm",
12002    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12003)]
12004pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
12005    static_assert_uimm_bits!(N, 2);
12006    unsafe {
12007        match N & 0b11 {
12008            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12009            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12010            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12011            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12012            _ => unreachable_unchecked(),
12013        }
12014    }
12015}
12016#[doc = "Extract vector from pair of vectors"]
12017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
12018#[inline]
12019#[target_feature(enable = "neon")]
12020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12021#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12022#[cfg_attr(
12023    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12024    assert_instr(ext, N = 3)
12025)]
12026#[rustc_legacy_const_generics(2)]
12027#[cfg_attr(
12028    not(target_arch = "arm"),
12029    stable(feature = "neon_intrinsics", since = "1.59.0")
12030)]
12031#[cfg_attr(
12032    target_arch = "arm",
12033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12034)]
12035pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
12036    static_assert_uimm_bits!(N, 2);
12037    unsafe {
12038        match N & 0b11 {
12039            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12040            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12041            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12042            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12043            _ => unreachable_unchecked(),
12044        }
12045    }
12046}
12047#[doc = "Extract vector from pair of vectors"]
12048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
12049#[inline]
12050#[target_feature(enable = "neon")]
12051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12052#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12053#[cfg_attr(
12054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12055    assert_instr(ext, N = 3)
12056)]
12057#[rustc_legacy_const_generics(2)]
12058#[cfg_attr(
12059    not(target_arch = "arm"),
12060    stable(feature = "neon_intrinsics", since = "1.59.0")
12061)]
12062#[cfg_attr(
12063    target_arch = "arm",
12064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12065)]
12066pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
12067    static_assert_uimm_bits!(N, 2);
12068    unsafe {
12069        match N & 0b11 {
12070            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12071            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12072            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12073            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12074            _ => unreachable_unchecked(),
12075        }
12076    }
12077}
12078#[doc = "Extract vector from pair of vectors"]
12079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
12080#[inline]
12081#[target_feature(enable = "neon")]
12082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12084#[cfg_attr(
12085    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12086    assert_instr(ext, N = 3)
12087)]
12088#[rustc_legacy_const_generics(2)]
12089#[cfg_attr(
12090    not(target_arch = "arm"),
12091    stable(feature = "neon_intrinsics", since = "1.59.0")
12092)]
12093#[cfg_attr(
12094    target_arch = "arm",
12095    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12096)]
12097pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
12098    static_assert_uimm_bits!(N, 2);
12099    unsafe {
12100        match N & 0b11 {
12101            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12102            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12103            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12104            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12105            _ => unreachable_unchecked(),
12106        }
12107    }
12108}
12109#[doc = "Extract vector from pair of vectors"]
12110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
12111#[inline]
12112#[target_feature(enable = "neon")]
12113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12115#[cfg_attr(
12116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12117    assert_instr(ext, N = 1)
12118)]
12119#[rustc_legacy_const_generics(2)]
12120#[cfg_attr(
12121    not(target_arch = "arm"),
12122    stable(feature = "neon_intrinsics", since = "1.59.0")
12123)]
12124#[cfg_attr(
12125    target_arch = "arm",
12126    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12127)]
12128pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
12129    static_assert_uimm_bits!(N, 1);
12130    unsafe {
12131        match N & 0b1 {
12132            0 => simd_shuffle!(a, b, [0, 1]),
12133            1 => simd_shuffle!(a, b, [1, 2]),
12134            _ => unreachable_unchecked(),
12135        }
12136    }
12137}
12138#[doc = "Extract vector from pair of vectors"]
12139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
12140#[inline]
12141#[target_feature(enable = "neon")]
12142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12144#[cfg_attr(
12145    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12146    assert_instr(ext, N = 1)
12147)]
12148#[rustc_legacy_const_generics(2)]
12149#[cfg_attr(
12150    not(target_arch = "arm"),
12151    stable(feature = "neon_intrinsics", since = "1.59.0")
12152)]
12153#[cfg_attr(
12154    target_arch = "arm",
12155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12156)]
12157pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
12158    static_assert_uimm_bits!(N, 1);
12159    unsafe {
12160        match N & 0b1 {
12161            0 => simd_shuffle!(a, b, [0, 1]),
12162            1 => simd_shuffle!(a, b, [1, 2]),
12163            _ => unreachable_unchecked(),
12164        }
12165    }
12166}
12167#[doc = "Extract vector from pair of vectors"]
12168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
12169#[inline]
12170#[target_feature(enable = "neon")]
12171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12172#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12173#[cfg_attr(
12174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12175    assert_instr(ext, N = 15)
12176)]
12177#[rustc_legacy_const_generics(2)]
12178#[cfg_attr(
12179    not(target_arch = "arm"),
12180    stable(feature = "neon_intrinsics", since = "1.59.0")
12181)]
12182#[cfg_attr(
12183    target_arch = "arm",
12184    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12185)]
12186pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
12187    static_assert_uimm_bits!(N, 4);
12188    unsafe {
12189        match N & 0b1111 {
12190            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12191            1 => simd_shuffle!(
12192                a,
12193                b,
12194                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12195            ),
12196            2 => simd_shuffle!(
12197                a,
12198                b,
12199                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12200            ),
12201            3 => simd_shuffle!(
12202                a,
12203                b,
12204                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12205            ),
12206            4 => simd_shuffle!(
12207                a,
12208                b,
12209                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12210            ),
12211            5 => simd_shuffle!(
12212                a,
12213                b,
12214                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12215            ),
12216            6 => simd_shuffle!(
12217                a,
12218                b,
12219                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12220            ),
12221            7 => simd_shuffle!(
12222                a,
12223                b,
12224                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12225            ),
12226            8 => simd_shuffle!(
12227                a,
12228                b,
12229                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12230            ),
12231            9 => simd_shuffle!(
12232                a,
12233                b,
12234                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12235            ),
12236            10 => simd_shuffle!(
12237                a,
12238                b,
12239                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12240            ),
12241            11 => simd_shuffle!(
12242                a,
12243                b,
12244                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12245            ),
12246            12 => simd_shuffle!(
12247                a,
12248                b,
12249                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12250            ),
12251            13 => simd_shuffle!(
12252                a,
12253                b,
12254                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12255            ),
12256            14 => simd_shuffle!(
12257                a,
12258                b,
12259                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12260            ),
12261            15 => simd_shuffle!(
12262                a,
12263                b,
12264                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12265            ),
12266            _ => unreachable_unchecked(),
12267        }
12268    }
12269}
12270#[doc = "Extract vector from pair of vectors"]
12271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
12272#[inline]
12273#[target_feature(enable = "neon")]
12274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12275#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12276#[cfg_attr(
12277    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12278    assert_instr(ext, N = 15)
12279)]
12280#[rustc_legacy_const_generics(2)]
12281#[cfg_attr(
12282    not(target_arch = "arm"),
12283    stable(feature = "neon_intrinsics", since = "1.59.0")
12284)]
12285#[cfg_attr(
12286    target_arch = "arm",
12287    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12288)]
12289pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
12290    static_assert_uimm_bits!(N, 4);
12291    unsafe {
12292        match N & 0b1111 {
12293            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12294            1 => simd_shuffle!(
12295                a,
12296                b,
12297                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12298            ),
12299            2 => simd_shuffle!(
12300                a,
12301                b,
12302                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12303            ),
12304            3 => simd_shuffle!(
12305                a,
12306                b,
12307                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12308            ),
12309            4 => simd_shuffle!(
12310                a,
12311                b,
12312                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12313            ),
12314            5 => simd_shuffle!(
12315                a,
12316                b,
12317                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12318            ),
12319            6 => simd_shuffle!(
12320                a,
12321                b,
12322                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12323            ),
12324            7 => simd_shuffle!(
12325                a,
12326                b,
12327                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12328            ),
12329            8 => simd_shuffle!(
12330                a,
12331                b,
12332                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12333            ),
12334            9 => simd_shuffle!(
12335                a,
12336                b,
12337                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12338            ),
12339            10 => simd_shuffle!(
12340                a,
12341                b,
12342                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12343            ),
12344            11 => simd_shuffle!(
12345                a,
12346                b,
12347                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12348            ),
12349            12 => simd_shuffle!(
12350                a,
12351                b,
12352                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12353            ),
12354            13 => simd_shuffle!(
12355                a,
12356                b,
12357                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12358            ),
12359            14 => simd_shuffle!(
12360                a,
12361                b,
12362                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12363            ),
12364            15 => simd_shuffle!(
12365                a,
12366                b,
12367                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12368            ),
12369            _ => unreachable_unchecked(),
12370        }
12371    }
12372}
12373#[doc = "Extract vector from pair of vectors"]
12374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
12375#[inline]
12376#[target_feature(enable = "neon")]
12377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12379#[cfg_attr(
12380    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12381    assert_instr(ext, N = 15)
12382)]
12383#[rustc_legacy_const_generics(2)]
12384#[cfg_attr(
12385    not(target_arch = "arm"),
12386    stable(feature = "neon_intrinsics", since = "1.59.0")
12387)]
12388#[cfg_attr(
12389    target_arch = "arm",
12390    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12391)]
12392pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
12393    static_assert_uimm_bits!(N, 4);
12394    unsafe {
12395        match N & 0b1111 {
12396            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12397            1 => simd_shuffle!(
12398                a,
12399                b,
12400                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12401            ),
12402            2 => simd_shuffle!(
12403                a,
12404                b,
12405                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12406            ),
12407            3 => simd_shuffle!(
12408                a,
12409                b,
12410                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12411            ),
12412            4 => simd_shuffle!(
12413                a,
12414                b,
12415                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12416            ),
12417            5 => simd_shuffle!(
12418                a,
12419                b,
12420                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12421            ),
12422            6 => simd_shuffle!(
12423                a,
12424                b,
12425                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12426            ),
12427            7 => simd_shuffle!(
12428                a,
12429                b,
12430                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12431            ),
12432            8 => simd_shuffle!(
12433                a,
12434                b,
12435                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12436            ),
12437            9 => simd_shuffle!(
12438                a,
12439                b,
12440                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12441            ),
12442            10 => simd_shuffle!(
12443                a,
12444                b,
12445                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12446            ),
12447            11 => simd_shuffle!(
12448                a,
12449                b,
12450                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12451            ),
12452            12 => simd_shuffle!(
12453                a,
12454                b,
12455                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12456            ),
12457            13 => simd_shuffle!(
12458                a,
12459                b,
12460                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12461            ),
12462            14 => simd_shuffle!(
12463                a,
12464                b,
12465                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12466            ),
12467            15 => simd_shuffle!(
12468                a,
12469                b,
12470                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12471            ),
12472            _ => unreachable_unchecked(),
12473        }
12474    }
12475}
12476#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
12478#[inline]
12479#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12481#[cfg_attr(
12482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12483    assert_instr(fmla)
12484)]
12485#[target_feature(enable = "neon,fp16")]
12486#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12487pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12488    unsafe extern "unadjusted" {
12489        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f16")]
12490        #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f16")]
12491        fn _vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
12492    }
12493    unsafe { _vfma_f16(b, c, a) }
12494}
12495#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
12497#[inline]
12498#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12500#[cfg_attr(
12501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12502    assert_instr(fmla)
12503)]
12504#[target_feature(enable = "neon,fp16")]
12505#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12506pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12507    unsafe extern "unadjusted" {
12508        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v8f16")]
12509        #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v8f16")]
12510        fn _vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
12511    }
12512    unsafe { _vfmaq_f16(b, c, a) }
12513}
12514#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
12516#[inline]
12517#[target_feature(enable = "neon")]
12518#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12520#[cfg_attr(
12521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12522    assert_instr(fmla)
12523)]
12524#[cfg_attr(
12525    not(target_arch = "arm"),
12526    stable(feature = "neon_intrinsics", since = "1.59.0")
12527)]
12528#[cfg_attr(
12529    target_arch = "arm",
12530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12531)]
12532pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12533    unsafe extern "unadjusted" {
12534        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f32")]
12535        #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")]
12536        fn _vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
12537    }
12538    unsafe { _vfma_f32(b, c, a) }
12539}
12540#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
12542#[inline]
12543#[target_feature(enable = "neon")]
12544#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12546#[cfg_attr(
12547    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12548    assert_instr(fmla)
12549)]
12550#[cfg_attr(
12551    not(target_arch = "arm"),
12552    stable(feature = "neon_intrinsics", since = "1.59.0")
12553)]
12554#[cfg_attr(
12555    target_arch = "arm",
12556    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12557)]
12558pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12559    unsafe extern "unadjusted" {
12560        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f32")]
12561        #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")]
12562        fn _vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
12563    }
12564    unsafe { _vfmaq_f32(b, c, a) }
12565}
12566#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
12568#[inline]
12569#[target_feature(enable = "neon")]
12570#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12572#[cfg_attr(
12573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12574    assert_instr(fmla)
12575)]
12576#[cfg_attr(
12577    not(target_arch = "arm"),
12578    stable(feature = "neon_intrinsics", since = "1.59.0")
12579)]
12580#[cfg_attr(
12581    target_arch = "arm",
12582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12583)]
12584pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12585    vfma_f32(a, b, vdup_n_f32_vfp4(c))
12586}
12587#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
12589#[inline]
12590#[target_feature(enable = "neon")]
12591#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12593#[cfg_attr(
12594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12595    assert_instr(fmla)
12596)]
12597#[cfg_attr(
12598    not(target_arch = "arm"),
12599    stable(feature = "neon_intrinsics", since = "1.59.0")
12600)]
12601#[cfg_attr(
12602    target_arch = "arm",
12603    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12604)]
12605pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12606    vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
12607}
12608#[doc = "Floating-point fused multiply-subtract from accumulator"]
12609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
12610#[inline]
12611#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12612#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12614#[cfg_attr(
12615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12616    assert_instr(fmls)
12617)]
12618#[target_feature(enable = "neon,fp16")]
12619#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12620pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12621    unsafe {
12622        let b: float16x4_t = simd_neg(b);
12623        vfma_f16(a, b, c)
12624    }
12625}
12626#[doc = "Floating-point fused multiply-subtract from accumulator"]
12627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
12628#[inline]
12629#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12630#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12632#[cfg_attr(
12633    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12634    assert_instr(fmls)
12635)]
12636#[target_feature(enable = "neon,fp16")]
12637#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12638pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12639    unsafe {
12640        let b: float16x8_t = simd_neg(b);
12641        vfmaq_f16(a, b, c)
12642    }
12643}
12644#[doc = "Floating-point fused multiply-subtract from accumulator"]
12645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
12646#[inline]
12647#[target_feature(enable = "neon")]
12648#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12650#[cfg_attr(
12651    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12652    assert_instr(fmls)
12653)]
12654#[cfg_attr(
12655    not(target_arch = "arm"),
12656    stable(feature = "neon_intrinsics", since = "1.59.0")
12657)]
12658#[cfg_attr(
12659    target_arch = "arm",
12660    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12661)]
12662pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12663    unsafe {
12664        let b: float32x2_t = simd_neg(b);
12665        vfma_f32(a, b, c)
12666    }
12667}
12668#[doc = "Floating-point fused multiply-subtract from accumulator"]
12669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
12670#[inline]
12671#[target_feature(enable = "neon")]
12672#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12674#[cfg_attr(
12675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12676    assert_instr(fmls)
12677)]
12678#[cfg_attr(
12679    not(target_arch = "arm"),
12680    stable(feature = "neon_intrinsics", since = "1.59.0")
12681)]
12682#[cfg_attr(
12683    target_arch = "arm",
12684    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12685)]
12686pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12687    unsafe {
12688        let b: float32x4_t = simd_neg(b);
12689        vfmaq_f32(a, b, c)
12690    }
12691}
12692#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
12694#[inline]
12695#[target_feature(enable = "neon")]
12696#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12698#[cfg_attr(
12699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12700    assert_instr(fmls)
12701)]
12702#[cfg_attr(
12703    not(target_arch = "arm"),
12704    stable(feature = "neon_intrinsics", since = "1.59.0")
12705)]
12706#[cfg_attr(
12707    target_arch = "arm",
12708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12709)]
12710pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12711    vfms_f32(a, b, vdup_n_f32_vfp4(c))
12712}
12713#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
12715#[inline]
12716#[target_feature(enable = "neon")]
12717#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12719#[cfg_attr(
12720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12721    assert_instr(fmls)
12722)]
12723#[cfg_attr(
12724    not(target_arch = "arm"),
12725    stable(feature = "neon_intrinsics", since = "1.59.0")
12726)]
12727#[cfg_attr(
12728    target_arch = "arm",
12729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12730)]
12731pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12732    vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
12733}
12734#[doc = "Duplicate vector element to vector"]
12735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
12736#[inline]
12737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12738#[target_feature(enable = "neon,fp16")]
12739#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12740#[cfg_attr(test, assert_instr(nop))]
12741pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
12742    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12743}
12744#[doc = "Duplicate vector element to vector"]
12745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
12746#[inline]
12747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12748#[target_feature(enable = "neon,fp16")]
12749#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12750#[cfg_attr(test, assert_instr(nop))]
12751pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
12752    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
12753}
12754#[doc = "Duplicate vector element to vector or scalar"]
12755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
12756#[inline]
12757#[target_feature(enable = "neon")]
12758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12759#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12760#[cfg_attr(
12761    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12762    assert_instr(ext)
12763)]
12764#[cfg_attr(
12765    not(target_arch = "arm"),
12766    stable(feature = "neon_intrinsics", since = "1.59.0")
12767)]
12768#[cfg_attr(
12769    target_arch = "arm",
12770    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12771)]
12772pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
12773    unsafe { simd_shuffle!(a, a, [2, 3]) }
12774}
12775#[doc = "Duplicate vector element to vector or scalar"]
12776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
12777#[inline]
12778#[target_feature(enable = "neon")]
12779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12780#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12781#[cfg_attr(
12782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12783    assert_instr(ext)
12784)]
12785#[cfg_attr(
12786    not(target_arch = "arm"),
12787    stable(feature = "neon_intrinsics", since = "1.59.0")
12788)]
12789#[cfg_attr(
12790    target_arch = "arm",
12791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12792)]
12793pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
12794    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12795}
12796#[doc = "Duplicate vector element to vector or scalar"]
12797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
12798#[inline]
12799#[target_feature(enable = "neon")]
12800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12802#[cfg_attr(
12803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12804    assert_instr(ext)
12805)]
12806#[cfg_attr(
12807    not(target_arch = "arm"),
12808    stable(feature = "neon_intrinsics", since = "1.59.0")
12809)]
12810#[cfg_attr(
12811    target_arch = "arm",
12812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12813)]
12814pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
12815    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12816}
12817#[doc = "Duplicate vector element to vector or scalar"]
12818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
12819#[inline]
12820#[target_feature(enable = "neon")]
12821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12823#[cfg_attr(
12824    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12825    assert_instr(ext)
12826)]
12827#[cfg_attr(
12828    not(target_arch = "arm"),
12829    stable(feature = "neon_intrinsics", since = "1.59.0")
12830)]
12831#[cfg_attr(
12832    target_arch = "arm",
12833    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12834)]
12835pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
12836    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12837}
12838#[doc = "Duplicate vector element to vector or scalar"]
12839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
12840#[inline]
12841#[target_feature(enable = "neon")]
12842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12844#[cfg_attr(
12845    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12846    assert_instr(ext)
12847)]
12848#[cfg_attr(
12849    not(target_arch = "arm"),
12850    stable(feature = "neon_intrinsics", since = "1.59.0")
12851)]
12852#[cfg_attr(
12853    target_arch = "arm",
12854    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12855)]
12856pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
12857    unsafe { simd_shuffle!(a, a, [2, 3]) }
12858}
12859#[doc = "Duplicate vector element to vector or scalar"]
12860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
12861#[inline]
12862#[target_feature(enable = "neon")]
12863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12865#[cfg_attr(
12866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12867    assert_instr(ext)
12868)]
12869#[cfg_attr(
12870    not(target_arch = "arm"),
12871    stable(feature = "neon_intrinsics", since = "1.59.0")
12872)]
12873#[cfg_attr(
12874    target_arch = "arm",
12875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12876)]
12877pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
12878    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12879}
12880#[doc = "Duplicate vector element to vector or scalar"]
12881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
12882#[inline]
12883#[target_feature(enable = "neon")]
12884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12886#[cfg_attr(
12887    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12888    assert_instr(ext)
12889)]
12890#[cfg_attr(
12891    not(target_arch = "arm"),
12892    stable(feature = "neon_intrinsics", since = "1.59.0")
12893)]
12894#[cfg_attr(
12895    target_arch = "arm",
12896    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12897)]
12898pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
12899    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12900}
12901#[doc = "Duplicate vector element to vector or scalar"]
12902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
12903#[inline]
12904#[target_feature(enable = "neon")]
12905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12907#[cfg_attr(
12908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12909    assert_instr(ext)
12910)]
12911#[cfg_attr(
12912    not(target_arch = "arm"),
12913    stable(feature = "neon_intrinsics", since = "1.59.0")
12914)]
12915#[cfg_attr(
12916    target_arch = "arm",
12917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12918)]
12919pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
12920    unsafe { simd_shuffle!(a, a, [2, 3]) }
12921}
12922#[doc = "Duplicate vector element to vector or scalar"]
12923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
12924#[inline]
12925#[target_feature(enable = "neon")]
12926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12927#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12928#[cfg_attr(
12929    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12930    assert_instr(ext)
12931)]
12932#[cfg_attr(
12933    not(target_arch = "arm"),
12934    stable(feature = "neon_intrinsics", since = "1.59.0")
12935)]
12936#[cfg_attr(
12937    target_arch = "arm",
12938    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12939)]
12940pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
12941    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12942}
12943#[doc = "Duplicate vector element to vector or scalar"]
12944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
12945#[inline]
12946#[target_feature(enable = "neon")]
12947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12948#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12949#[cfg_attr(
12950    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12951    assert_instr(ext)
12952)]
12953#[cfg_attr(
12954    not(target_arch = "arm"),
12955    stable(feature = "neon_intrinsics", since = "1.59.0")
12956)]
12957#[cfg_attr(
12958    target_arch = "arm",
12959    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12960)]
12961pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
12962    unsafe { int64x1_t([simd_extract!(a, 1)]) }
12963}
12964#[doc = "Duplicate vector element to vector or scalar"]
12965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
12966#[inline]
12967#[target_feature(enable = "neon")]
12968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12969#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12970#[cfg_attr(
12971    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12972    assert_instr(ext)
12973)]
12974#[cfg_attr(
12975    not(target_arch = "arm"),
12976    stable(feature = "neon_intrinsics", since = "1.59.0")
12977)]
12978#[cfg_attr(
12979    target_arch = "arm",
12980    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12981)]
12982pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
12983    unsafe { uint64x1_t([simd_extract!(a, 1)]) }
12984}
12985#[doc = "Duplicate vector element to scalar"]
12986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
12987#[inline]
12988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12989#[target_feature(enable = "neon,fp16")]
12990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12991#[cfg_attr(
12992    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12993    assert_instr(nop, LANE = 0)
12994)]
12995#[rustc_legacy_const_generics(1)]
12996#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12997pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
12998    static_assert_uimm_bits!(LANE, 2);
12999    unsafe { simd_extract!(a, LANE as u32) }
13000}
13001#[doc = "Duplicate vector element to scalar"]
13002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
13003#[inline]
13004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13005#[target_feature(enable = "neon,fp16")]
13006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
13007#[cfg_attr(
13008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13009    assert_instr(nop, LANE = 0)
13010)]
13011#[rustc_legacy_const_generics(1)]
13012#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
13013pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
13014    static_assert_uimm_bits!(LANE, 3);
13015    unsafe { simd_extract!(a, LANE as u32) }
13016}
13017#[doc = "Move vector element to general-purpose register"]
13018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
13019#[inline]
13020#[target_feature(enable = "neon")]
13021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13022#[rustc_legacy_const_generics(1)]
13023#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13024#[cfg_attr(
13025    not(target_arch = "arm"),
13026    stable(feature = "neon_intrinsics", since = "1.59.0")
13027)]
13028#[cfg_attr(
13029    target_arch = "arm",
13030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13031)]
13032pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
13033    static_assert_uimm_bits!(IMM5, 1);
13034    unsafe { simd_extract!(v, IMM5 as u32) }
13035}
13036#[doc = "Move vector element to general-purpose register"]
13037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
13038#[inline]
13039#[target_feature(enable = "neon")]
13040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13041#[rustc_legacy_const_generics(1)]
13042#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13043#[cfg_attr(
13044    not(target_arch = "arm"),
13045    stable(feature = "neon_intrinsics", since = "1.59.0")
13046)]
13047#[cfg_attr(
13048    target_arch = "arm",
13049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13050)]
13051pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
13052    static_assert_uimm_bits!(IMM5, 2);
13053    unsafe { simd_extract!(v, IMM5 as u32) }
13054}
13055#[doc = "Move vector element to general-purpose register"]
13056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
13057#[inline]
13058#[target_feature(enable = "neon")]
13059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13060#[rustc_legacy_const_generics(1)]
13061#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13062#[cfg_attr(
13063    not(target_arch = "arm"),
13064    stable(feature = "neon_intrinsics", since = "1.59.0")
13065)]
13066#[cfg_attr(
13067    target_arch = "arm",
13068    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13069)]
13070pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
13071    static_assert_uimm_bits!(IMM5, 3);
13072    unsafe { simd_extract!(v, IMM5 as u32) }
13073}
13074#[doc = "Move vector element to general-purpose register"]
13075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
13076#[inline]
13077#[target_feature(enable = "neon")]
13078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13079#[rustc_legacy_const_generics(1)]
13080#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13081#[cfg_attr(
13082    not(target_arch = "arm"),
13083    stable(feature = "neon_intrinsics", since = "1.59.0")
13084)]
13085#[cfg_attr(
13086    target_arch = "arm",
13087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13088)]
13089pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
13090    static_assert_uimm_bits!(IMM5, 2);
13091    unsafe { simd_extract!(v, IMM5 as u32) }
13092}
13093#[doc = "Move vector element to general-purpose register"]
13094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
13095#[inline]
13096#[target_feature(enable = "neon")]
13097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13098#[rustc_legacy_const_generics(1)]
13099#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13100#[cfg_attr(
13101    not(target_arch = "arm"),
13102    stable(feature = "neon_intrinsics", since = "1.59.0")
13103)]
13104#[cfg_attr(
13105    target_arch = "arm",
13106    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13107)]
13108pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
13109    static_assert_uimm_bits!(IMM5, 1);
13110    unsafe { simd_extract!(v, IMM5 as u32) }
13111}
13112#[doc = "Move vector element to general-purpose register"]
13113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
13114#[inline]
13115#[target_feature(enable = "neon")]
13116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13117#[rustc_legacy_const_generics(1)]
13118#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13119#[cfg_attr(
13120    not(target_arch = "arm"),
13121    stable(feature = "neon_intrinsics", since = "1.59.0")
13122)]
13123#[cfg_attr(
13124    target_arch = "arm",
13125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13126)]
13127pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
13128    static_assert_uimm_bits!(IMM5, 3);
13129    unsafe { simd_extract!(v, IMM5 as u32) }
13130}
13131#[doc = "Move vector element to general-purpose register"]
13132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
13133#[inline]
13134#[target_feature(enable = "neon")]
13135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13136#[rustc_legacy_const_generics(1)]
13137#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13138#[cfg_attr(
13139    not(target_arch = "arm"),
13140    stable(feature = "neon_intrinsics", since = "1.59.0")
13141)]
13142#[cfg_attr(
13143    target_arch = "arm",
13144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13145)]
13146pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
13147    static_assert_uimm_bits!(IMM5, 2);
13148    unsafe { simd_extract!(v, IMM5 as u32) }
13149}
13150#[doc = "Move vector element to general-purpose register"]
13151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
13152#[inline]
13153#[target_feature(enable = "neon")]
13154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13155#[rustc_legacy_const_generics(1)]
13156#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13157#[cfg_attr(
13158    not(target_arch = "arm"),
13159    stable(feature = "neon_intrinsics", since = "1.59.0")
13160)]
13161#[cfg_attr(
13162    target_arch = "arm",
13163    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13164)]
13165pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
13166    static_assert_uimm_bits!(IMM5, 1);
13167    unsafe { simd_extract!(v, IMM5 as u32) }
13168}
13169#[doc = "Move vector element to general-purpose register"]
13170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
13171#[inline]
13172#[target_feature(enable = "neon")]
13173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13174#[rustc_legacy_const_generics(1)]
13175#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13176#[cfg_attr(
13177    not(target_arch = "arm"),
13178    stable(feature = "neon_intrinsics", since = "1.59.0")
13179)]
13180#[cfg_attr(
13181    target_arch = "arm",
13182    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13183)]
13184pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
13185    static_assert_uimm_bits!(IMM5, 3);
13186    unsafe { simd_extract!(v, IMM5 as u32) }
13187}
13188#[doc = "Move vector element to general-purpose register"]
13189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
13190#[inline]
13191#[target_feature(enable = "neon")]
13192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13193#[rustc_legacy_const_generics(1)]
13194#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13195#[cfg_attr(
13196    not(target_arch = "arm"),
13197    stable(feature = "neon_intrinsics", since = "1.59.0")
13198)]
13199#[cfg_attr(
13200    target_arch = "arm",
13201    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13202)]
13203pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
13204    static_assert_uimm_bits!(IMM5, 2);
13205    unsafe { simd_extract!(v, IMM5 as u32) }
13206}
13207#[doc = "Move vector element to general-purpose register"]
13208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
13209#[inline]
13210#[target_feature(enable = "neon")]
13211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13212#[rustc_legacy_const_generics(1)]
13213#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13214#[cfg_attr(
13215    not(target_arch = "arm"),
13216    stable(feature = "neon_intrinsics", since = "1.59.0")
13217)]
13218#[cfg_attr(
13219    target_arch = "arm",
13220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13221)]
13222pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
13223    static_assert_uimm_bits!(IMM5, 3);
13224    unsafe { simd_extract!(v, IMM5 as u32) }
13225}
13226#[doc = "Move vector element to general-purpose register"]
13227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
13228#[inline]
13229#[target_feature(enable = "neon")]
13230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13231#[rustc_legacy_const_generics(1)]
13232#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13233#[cfg_attr(
13234    not(target_arch = "arm"),
13235    stable(feature = "neon_intrinsics", since = "1.59.0")
13236)]
13237#[cfg_attr(
13238    target_arch = "arm",
13239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13240)]
13241pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
13242    static_assert_uimm_bits!(IMM5, 1);
13243    unsafe { simd_extract!(v, IMM5 as u32) }
13244}
13245#[doc = "Move vector element to general-purpose register"]
13246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
13247#[inline]
13248#[target_feature(enable = "neon")]
13249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13250#[rustc_legacy_const_generics(1)]
13251#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13252#[cfg_attr(
13253    not(target_arch = "arm"),
13254    stable(feature = "neon_intrinsics", since = "1.59.0")
13255)]
13256#[cfg_attr(
13257    target_arch = "arm",
13258    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13259)]
13260pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
13261    static_assert_uimm_bits!(IMM5, 4);
13262    unsafe { simd_extract!(v, IMM5 as u32) }
13263}
13264#[doc = "Move vector element to general-purpose register"]
13265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
13266#[inline]
13267#[target_feature(enable = "neon")]
13268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13269#[rustc_legacy_const_generics(1)]
13270#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13271#[cfg_attr(
13272    not(target_arch = "arm"),
13273    stable(feature = "neon_intrinsics", since = "1.59.0")
13274)]
13275#[cfg_attr(
13276    target_arch = "arm",
13277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13278)]
13279pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
13280    static_assert_uimm_bits!(IMM5, 3);
13281    unsafe { simd_extract!(v, IMM5 as u32) }
13282}
13283#[doc = "Move vector element to general-purpose register"]
13284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
13285#[inline]
13286#[target_feature(enable = "neon")]
13287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13288#[rustc_legacy_const_generics(1)]
13289#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13290#[cfg_attr(
13291    not(target_arch = "arm"),
13292    stable(feature = "neon_intrinsics", since = "1.59.0")
13293)]
13294#[cfg_attr(
13295    target_arch = "arm",
13296    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13297)]
13298pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
13299    static_assert_uimm_bits!(IMM5, 2);
13300    unsafe { simd_extract!(v, IMM5 as u32) }
13301}
13302#[doc = "Move vector element to general-purpose register"]
13303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
13304#[inline]
13305#[target_feature(enable = "neon")]
13306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13307#[rustc_legacy_const_generics(1)]
13308#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13309#[cfg_attr(
13310    not(target_arch = "arm"),
13311    stable(feature = "neon_intrinsics", since = "1.59.0")
13312)]
13313#[cfg_attr(
13314    target_arch = "arm",
13315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13316)]
13317pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
13318    static_assert_uimm_bits!(IMM5, 1);
13319    unsafe { simd_extract!(v, IMM5 as u32) }
13320}
13321#[doc = "Move vector element to general-purpose register"]
13322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
13323#[inline]
13324#[target_feature(enable = "neon")]
13325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13326#[rustc_legacy_const_generics(1)]
13327#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13328#[cfg_attr(
13329    not(target_arch = "arm"),
13330    stable(feature = "neon_intrinsics", since = "1.59.0")
13331)]
13332#[cfg_attr(
13333    target_arch = "arm",
13334    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13335)]
13336pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
13337    static_assert_uimm_bits!(IMM5, 4);
13338    unsafe { simd_extract!(v, IMM5 as u32) }
13339}
13340#[doc = "Move vector element to general-purpose register"]
13341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
13342#[inline]
13343#[target_feature(enable = "neon")]
13344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13345#[rustc_legacy_const_generics(1)]
13346#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13347#[cfg_attr(
13348    not(target_arch = "arm"),
13349    stable(feature = "neon_intrinsics", since = "1.59.0")
13350)]
13351#[cfg_attr(
13352    target_arch = "arm",
13353    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13354)]
13355pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
13356    static_assert_uimm_bits!(IMM5, 3);
13357    unsafe { simd_extract!(v, IMM5 as u32) }
13358}
13359#[doc = "Move vector element to general-purpose register"]
13360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
13361#[inline]
13362#[target_feature(enable = "neon")]
13363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13364#[rustc_legacy_const_generics(1)]
13365#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13366#[cfg_attr(
13367    not(target_arch = "arm"),
13368    stable(feature = "neon_intrinsics", since = "1.59.0")
13369)]
13370#[cfg_attr(
13371    target_arch = "arm",
13372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13373)]
13374pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
13375    static_assert_uimm_bits!(IMM5, 2);
13376    unsafe { simd_extract!(v, IMM5 as u32) }
13377}
13378#[doc = "Move vector element to general-purpose register"]
13379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
13380#[inline]
13381#[target_feature(enable = "neon")]
13382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13383#[rustc_legacy_const_generics(1)]
13384#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13385#[cfg_attr(
13386    not(target_arch = "arm"),
13387    stable(feature = "neon_intrinsics", since = "1.59.0")
13388)]
13389#[cfg_attr(
13390    target_arch = "arm",
13391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13392)]
13393pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
13394    static_assert_uimm_bits!(IMM5, 2);
13395    unsafe { simd_extract!(v, IMM5 as u32) }
13396}
13397#[doc = "Move vector element to general-purpose register"]
13398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
13399#[inline]
13400#[target_feature(enable = "neon")]
13401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13402#[rustc_legacy_const_generics(1)]
13403#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13404#[cfg_attr(
13405    not(target_arch = "arm"),
13406    stable(feature = "neon_intrinsics", since = "1.59.0")
13407)]
13408#[cfg_attr(
13409    target_arch = "arm",
13410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13411)]
13412pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
13413    static_assert_uimm_bits!(IMM5, 4);
13414    unsafe { simd_extract!(v, IMM5 as u32) }
13415}
13416#[doc = "Move vector element to general-purpose register"]
13417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
13418#[inline]
13419#[target_feature(enable = "neon")]
13420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13421#[rustc_legacy_const_generics(1)]
13422#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13423#[cfg_attr(
13424    not(target_arch = "arm"),
13425    stable(feature = "neon_intrinsics", since = "1.59.0")
13426)]
13427#[cfg_attr(
13428    target_arch = "arm",
13429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13430)]
13431pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
13432    static_assert!(IMM5 == 0);
13433    unsafe { simd_extract!(v, IMM5 as u32) }
13434}
13435#[doc = "Move vector element to general-purpose register"]
13436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
13437#[inline]
13438#[target_feature(enable = "neon")]
13439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13440#[rustc_legacy_const_generics(1)]
13441#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13442#[cfg_attr(
13443    not(target_arch = "arm"),
13444    stable(feature = "neon_intrinsics", since = "1.59.0")
13445)]
13446#[cfg_attr(
13447    target_arch = "arm",
13448    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13449)]
13450pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
13451    static_assert!(IMM5 == 0);
13452    unsafe { simd_extract!(v, IMM5 as u32) }
13453}
13454#[doc = "Move vector element to general-purpose register"]
13455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
13456#[inline]
13457#[target_feature(enable = "neon")]
13458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13459#[rustc_legacy_const_generics(1)]
13460#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13461#[cfg_attr(
13462    not(target_arch = "arm"),
13463    stable(feature = "neon_intrinsics", since = "1.59.0")
13464)]
13465#[cfg_attr(
13466    target_arch = "arm",
13467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13468)]
13469pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
13470    static_assert!(IMM5 == 0);
13471    unsafe { simd_extract!(v, 0) }
13472}
13473#[doc = "Duplicate vector element to vector or scalar"]
13474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
13475#[inline]
13476#[target_feature(enable = "neon")]
13477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13478#[cfg_attr(test, assert_instr(nop))]
13479#[cfg_attr(
13480    not(target_arch = "arm"),
13481    stable(feature = "neon_intrinsics", since = "1.59.0")
13482)]
13483#[cfg_attr(
13484    target_arch = "arm",
13485    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13486)]
13487pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
13488    unsafe { simd_shuffle!(a, a, [0, 1]) }
13489}
13490#[doc = "Duplicate vector element to vector or scalar"]
13491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
13492#[inline]
13493#[target_feature(enable = "neon")]
13494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13495#[cfg_attr(test, assert_instr(nop))]
13496#[cfg_attr(
13497    not(target_arch = "arm"),
13498    stable(feature = "neon_intrinsics", since = "1.59.0")
13499)]
13500#[cfg_attr(
13501    target_arch = "arm",
13502    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13503)]
13504pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
13505    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13506}
13507#[doc = "Duplicate vector element to vector or scalar"]
13508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
13509#[inline]
13510#[target_feature(enable = "neon")]
13511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13512#[cfg_attr(test, assert_instr(nop))]
13513#[cfg_attr(
13514    not(target_arch = "arm"),
13515    stable(feature = "neon_intrinsics", since = "1.59.0")
13516)]
13517#[cfg_attr(
13518    target_arch = "arm",
13519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13520)]
13521pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
13522    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13523}
13524#[doc = "Duplicate vector element to vector or scalar"]
13525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
13526#[inline]
13527#[target_feature(enable = "neon")]
13528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13529#[cfg_attr(test, assert_instr(nop))]
13530#[cfg_attr(
13531    not(target_arch = "arm"),
13532    stable(feature = "neon_intrinsics", since = "1.59.0")
13533)]
13534#[cfg_attr(
13535    target_arch = "arm",
13536    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13537)]
13538pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
13539    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13540}
13541#[doc = "Duplicate vector element to vector or scalar"]
13542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
13543#[inline]
13544#[target_feature(enable = "neon")]
13545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13546#[cfg_attr(test, assert_instr(nop))]
13547#[cfg_attr(
13548    not(target_arch = "arm"),
13549    stable(feature = "neon_intrinsics", since = "1.59.0")
13550)]
13551#[cfg_attr(
13552    target_arch = "arm",
13553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13554)]
13555pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
13556    unsafe { simd_shuffle!(a, a, [0, 1]) }
13557}
13558#[doc = "Duplicate vector element to vector or scalar"]
13559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
13560#[inline]
13561#[target_feature(enable = "neon")]
13562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13563#[cfg_attr(test, assert_instr(nop))]
13564#[cfg_attr(
13565    not(target_arch = "arm"),
13566    stable(feature = "neon_intrinsics", since = "1.59.0")
13567)]
13568#[cfg_attr(
13569    target_arch = "arm",
13570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13571)]
13572pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
13573    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13574}
13575#[doc = "Duplicate vector element to vector or scalar"]
13576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
13577#[inline]
13578#[target_feature(enable = "neon")]
13579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13580#[cfg_attr(test, assert_instr(nop))]
13581#[cfg_attr(
13582    not(target_arch = "arm"),
13583    stable(feature = "neon_intrinsics", since = "1.59.0")
13584)]
13585#[cfg_attr(
13586    target_arch = "arm",
13587    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13588)]
13589pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
13590    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13591}
13592#[doc = "Duplicate vector element to vector or scalar"]
13593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
13594#[inline]
13595#[target_feature(enable = "neon")]
13596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13597#[cfg_attr(test, assert_instr(nop))]
13598#[cfg_attr(
13599    not(target_arch = "arm"),
13600    stable(feature = "neon_intrinsics", since = "1.59.0")
13601)]
13602#[cfg_attr(
13603    target_arch = "arm",
13604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13605)]
13606pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
13607    unsafe { simd_shuffle!(a, a, [0, 1]) }
13608}
13609#[doc = "Duplicate vector element to vector or scalar"]
13610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
13611#[inline]
13612#[target_feature(enable = "neon")]
13613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13614#[cfg_attr(test, assert_instr(nop))]
13615#[cfg_attr(
13616    not(target_arch = "arm"),
13617    stable(feature = "neon_intrinsics", since = "1.59.0")
13618)]
13619#[cfg_attr(
13620    target_arch = "arm",
13621    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13622)]
13623pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
13624    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13625}
13626#[doc = "Duplicate vector element to vector or scalar"]
13627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
13628#[inline]
13629#[target_feature(enable = "neon")]
13630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13631#[cfg_attr(test, assert_instr(nop))]
13632#[cfg_attr(
13633    not(target_arch = "arm"),
13634    stable(feature = "neon_intrinsics", since = "1.59.0")
13635)]
13636#[cfg_attr(
13637    target_arch = "arm",
13638    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13639)]
13640pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
13641    unsafe { int64x1_t([simd_extract!(a, 0)]) }
13642}
13643#[doc = "Duplicate vector element to vector or scalar"]
13644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
13645#[inline]
13646#[target_feature(enable = "neon")]
13647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13648#[cfg_attr(test, assert_instr(nop))]
13649#[cfg_attr(
13650    not(target_arch = "arm"),
13651    stable(feature = "neon_intrinsics", since = "1.59.0")
13652)]
13653#[cfg_attr(
13654    target_arch = "arm",
13655    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13656)]
13657pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
13658    unsafe { uint64x1_t([simd_extract!(a, 0)]) }
13659}
13660#[doc = "Halving add"]
13661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
13662#[inline]
13663#[target_feature(enable = "neon")]
13664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13665#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13666#[cfg_attr(
13667    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13668    assert_instr(shadd)
13669)]
13670#[cfg_attr(
13671    not(target_arch = "arm"),
13672    stable(feature = "neon_intrinsics", since = "1.59.0")
13673)]
13674#[cfg_attr(
13675    target_arch = "arm",
13676    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13677)]
13678pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
13679    unsafe extern "unadjusted" {
13680        #[cfg_attr(
13681            any(target_arch = "aarch64", target_arch = "arm64ec"),
13682            link_name = "llvm.aarch64.neon.shadd.v8i8"
13683        )]
13684        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
13685        fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
13686    }
13687    unsafe { _vhadd_s8(a, b) }
13688}
13689#[doc = "Halving add"]
13690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
13691#[inline]
13692#[target_feature(enable = "neon")]
13693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13695#[cfg_attr(
13696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13697    assert_instr(shadd)
13698)]
13699#[cfg_attr(
13700    not(target_arch = "arm"),
13701    stable(feature = "neon_intrinsics", since = "1.59.0")
13702)]
13703#[cfg_attr(
13704    target_arch = "arm",
13705    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13706)]
13707pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
13708    unsafe extern "unadjusted" {
13709        #[cfg_attr(
13710            any(target_arch = "aarch64", target_arch = "arm64ec"),
13711            link_name = "llvm.aarch64.neon.shadd.v16i8"
13712        )]
13713        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
13714        fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
13715    }
13716    unsafe { _vhaddq_s8(a, b) }
13717}
13718#[doc = "Halving add"]
13719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
13720#[inline]
13721#[target_feature(enable = "neon")]
13722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13723#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13724#[cfg_attr(
13725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13726    assert_instr(shadd)
13727)]
13728#[cfg_attr(
13729    not(target_arch = "arm"),
13730    stable(feature = "neon_intrinsics", since = "1.59.0")
13731)]
13732#[cfg_attr(
13733    target_arch = "arm",
13734    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13735)]
13736pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13737    unsafe extern "unadjusted" {
13738        #[cfg_attr(
13739            any(target_arch = "aarch64", target_arch = "arm64ec"),
13740            link_name = "llvm.aarch64.neon.shadd.v4i16"
13741        )]
13742        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
13743        fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13744    }
13745    unsafe { _vhadd_s16(a, b) }
13746}
13747#[doc = "Halving add"]
13748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
13749#[inline]
13750#[target_feature(enable = "neon")]
13751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13752#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13753#[cfg_attr(
13754    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13755    assert_instr(shadd)
13756)]
13757#[cfg_attr(
13758    not(target_arch = "arm"),
13759    stable(feature = "neon_intrinsics", since = "1.59.0")
13760)]
13761#[cfg_attr(
13762    target_arch = "arm",
13763    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13764)]
13765pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13766    unsafe extern "unadjusted" {
13767        #[cfg_attr(
13768            any(target_arch = "aarch64", target_arch = "arm64ec"),
13769            link_name = "llvm.aarch64.neon.shadd.v8i16"
13770        )]
13771        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
13772        fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13773    }
13774    unsafe { _vhaddq_s16(a, b) }
13775}
13776#[doc = "Halving add"]
13777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
13778#[inline]
13779#[target_feature(enable = "neon")]
13780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13781#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13782#[cfg_attr(
13783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13784    assert_instr(shadd)
13785)]
13786#[cfg_attr(
13787    not(target_arch = "arm"),
13788    stable(feature = "neon_intrinsics", since = "1.59.0")
13789)]
13790#[cfg_attr(
13791    target_arch = "arm",
13792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13793)]
13794pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13795    unsafe extern "unadjusted" {
13796        #[cfg_attr(
13797            any(target_arch = "aarch64", target_arch = "arm64ec"),
13798            link_name = "llvm.aarch64.neon.shadd.v2i32"
13799        )]
13800        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
13801        fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
13802    }
13803    unsafe { _vhadd_s32(a, b) }
13804}
13805#[doc = "Halving add"]
13806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
13807#[inline]
13808#[target_feature(enable = "neon")]
13809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13810#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13811#[cfg_attr(
13812    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13813    assert_instr(shadd)
13814)]
13815#[cfg_attr(
13816    not(target_arch = "arm"),
13817    stable(feature = "neon_intrinsics", since = "1.59.0")
13818)]
13819#[cfg_attr(
13820    target_arch = "arm",
13821    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13822)]
13823pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
13824    unsafe extern "unadjusted" {
13825        #[cfg_attr(
13826            any(target_arch = "aarch64", target_arch = "arm64ec"),
13827            link_name = "llvm.aarch64.neon.shadd.v4i32"
13828        )]
13829        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
13830        fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
13831    }
13832    unsafe { _vhaddq_s32(a, b) }
13833}
13834#[doc = "Halving add"]
13835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
13836#[inline]
13837#[target_feature(enable = "neon")]
13838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13839#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13840#[cfg_attr(
13841    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13842    assert_instr(uhadd)
13843)]
13844#[cfg_attr(
13845    not(target_arch = "arm"),
13846    stable(feature = "neon_intrinsics", since = "1.59.0")
13847)]
13848#[cfg_attr(
13849    target_arch = "arm",
13850    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13851)]
13852pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
13853    unsafe extern "unadjusted" {
13854        #[cfg_attr(
13855            any(target_arch = "aarch64", target_arch = "arm64ec"),
13856            link_name = "llvm.aarch64.neon.uhadd.v8i8"
13857        )]
13858        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
13859        fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
13860    }
13861    unsafe { _vhadd_u8(a, b) }
13862}
13863#[doc = "Halving add"]
13864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
13865#[inline]
13866#[target_feature(enable = "neon")]
13867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13868#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13869#[cfg_attr(
13870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13871    assert_instr(uhadd)
13872)]
13873#[cfg_attr(
13874    not(target_arch = "arm"),
13875    stable(feature = "neon_intrinsics", since = "1.59.0")
13876)]
13877#[cfg_attr(
13878    target_arch = "arm",
13879    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13880)]
13881pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
13882    unsafe extern "unadjusted" {
13883        #[cfg_attr(
13884            any(target_arch = "aarch64", target_arch = "arm64ec"),
13885            link_name = "llvm.aarch64.neon.uhadd.v16i8"
13886        )]
13887        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
13888        fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
13889    }
13890    unsafe { _vhaddq_u8(a, b) }
13891}
13892#[doc = "Halving add"]
13893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
13894#[inline]
13895#[target_feature(enable = "neon")]
13896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13897#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13898#[cfg_attr(
13899    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13900    assert_instr(uhadd)
13901)]
13902#[cfg_attr(
13903    not(target_arch = "arm"),
13904    stable(feature = "neon_intrinsics", since = "1.59.0")
13905)]
13906#[cfg_attr(
13907    target_arch = "arm",
13908    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13909)]
13910pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
13911    unsafe extern "unadjusted" {
13912        #[cfg_attr(
13913            any(target_arch = "aarch64", target_arch = "arm64ec"),
13914            link_name = "llvm.aarch64.neon.uhadd.v4i16"
13915        )]
13916        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
13917        fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
13918    }
13919    unsafe { _vhadd_u16(a, b) }
13920}
13921#[doc = "Halving add"]
13922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
13923#[inline]
13924#[target_feature(enable = "neon")]
13925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13926#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13927#[cfg_attr(
13928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13929    assert_instr(uhadd)
13930)]
13931#[cfg_attr(
13932    not(target_arch = "arm"),
13933    stable(feature = "neon_intrinsics", since = "1.59.0")
13934)]
13935#[cfg_attr(
13936    target_arch = "arm",
13937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13938)]
13939pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
13940    unsafe extern "unadjusted" {
13941        #[cfg_attr(
13942            any(target_arch = "aarch64", target_arch = "arm64ec"),
13943            link_name = "llvm.aarch64.neon.uhadd.v8i16"
13944        )]
13945        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
13946        fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
13947    }
13948    unsafe { _vhaddq_u16(a, b) }
13949}
13950#[doc = "Halving add"]
13951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
13952#[inline]
13953#[target_feature(enable = "neon")]
13954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13956#[cfg_attr(
13957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13958    assert_instr(uhadd)
13959)]
13960#[cfg_attr(
13961    not(target_arch = "arm"),
13962    stable(feature = "neon_intrinsics", since = "1.59.0")
13963)]
13964#[cfg_attr(
13965    target_arch = "arm",
13966    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13967)]
13968pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
13969    unsafe extern "unadjusted" {
13970        #[cfg_attr(
13971            any(target_arch = "aarch64", target_arch = "arm64ec"),
13972            link_name = "llvm.aarch64.neon.uhadd.v2i32"
13973        )]
13974        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
13975        fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
13976    }
13977    unsafe { _vhadd_u32(a, b) }
13978}
13979#[doc = "Halving add"]
13980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
13981#[inline]
13982#[target_feature(enable = "neon")]
13983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13984#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13985#[cfg_attr(
13986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13987    assert_instr(uhadd)
13988)]
13989#[cfg_attr(
13990    not(target_arch = "arm"),
13991    stable(feature = "neon_intrinsics", since = "1.59.0")
13992)]
13993#[cfg_attr(
13994    target_arch = "arm",
13995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13996)]
13997pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
13998    unsafe extern "unadjusted" {
13999        #[cfg_attr(
14000            any(target_arch = "aarch64", target_arch = "arm64ec"),
14001            link_name = "llvm.aarch64.neon.uhadd.v4i32"
14002        )]
14003        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
14004        fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
14005    }
14006    unsafe { _vhaddq_u32(a, b) }
14007}
14008#[doc = "Signed halving subtract"]
14009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
14010#[inline]
14011#[target_feature(enable = "neon")]
14012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14013#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
14014#[cfg_attr(
14015    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14016    assert_instr(shsub)
14017)]
14018#[cfg_attr(
14019    not(target_arch = "arm"),
14020    stable(feature = "neon_intrinsics", since = "1.59.0")
14021)]
14022#[cfg_attr(
14023    target_arch = "arm",
14024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14025)]
14026pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
14027    unsafe extern "unadjusted" {
14028        #[cfg_attr(
14029            any(target_arch = "aarch64", target_arch = "arm64ec"),
14030            link_name = "llvm.aarch64.neon.shsub.v4i16"
14031        )]
14032        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
14033        fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
14034    }
14035    unsafe { _vhsub_s16(a, b) }
14036}
14037#[doc = "Signed halving subtract"]
14038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
14039#[inline]
14040#[target_feature(enable = "neon")]
14041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14042#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
14043#[cfg_attr(
14044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14045    assert_instr(shsub)
14046)]
14047#[cfg_attr(
14048    not(target_arch = "arm"),
14049    stable(feature = "neon_intrinsics", since = "1.59.0")
14050)]
14051#[cfg_attr(
14052    target_arch = "arm",
14053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14054)]
14055pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
14056    unsafe extern "unadjusted" {
14057        #[cfg_attr(
14058            any(target_arch = "aarch64", target_arch = "arm64ec"),
14059            link_name = "llvm.aarch64.neon.shsub.v8i16"
14060        )]
14061        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
14062        fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
14063    }
14064    unsafe { _vhsubq_s16(a, b) }
14065}
14066#[doc = "Signed halving subtract"]
14067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
14068#[inline]
14069#[target_feature(enable = "neon")]
14070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14071#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
14072#[cfg_attr(
14073    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14074    assert_instr(shsub)
14075)]
14076#[cfg_attr(
14077    not(target_arch = "arm"),
14078    stable(feature = "neon_intrinsics", since = "1.59.0")
14079)]
14080#[cfg_attr(
14081    target_arch = "arm",
14082    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14083)]
14084pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
14085    unsafe extern "unadjusted" {
14086        #[cfg_attr(
14087            any(target_arch = "aarch64", target_arch = "arm64ec"),
14088            link_name = "llvm.aarch64.neon.shsub.v2i32"
14089        )]
14090        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
14091        fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
14092    }
14093    unsafe { _vhsub_s32(a, b) }
14094}
14095#[doc = "Signed halving subtract"]
14096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
14097#[inline]
14098#[target_feature(enable = "neon")]
14099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14100#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
14101#[cfg_attr(
14102    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14103    assert_instr(shsub)
14104)]
14105#[cfg_attr(
14106    not(target_arch = "arm"),
14107    stable(feature = "neon_intrinsics", since = "1.59.0")
14108)]
14109#[cfg_attr(
14110    target_arch = "arm",
14111    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14112)]
14113pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14114    unsafe extern "unadjusted" {
14115        #[cfg_attr(
14116            any(target_arch = "aarch64", target_arch = "arm64ec"),
14117            link_name = "llvm.aarch64.neon.shsub.v4i32"
14118        )]
14119        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
14120        fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
14121    }
14122    unsafe { _vhsubq_s32(a, b) }
14123}
14124#[doc = "Signed halving subtract"]
14125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
14126#[inline]
14127#[target_feature(enable = "neon")]
14128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14129#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14130#[cfg_attr(
14131    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14132    assert_instr(shsub)
14133)]
14134#[cfg_attr(
14135    not(target_arch = "arm"),
14136    stable(feature = "neon_intrinsics", since = "1.59.0")
14137)]
14138#[cfg_attr(
14139    target_arch = "arm",
14140    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14141)]
14142pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
14143    unsafe extern "unadjusted" {
14144        #[cfg_attr(
14145            any(target_arch = "aarch64", target_arch = "arm64ec"),
14146            link_name = "llvm.aarch64.neon.shsub.v8i8"
14147        )]
14148        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
14149        fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
14150    }
14151    unsafe { _vhsub_s8(a, b) }
14152}
14153#[doc = "Signed halving subtract"]
14154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
14155#[inline]
14156#[target_feature(enable = "neon")]
14157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14159#[cfg_attr(
14160    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14161    assert_instr(shsub)
14162)]
14163#[cfg_attr(
14164    not(target_arch = "arm"),
14165    stable(feature = "neon_intrinsics", since = "1.59.0")
14166)]
14167#[cfg_attr(
14168    target_arch = "arm",
14169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14170)]
14171pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14172    unsafe extern "unadjusted" {
14173        #[cfg_attr(
14174            any(target_arch = "aarch64", target_arch = "arm64ec"),
14175            link_name = "llvm.aarch64.neon.shsub.v16i8"
14176        )]
14177        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
14178        fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
14179    }
14180    unsafe { _vhsubq_s8(a, b) }
14181}
14182#[doc = "Signed halving subtract"]
14183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
14184#[inline]
14185#[target_feature(enable = "neon")]
14186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14187#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14188#[cfg_attr(
14189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14190    assert_instr(uhsub)
14191)]
14192#[cfg_attr(
14193    not(target_arch = "arm"),
14194    stable(feature = "neon_intrinsics", since = "1.59.0")
14195)]
14196#[cfg_attr(
14197    target_arch = "arm",
14198    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14199)]
14200pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
14201    unsafe extern "unadjusted" {
14202        #[cfg_attr(
14203            any(target_arch = "aarch64", target_arch = "arm64ec"),
14204            link_name = "llvm.aarch64.neon.uhsub.v8i8"
14205        )]
14206        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
14207        fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
14208    }
14209    unsafe { _vhsub_u8(a, b) }
14210}
14211#[doc = "Signed halving subtract"]
14212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
14213#[inline]
14214#[target_feature(enable = "neon")]
14215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14217#[cfg_attr(
14218    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14219    assert_instr(uhsub)
14220)]
14221#[cfg_attr(
14222    not(target_arch = "arm"),
14223    stable(feature = "neon_intrinsics", since = "1.59.0")
14224)]
14225#[cfg_attr(
14226    target_arch = "arm",
14227    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14228)]
14229pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14230    unsafe extern "unadjusted" {
14231        #[cfg_attr(
14232            any(target_arch = "aarch64", target_arch = "arm64ec"),
14233            link_name = "llvm.aarch64.neon.uhsub.v16i8"
14234        )]
14235        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
14236        fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
14237    }
14238    unsafe { _vhsubq_u8(a, b) }
14239}
14240#[doc = "Signed halving subtract"]
14241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
14242#[inline]
14243#[target_feature(enable = "neon")]
14244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14246#[cfg_attr(
14247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14248    assert_instr(uhsub)
14249)]
14250#[cfg_attr(
14251    not(target_arch = "arm"),
14252    stable(feature = "neon_intrinsics", since = "1.59.0")
14253)]
14254#[cfg_attr(
14255    target_arch = "arm",
14256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14257)]
14258pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
14259    unsafe extern "unadjusted" {
14260        #[cfg_attr(
14261            any(target_arch = "aarch64", target_arch = "arm64ec"),
14262            link_name = "llvm.aarch64.neon.uhsub.v4i16"
14263        )]
14264        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
14265        fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
14266    }
14267    unsafe { _vhsub_u16(a, b) }
14268}
14269#[doc = "Signed halving subtract"]
14270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
14271#[inline]
14272#[target_feature(enable = "neon")]
14273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14274#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14275#[cfg_attr(
14276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14277    assert_instr(uhsub)
14278)]
14279#[cfg_attr(
14280    not(target_arch = "arm"),
14281    stable(feature = "neon_intrinsics", since = "1.59.0")
14282)]
14283#[cfg_attr(
14284    target_arch = "arm",
14285    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14286)]
14287pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14288    unsafe extern "unadjusted" {
14289        #[cfg_attr(
14290            any(target_arch = "aarch64", target_arch = "arm64ec"),
14291            link_name = "llvm.aarch64.neon.uhsub.v8i16"
14292        )]
14293        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
14294        fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
14295    }
14296    unsafe { _vhsubq_u16(a, b) }
14297}
14298#[doc = "Signed halving subtract"]
14299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
14300#[inline]
14301#[target_feature(enable = "neon")]
14302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14304#[cfg_attr(
14305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14306    assert_instr(uhsub)
14307)]
14308#[cfg_attr(
14309    not(target_arch = "arm"),
14310    stable(feature = "neon_intrinsics", since = "1.59.0")
14311)]
14312#[cfg_attr(
14313    target_arch = "arm",
14314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14315)]
14316pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
14317    unsafe extern "unadjusted" {
14318        #[cfg_attr(
14319            any(target_arch = "aarch64", target_arch = "arm64ec"),
14320            link_name = "llvm.aarch64.neon.uhsub.v2i32"
14321        )]
14322        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
14323        fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
14324    }
14325    unsafe { _vhsub_u32(a, b) }
14326}
14327#[doc = "Signed halving subtract"]
14328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
14329#[inline]
14330#[target_feature(enable = "neon")]
14331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14332#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14333#[cfg_attr(
14334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14335    assert_instr(uhsub)
14336)]
14337#[cfg_attr(
14338    not(target_arch = "arm"),
14339    stable(feature = "neon_intrinsics", since = "1.59.0")
14340)]
14341#[cfg_attr(
14342    target_arch = "arm",
14343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14344)]
14345pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14346    unsafe extern "unadjusted" {
14347        #[cfg_attr(
14348            any(target_arch = "aarch64", target_arch = "arm64ec"),
14349            link_name = "llvm.aarch64.neon.uhsub.v4i32"
14350        )]
14351        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
14352        fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
14353    }
14354    unsafe { _vhsubq_u32(a, b) }
14355}
14356#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
14358#[doc = "## Safety"]
14359#[doc = "  * Neon instrinsic unsafe"]
14360#[inline]
14361#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14363#[cfg_attr(
14364    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14365    assert_instr(ld1r)
14366)]
14367#[target_feature(enable = "neon,fp16")]
14368#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14369pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
14370    let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
14371    simd_shuffle!(x, x, [0, 0, 0, 0])
14372}
14373#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
14375#[doc = "## Safety"]
14376#[doc = "  * Neon instrinsic unsafe"]
14377#[inline]
14378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14380#[cfg_attr(
14381    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14382    assert_instr(ld1r)
14383)]
14384#[target_feature(enable = "neon,fp16")]
14385#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14386pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
14387    let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
14388    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14389}
14390#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
14392#[doc = "## Safety"]
14393#[doc = "  * Neon instrinsic unsafe"]
14394#[inline]
14395#[target_feature(enable = "neon")]
14396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14397#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14398#[cfg_attr(
14399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14400    assert_instr(ld1r)
14401)]
14402#[cfg_attr(
14403    not(target_arch = "arm"),
14404    stable(feature = "neon_intrinsics", since = "1.59.0")
14405)]
14406#[cfg_attr(
14407    target_arch = "arm",
14408    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14409)]
14410pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
14411    let x = vld1_lane_f32::<0>(ptr, transmute(f32x2::splat(0.0)));
14412    simd_shuffle!(x, x, [0, 0])
14413}
14414#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
14416#[doc = "## Safety"]
14417#[doc = "  * Neon instrinsic unsafe"]
14418#[inline]
14419#[target_feature(enable = "neon")]
14420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14421#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14422#[cfg_attr(
14423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14424    assert_instr(ld1r)
14425)]
14426#[cfg_attr(
14427    not(target_arch = "arm"),
14428    stable(feature = "neon_intrinsics", since = "1.59.0")
14429)]
14430#[cfg_attr(
14431    target_arch = "arm",
14432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14433)]
14434pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
14435    let x = vld1_lane_p16::<0>(ptr, transmute(u16x4::splat(0)));
14436    simd_shuffle!(x, x, [0, 0, 0, 0])
14437}
14438#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
14440#[doc = "## Safety"]
14441#[doc = "  * Neon instrinsic unsafe"]
14442#[inline]
14443#[target_feature(enable = "neon")]
14444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14446#[cfg_attr(
14447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14448    assert_instr(ld1r)
14449)]
14450#[cfg_attr(
14451    not(target_arch = "arm"),
14452    stable(feature = "neon_intrinsics", since = "1.59.0")
14453)]
14454#[cfg_attr(
14455    target_arch = "arm",
14456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14457)]
14458pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
14459    let x = vld1_lane_p8::<0>(ptr, transmute(u8x8::splat(0)));
14460    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14461}
14462#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
14464#[doc = "## Safety"]
14465#[doc = "  * Neon instrinsic unsafe"]
14466#[inline]
14467#[target_feature(enable = "neon")]
14468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14469#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14470#[cfg_attr(
14471    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14472    assert_instr(ld1r)
14473)]
14474#[cfg_attr(
14475    not(target_arch = "arm"),
14476    stable(feature = "neon_intrinsics", since = "1.59.0")
14477)]
14478#[cfg_attr(
14479    target_arch = "arm",
14480    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14481)]
14482pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
14483    let x = vld1_lane_s16::<0>(ptr, transmute(i16x4::splat(0)));
14484    simd_shuffle!(x, x, [0, 0, 0, 0])
14485}
14486#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
14488#[doc = "## Safety"]
14489#[doc = "  * Neon instrinsic unsafe"]
14490#[inline]
14491#[target_feature(enable = "neon")]
14492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14493#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14494#[cfg_attr(
14495    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14496    assert_instr(ld1r)
14497)]
14498#[cfg_attr(
14499    not(target_arch = "arm"),
14500    stable(feature = "neon_intrinsics", since = "1.59.0")
14501)]
14502#[cfg_attr(
14503    target_arch = "arm",
14504    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14505)]
14506pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
14507    let x = vld1_lane_s32::<0>(ptr, transmute(i32x2::splat(0)));
14508    simd_shuffle!(x, x, [0, 0])
14509}
14510#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
14512#[doc = "## Safety"]
14513#[doc = "  * Neon instrinsic unsafe"]
14514#[inline]
14515#[target_feature(enable = "neon")]
14516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14518#[cfg_attr(
14519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14520    assert_instr(ld1r)
14521)]
14522#[cfg_attr(
14523    not(target_arch = "arm"),
14524    stable(feature = "neon_intrinsics", since = "1.59.0")
14525)]
14526#[cfg_attr(
14527    target_arch = "arm",
14528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14529)]
14530pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
14531    let x = vld1_lane_s8::<0>(ptr, transmute(i8x8::splat(0)));
14532    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14533}
14534#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
14536#[doc = "## Safety"]
14537#[doc = "  * Neon instrinsic unsafe"]
14538#[inline]
14539#[target_feature(enable = "neon")]
14540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14542#[cfg_attr(
14543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14544    assert_instr(ld1r)
14545)]
14546#[cfg_attr(
14547    not(target_arch = "arm"),
14548    stable(feature = "neon_intrinsics", since = "1.59.0")
14549)]
14550#[cfg_attr(
14551    target_arch = "arm",
14552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14553)]
14554pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
14555    let x = vld1_lane_u16::<0>(ptr, transmute(u16x4::splat(0)));
14556    simd_shuffle!(x, x, [0, 0, 0, 0])
14557}
14558#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
14560#[doc = "## Safety"]
14561#[doc = "  * Neon instrinsic unsafe"]
14562#[inline]
14563#[target_feature(enable = "neon")]
14564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14565#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14566#[cfg_attr(
14567    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14568    assert_instr(ld1r)
14569)]
14570#[cfg_attr(
14571    not(target_arch = "arm"),
14572    stable(feature = "neon_intrinsics", since = "1.59.0")
14573)]
14574#[cfg_attr(
14575    target_arch = "arm",
14576    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14577)]
14578pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
14579    let x = vld1_lane_u32::<0>(ptr, transmute(u32x2::splat(0)));
14580    simd_shuffle!(x, x, [0, 0])
14581}
14582#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
14584#[doc = "## Safety"]
14585#[doc = "  * Neon instrinsic unsafe"]
14586#[inline]
14587#[target_feature(enable = "neon")]
14588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14589#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14590#[cfg_attr(
14591    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14592    assert_instr(ld1r)
14593)]
14594#[cfg_attr(
14595    not(target_arch = "arm"),
14596    stable(feature = "neon_intrinsics", since = "1.59.0")
14597)]
14598#[cfg_attr(
14599    target_arch = "arm",
14600    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14601)]
14602pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
14603    let x = vld1_lane_u8::<0>(ptr, transmute(u8x8::splat(0)));
14604    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14605}
14606#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
14608#[doc = "## Safety"]
14609#[doc = "  * Neon instrinsic unsafe"]
14610#[inline]
14611#[target_feature(enable = "neon")]
14612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14614#[cfg_attr(
14615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14616    assert_instr(ld1r)
14617)]
14618#[cfg_attr(
14619    not(target_arch = "arm"),
14620    stable(feature = "neon_intrinsics", since = "1.59.0")
14621)]
14622#[cfg_attr(
14623    target_arch = "arm",
14624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14625)]
14626pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
14627    let x = vld1q_lane_f32::<0>(ptr, transmute(f32x4::splat(0.0)));
14628    simd_shuffle!(x, x, [0, 0, 0, 0])
14629}
14630#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
14632#[doc = "## Safety"]
14633#[doc = "  * Neon instrinsic unsafe"]
14634#[inline]
14635#[target_feature(enable = "neon")]
14636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14637#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14638#[cfg_attr(
14639    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14640    assert_instr(ld1r)
14641)]
14642#[cfg_attr(
14643    not(target_arch = "arm"),
14644    stable(feature = "neon_intrinsics", since = "1.59.0")
14645)]
14646#[cfg_attr(
14647    target_arch = "arm",
14648    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14649)]
14650pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
14651    let x = vld1q_lane_p16::<0>(ptr, transmute(u16x8::splat(0)));
14652    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14653}
14654#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
14656#[doc = "## Safety"]
14657#[doc = "  * Neon instrinsic unsafe"]
14658#[inline]
14659#[target_feature(enable = "neon")]
14660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14662#[cfg_attr(
14663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14664    assert_instr(ld1r)
14665)]
14666#[cfg_attr(
14667    not(target_arch = "arm"),
14668    stable(feature = "neon_intrinsics", since = "1.59.0")
14669)]
14670#[cfg_attr(
14671    target_arch = "arm",
14672    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14673)]
14674pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
14675    let x = vld1q_lane_p8::<0>(ptr, transmute(u8x16::splat(0)));
14676    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14677}
14678#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
14680#[doc = "## Safety"]
14681#[doc = "  * Neon instrinsic unsafe"]
14682#[inline]
14683#[target_feature(enable = "neon")]
14684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14686#[cfg_attr(
14687    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14688    assert_instr(ld1r)
14689)]
14690#[cfg_attr(
14691    not(target_arch = "arm"),
14692    stable(feature = "neon_intrinsics", since = "1.59.0")
14693)]
14694#[cfg_attr(
14695    target_arch = "arm",
14696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14697)]
14698pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
14699    let x = vld1q_lane_s16::<0>(ptr, transmute(i16x8::splat(0)));
14700    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14701}
14702#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
14704#[doc = "## Safety"]
14705#[doc = "  * Neon instrinsic unsafe"]
14706#[inline]
14707#[target_feature(enable = "neon")]
14708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14709#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14710#[cfg_attr(
14711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14712    assert_instr(ld1r)
14713)]
14714#[cfg_attr(
14715    not(target_arch = "arm"),
14716    stable(feature = "neon_intrinsics", since = "1.59.0")
14717)]
14718#[cfg_attr(
14719    target_arch = "arm",
14720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14721)]
14722pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
14723    let x = vld1q_lane_s32::<0>(ptr, transmute(i32x4::splat(0)));
14724    simd_shuffle!(x, x, [0, 0, 0, 0])
14725}
14726#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
14728#[doc = "## Safety"]
14729#[doc = "  * Neon instrinsic unsafe"]
14730#[inline]
14731#[target_feature(enable = "neon")]
14732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14733#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14734#[cfg_attr(
14735    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14736    assert_instr(ld1)
14737)]
14738#[cfg_attr(
14739    not(target_arch = "arm"),
14740    stable(feature = "neon_intrinsics", since = "1.59.0")
14741)]
14742#[cfg_attr(
14743    target_arch = "arm",
14744    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14745)]
14746pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
14747    let x = vld1q_lane_s64::<0>(ptr, transmute(i64x2::splat(0)));
14748    simd_shuffle!(x, x, [0, 0])
14749}
14750#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
14752#[doc = "## Safety"]
14753#[doc = "  * Neon instrinsic unsafe"]
14754#[inline]
14755#[target_feature(enable = "neon")]
14756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14758#[cfg_attr(
14759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14760    assert_instr(ld1r)
14761)]
14762#[cfg_attr(
14763    not(target_arch = "arm"),
14764    stable(feature = "neon_intrinsics", since = "1.59.0")
14765)]
14766#[cfg_attr(
14767    target_arch = "arm",
14768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14769)]
14770pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
14771    let x = vld1q_lane_s8::<0>(ptr, transmute(i8x16::splat(0)));
14772    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14773}
14774#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
14776#[doc = "## Safety"]
14777#[doc = "  * Neon instrinsic unsafe"]
14778#[inline]
14779#[target_feature(enable = "neon")]
14780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14781#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14782#[cfg_attr(
14783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14784    assert_instr(ld1r)
14785)]
14786#[cfg_attr(
14787    not(target_arch = "arm"),
14788    stable(feature = "neon_intrinsics", since = "1.59.0")
14789)]
14790#[cfg_attr(
14791    target_arch = "arm",
14792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14793)]
14794pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
14795    let x = vld1q_lane_u16::<0>(ptr, transmute(u16x8::splat(0)));
14796    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14797}
14798#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
14800#[doc = "## Safety"]
14801#[doc = "  * Neon instrinsic unsafe"]
14802#[inline]
14803#[target_feature(enable = "neon")]
14804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14805#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14806#[cfg_attr(
14807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14808    assert_instr(ld1r)
14809)]
14810#[cfg_attr(
14811    not(target_arch = "arm"),
14812    stable(feature = "neon_intrinsics", since = "1.59.0")
14813)]
14814#[cfg_attr(
14815    target_arch = "arm",
14816    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14817)]
14818pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
14819    let x = vld1q_lane_u32::<0>(ptr, transmute(u32x4::splat(0)));
14820    simd_shuffle!(x, x, [0, 0, 0, 0])
14821}
14822#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
14824#[doc = "## Safety"]
14825#[doc = "  * Neon instrinsic unsafe"]
14826#[inline]
14827#[target_feature(enable = "neon")]
14828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14830#[cfg_attr(
14831    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14832    assert_instr(ld1)
14833)]
14834#[cfg_attr(
14835    not(target_arch = "arm"),
14836    stable(feature = "neon_intrinsics", since = "1.59.0")
14837)]
14838#[cfg_attr(
14839    target_arch = "arm",
14840    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14841)]
14842pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
14843    let x = vld1q_lane_u64::<0>(ptr, transmute(u64x2::splat(0)));
14844    simd_shuffle!(x, x, [0, 0])
14845}
14846#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
14848#[doc = "## Safety"]
14849#[doc = "  * Neon instrinsic unsafe"]
14850#[inline]
14851#[target_feature(enable = "neon")]
14852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14853#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14854#[cfg_attr(
14855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14856    assert_instr(ld1r)
14857)]
14858#[cfg_attr(
14859    not(target_arch = "arm"),
14860    stable(feature = "neon_intrinsics", since = "1.59.0")
14861)]
14862#[cfg_attr(
14863    target_arch = "arm",
14864    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14865)]
14866pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
14867    let x = vld1q_lane_u8::<0>(ptr, transmute(u8x16::splat(0)));
14868    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14869}
14870#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
14872#[doc = "## Safety"]
14873#[doc = "  * Neon instrinsic unsafe"]
14874#[inline]
14875#[target_feature(enable = "neon,aes")]
14876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14878#[cfg_attr(
14879    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14880    assert_instr(ldr)
14881)]
14882#[cfg_attr(
14883    not(target_arch = "arm"),
14884    stable(feature = "neon_intrinsics", since = "1.59.0")
14885)]
14886#[cfg_attr(
14887    target_arch = "arm",
14888    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14889)]
14890pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
14891    let x: poly64x1_t;
14892    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14893    {
14894        x = crate::core_arch::aarch64::vld1_p64(ptr);
14895    }
14896    #[cfg(target_arch = "arm")]
14897    {
14898        x = crate::core_arch::arm::vld1_p64(ptr);
14899    };
14900    x
14901}
14902#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
14904#[doc = "## Safety"]
14905#[doc = "  * Neon instrinsic unsafe"]
14906#[inline]
14907#[target_feature(enable = "neon")]
14908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14910#[cfg_attr(
14911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14912    assert_instr(ldr)
14913)]
14914#[cfg_attr(
14915    not(target_arch = "arm"),
14916    stable(feature = "neon_intrinsics", since = "1.59.0")
14917)]
14918#[cfg_attr(
14919    target_arch = "arm",
14920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14921)]
14922pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
14923    let x: int64x1_t;
14924    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14925    {
14926        x = crate::core_arch::aarch64::vld1_s64(ptr);
14927    }
14928    #[cfg(target_arch = "arm")]
14929    {
14930        x = crate::core_arch::arm::vld1_s64(ptr);
14931    };
14932    x
14933}
14934#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
14936#[doc = "## Safety"]
14937#[doc = "  * Neon instrinsic unsafe"]
14938#[inline]
14939#[target_feature(enable = "neon")]
14940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14942#[cfg_attr(
14943    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14944    assert_instr(ldr)
14945)]
14946#[cfg_attr(
14947    not(target_arch = "arm"),
14948    stable(feature = "neon_intrinsics", since = "1.59.0")
14949)]
14950#[cfg_attr(
14951    target_arch = "arm",
14952    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14953)]
14954pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
14955    let x: uint64x1_t;
14956    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14957    {
14958        x = crate::core_arch::aarch64::vld1_u64(ptr);
14959    }
14960    #[cfg(target_arch = "arm")]
14961    {
14962        x = crate::core_arch::arm::vld1_u64(ptr);
14963    };
14964    x
14965}
14966#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14968#[doc = "## Safety"]
14969#[doc = "  * Neon instrinsic unsafe"]
14970#[inline]
14971#[cfg(target_endian = "little")]
14972#[cfg(target_arch = "arm")]
14973#[target_feature(enable = "neon,v7")]
14974#[target_feature(enable = "neon,fp16")]
14975#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14977pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14978    transmute(vld1_v4f16(
14979        ptr as *const i8,
14980        crate::mem::align_of::<f16>() as i32,
14981    ))
14982}
14983#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14985#[doc = "## Safety"]
14986#[doc = "  * Neon instrinsic unsafe"]
14987#[inline]
14988#[cfg(target_endian = "big")]
14989#[cfg(target_arch = "arm")]
14990#[target_feature(enable = "neon,v7")]
14991#[target_feature(enable = "neon,fp16")]
14992#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14994pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14995    let ret_val: float16x4_t = transmute(vld1_v4f16(
14996        ptr as *const i8,
14997        crate::mem::align_of::<f16>() as i32,
14998    ));
14999    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15000}
15001#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
15003#[doc = "## Safety"]
15004#[doc = "  * Neon instrinsic unsafe"]
15005#[inline]
15006#[cfg(target_endian = "little")]
15007#[cfg(target_arch = "arm")]
15008#[target_feature(enable = "neon,v7")]
15009#[target_feature(enable = "neon,fp16")]
15010#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15011#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15012pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
15013    transmute(vld1q_v8f16(
15014        ptr as *const i8,
15015        crate::mem::align_of::<f16>() as i32,
15016    ))
15017}
15018#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
15020#[doc = "## Safety"]
15021#[doc = "  * Neon instrinsic unsafe"]
15022#[inline]
15023#[cfg(target_endian = "big")]
15024#[cfg(target_arch = "arm")]
15025#[target_feature(enable = "neon,v7")]
15026#[target_feature(enable = "neon,fp16")]
15027#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15028#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15029pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
15030    let ret_val: float16x8_t = transmute(vld1q_v8f16(
15031        ptr as *const i8,
15032        crate::mem::align_of::<f16>() as i32,
15033    ));
15034    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15035}
15036#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
15038#[doc = "## Safety"]
15039#[doc = "  * Neon instrinsic unsafe"]
15040#[inline]
15041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15043#[cfg_attr(
15044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15045    assert_instr(ld1)
15046)]
15047#[target_feature(enable = "neon,fp16")]
15048#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15049pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
15050    unsafe extern "unadjusted" {
15051        #[cfg_attr(
15052            any(target_arch = "aarch64", target_arch = "arm64ec"),
15053            link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0f16"
15054        )]
15055        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0f16")]
15056        fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
15057    }
15058    _vld1_f16_x2(a)
15059}
15060#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
15062#[doc = "## Safety"]
15063#[doc = "  * Neon instrinsic unsafe"]
15064#[inline]
15065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15067#[cfg_attr(
15068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15069    assert_instr(ld1)
15070)]
15071#[target_feature(enable = "neon,fp16")]
15072#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15073pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
15074    unsafe extern "unadjusted" {
15075        #[cfg_attr(
15076            any(target_arch = "aarch64", target_arch = "arm64ec"),
15077            link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0f16"
15078        )]
15079        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0f16")]
15080        fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
15081    }
15082    _vld1_f16_x3(a)
15083}
15084#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
15086#[doc = "## Safety"]
15087#[doc = "  * Neon instrinsic unsafe"]
15088#[inline]
15089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15091#[cfg_attr(
15092    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15093    assert_instr(ld1)
15094)]
15095#[target_feature(enable = "neon,fp16")]
15096#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15097pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
15098    unsafe extern "unadjusted" {
15099        #[cfg_attr(
15100            any(target_arch = "aarch64", target_arch = "arm64ec"),
15101            link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0f16"
15102        )]
15103        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0f16")]
15104        fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
15105    }
15106    _vld1_f16_x4(a)
15107}
15108#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
15110#[doc = "## Safety"]
15111#[doc = "  * Neon instrinsic unsafe"]
15112#[inline]
15113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15115#[cfg_attr(
15116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15117    assert_instr(ld1)
15118)]
15119#[target_feature(enable = "neon,fp16")]
15120#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15121pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
15122    unsafe extern "unadjusted" {
15123        #[cfg_attr(
15124            any(target_arch = "aarch64", target_arch = "arm64ec"),
15125            link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0f16"
15126        )]
15127        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0f16")]
15128        fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
15129    }
15130    _vld1q_f16_x2(a)
15131}
15132#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
15134#[doc = "## Safety"]
15135#[doc = "  * Neon instrinsic unsafe"]
15136#[inline]
15137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15139#[cfg_attr(
15140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15141    assert_instr(ld1)
15142)]
15143#[target_feature(enable = "neon,fp16")]
15144#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15145pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
15146    unsafe extern "unadjusted" {
15147        #[cfg_attr(
15148            any(target_arch = "aarch64", target_arch = "arm64ec"),
15149            link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0f16"
15150        )]
15151        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0f16")]
15152        fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
15153    }
15154    _vld1q_f16_x3(a)
15155}
15156#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
15158#[doc = "## Safety"]
15159#[doc = "  * Neon instrinsic unsafe"]
15160#[inline]
15161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15163#[cfg_attr(
15164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15165    assert_instr(ld1)
15166)]
15167#[target_feature(enable = "neon,fp16")]
15168#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15169pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
15170    unsafe extern "unadjusted" {
15171        #[cfg_attr(
15172            any(target_arch = "aarch64", target_arch = "arm64ec"),
15173            link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0f16"
15174        )]
15175        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0f16")]
15176        fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
15177    }
15178    _vld1q_f16_x4(a)
15179}
15180#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15182#[doc = "## Safety"]
15183#[doc = "  * Neon instrinsic unsafe"]
15184#[inline]
15185#[cfg(target_endian = "little")]
15186#[cfg(target_arch = "arm")]
15187#[target_feature(enable = "neon,v7")]
15188#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15190pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15191    transmute(vld1_v2f32(
15192        ptr as *const i8,
15193        crate::mem::align_of::<f32>() as i32,
15194    ))
15195}
15196#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15198#[doc = "## Safety"]
15199#[doc = "  * Neon instrinsic unsafe"]
15200#[inline]
15201#[cfg(target_endian = "big")]
15202#[cfg(target_arch = "arm")]
15203#[target_feature(enable = "neon,v7")]
15204#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15206pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15207    let ret_val: float32x2_t = transmute(vld1_v2f32(
15208        ptr as *const i8,
15209        crate::mem::align_of::<f32>() as i32,
15210    ));
15211    simd_shuffle!(ret_val, ret_val, [1, 0])
15212}
15213#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15215#[doc = "## Safety"]
15216#[doc = "  * Neon instrinsic unsafe"]
15217#[inline]
15218#[cfg(target_endian = "little")]
15219#[cfg(target_arch = "arm")]
15220#[target_feature(enable = "neon,v7")]
15221#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15222#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15223pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15224    transmute(vld1q_v4f32(
15225        ptr as *const i8,
15226        crate::mem::align_of::<f32>() as i32,
15227    ))
15228}
15229#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15231#[doc = "## Safety"]
15232#[doc = "  * Neon instrinsic unsafe"]
15233#[inline]
15234#[cfg(target_endian = "big")]
15235#[cfg(target_arch = "arm")]
15236#[target_feature(enable = "neon,v7")]
15237#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15239pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15240    let ret_val: float32x4_t = transmute(vld1q_v4f32(
15241        ptr as *const i8,
15242        crate::mem::align_of::<f32>() as i32,
15243    ));
15244    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15245}
15246#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15248#[doc = "## Safety"]
15249#[doc = "  * Neon instrinsic unsafe"]
15250#[inline]
15251#[cfg(target_endian = "little")]
15252#[cfg(target_arch = "arm")]
15253#[target_feature(enable = "neon,v7")]
15254#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15256pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15257    transmute(vld1_v8i8(
15258        ptr as *const i8,
15259        crate::mem::align_of::<u8>() as i32,
15260    ))
15261}
15262#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15264#[doc = "## Safety"]
15265#[doc = "  * Neon instrinsic unsafe"]
15266#[inline]
15267#[cfg(target_endian = "big")]
15268#[cfg(target_arch = "arm")]
15269#[target_feature(enable = "neon,v7")]
15270#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15271#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15272pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15273    let ret_val: uint8x8_t = transmute(vld1_v8i8(
15274        ptr as *const i8,
15275        crate::mem::align_of::<u8>() as i32,
15276    ));
15277    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15278}
15279#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15281#[doc = "## Safety"]
15282#[doc = "  * Neon instrinsic unsafe"]
15283#[inline]
15284#[cfg(target_endian = "little")]
15285#[cfg(target_arch = "arm")]
15286#[target_feature(enable = "neon,v7")]
15287#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15288#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15289pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15290    transmute(vld1q_v16i8(
15291        ptr as *const i8,
15292        crate::mem::align_of::<u8>() as i32,
15293    ))
15294}
15295#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15297#[doc = "## Safety"]
15298#[doc = "  * Neon instrinsic unsafe"]
15299#[inline]
15300#[cfg(target_endian = "big")]
15301#[cfg(target_arch = "arm")]
15302#[target_feature(enable = "neon,v7")]
15303#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15304#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15305pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15306    let ret_val: uint8x16_t = transmute(vld1q_v16i8(
15307        ptr as *const i8,
15308        crate::mem::align_of::<u8>() as i32,
15309    ));
15310    simd_shuffle!(
15311        ret_val,
15312        ret_val,
15313        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15314    )
15315}
15316#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15318#[doc = "## Safety"]
15319#[doc = "  * Neon instrinsic unsafe"]
15320#[inline]
15321#[cfg(target_endian = "little")]
15322#[cfg(target_arch = "arm")]
15323#[target_feature(enable = "neon,v7")]
15324#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15325#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15326pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15327    transmute(vld1_v4i16(
15328        ptr as *const i8,
15329        crate::mem::align_of::<u16>() as i32,
15330    ))
15331}
15332#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15334#[doc = "## Safety"]
15335#[doc = "  * Neon instrinsic unsafe"]
15336#[inline]
15337#[cfg(target_endian = "big")]
15338#[cfg(target_arch = "arm")]
15339#[target_feature(enable = "neon,v7")]
15340#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15341#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15342pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15343    let ret_val: uint16x4_t = transmute(vld1_v4i16(
15344        ptr as *const i8,
15345        crate::mem::align_of::<u16>() as i32,
15346    ));
15347    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15348}
15349#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15351#[doc = "## Safety"]
15352#[doc = "  * Neon instrinsic unsafe"]
15353#[inline]
15354#[cfg(target_endian = "little")]
15355#[cfg(target_arch = "arm")]
15356#[target_feature(enable = "neon,v7")]
15357#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15358#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15359pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15360    transmute(vld1q_v8i16(
15361        ptr as *const i8,
15362        crate::mem::align_of::<u16>() as i32,
15363    ))
15364}
15365#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15367#[doc = "## Safety"]
15368#[doc = "  * Neon instrinsic unsafe"]
15369#[inline]
15370#[cfg(target_endian = "big")]
15371#[cfg(target_arch = "arm")]
15372#[target_feature(enable = "neon,v7")]
15373#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15374#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15375pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15376    let ret_val: uint16x8_t = transmute(vld1q_v8i16(
15377        ptr as *const i8,
15378        crate::mem::align_of::<u16>() as i32,
15379    ));
15380    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15381}
15382#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15384#[doc = "## Safety"]
15385#[doc = "  * Neon instrinsic unsafe"]
15386#[inline]
15387#[cfg(target_endian = "little")]
15388#[cfg(target_arch = "arm")]
15389#[target_feature(enable = "neon,v7")]
15390#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15392pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15393    transmute(vld1_v2i32(
15394        ptr as *const i8,
15395        crate::mem::align_of::<u32>() as i32,
15396    ))
15397}
15398#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15400#[doc = "## Safety"]
15401#[doc = "  * Neon instrinsic unsafe"]
15402#[inline]
15403#[cfg(target_endian = "big")]
15404#[cfg(target_arch = "arm")]
15405#[target_feature(enable = "neon,v7")]
15406#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15408pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15409    let ret_val: uint32x2_t = transmute(vld1_v2i32(
15410        ptr as *const i8,
15411        crate::mem::align_of::<u32>() as i32,
15412    ));
15413    simd_shuffle!(ret_val, ret_val, [1, 0])
15414}
15415#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15417#[doc = "## Safety"]
15418#[doc = "  * Neon instrinsic unsafe"]
15419#[inline]
15420#[cfg(target_endian = "little")]
15421#[cfg(target_arch = "arm")]
15422#[target_feature(enable = "neon,v7")]
15423#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15424#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15425pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15426    transmute(vld1q_v4i32(
15427        ptr as *const i8,
15428        crate::mem::align_of::<u32>() as i32,
15429    ))
15430}
15431#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15433#[doc = "## Safety"]
15434#[doc = "  * Neon instrinsic unsafe"]
15435#[inline]
15436#[cfg(target_endian = "big")]
15437#[cfg(target_arch = "arm")]
15438#[target_feature(enable = "neon,v7")]
15439#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15440#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15441pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15442    let ret_val: uint32x4_t = transmute(vld1q_v4i32(
15443        ptr as *const i8,
15444        crate::mem::align_of::<u32>() as i32,
15445    ));
15446    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15447}
15448#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
15450#[doc = "## Safety"]
15451#[doc = "  * Neon instrinsic unsafe"]
15452#[inline]
15453#[cfg(target_arch = "arm")]
15454#[target_feature(enable = "neon,v7")]
15455#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15457pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
15458    transmute(vld1_v1i64(
15459        ptr as *const i8,
15460        crate::mem::align_of::<u64>() as i32,
15461    ))
15462}
15463#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15465#[doc = "## Safety"]
15466#[doc = "  * Neon instrinsic unsafe"]
15467#[inline]
15468#[cfg(target_endian = "little")]
15469#[cfg(target_arch = "arm")]
15470#[target_feature(enable = "neon,v7")]
15471#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15472#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15473pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15474    transmute(vld1q_v2i64(
15475        ptr as *const i8,
15476        crate::mem::align_of::<u64>() as i32,
15477    ))
15478}
15479#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15481#[doc = "## Safety"]
15482#[doc = "  * Neon instrinsic unsafe"]
15483#[inline]
15484#[cfg(target_endian = "big")]
15485#[cfg(target_arch = "arm")]
15486#[target_feature(enable = "neon,v7")]
15487#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15489pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15490    let ret_val: uint64x2_t = transmute(vld1q_v2i64(
15491        ptr as *const i8,
15492        crate::mem::align_of::<u64>() as i32,
15493    ));
15494    simd_shuffle!(ret_val, ret_val, [1, 0])
15495}
15496#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15498#[doc = "## Safety"]
15499#[doc = "  * Neon instrinsic unsafe"]
15500#[inline]
15501#[cfg(target_endian = "little")]
15502#[cfg(target_arch = "arm")]
15503#[target_feature(enable = "neon,v7")]
15504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15505#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15506pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15507    transmute(vld1_v8i8(
15508        ptr as *const i8,
15509        crate::mem::align_of::<p8>() as i32,
15510    ))
15511}
15512#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15514#[doc = "## Safety"]
15515#[doc = "  * Neon instrinsic unsafe"]
15516#[inline]
15517#[cfg(target_endian = "big")]
15518#[cfg(target_arch = "arm")]
15519#[target_feature(enable = "neon,v7")]
15520#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15521#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15522pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15523    let ret_val: poly8x8_t = transmute(vld1_v8i8(
15524        ptr as *const i8,
15525        crate::mem::align_of::<p8>() as i32,
15526    ));
15527    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15528}
15529#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15531#[doc = "## Safety"]
15532#[doc = "  * Neon instrinsic unsafe"]
15533#[inline]
15534#[cfg(target_endian = "little")]
15535#[cfg(target_arch = "arm")]
15536#[target_feature(enable = "neon,v7")]
15537#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15539pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15540    transmute(vld1q_v16i8(
15541        ptr as *const i8,
15542        crate::mem::align_of::<p8>() as i32,
15543    ))
15544}
15545#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15547#[doc = "## Safety"]
15548#[doc = "  * Neon instrinsic unsafe"]
15549#[inline]
15550#[cfg(target_endian = "big")]
15551#[cfg(target_arch = "arm")]
15552#[target_feature(enable = "neon,v7")]
15553#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15554#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15555pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15556    let ret_val: poly8x16_t = transmute(vld1q_v16i8(
15557        ptr as *const i8,
15558        crate::mem::align_of::<p8>() as i32,
15559    ));
15560    simd_shuffle!(
15561        ret_val,
15562        ret_val,
15563        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15564    )
15565}
15566#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15568#[doc = "## Safety"]
15569#[doc = "  * Neon instrinsic unsafe"]
15570#[inline]
15571#[cfg(target_endian = "little")]
15572#[cfg(target_arch = "arm")]
15573#[target_feature(enable = "neon,v7")]
15574#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15576pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15577    transmute(vld1_v4i16(
15578        ptr as *const i8,
15579        crate::mem::align_of::<p16>() as i32,
15580    ))
15581}
15582#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15584#[doc = "## Safety"]
15585#[doc = "  * Neon instrinsic unsafe"]
15586#[inline]
15587#[cfg(target_endian = "big")]
15588#[cfg(target_arch = "arm")]
15589#[target_feature(enable = "neon,v7")]
15590#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15592pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15593    let ret_val: poly16x4_t = transmute(vld1_v4i16(
15594        ptr as *const i8,
15595        crate::mem::align_of::<p16>() as i32,
15596    ));
15597    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15598}
15599#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15601#[doc = "## Safety"]
15602#[doc = "  * Neon instrinsic unsafe"]
15603#[inline]
15604#[cfg(target_endian = "little")]
15605#[cfg(target_arch = "arm")]
15606#[target_feature(enable = "neon,v7")]
15607#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15609pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15610    transmute(vld1q_v8i16(
15611        ptr as *const i8,
15612        crate::mem::align_of::<p16>() as i32,
15613    ))
15614}
15615#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15617#[doc = "## Safety"]
15618#[doc = "  * Neon instrinsic unsafe"]
15619#[inline]
15620#[cfg(target_endian = "big")]
15621#[cfg(target_arch = "arm")]
15622#[target_feature(enable = "neon,v7")]
15623#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15624#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15625pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15626    let ret_val: poly16x8_t = transmute(vld1q_v8i16(
15627        ptr as *const i8,
15628        crate::mem::align_of::<p16>() as i32,
15629    ));
15630    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15631}
15632#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15634#[doc = "## Safety"]
15635#[doc = "  * Neon instrinsic unsafe"]
15636#[inline]
15637#[cfg(target_endian = "little")]
15638#[cfg(target_arch = "arm")]
15639#[target_feature(enable = "neon,aes")]
15640#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15641#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15642pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15643    transmute(vld1q_v2i64(
15644        ptr as *const i8,
15645        crate::mem::align_of::<p64>() as i32,
15646    ))
15647}
15648#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15650#[doc = "## Safety"]
15651#[doc = "  * Neon instrinsic unsafe"]
15652#[inline]
15653#[cfg(target_endian = "big")]
15654#[cfg(target_arch = "arm")]
15655#[target_feature(enable = "neon,aes")]
15656#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15658pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15659    let ret_val: poly64x2_t = transmute(vld1q_v2i64(
15660        ptr as *const i8,
15661        crate::mem::align_of::<p64>() as i32,
15662    ));
15663    simd_shuffle!(ret_val, ret_val, [1, 0])
15664}
15665#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
15667#[doc = "## Safety"]
15668#[doc = "  * Neon instrinsic unsafe"]
15669#[inline]
15670#[target_feature(enable = "neon")]
15671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15673#[cfg_attr(
15674    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15675    assert_instr(ld1)
15676)]
15677#[cfg_attr(
15678    not(target_arch = "arm"),
15679    stable(feature = "neon_intrinsics", since = "1.59.0")
15680)]
15681#[cfg_attr(
15682    target_arch = "arm",
15683    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15684)]
15685pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
15686    unsafe extern "unadjusted" {
15687        #[cfg_attr(
15688            any(target_arch = "aarch64", target_arch = "arm64ec"),
15689            link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
15690        )]
15691        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
15692        fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
15693    }
15694    _vld1_f32_x2(a)
15695}
15696#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
15698#[doc = "## Safety"]
15699#[doc = "  * Neon instrinsic unsafe"]
15700#[inline]
15701#[target_feature(enable = "neon")]
15702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15704#[cfg_attr(
15705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15706    assert_instr(ld1)
15707)]
15708#[cfg_attr(
15709    not(target_arch = "arm"),
15710    stable(feature = "neon_intrinsics", since = "1.59.0")
15711)]
15712#[cfg_attr(
15713    target_arch = "arm",
15714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15715)]
15716pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
15717    unsafe extern "unadjusted" {
15718        #[cfg_attr(
15719            any(target_arch = "aarch64", target_arch = "arm64ec"),
15720            link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
15721        )]
15722        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
15723        fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
15724    }
15725    _vld1_f32_x3(a)
15726}
15727#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
15729#[doc = "## Safety"]
15730#[doc = "  * Neon instrinsic unsafe"]
15731#[inline]
15732#[target_feature(enable = "neon")]
15733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15735#[cfg_attr(
15736    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15737    assert_instr(ld1)
15738)]
15739#[cfg_attr(
15740    not(target_arch = "arm"),
15741    stable(feature = "neon_intrinsics", since = "1.59.0")
15742)]
15743#[cfg_attr(
15744    target_arch = "arm",
15745    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15746)]
15747pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
15748    unsafe extern "unadjusted" {
15749        #[cfg_attr(
15750            any(target_arch = "aarch64", target_arch = "arm64ec"),
15751            link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
15752        )]
15753        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
15754        fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
15755    }
15756    _vld1_f32_x4(a)
15757}
15758#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
15760#[doc = "## Safety"]
15761#[doc = "  * Neon instrinsic unsafe"]
15762#[inline]
15763#[target_feature(enable = "neon")]
15764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15766#[cfg_attr(
15767    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15768    assert_instr(ld1)
15769)]
15770#[cfg_attr(
15771    not(target_arch = "arm"),
15772    stable(feature = "neon_intrinsics", since = "1.59.0")
15773)]
15774#[cfg_attr(
15775    target_arch = "arm",
15776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15777)]
15778pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
15779    unsafe extern "unadjusted" {
15780        #[cfg_attr(
15781            any(target_arch = "aarch64", target_arch = "arm64ec"),
15782            link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
15783        )]
15784        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
15785        fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
15786    }
15787    _vld1q_f32_x2(a)
15788}
15789#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
15791#[doc = "## Safety"]
15792#[doc = "  * Neon instrinsic unsafe"]
15793#[inline]
15794#[target_feature(enable = "neon")]
15795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15797#[cfg_attr(
15798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15799    assert_instr(ld1)
15800)]
15801#[cfg_attr(
15802    not(target_arch = "arm"),
15803    stable(feature = "neon_intrinsics", since = "1.59.0")
15804)]
15805#[cfg_attr(
15806    target_arch = "arm",
15807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15808)]
15809pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
15810    unsafe extern "unadjusted" {
15811        #[cfg_attr(
15812            any(target_arch = "aarch64", target_arch = "arm64ec"),
15813            link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
15814        )]
15815        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
15816        fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
15817    }
15818    _vld1q_f32_x3(a)
15819}
15820#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
15822#[doc = "## Safety"]
15823#[doc = "  * Neon instrinsic unsafe"]
15824#[inline]
15825#[target_feature(enable = "neon")]
15826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15828#[cfg_attr(
15829    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15830    assert_instr(ld1)
15831)]
15832#[cfg_attr(
15833    not(target_arch = "arm"),
15834    stable(feature = "neon_intrinsics", since = "1.59.0")
15835)]
15836#[cfg_attr(
15837    target_arch = "arm",
15838    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15839)]
15840pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
15841    unsafe extern "unadjusted" {
15842        #[cfg_attr(
15843            any(target_arch = "aarch64", target_arch = "arm64ec"),
15844            link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
15845        )]
15846        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
15847        fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
15848    }
15849    _vld1q_f32_x4(a)
15850}
15851#[doc = "Load one single-element structure to one lane of one register"]
15852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
15853#[doc = "## Safety"]
15854#[doc = "  * Neon instrinsic unsafe"]
15855#[inline]
15856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15858#[cfg_attr(
15859    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15860    assert_instr(ld1, LANE = 0)
15861)]
15862#[rustc_legacy_const_generics(2)]
15863#[target_feature(enable = "neon,fp16")]
15864#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15865pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
15866    static_assert_uimm_bits!(LANE, 2);
15867    simd_insert!(src, LANE as u32, *ptr)
15868}
15869#[doc = "Load one single-element structure to one lane of one register"]
15870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
15871#[doc = "## Safety"]
15872#[doc = "  * Neon instrinsic unsafe"]
15873#[inline]
15874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15875#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15876#[cfg_attr(
15877    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15878    assert_instr(ld1, LANE = 0)
15879)]
15880#[rustc_legacy_const_generics(2)]
15881#[target_feature(enable = "neon,fp16")]
15882#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15883pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
15884    static_assert_uimm_bits!(LANE, 3);
15885    simd_insert!(src, LANE as u32, *ptr)
15886}
15887#[doc = "Load one single-element structure to one lane of one register."]
15888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
15889#[doc = "## Safety"]
15890#[doc = "  * Neon instrinsic unsafe"]
15891#[inline]
15892#[target_feature(enable = "neon")]
15893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15894#[rustc_legacy_const_generics(2)]
15895#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15896#[cfg_attr(
15897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15898    assert_instr(ld1, LANE = 1)
15899)]
15900#[cfg_attr(
15901    not(target_arch = "arm"),
15902    stable(feature = "neon_intrinsics", since = "1.59.0")
15903)]
15904#[cfg_attr(
15905    target_arch = "arm",
15906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15907)]
15908pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t) -> float32x2_t {
15909    static_assert_uimm_bits!(LANE, 1);
15910    simd_insert!(src, LANE as u32, *ptr)
15911}
15912#[doc = "Load one single-element structure to one lane of one register."]
15913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
15914#[doc = "## Safety"]
15915#[doc = "  * Neon instrinsic unsafe"]
15916#[inline]
15917#[target_feature(enable = "neon")]
15918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15919#[rustc_legacy_const_generics(2)]
15920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15921#[cfg_attr(
15922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15923    assert_instr(ld1, LANE = 3)
15924)]
15925#[cfg_attr(
15926    not(target_arch = "arm"),
15927    stable(feature = "neon_intrinsics", since = "1.59.0")
15928)]
15929#[cfg_attr(
15930    target_arch = "arm",
15931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15932)]
15933pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -> poly16x4_t {
15934    static_assert_uimm_bits!(LANE, 2);
15935    simd_insert!(src, LANE as u32, *ptr)
15936}
15937#[doc = "Load one single-element structure to one lane of one register."]
15938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
15939#[doc = "## Safety"]
15940#[doc = "  * Neon instrinsic unsafe"]
15941#[inline]
15942#[target_feature(enable = "neon")]
15943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15944#[rustc_legacy_const_generics(2)]
15945#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15946#[cfg_attr(
15947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15948    assert_instr(ld1, LANE = 7)
15949)]
15950#[cfg_attr(
15951    not(target_arch = "arm"),
15952    stable(feature = "neon_intrinsics", since = "1.59.0")
15953)]
15954#[cfg_attr(
15955    target_arch = "arm",
15956    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15957)]
15958pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> poly8x8_t {
15959    static_assert_uimm_bits!(LANE, 3);
15960    simd_insert!(src, LANE as u32, *ptr)
15961}
15962#[doc = "Load one single-element structure to one lane of one register."]
15963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
15964#[doc = "## Safety"]
15965#[doc = "  * Neon instrinsic unsafe"]
15966#[inline]
15967#[target_feature(enable = "neon")]
15968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15969#[rustc_legacy_const_generics(2)]
15970#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15971#[cfg_attr(
15972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15973    assert_instr(ld1, LANE = 3)
15974)]
15975#[cfg_attr(
15976    not(target_arch = "arm"),
15977    stable(feature = "neon_intrinsics", since = "1.59.0")
15978)]
15979#[cfg_attr(
15980    target_arch = "arm",
15981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15982)]
15983pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) -> int16x4_t {
15984    static_assert_uimm_bits!(LANE, 2);
15985    simd_insert!(src, LANE as u32, *ptr)
15986}
15987#[doc = "Load one single-element structure to one lane of one register."]
15988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
15989#[doc = "## Safety"]
15990#[doc = "  * Neon instrinsic unsafe"]
15991#[inline]
15992#[target_feature(enable = "neon")]
15993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15994#[rustc_legacy_const_generics(2)]
15995#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15996#[cfg_attr(
15997    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15998    assert_instr(ld1, LANE = 1)
15999)]
16000#[cfg_attr(
16001    not(target_arch = "arm"),
16002    stable(feature = "neon_intrinsics", since = "1.59.0")
16003)]
16004#[cfg_attr(
16005    target_arch = "arm",
16006    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16007)]
16008pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) -> int32x2_t {
16009    static_assert_uimm_bits!(LANE, 1);
16010    simd_insert!(src, LANE as u32, *ptr)
16011}
16012#[doc = "Load one single-element structure to one lane of one register."]
16013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
16014#[doc = "## Safety"]
16015#[doc = "  * Neon instrinsic unsafe"]
16016#[inline]
16017#[target_feature(enable = "neon")]
16018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16019#[rustc_legacy_const_generics(2)]
16020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16021#[cfg_attr(
16022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16023    assert_instr(ldr, LANE = 0)
16024)]
16025#[cfg_attr(
16026    not(target_arch = "arm"),
16027    stable(feature = "neon_intrinsics", since = "1.59.0")
16028)]
16029#[cfg_attr(
16030    target_arch = "arm",
16031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16032)]
16033pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
16034    static_assert!(LANE == 0);
16035    simd_insert!(src, LANE as u32, *ptr)
16036}
16037#[doc = "Load one single-element structure to one lane of one register."]
16038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
16039#[doc = "## Safety"]
16040#[doc = "  * Neon instrinsic unsafe"]
16041#[inline]
16042#[target_feature(enable = "neon")]
16043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16044#[rustc_legacy_const_generics(2)]
16045#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16046#[cfg_attr(
16047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16048    assert_instr(ld1, LANE = 7)
16049)]
16050#[cfg_attr(
16051    not(target_arch = "arm"),
16052    stable(feature = "neon_intrinsics", since = "1.59.0")
16053)]
16054#[cfg_attr(
16055    target_arch = "arm",
16056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16057)]
16058pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> int8x8_t {
16059    static_assert_uimm_bits!(LANE, 3);
16060    simd_insert!(src, LANE as u32, *ptr)
16061}
16062#[doc = "Load one single-element structure to one lane of one register."]
16063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
16064#[doc = "## Safety"]
16065#[doc = "  * Neon instrinsic unsafe"]
16066#[inline]
16067#[target_feature(enable = "neon")]
16068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16069#[rustc_legacy_const_generics(2)]
16070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
16071#[cfg_attr(
16072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16073    assert_instr(ld1, LANE = 3)
16074)]
16075#[cfg_attr(
16076    not(target_arch = "arm"),
16077    stable(feature = "neon_intrinsics", since = "1.59.0")
16078)]
16079#[cfg_attr(
16080    target_arch = "arm",
16081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16082)]
16083pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -> uint16x4_t {
16084    static_assert_uimm_bits!(LANE, 2);
16085    simd_insert!(src, LANE as u32, *ptr)
16086}
16087#[doc = "Load one single-element structure to one lane of one register."]
16088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
16089#[doc = "## Safety"]
16090#[doc = "  * Neon instrinsic unsafe"]
16091#[inline]
16092#[target_feature(enable = "neon")]
16093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16094#[rustc_legacy_const_generics(2)]
16095#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
16096#[cfg_attr(
16097    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16098    assert_instr(ld1, LANE = 1)
16099)]
16100#[cfg_attr(
16101    not(target_arch = "arm"),
16102    stable(feature = "neon_intrinsics", since = "1.59.0")
16103)]
16104#[cfg_attr(
16105    target_arch = "arm",
16106    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16107)]
16108pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -> uint32x2_t {
16109    static_assert_uimm_bits!(LANE, 1);
16110    simd_insert!(src, LANE as u32, *ptr)
16111}
16112#[doc = "Load one single-element structure to one lane of one register."]
16113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
16114#[doc = "## Safety"]
16115#[doc = "  * Neon instrinsic unsafe"]
16116#[inline]
16117#[target_feature(enable = "neon")]
16118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16119#[rustc_legacy_const_generics(2)]
16120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16121#[cfg_attr(
16122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16123    assert_instr(ldr, LANE = 0)
16124)]
16125#[cfg_attr(
16126    not(target_arch = "arm"),
16127    stable(feature = "neon_intrinsics", since = "1.59.0")
16128)]
16129#[cfg_attr(
16130    target_arch = "arm",
16131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16132)]
16133pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
16134    static_assert!(LANE == 0);
16135    simd_insert!(src, LANE as u32, *ptr)
16136}
16137#[doc = "Load one single-element structure to one lane of one register."]
16138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
16139#[doc = "## Safety"]
16140#[doc = "  * Neon instrinsic unsafe"]
16141#[inline]
16142#[target_feature(enable = "neon")]
16143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16144#[rustc_legacy_const_generics(2)]
16145#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16146#[cfg_attr(
16147    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16148    assert_instr(ld1, LANE = 7)
16149)]
16150#[cfg_attr(
16151    not(target_arch = "arm"),
16152    stable(feature = "neon_intrinsics", since = "1.59.0")
16153)]
16154#[cfg_attr(
16155    target_arch = "arm",
16156    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16157)]
16158pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> uint8x8_t {
16159    static_assert_uimm_bits!(LANE, 3);
16160    simd_insert!(src, LANE as u32, *ptr)
16161}
16162#[doc = "Load one single-element structure to one lane of one register."]
16163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
16164#[doc = "## Safety"]
16165#[doc = "  * Neon instrinsic unsafe"]
16166#[inline]
16167#[target_feature(enable = "neon")]
16168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16169#[rustc_legacy_const_generics(2)]
16170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16171#[cfg_attr(
16172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16173    assert_instr(ld1, LANE = 3)
16174)]
16175#[cfg_attr(
16176    not(target_arch = "arm"),
16177    stable(feature = "neon_intrinsics", since = "1.59.0")
16178)]
16179#[cfg_attr(
16180    target_arch = "arm",
16181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16182)]
16183pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t) -> float32x4_t {
16184    static_assert_uimm_bits!(LANE, 2);
16185    simd_insert!(src, LANE as u32, *ptr)
16186}
16187#[doc = "Load one single-element structure to one lane of one register."]
16188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
16189#[doc = "## Safety"]
16190#[doc = "  * Neon instrinsic unsafe"]
16191#[inline]
16192#[target_feature(enable = "neon")]
16193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16194#[rustc_legacy_const_generics(2)]
16195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16196#[cfg_attr(
16197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16198    assert_instr(ld1, LANE = 7)
16199)]
16200#[cfg_attr(
16201    not(target_arch = "arm"),
16202    stable(feature = "neon_intrinsics", since = "1.59.0")
16203)]
16204#[cfg_attr(
16205    target_arch = "arm",
16206    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16207)]
16208pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t) -> poly16x8_t {
16209    static_assert_uimm_bits!(LANE, 3);
16210    simd_insert!(src, LANE as u32, *ptr)
16211}
16212#[doc = "Load one single-element structure to one lane of one register."]
16213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
16214#[doc = "## Safety"]
16215#[doc = "  * Neon instrinsic unsafe"]
16216#[inline]
16217#[target_feature(enable = "neon")]
16218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16219#[rustc_legacy_const_generics(2)]
16220#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16221#[cfg_attr(
16222    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16223    assert_instr(ld1, LANE = 15)
16224)]
16225#[cfg_attr(
16226    not(target_arch = "arm"),
16227    stable(feature = "neon_intrinsics", since = "1.59.0")
16228)]
16229#[cfg_attr(
16230    target_arch = "arm",
16231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16232)]
16233pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) -> poly8x16_t {
16234    static_assert_uimm_bits!(LANE, 4);
16235    simd_insert!(src, LANE as u32, *ptr)
16236}
16237#[doc = "Load one single-element structure to one lane of one register."]
16238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
16239#[doc = "## Safety"]
16240#[doc = "  * Neon instrinsic unsafe"]
16241#[inline]
16242#[target_feature(enable = "neon")]
16243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16244#[rustc_legacy_const_generics(2)]
16245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16246#[cfg_attr(
16247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16248    assert_instr(ld1, LANE = 7)
16249)]
16250#[cfg_attr(
16251    not(target_arch = "arm"),
16252    stable(feature = "neon_intrinsics", since = "1.59.0")
16253)]
16254#[cfg_attr(
16255    target_arch = "arm",
16256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16257)]
16258pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -> int16x8_t {
16259    static_assert_uimm_bits!(LANE, 3);
16260    simd_insert!(src, LANE as u32, *ptr)
16261}
16262#[doc = "Load one single-element structure to one lane of one register."]
16263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
16264#[doc = "## Safety"]
16265#[doc = "  * Neon instrinsic unsafe"]
16266#[inline]
16267#[target_feature(enable = "neon")]
16268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16269#[rustc_legacy_const_generics(2)]
16270#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16271#[cfg_attr(
16272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16273    assert_instr(ld1, LANE = 3)
16274)]
16275#[cfg_attr(
16276    not(target_arch = "arm"),
16277    stable(feature = "neon_intrinsics", since = "1.59.0")
16278)]
16279#[cfg_attr(
16280    target_arch = "arm",
16281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16282)]
16283pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -> int32x4_t {
16284    static_assert_uimm_bits!(LANE, 2);
16285    simd_insert!(src, LANE as u32, *ptr)
16286}
16287#[doc = "Load one single-element structure to one lane of one register."]
16288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
16289#[doc = "## Safety"]
16290#[doc = "  * Neon instrinsic unsafe"]
16291#[inline]
16292#[target_feature(enable = "neon")]
16293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16294#[rustc_legacy_const_generics(2)]
16295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16296#[cfg_attr(
16297    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16298    assert_instr(ld1, LANE = 1)
16299)]
16300#[cfg_attr(
16301    not(target_arch = "arm"),
16302    stable(feature = "neon_intrinsics", since = "1.59.0")
16303)]
16304#[cfg_attr(
16305    target_arch = "arm",
16306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16307)]
16308pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
16309    static_assert_uimm_bits!(LANE, 1);
16310    simd_insert!(src, LANE as u32, *ptr)
16311}
16312#[doc = "Load one single-element structure to one lane of one register."]
16313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
16314#[doc = "## Safety"]
16315#[doc = "  * Neon instrinsic unsafe"]
16316#[inline]
16317#[target_feature(enable = "neon")]
16318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16319#[rustc_legacy_const_generics(2)]
16320#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16321#[cfg_attr(
16322    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16323    assert_instr(ld1, LANE = 15)
16324)]
16325#[cfg_attr(
16326    not(target_arch = "arm"),
16327    stable(feature = "neon_intrinsics", since = "1.59.0")
16328)]
16329#[cfg_attr(
16330    target_arch = "arm",
16331    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16332)]
16333pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) -> int8x16_t {
16334    static_assert_uimm_bits!(LANE, 4);
16335    simd_insert!(src, LANE as u32, *ptr)
16336}
16337#[doc = "Load one single-element structure to one lane of one register."]
16338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
16339#[doc = "## Safety"]
16340#[doc = "  * Neon instrinsic unsafe"]
16341#[inline]
16342#[target_feature(enable = "neon")]
16343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16344#[rustc_legacy_const_generics(2)]
16345#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16346#[cfg_attr(
16347    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16348    assert_instr(ld1, LANE = 7)
16349)]
16350#[cfg_attr(
16351    not(target_arch = "arm"),
16352    stable(feature = "neon_intrinsics", since = "1.59.0")
16353)]
16354#[cfg_attr(
16355    target_arch = "arm",
16356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16357)]
16358pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t) -> uint16x8_t {
16359    static_assert_uimm_bits!(LANE, 3);
16360    simd_insert!(src, LANE as u32, *ptr)
16361}
16362#[doc = "Load one single-element structure to one lane of one register."]
16363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
16364#[doc = "## Safety"]
16365#[doc = "  * Neon instrinsic unsafe"]
16366#[inline]
16367#[target_feature(enable = "neon")]
16368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16369#[rustc_legacy_const_generics(2)]
16370#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16371#[cfg_attr(
16372    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16373    assert_instr(ld1, LANE = 3)
16374)]
16375#[cfg_attr(
16376    not(target_arch = "arm"),
16377    stable(feature = "neon_intrinsics", since = "1.59.0")
16378)]
16379#[cfg_attr(
16380    target_arch = "arm",
16381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16382)]
16383pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t) -> uint32x4_t {
16384    static_assert_uimm_bits!(LANE, 2);
16385    simd_insert!(src, LANE as u32, *ptr)
16386}
16387#[doc = "Load one single-element structure to one lane of one register."]
16388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
16389#[doc = "## Safety"]
16390#[doc = "  * Neon instrinsic unsafe"]
16391#[inline]
16392#[target_feature(enable = "neon")]
16393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16394#[rustc_legacy_const_generics(2)]
16395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16396#[cfg_attr(
16397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16398    assert_instr(ld1, LANE = 1)
16399)]
16400#[cfg_attr(
16401    not(target_arch = "arm"),
16402    stable(feature = "neon_intrinsics", since = "1.59.0")
16403)]
16404#[cfg_attr(
16405    target_arch = "arm",
16406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16407)]
16408pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
16409    static_assert_uimm_bits!(LANE, 1);
16410    simd_insert!(src, LANE as u32, *ptr)
16411}
16412#[doc = "Load one single-element structure to one lane of one register."]
16413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
16414#[doc = "## Safety"]
16415#[doc = "  * Neon instrinsic unsafe"]
16416#[inline]
16417#[target_feature(enable = "neon")]
16418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16419#[rustc_legacy_const_generics(2)]
16420#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16421#[cfg_attr(
16422    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16423    assert_instr(ld1, LANE = 15)
16424)]
16425#[cfg_attr(
16426    not(target_arch = "arm"),
16427    stable(feature = "neon_intrinsics", since = "1.59.0")
16428)]
16429#[cfg_attr(
16430    target_arch = "arm",
16431    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16432)]
16433pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) -> uint8x16_t {
16434    static_assert_uimm_bits!(LANE, 4);
16435    simd_insert!(src, LANE as u32, *ptr)
16436}
16437#[doc = "Load one single-element structure to one lane of one register."]
16438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
16439#[doc = "## Safety"]
16440#[doc = "  * Neon instrinsic unsafe"]
16441#[inline]
16442#[target_feature(enable = "neon,aes")]
16443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16444#[rustc_legacy_const_generics(2)]
16445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16446#[cfg_attr(
16447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16448    assert_instr(ldr, LANE = 0)
16449)]
16450#[cfg_attr(
16451    not(target_arch = "arm"),
16452    stable(feature = "neon_intrinsics", since = "1.59.0")
16453)]
16454#[cfg_attr(
16455    target_arch = "arm",
16456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16457)]
16458pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
16459    static_assert!(LANE == 0);
16460    simd_insert!(src, LANE as u32, *ptr)
16461}
16462#[doc = "Load one single-element structure to one lane of one register."]
16463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
16464#[doc = "## Safety"]
16465#[doc = "  * Neon instrinsic unsafe"]
16466#[inline]
16467#[target_feature(enable = "neon,aes")]
16468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16469#[rustc_legacy_const_generics(2)]
16470#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16471#[cfg_attr(
16472    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16473    assert_instr(ld1, LANE = 1)
16474)]
16475#[cfg_attr(
16476    not(target_arch = "arm"),
16477    stable(feature = "neon_intrinsics", since = "1.59.0")
16478)]
16479#[cfg_attr(
16480    target_arch = "arm",
16481    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16482)]
16483pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
16484    static_assert_uimm_bits!(LANE, 1);
16485    simd_insert!(src, LANE as u32, *ptr)
16486}
16487#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
16489#[doc = "## Safety"]
16490#[doc = "  * Neon instrinsic unsafe"]
16491#[inline]
16492#[cfg(target_arch = "arm")]
16493#[target_feature(enable = "neon,aes")]
16494#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16496pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
16497    let a: *const i8 = ptr as *const i8;
16498    let b: i32 = crate::mem::align_of::<p64>() as i32;
16499    unsafe extern "unadjusted" {
16500        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
16501        fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
16502    }
16503    transmute(_vld1_v1i64(a, b))
16504}
16505#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
16507#[doc = "## Safety"]
16508#[doc = "  * Neon instrinsic unsafe"]
16509#[inline]
16510#[target_feature(enable = "neon,aes")]
16511#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16513#[cfg_attr(
16514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16515    assert_instr(ld1)
16516)]
16517#[cfg_attr(
16518    not(target_arch = "arm"),
16519    stable(feature = "neon_intrinsics", since = "1.59.0")
16520)]
16521#[cfg_attr(
16522    target_arch = "arm",
16523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16524)]
16525pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
16526    transmute(vld1_s64_x2(transmute(a)))
16527}
16528#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
16530#[doc = "## Safety"]
16531#[doc = "  * Neon instrinsic unsafe"]
16532#[inline]
16533#[target_feature(enable = "neon,aes")]
16534#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16536#[cfg_attr(
16537    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16538    assert_instr(ld1)
16539)]
16540#[cfg_attr(
16541    not(target_arch = "arm"),
16542    stable(feature = "neon_intrinsics", since = "1.59.0")
16543)]
16544#[cfg_attr(
16545    target_arch = "arm",
16546    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16547)]
16548pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
16549    transmute(vld1_s64_x3(transmute(a)))
16550}
16551#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
16553#[doc = "## Safety"]
16554#[doc = "  * Neon instrinsic unsafe"]
16555#[inline]
16556#[target_feature(enable = "neon,aes")]
16557#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16559#[cfg_attr(
16560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16561    assert_instr(ld1)
16562)]
16563#[cfg_attr(
16564    not(target_arch = "arm"),
16565    stable(feature = "neon_intrinsics", since = "1.59.0")
16566)]
16567#[cfg_attr(
16568    target_arch = "arm",
16569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16570)]
16571pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
16572    transmute(vld1_s64_x4(transmute(a)))
16573}
16574#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16576#[doc = "## Safety"]
16577#[doc = "  * Neon instrinsic unsafe"]
16578#[inline]
16579#[cfg(target_endian = "little")]
16580#[target_feature(enable = "neon,aes")]
16581#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16583#[cfg_attr(
16584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16585    assert_instr(ld1)
16586)]
16587#[cfg_attr(
16588    not(target_arch = "arm"),
16589    stable(feature = "neon_intrinsics", since = "1.59.0")
16590)]
16591#[cfg_attr(
16592    target_arch = "arm",
16593    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16594)]
16595pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16596    transmute(vld1q_s64_x2(transmute(a)))
16597}
16598#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16600#[doc = "## Safety"]
16601#[doc = "  * Neon instrinsic unsafe"]
16602#[inline]
16603#[cfg(target_endian = "big")]
16604#[target_feature(enable = "neon,aes")]
16605#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16607#[cfg_attr(
16608    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16609    assert_instr(ld1)
16610)]
16611#[cfg_attr(
16612    not(target_arch = "arm"),
16613    stable(feature = "neon_intrinsics", since = "1.59.0")
16614)]
16615#[cfg_attr(
16616    target_arch = "arm",
16617    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16618)]
16619pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16620    let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
16621    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16622    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16623    ret_val
16624}
16625#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16627#[doc = "## Safety"]
16628#[doc = "  * Neon instrinsic unsafe"]
16629#[inline]
16630#[cfg(target_endian = "little")]
16631#[target_feature(enable = "neon,aes")]
16632#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16634#[cfg_attr(
16635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16636    assert_instr(ld1)
16637)]
16638#[cfg_attr(
16639    not(target_arch = "arm"),
16640    stable(feature = "neon_intrinsics", since = "1.59.0")
16641)]
16642#[cfg_attr(
16643    target_arch = "arm",
16644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16645)]
16646pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16647    transmute(vld1q_s64_x3(transmute(a)))
16648}
16649#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16651#[doc = "## Safety"]
16652#[doc = "  * Neon instrinsic unsafe"]
16653#[inline]
16654#[cfg(target_endian = "big")]
16655#[target_feature(enable = "neon,aes")]
16656#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16658#[cfg_attr(
16659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16660    assert_instr(ld1)
16661)]
16662#[cfg_attr(
16663    not(target_arch = "arm"),
16664    stable(feature = "neon_intrinsics", since = "1.59.0")
16665)]
16666#[cfg_attr(
16667    target_arch = "arm",
16668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16669)]
16670pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16671    let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
16672    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16673    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16674    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16675    ret_val
16676}
16677#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16679#[doc = "## Safety"]
16680#[doc = "  * Neon instrinsic unsafe"]
16681#[inline]
16682#[cfg(target_endian = "little")]
16683#[target_feature(enable = "neon,aes")]
16684#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16686#[cfg_attr(
16687    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16688    assert_instr(ld1)
16689)]
16690#[cfg_attr(
16691    not(target_arch = "arm"),
16692    stable(feature = "neon_intrinsics", since = "1.59.0")
16693)]
16694#[cfg_attr(
16695    target_arch = "arm",
16696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16697)]
16698pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16699    transmute(vld1q_s64_x4(transmute(a)))
16700}
16701#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16703#[doc = "## Safety"]
16704#[doc = "  * Neon instrinsic unsafe"]
16705#[inline]
16706#[cfg(target_endian = "big")]
16707#[target_feature(enable = "neon,aes")]
16708#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16710#[cfg_attr(
16711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16712    assert_instr(ld1)
16713)]
16714#[cfg_attr(
16715    not(target_arch = "arm"),
16716    stable(feature = "neon_intrinsics", since = "1.59.0")
16717)]
16718#[cfg_attr(
16719    target_arch = "arm",
16720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16721)]
16722pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16723    let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
16724    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16725    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16726    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16727    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
16728    ret_val
16729}
16730#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
16732#[doc = "## Safety"]
16733#[doc = "  * Neon instrinsic unsafe"]
16734#[inline]
16735#[cfg(target_arch = "arm")]
16736#[target_feature(enable = "neon,v7")]
16737#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16739pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
16740    vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16741}
16742#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
16744#[doc = "## Safety"]
16745#[doc = "  * Neon instrinsic unsafe"]
16746#[inline]
16747#[cfg(target_arch = "arm")]
16748#[target_feature(enable = "neon,v7")]
16749#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16750#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16751pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
16752    vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16753}
16754#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
16756#[doc = "## Safety"]
16757#[doc = "  * Neon instrinsic unsafe"]
16758#[inline]
16759#[cfg(target_arch = "arm")]
16760#[target_feature(enable = "neon,v7")]
16761#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16762#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16763pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
16764    vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16765}
16766#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
16768#[doc = "## Safety"]
16769#[doc = "  * Neon instrinsic unsafe"]
16770#[inline]
16771#[cfg(target_arch = "arm")]
16772#[target_feature(enable = "neon,v7")]
16773#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16774#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16775pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
16776    vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16777}
16778#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
16780#[doc = "## Safety"]
16781#[doc = "  * Neon instrinsic unsafe"]
16782#[inline]
16783#[cfg(target_arch = "arm")]
16784#[target_feature(enable = "neon,v7")]
16785#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16787pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
16788    vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16789}
16790#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
16792#[doc = "## Safety"]
16793#[doc = "  * Neon instrinsic unsafe"]
16794#[inline]
16795#[cfg(target_arch = "arm")]
16796#[target_feature(enable = "neon,v7")]
16797#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16798#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
16799pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
16800    vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16801}
16802#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
16804#[doc = "## Safety"]
16805#[doc = "  * Neon instrinsic unsafe"]
16806#[inline]
16807#[cfg(target_arch = "arm")]
16808#[target_feature(enable = "neon,v7")]
16809#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16811pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
16812    vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16813}
16814#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
16816#[doc = "## Safety"]
16817#[doc = "  * Neon instrinsic unsafe"]
16818#[inline]
16819#[cfg(target_arch = "arm")]
16820#[target_feature(enable = "neon,v7")]
16821#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
16823pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
16824    vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16825}
16826#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
16828#[doc = "## Safety"]
16829#[doc = "  * Neon instrinsic unsafe"]
16830#[inline]
16831#[target_feature(enable = "neon")]
16832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16833#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16834#[cfg_attr(
16835    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16836    assert_instr(ld1)
16837)]
16838#[cfg_attr(
16839    not(target_arch = "arm"),
16840    stable(feature = "neon_intrinsics", since = "1.59.0")
16841)]
16842#[cfg_attr(
16843    target_arch = "arm",
16844    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16845)]
16846pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
16847    unsafe extern "unadjusted" {
16848        #[cfg_attr(
16849            any(target_arch = "aarch64", target_arch = "arm64ec"),
16850            link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
16851        )]
16852        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
16853        fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
16854    }
16855    _vld1_s8_x2(a)
16856}
16857#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
16859#[doc = "## Safety"]
16860#[doc = "  * Neon instrinsic unsafe"]
16861#[inline]
16862#[target_feature(enable = "neon")]
16863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16865#[cfg_attr(
16866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16867    assert_instr(ld1)
16868)]
16869#[cfg_attr(
16870    not(target_arch = "arm"),
16871    stable(feature = "neon_intrinsics", since = "1.59.0")
16872)]
16873#[cfg_attr(
16874    target_arch = "arm",
16875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16876)]
16877pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
16878    unsafe extern "unadjusted" {
16879        #[cfg_attr(
16880            any(target_arch = "aarch64", target_arch = "arm64ec"),
16881            link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
16882        )]
16883        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
16884        fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
16885    }
16886    _vld1_s8_x3(a)
16887}
16888#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
16890#[doc = "## Safety"]
16891#[doc = "  * Neon instrinsic unsafe"]
16892#[inline]
16893#[target_feature(enable = "neon")]
16894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16896#[cfg_attr(
16897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16898    assert_instr(ld1)
16899)]
16900#[cfg_attr(
16901    not(target_arch = "arm"),
16902    stable(feature = "neon_intrinsics", since = "1.59.0")
16903)]
16904#[cfg_attr(
16905    target_arch = "arm",
16906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16907)]
16908pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
16909    unsafe extern "unadjusted" {
16910        #[cfg_attr(
16911            any(target_arch = "aarch64", target_arch = "arm64ec"),
16912            link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
16913        )]
16914        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
16915        fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
16916    }
16917    _vld1_s8_x4(a)
16918}
16919#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
16921#[doc = "## Safety"]
16922#[doc = "  * Neon instrinsic unsafe"]
16923#[inline]
16924#[target_feature(enable = "neon")]
16925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16927#[cfg_attr(
16928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16929    assert_instr(ld1)
16930)]
16931#[cfg_attr(
16932    not(target_arch = "arm"),
16933    stable(feature = "neon_intrinsics", since = "1.59.0")
16934)]
16935#[cfg_attr(
16936    target_arch = "arm",
16937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16938)]
16939pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
16940    unsafe extern "unadjusted" {
16941        #[cfg_attr(
16942            any(target_arch = "aarch64", target_arch = "arm64ec"),
16943            link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
16944        )]
16945        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
16946        fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
16947    }
16948    _vld1q_s8_x2(a)
16949}
16950#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
16952#[doc = "## Safety"]
16953#[doc = "  * Neon instrinsic unsafe"]
16954#[inline]
16955#[target_feature(enable = "neon")]
16956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16957#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16958#[cfg_attr(
16959    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16960    assert_instr(ld1)
16961)]
16962#[cfg_attr(
16963    not(target_arch = "arm"),
16964    stable(feature = "neon_intrinsics", since = "1.59.0")
16965)]
16966#[cfg_attr(
16967    target_arch = "arm",
16968    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16969)]
16970pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
16971    unsafe extern "unadjusted" {
16972        #[cfg_attr(
16973            any(target_arch = "aarch64", target_arch = "arm64ec"),
16974            link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
16975        )]
16976        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
16977        fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
16978    }
16979    _vld1q_s8_x3(a)
16980}
16981#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
16983#[doc = "## Safety"]
16984#[doc = "  * Neon instrinsic unsafe"]
16985#[inline]
16986#[target_feature(enable = "neon")]
16987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16989#[cfg_attr(
16990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16991    assert_instr(ld1)
16992)]
16993#[cfg_attr(
16994    not(target_arch = "arm"),
16995    stable(feature = "neon_intrinsics", since = "1.59.0")
16996)]
16997#[cfg_attr(
16998    target_arch = "arm",
16999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17000)]
17001pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
17002    unsafe extern "unadjusted" {
17003        #[cfg_attr(
17004            any(target_arch = "aarch64", target_arch = "arm64ec"),
17005            link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
17006        )]
17007        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
17008        fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
17009    }
17010    _vld1q_s8_x4(a)
17011}
17012#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
17014#[doc = "## Safety"]
17015#[doc = "  * Neon instrinsic unsafe"]
17016#[inline]
17017#[target_feature(enable = "neon")]
17018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17020#[cfg_attr(
17021    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17022    assert_instr(ld1)
17023)]
17024#[cfg_attr(
17025    not(target_arch = "arm"),
17026    stable(feature = "neon_intrinsics", since = "1.59.0")
17027)]
17028#[cfg_attr(
17029    target_arch = "arm",
17030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17031)]
17032pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
17033    unsafe extern "unadjusted" {
17034        #[cfg_attr(
17035            any(target_arch = "aarch64", target_arch = "arm64ec"),
17036            link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
17037        )]
17038        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
17039        fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
17040    }
17041    _vld1_s16_x2(a)
17042}
17043#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
17045#[doc = "## Safety"]
17046#[doc = "  * Neon instrinsic unsafe"]
17047#[inline]
17048#[target_feature(enable = "neon")]
17049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17051#[cfg_attr(
17052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17053    assert_instr(ld1)
17054)]
17055#[cfg_attr(
17056    not(target_arch = "arm"),
17057    stable(feature = "neon_intrinsics", since = "1.59.0")
17058)]
17059#[cfg_attr(
17060    target_arch = "arm",
17061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17062)]
17063pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
17064    unsafe extern "unadjusted" {
17065        #[cfg_attr(
17066            any(target_arch = "aarch64", target_arch = "arm64ec"),
17067            link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
17068        )]
17069        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
17070        fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
17071    }
17072    _vld1_s16_x3(a)
17073}
17074#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
17076#[doc = "## Safety"]
17077#[doc = "  * Neon instrinsic unsafe"]
17078#[inline]
17079#[target_feature(enable = "neon")]
17080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17082#[cfg_attr(
17083    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17084    assert_instr(ld1)
17085)]
17086#[cfg_attr(
17087    not(target_arch = "arm"),
17088    stable(feature = "neon_intrinsics", since = "1.59.0")
17089)]
17090#[cfg_attr(
17091    target_arch = "arm",
17092    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17093)]
17094pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
17095    unsafe extern "unadjusted" {
17096        #[cfg_attr(
17097            any(target_arch = "aarch64", target_arch = "arm64ec"),
17098            link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
17099        )]
17100        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
17101        fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
17102    }
17103    _vld1_s16_x4(a)
17104}
17105#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
17107#[doc = "## Safety"]
17108#[doc = "  * Neon instrinsic unsafe"]
17109#[inline]
17110#[target_feature(enable = "neon")]
17111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17113#[cfg_attr(
17114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17115    assert_instr(ld1)
17116)]
17117#[cfg_attr(
17118    not(target_arch = "arm"),
17119    stable(feature = "neon_intrinsics", since = "1.59.0")
17120)]
17121#[cfg_attr(
17122    target_arch = "arm",
17123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17124)]
17125pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
17126    unsafe extern "unadjusted" {
17127        #[cfg_attr(
17128            any(target_arch = "aarch64", target_arch = "arm64ec"),
17129            link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
17130        )]
17131        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
17132        fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
17133    }
17134    _vld1q_s16_x2(a)
17135}
17136#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
17138#[doc = "## Safety"]
17139#[doc = "  * Neon instrinsic unsafe"]
17140#[inline]
17141#[target_feature(enable = "neon")]
17142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17144#[cfg_attr(
17145    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17146    assert_instr(ld1)
17147)]
17148#[cfg_attr(
17149    not(target_arch = "arm"),
17150    stable(feature = "neon_intrinsics", since = "1.59.0")
17151)]
17152#[cfg_attr(
17153    target_arch = "arm",
17154    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17155)]
17156pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
17157    unsafe extern "unadjusted" {
17158        #[cfg_attr(
17159            any(target_arch = "aarch64", target_arch = "arm64ec"),
17160            link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
17161        )]
17162        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
17163        fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
17164    }
17165    _vld1q_s16_x3(a)
17166}
17167#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
17169#[doc = "## Safety"]
17170#[doc = "  * Neon instrinsic unsafe"]
17171#[inline]
17172#[target_feature(enable = "neon")]
17173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17175#[cfg_attr(
17176    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17177    assert_instr(ld1)
17178)]
17179#[cfg_attr(
17180    not(target_arch = "arm"),
17181    stable(feature = "neon_intrinsics", since = "1.59.0")
17182)]
17183#[cfg_attr(
17184    target_arch = "arm",
17185    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17186)]
17187pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
17188    unsafe extern "unadjusted" {
17189        #[cfg_attr(
17190            any(target_arch = "aarch64", target_arch = "arm64ec"),
17191            link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
17192        )]
17193        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
17194        fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
17195    }
17196    _vld1q_s16_x4(a)
17197}
17198#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
17200#[doc = "## Safety"]
17201#[doc = "  * Neon instrinsic unsafe"]
17202#[inline]
17203#[target_feature(enable = "neon")]
17204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17206#[cfg_attr(
17207    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17208    assert_instr(ld1)
17209)]
17210#[cfg_attr(
17211    not(target_arch = "arm"),
17212    stable(feature = "neon_intrinsics", since = "1.59.0")
17213)]
17214#[cfg_attr(
17215    target_arch = "arm",
17216    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17217)]
17218pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
17219    unsafe extern "unadjusted" {
17220        #[cfg_attr(
17221            any(target_arch = "aarch64", target_arch = "arm64ec"),
17222            link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
17223        )]
17224        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
17225        fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
17226    }
17227    _vld1_s32_x2(a)
17228}
17229#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
17231#[doc = "## Safety"]
17232#[doc = "  * Neon instrinsic unsafe"]
17233#[inline]
17234#[target_feature(enable = "neon")]
17235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17237#[cfg_attr(
17238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17239    assert_instr(ld1)
17240)]
17241#[cfg_attr(
17242    not(target_arch = "arm"),
17243    stable(feature = "neon_intrinsics", since = "1.59.0")
17244)]
17245#[cfg_attr(
17246    target_arch = "arm",
17247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17248)]
17249pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
17250    unsafe extern "unadjusted" {
17251        #[cfg_attr(
17252            any(target_arch = "aarch64", target_arch = "arm64ec"),
17253            link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
17254        )]
17255        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
17256        fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
17257    }
17258    _vld1_s32_x3(a)
17259}
17260#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
17262#[doc = "## Safety"]
17263#[doc = "  * Neon instrinsic unsafe"]
17264#[inline]
17265#[target_feature(enable = "neon")]
17266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17268#[cfg_attr(
17269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17270    assert_instr(ld1)
17271)]
17272#[cfg_attr(
17273    not(target_arch = "arm"),
17274    stable(feature = "neon_intrinsics", since = "1.59.0")
17275)]
17276#[cfg_attr(
17277    target_arch = "arm",
17278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17279)]
17280pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
17281    unsafe extern "unadjusted" {
17282        #[cfg_attr(
17283            any(target_arch = "aarch64", target_arch = "arm64ec"),
17284            link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
17285        )]
17286        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
17287        fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
17288    }
17289    _vld1_s32_x4(a)
17290}
17291#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
17293#[doc = "## Safety"]
17294#[doc = "  * Neon instrinsic unsafe"]
17295#[inline]
17296#[target_feature(enable = "neon")]
17297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17299#[cfg_attr(
17300    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17301    assert_instr(ld1)
17302)]
17303#[cfg_attr(
17304    not(target_arch = "arm"),
17305    stable(feature = "neon_intrinsics", since = "1.59.0")
17306)]
17307#[cfg_attr(
17308    target_arch = "arm",
17309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17310)]
17311pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
17312    unsafe extern "unadjusted" {
17313        #[cfg_attr(
17314            any(target_arch = "aarch64", target_arch = "arm64ec"),
17315            link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
17316        )]
17317        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
17318        fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
17319    }
17320    _vld1q_s32_x2(a)
17321}
17322#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
17324#[doc = "## Safety"]
17325#[doc = "  * Neon instrinsic unsafe"]
17326#[inline]
17327#[target_feature(enable = "neon")]
17328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17330#[cfg_attr(
17331    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17332    assert_instr(ld1)
17333)]
17334#[cfg_attr(
17335    not(target_arch = "arm"),
17336    stable(feature = "neon_intrinsics", since = "1.59.0")
17337)]
17338#[cfg_attr(
17339    target_arch = "arm",
17340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17341)]
17342pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
17343    unsafe extern "unadjusted" {
17344        #[cfg_attr(
17345            any(target_arch = "aarch64", target_arch = "arm64ec"),
17346            link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
17347        )]
17348        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
17349        fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
17350    }
17351    _vld1q_s32_x3(a)
17352}
17353#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
17355#[doc = "## Safety"]
17356#[doc = "  * Neon instrinsic unsafe"]
17357#[inline]
17358#[target_feature(enable = "neon")]
17359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17361#[cfg_attr(
17362    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17363    assert_instr(ld1)
17364)]
17365#[cfg_attr(
17366    not(target_arch = "arm"),
17367    stable(feature = "neon_intrinsics", since = "1.59.0")
17368)]
17369#[cfg_attr(
17370    target_arch = "arm",
17371    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17372)]
17373pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
17374    unsafe extern "unadjusted" {
17375        #[cfg_attr(
17376            any(target_arch = "aarch64", target_arch = "arm64ec"),
17377            link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
17378        )]
17379        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
17380        fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
17381    }
17382    _vld1q_s32_x4(a)
17383}
17384#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
17386#[doc = "## Safety"]
17387#[doc = "  * Neon instrinsic unsafe"]
17388#[inline]
17389#[target_feature(enable = "neon")]
17390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17392#[cfg_attr(
17393    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17394    assert_instr(ld1)
17395)]
17396#[cfg_attr(
17397    not(target_arch = "arm"),
17398    stable(feature = "neon_intrinsics", since = "1.59.0")
17399)]
17400#[cfg_attr(
17401    target_arch = "arm",
17402    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17403)]
17404pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
17405    unsafe extern "unadjusted" {
17406        #[cfg_attr(
17407            any(target_arch = "aarch64", target_arch = "arm64ec"),
17408            link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
17409        )]
17410        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
17411        fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
17412    }
17413    _vld1_s64_x2(a)
17414}
17415#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
17417#[doc = "## Safety"]
17418#[doc = "  * Neon instrinsic unsafe"]
17419#[inline]
17420#[target_feature(enable = "neon")]
17421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17423#[cfg_attr(
17424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17425    assert_instr(ld1)
17426)]
17427#[cfg_attr(
17428    not(target_arch = "arm"),
17429    stable(feature = "neon_intrinsics", since = "1.59.0")
17430)]
17431#[cfg_attr(
17432    target_arch = "arm",
17433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17434)]
17435pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
17436    unsafe extern "unadjusted" {
17437        #[cfg_attr(
17438            any(target_arch = "aarch64", target_arch = "arm64ec"),
17439            link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
17440        )]
17441        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
17442        fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
17443    }
17444    _vld1_s64_x3(a)
17445}
17446#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
17448#[doc = "## Safety"]
17449#[doc = "  * Neon instrinsic unsafe"]
17450#[inline]
17451#[target_feature(enable = "neon")]
17452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17454#[cfg_attr(
17455    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17456    assert_instr(ld1)
17457)]
17458#[cfg_attr(
17459    not(target_arch = "arm"),
17460    stable(feature = "neon_intrinsics", since = "1.59.0")
17461)]
17462#[cfg_attr(
17463    target_arch = "arm",
17464    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17465)]
17466pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
17467    unsafe extern "unadjusted" {
17468        #[cfg_attr(
17469            any(target_arch = "aarch64", target_arch = "arm64ec"),
17470            link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
17471        )]
17472        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
17473        fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
17474    }
17475    _vld1_s64_x4(a)
17476}
17477#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
17479#[doc = "## Safety"]
17480#[doc = "  * Neon instrinsic unsafe"]
17481#[inline]
17482#[target_feature(enable = "neon")]
17483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17485#[cfg_attr(
17486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17487    assert_instr(ld1)
17488)]
17489#[cfg_attr(
17490    not(target_arch = "arm"),
17491    stable(feature = "neon_intrinsics", since = "1.59.0")
17492)]
17493#[cfg_attr(
17494    target_arch = "arm",
17495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17496)]
17497pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
17498    unsafe extern "unadjusted" {
17499        #[cfg_attr(
17500            any(target_arch = "aarch64", target_arch = "arm64ec"),
17501            link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
17502        )]
17503        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
17504        fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
17505    }
17506    _vld1q_s64_x2(a)
17507}
17508#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
17510#[doc = "## Safety"]
17511#[doc = "  * Neon instrinsic unsafe"]
17512#[inline]
17513#[target_feature(enable = "neon")]
17514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17516#[cfg_attr(
17517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17518    assert_instr(ld1)
17519)]
17520#[cfg_attr(
17521    not(target_arch = "arm"),
17522    stable(feature = "neon_intrinsics", since = "1.59.0")
17523)]
17524#[cfg_attr(
17525    target_arch = "arm",
17526    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17527)]
17528pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
17529    unsafe extern "unadjusted" {
17530        #[cfg_attr(
17531            any(target_arch = "aarch64", target_arch = "arm64ec"),
17532            link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
17533        )]
17534        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
17535        fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
17536    }
17537    _vld1q_s64_x3(a)
17538}
17539#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
17541#[doc = "## Safety"]
17542#[doc = "  * Neon instrinsic unsafe"]
17543#[inline]
17544#[target_feature(enable = "neon")]
17545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17547#[cfg_attr(
17548    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17549    assert_instr(ld1)
17550)]
17551#[cfg_attr(
17552    not(target_arch = "arm"),
17553    stable(feature = "neon_intrinsics", since = "1.59.0")
17554)]
17555#[cfg_attr(
17556    target_arch = "arm",
17557    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17558)]
17559pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
17560    unsafe extern "unadjusted" {
17561        #[cfg_attr(
17562            any(target_arch = "aarch64", target_arch = "arm64ec"),
17563            link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
17564        )]
17565        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
17566        fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
17567    }
17568    _vld1q_s64_x4(a)
17569}
17570#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17572#[doc = "## Safety"]
17573#[doc = "  * Neon instrinsic unsafe"]
17574#[inline]
17575#[cfg(target_endian = "little")]
17576#[target_feature(enable = "neon")]
17577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17579#[cfg_attr(
17580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17581    assert_instr(ld1)
17582)]
17583#[cfg_attr(
17584    not(target_arch = "arm"),
17585    stable(feature = "neon_intrinsics", since = "1.59.0")
17586)]
17587#[cfg_attr(
17588    target_arch = "arm",
17589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17590)]
17591pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17592    transmute(vld1_s8_x2(transmute(a)))
17593}
17594#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17596#[doc = "## Safety"]
17597#[doc = "  * Neon instrinsic unsafe"]
17598#[inline]
17599#[cfg(target_endian = "big")]
17600#[target_feature(enable = "neon")]
17601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17603#[cfg_attr(
17604    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17605    assert_instr(ld1)
17606)]
17607#[cfg_attr(
17608    not(target_arch = "arm"),
17609    stable(feature = "neon_intrinsics", since = "1.59.0")
17610)]
17611#[cfg_attr(
17612    target_arch = "arm",
17613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17614)]
17615pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17616    let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
17617    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17618    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17619    ret_val
17620}
17621#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17623#[doc = "## Safety"]
17624#[doc = "  * Neon instrinsic unsafe"]
17625#[inline]
17626#[cfg(target_endian = "little")]
17627#[target_feature(enable = "neon")]
17628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17630#[cfg_attr(
17631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17632    assert_instr(ld1)
17633)]
17634#[cfg_attr(
17635    not(target_arch = "arm"),
17636    stable(feature = "neon_intrinsics", since = "1.59.0")
17637)]
17638#[cfg_attr(
17639    target_arch = "arm",
17640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17641)]
17642pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17643    transmute(vld1_s8_x3(transmute(a)))
17644}
17645#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17647#[doc = "## Safety"]
17648#[doc = "  * Neon instrinsic unsafe"]
17649#[inline]
17650#[cfg(target_endian = "big")]
17651#[target_feature(enable = "neon")]
17652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17654#[cfg_attr(
17655    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17656    assert_instr(ld1)
17657)]
17658#[cfg_attr(
17659    not(target_arch = "arm"),
17660    stable(feature = "neon_intrinsics", since = "1.59.0")
17661)]
17662#[cfg_attr(
17663    target_arch = "arm",
17664    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17665)]
17666pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17667    let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
17668    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17669    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17670    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17671    ret_val
17672}
17673#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17675#[doc = "## Safety"]
17676#[doc = "  * Neon instrinsic unsafe"]
17677#[inline]
17678#[cfg(target_endian = "little")]
17679#[target_feature(enable = "neon")]
17680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17682#[cfg_attr(
17683    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17684    assert_instr(ld1)
17685)]
17686#[cfg_attr(
17687    not(target_arch = "arm"),
17688    stable(feature = "neon_intrinsics", since = "1.59.0")
17689)]
17690#[cfg_attr(
17691    target_arch = "arm",
17692    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17693)]
17694pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17695    transmute(vld1_s8_x4(transmute(a)))
17696}
17697#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17699#[doc = "## Safety"]
17700#[doc = "  * Neon instrinsic unsafe"]
17701#[inline]
17702#[cfg(target_endian = "big")]
17703#[target_feature(enable = "neon")]
17704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17706#[cfg_attr(
17707    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17708    assert_instr(ld1)
17709)]
17710#[cfg_attr(
17711    not(target_arch = "arm"),
17712    stable(feature = "neon_intrinsics", since = "1.59.0")
17713)]
17714#[cfg_attr(
17715    target_arch = "arm",
17716    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17717)]
17718pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17719    let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
17720    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17721    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17722    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17723    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
17724    ret_val
17725}
17726#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17728#[doc = "## Safety"]
17729#[doc = "  * Neon instrinsic unsafe"]
17730#[inline]
17731#[cfg(target_endian = "little")]
17732#[target_feature(enable = "neon")]
17733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17735#[cfg_attr(
17736    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17737    assert_instr(ld1)
17738)]
17739#[cfg_attr(
17740    not(target_arch = "arm"),
17741    stable(feature = "neon_intrinsics", since = "1.59.0")
17742)]
17743#[cfg_attr(
17744    target_arch = "arm",
17745    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17746)]
17747pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17748    transmute(vld1q_s8_x2(transmute(a)))
17749}
17750#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17752#[doc = "## Safety"]
17753#[doc = "  * Neon instrinsic unsafe"]
17754#[inline]
17755#[cfg(target_endian = "big")]
17756#[target_feature(enable = "neon")]
17757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17759#[cfg_attr(
17760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17761    assert_instr(ld1)
17762)]
17763#[cfg_attr(
17764    not(target_arch = "arm"),
17765    stable(feature = "neon_intrinsics", since = "1.59.0")
17766)]
17767#[cfg_attr(
17768    target_arch = "arm",
17769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17770)]
17771pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17772    let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
17773    ret_val.0 = unsafe {
17774        simd_shuffle!(
17775            ret_val.0,
17776            ret_val.0,
17777            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17778        )
17779    };
17780    ret_val.1 = unsafe {
17781        simd_shuffle!(
17782            ret_val.1,
17783            ret_val.1,
17784            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17785        )
17786    };
17787    ret_val
17788}
17789#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17791#[doc = "## Safety"]
17792#[doc = "  * Neon instrinsic unsafe"]
17793#[inline]
17794#[cfg(target_endian = "little")]
17795#[target_feature(enable = "neon")]
17796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17798#[cfg_attr(
17799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17800    assert_instr(ld1)
17801)]
17802#[cfg_attr(
17803    not(target_arch = "arm"),
17804    stable(feature = "neon_intrinsics", since = "1.59.0")
17805)]
17806#[cfg_attr(
17807    target_arch = "arm",
17808    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17809)]
17810pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17811    transmute(vld1q_s8_x3(transmute(a)))
17812}
17813#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17815#[doc = "## Safety"]
17816#[doc = "  * Neon instrinsic unsafe"]
17817#[inline]
17818#[cfg(target_endian = "big")]
17819#[target_feature(enable = "neon")]
17820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17822#[cfg_attr(
17823    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17824    assert_instr(ld1)
17825)]
17826#[cfg_attr(
17827    not(target_arch = "arm"),
17828    stable(feature = "neon_intrinsics", since = "1.59.0")
17829)]
17830#[cfg_attr(
17831    target_arch = "arm",
17832    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17833)]
17834pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17835    let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
17836    ret_val.0 = unsafe {
17837        simd_shuffle!(
17838            ret_val.0,
17839            ret_val.0,
17840            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17841        )
17842    };
17843    ret_val.1 = unsafe {
17844        simd_shuffle!(
17845            ret_val.1,
17846            ret_val.1,
17847            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17848        )
17849    };
17850    ret_val.2 = unsafe {
17851        simd_shuffle!(
17852            ret_val.2,
17853            ret_val.2,
17854            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17855        )
17856    };
17857    ret_val
17858}
17859#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17861#[doc = "## Safety"]
17862#[doc = "  * Neon instrinsic unsafe"]
17863#[inline]
17864#[cfg(target_endian = "little")]
17865#[target_feature(enable = "neon")]
17866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17868#[cfg_attr(
17869    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17870    assert_instr(ld1)
17871)]
17872#[cfg_attr(
17873    not(target_arch = "arm"),
17874    stable(feature = "neon_intrinsics", since = "1.59.0")
17875)]
17876#[cfg_attr(
17877    target_arch = "arm",
17878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17879)]
17880pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17881    transmute(vld1q_s8_x4(transmute(a)))
17882}
17883#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17885#[doc = "## Safety"]
17886#[doc = "  * Neon instrinsic unsafe"]
17887#[inline]
17888#[cfg(target_endian = "big")]
17889#[target_feature(enable = "neon")]
17890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17892#[cfg_attr(
17893    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17894    assert_instr(ld1)
17895)]
17896#[cfg_attr(
17897    not(target_arch = "arm"),
17898    stable(feature = "neon_intrinsics", since = "1.59.0")
17899)]
17900#[cfg_attr(
17901    target_arch = "arm",
17902    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17903)]
17904pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17905    let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
17906    ret_val.0 = unsafe {
17907        simd_shuffle!(
17908            ret_val.0,
17909            ret_val.0,
17910            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17911        )
17912    };
17913    ret_val.1 = unsafe {
17914        simd_shuffle!(
17915            ret_val.1,
17916            ret_val.1,
17917            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17918        )
17919    };
17920    ret_val.2 = unsafe {
17921        simd_shuffle!(
17922            ret_val.2,
17923            ret_val.2,
17924            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17925        )
17926    };
17927    ret_val.3 = unsafe {
17928        simd_shuffle!(
17929            ret_val.3,
17930            ret_val.3,
17931            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17932        )
17933    };
17934    ret_val
17935}
17936#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17938#[doc = "## Safety"]
17939#[doc = "  * Neon instrinsic unsafe"]
17940#[inline]
17941#[cfg(target_endian = "little")]
17942#[target_feature(enable = "neon")]
17943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17945#[cfg_attr(
17946    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17947    assert_instr(ld1)
17948)]
17949#[cfg_attr(
17950    not(target_arch = "arm"),
17951    stable(feature = "neon_intrinsics", since = "1.59.0")
17952)]
17953#[cfg_attr(
17954    target_arch = "arm",
17955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17956)]
17957pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17958    transmute(vld1_s16_x2(transmute(a)))
17959}
17960#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17962#[doc = "## Safety"]
17963#[doc = "  * Neon instrinsic unsafe"]
17964#[inline]
17965#[cfg(target_endian = "big")]
17966#[target_feature(enable = "neon")]
17967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17969#[cfg_attr(
17970    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17971    assert_instr(ld1)
17972)]
17973#[cfg_attr(
17974    not(target_arch = "arm"),
17975    stable(feature = "neon_intrinsics", since = "1.59.0")
17976)]
17977#[cfg_attr(
17978    target_arch = "arm",
17979    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17980)]
17981pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17982    let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
17983    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17984    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17985    ret_val
17986}
17987#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17989#[doc = "## Safety"]
17990#[doc = "  * Neon instrinsic unsafe"]
17991#[inline]
17992#[cfg(target_endian = "little")]
17993#[target_feature(enable = "neon")]
17994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17996#[cfg_attr(
17997    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17998    assert_instr(ld1)
17999)]
18000#[cfg_attr(
18001    not(target_arch = "arm"),
18002    stable(feature = "neon_intrinsics", since = "1.59.0")
18003)]
18004#[cfg_attr(
18005    target_arch = "arm",
18006    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18007)]
18008pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
18009    transmute(vld1_s16_x3(transmute(a)))
18010}
18011#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
18013#[doc = "## Safety"]
18014#[doc = "  * Neon instrinsic unsafe"]
18015#[inline]
18016#[cfg(target_endian = "big")]
18017#[target_feature(enable = "neon")]
18018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18020#[cfg_attr(
18021    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18022    assert_instr(ld1)
18023)]
18024#[cfg_attr(
18025    not(target_arch = "arm"),
18026    stable(feature = "neon_intrinsics", since = "1.59.0")
18027)]
18028#[cfg_attr(
18029    target_arch = "arm",
18030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18031)]
18032pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
18033    let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
18034    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18035    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18036    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18037    ret_val
18038}
18039#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
18041#[doc = "## Safety"]
18042#[doc = "  * Neon instrinsic unsafe"]
18043#[inline]
18044#[cfg(target_endian = "little")]
18045#[target_feature(enable = "neon")]
18046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18048#[cfg_attr(
18049    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18050    assert_instr(ld1)
18051)]
18052#[cfg_attr(
18053    not(target_arch = "arm"),
18054    stable(feature = "neon_intrinsics", since = "1.59.0")
18055)]
18056#[cfg_attr(
18057    target_arch = "arm",
18058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18059)]
18060pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
18061    transmute(vld1_s16_x4(transmute(a)))
18062}
18063#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
18065#[doc = "## Safety"]
18066#[doc = "  * Neon instrinsic unsafe"]
18067#[inline]
18068#[cfg(target_endian = "big")]
18069#[target_feature(enable = "neon")]
18070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18072#[cfg_attr(
18073    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18074    assert_instr(ld1)
18075)]
18076#[cfg_attr(
18077    not(target_arch = "arm"),
18078    stable(feature = "neon_intrinsics", since = "1.59.0")
18079)]
18080#[cfg_attr(
18081    target_arch = "arm",
18082    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18083)]
18084pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
18085    let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
18086    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18087    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18088    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18089    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18090    ret_val
18091}
18092#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18094#[doc = "## Safety"]
18095#[doc = "  * Neon instrinsic unsafe"]
18096#[inline]
18097#[cfg(target_endian = "little")]
18098#[target_feature(enable = "neon")]
18099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18101#[cfg_attr(
18102    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18103    assert_instr(ld1)
18104)]
18105#[cfg_attr(
18106    not(target_arch = "arm"),
18107    stable(feature = "neon_intrinsics", since = "1.59.0")
18108)]
18109#[cfg_attr(
18110    target_arch = "arm",
18111    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18112)]
18113pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18114    transmute(vld1q_s16_x2(transmute(a)))
18115}
18116#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18118#[doc = "## Safety"]
18119#[doc = "  * Neon instrinsic unsafe"]
18120#[inline]
18121#[cfg(target_endian = "big")]
18122#[target_feature(enable = "neon")]
18123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18125#[cfg_attr(
18126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18127    assert_instr(ld1)
18128)]
18129#[cfg_attr(
18130    not(target_arch = "arm"),
18131    stable(feature = "neon_intrinsics", since = "1.59.0")
18132)]
18133#[cfg_attr(
18134    target_arch = "arm",
18135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18136)]
18137pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18138    let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
18139    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18140    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18141    ret_val
18142}
18143#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18145#[doc = "## Safety"]
18146#[doc = "  * Neon instrinsic unsafe"]
18147#[inline]
18148#[cfg(target_endian = "little")]
18149#[target_feature(enable = "neon")]
18150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18151#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18152#[cfg_attr(
18153    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18154    assert_instr(ld1)
18155)]
18156#[cfg_attr(
18157    not(target_arch = "arm"),
18158    stable(feature = "neon_intrinsics", since = "1.59.0")
18159)]
18160#[cfg_attr(
18161    target_arch = "arm",
18162    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18163)]
18164pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18165    transmute(vld1q_s16_x3(transmute(a)))
18166}
18167#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18169#[doc = "## Safety"]
18170#[doc = "  * Neon instrinsic unsafe"]
18171#[inline]
18172#[cfg(target_endian = "big")]
18173#[target_feature(enable = "neon")]
18174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18176#[cfg_attr(
18177    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18178    assert_instr(ld1)
18179)]
18180#[cfg_attr(
18181    not(target_arch = "arm"),
18182    stable(feature = "neon_intrinsics", since = "1.59.0")
18183)]
18184#[cfg_attr(
18185    target_arch = "arm",
18186    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18187)]
18188pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18189    let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
18190    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18191    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18192    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18193    ret_val
18194}
18195#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18197#[doc = "## Safety"]
18198#[doc = "  * Neon instrinsic unsafe"]
18199#[inline]
18200#[cfg(target_endian = "little")]
18201#[target_feature(enable = "neon")]
18202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18204#[cfg_attr(
18205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18206    assert_instr(ld1)
18207)]
18208#[cfg_attr(
18209    not(target_arch = "arm"),
18210    stable(feature = "neon_intrinsics", since = "1.59.0")
18211)]
18212#[cfg_attr(
18213    target_arch = "arm",
18214    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18215)]
18216pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18217    transmute(vld1q_s16_x4(transmute(a)))
18218}
18219#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18221#[doc = "## Safety"]
18222#[doc = "  * Neon instrinsic unsafe"]
18223#[inline]
18224#[cfg(target_endian = "big")]
18225#[target_feature(enable = "neon")]
18226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18228#[cfg_attr(
18229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18230    assert_instr(ld1)
18231)]
18232#[cfg_attr(
18233    not(target_arch = "arm"),
18234    stable(feature = "neon_intrinsics", since = "1.59.0")
18235)]
18236#[cfg_attr(
18237    target_arch = "arm",
18238    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18239)]
18240pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18241    let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
18242    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18243    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18244    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18245    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18246    ret_val
18247}
18248#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18250#[doc = "## Safety"]
18251#[doc = "  * Neon instrinsic unsafe"]
18252#[inline]
18253#[cfg(target_endian = "little")]
18254#[target_feature(enable = "neon")]
18255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18257#[cfg_attr(
18258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18259    assert_instr(ld1)
18260)]
18261#[cfg_attr(
18262    not(target_arch = "arm"),
18263    stable(feature = "neon_intrinsics", since = "1.59.0")
18264)]
18265#[cfg_attr(
18266    target_arch = "arm",
18267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18268)]
18269pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18270    transmute(vld1_s32_x2(transmute(a)))
18271}
18272#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18274#[doc = "## Safety"]
18275#[doc = "  * Neon instrinsic unsafe"]
18276#[inline]
18277#[cfg(target_endian = "big")]
18278#[target_feature(enable = "neon")]
18279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18281#[cfg_attr(
18282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18283    assert_instr(ld1)
18284)]
18285#[cfg_attr(
18286    not(target_arch = "arm"),
18287    stable(feature = "neon_intrinsics", since = "1.59.0")
18288)]
18289#[cfg_attr(
18290    target_arch = "arm",
18291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18292)]
18293pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18294    let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
18295    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18296    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18297    ret_val
18298}
18299#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18301#[doc = "## Safety"]
18302#[doc = "  * Neon instrinsic unsafe"]
18303#[inline]
18304#[cfg(target_endian = "little")]
18305#[target_feature(enable = "neon")]
18306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18308#[cfg_attr(
18309    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18310    assert_instr(ld1)
18311)]
18312#[cfg_attr(
18313    not(target_arch = "arm"),
18314    stable(feature = "neon_intrinsics", since = "1.59.0")
18315)]
18316#[cfg_attr(
18317    target_arch = "arm",
18318    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18319)]
18320pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18321    transmute(vld1_s32_x3(transmute(a)))
18322}
18323#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18325#[doc = "## Safety"]
18326#[doc = "  * Neon instrinsic unsafe"]
18327#[inline]
18328#[cfg(target_endian = "big")]
18329#[target_feature(enable = "neon")]
18330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18332#[cfg_attr(
18333    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18334    assert_instr(ld1)
18335)]
18336#[cfg_attr(
18337    not(target_arch = "arm"),
18338    stable(feature = "neon_intrinsics", since = "1.59.0")
18339)]
18340#[cfg_attr(
18341    target_arch = "arm",
18342    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18343)]
18344pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18345    let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
18346    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18347    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18348    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18349    ret_val
18350}
18351#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18353#[doc = "## Safety"]
18354#[doc = "  * Neon instrinsic unsafe"]
18355#[inline]
18356#[cfg(target_endian = "little")]
18357#[target_feature(enable = "neon")]
18358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18360#[cfg_attr(
18361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18362    assert_instr(ld1)
18363)]
18364#[cfg_attr(
18365    not(target_arch = "arm"),
18366    stable(feature = "neon_intrinsics", since = "1.59.0")
18367)]
18368#[cfg_attr(
18369    target_arch = "arm",
18370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18371)]
18372pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18373    transmute(vld1_s32_x4(transmute(a)))
18374}
18375#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18377#[doc = "## Safety"]
18378#[doc = "  * Neon instrinsic unsafe"]
18379#[inline]
18380#[cfg(target_endian = "big")]
18381#[target_feature(enable = "neon")]
18382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18384#[cfg_attr(
18385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18386    assert_instr(ld1)
18387)]
18388#[cfg_attr(
18389    not(target_arch = "arm"),
18390    stable(feature = "neon_intrinsics", since = "1.59.0")
18391)]
18392#[cfg_attr(
18393    target_arch = "arm",
18394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18395)]
18396pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18397    let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
18398    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18399    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18400    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18401    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18402    ret_val
18403}
18404#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18406#[doc = "## Safety"]
18407#[doc = "  * Neon instrinsic unsafe"]
18408#[inline]
18409#[cfg(target_endian = "little")]
18410#[target_feature(enable = "neon")]
18411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18413#[cfg_attr(
18414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18415    assert_instr(ld1)
18416)]
18417#[cfg_attr(
18418    not(target_arch = "arm"),
18419    stable(feature = "neon_intrinsics", since = "1.59.0")
18420)]
18421#[cfg_attr(
18422    target_arch = "arm",
18423    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18424)]
18425pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18426    transmute(vld1q_s32_x2(transmute(a)))
18427}
18428#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18430#[doc = "## Safety"]
18431#[doc = "  * Neon instrinsic unsafe"]
18432#[inline]
18433#[cfg(target_endian = "big")]
18434#[target_feature(enable = "neon")]
18435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18437#[cfg_attr(
18438    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18439    assert_instr(ld1)
18440)]
18441#[cfg_attr(
18442    not(target_arch = "arm"),
18443    stable(feature = "neon_intrinsics", since = "1.59.0")
18444)]
18445#[cfg_attr(
18446    target_arch = "arm",
18447    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18448)]
18449pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18450    let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
18451    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18452    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18453    ret_val
18454}
18455#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18457#[doc = "## Safety"]
18458#[doc = "  * Neon instrinsic unsafe"]
18459#[inline]
18460#[cfg(target_endian = "little")]
18461#[target_feature(enable = "neon")]
18462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18464#[cfg_attr(
18465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18466    assert_instr(ld1)
18467)]
18468#[cfg_attr(
18469    not(target_arch = "arm"),
18470    stable(feature = "neon_intrinsics", since = "1.59.0")
18471)]
18472#[cfg_attr(
18473    target_arch = "arm",
18474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18475)]
18476pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18477    transmute(vld1q_s32_x3(transmute(a)))
18478}
18479#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18481#[doc = "## Safety"]
18482#[doc = "  * Neon instrinsic unsafe"]
18483#[inline]
18484#[cfg(target_endian = "big")]
18485#[target_feature(enable = "neon")]
18486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18488#[cfg_attr(
18489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18490    assert_instr(ld1)
18491)]
18492#[cfg_attr(
18493    not(target_arch = "arm"),
18494    stable(feature = "neon_intrinsics", since = "1.59.0")
18495)]
18496#[cfg_attr(
18497    target_arch = "arm",
18498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18499)]
18500pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18501    let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
18502    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18503    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18504    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18505    ret_val
18506}
18507#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18509#[doc = "## Safety"]
18510#[doc = "  * Neon instrinsic unsafe"]
18511#[inline]
18512#[cfg(target_endian = "little")]
18513#[target_feature(enable = "neon")]
18514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18516#[cfg_attr(
18517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18518    assert_instr(ld1)
18519)]
18520#[cfg_attr(
18521    not(target_arch = "arm"),
18522    stable(feature = "neon_intrinsics", since = "1.59.0")
18523)]
18524#[cfg_attr(
18525    target_arch = "arm",
18526    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18527)]
18528pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18529    transmute(vld1q_s32_x4(transmute(a)))
18530}
18531#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18533#[doc = "## Safety"]
18534#[doc = "  * Neon instrinsic unsafe"]
18535#[inline]
18536#[cfg(target_endian = "big")]
18537#[target_feature(enable = "neon")]
18538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18540#[cfg_attr(
18541    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18542    assert_instr(ld1)
18543)]
18544#[cfg_attr(
18545    not(target_arch = "arm"),
18546    stable(feature = "neon_intrinsics", since = "1.59.0")
18547)]
18548#[cfg_attr(
18549    target_arch = "arm",
18550    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18551)]
18552pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18553    let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
18554    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18555    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18556    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18557    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18558    ret_val
18559}
18560#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
18562#[doc = "## Safety"]
18563#[doc = "  * Neon instrinsic unsafe"]
18564#[inline]
18565#[target_feature(enable = "neon")]
18566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18568#[cfg_attr(
18569    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18570    assert_instr(ld1)
18571)]
18572#[cfg_attr(
18573    not(target_arch = "arm"),
18574    stable(feature = "neon_intrinsics", since = "1.59.0")
18575)]
18576#[cfg_attr(
18577    target_arch = "arm",
18578    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18579)]
18580pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
18581    transmute(vld1_s64_x2(transmute(a)))
18582}
18583#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
18585#[doc = "## Safety"]
18586#[doc = "  * Neon instrinsic unsafe"]
18587#[inline]
18588#[target_feature(enable = "neon")]
18589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18591#[cfg_attr(
18592    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18593    assert_instr(ld1)
18594)]
18595#[cfg_attr(
18596    not(target_arch = "arm"),
18597    stable(feature = "neon_intrinsics", since = "1.59.0")
18598)]
18599#[cfg_attr(
18600    target_arch = "arm",
18601    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18602)]
18603pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
18604    transmute(vld1_s64_x3(transmute(a)))
18605}
18606#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
18608#[doc = "## Safety"]
18609#[doc = "  * Neon instrinsic unsafe"]
18610#[inline]
18611#[target_feature(enable = "neon")]
18612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18614#[cfg_attr(
18615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18616    assert_instr(ld1)
18617)]
18618#[cfg_attr(
18619    not(target_arch = "arm"),
18620    stable(feature = "neon_intrinsics", since = "1.59.0")
18621)]
18622#[cfg_attr(
18623    target_arch = "arm",
18624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18625)]
18626pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
18627    transmute(vld1_s64_x4(transmute(a)))
18628}
18629#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18631#[doc = "## Safety"]
18632#[doc = "  * Neon instrinsic unsafe"]
18633#[inline]
18634#[cfg(target_endian = "little")]
18635#[target_feature(enable = "neon")]
18636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18638#[cfg_attr(
18639    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18640    assert_instr(ld1)
18641)]
18642#[cfg_attr(
18643    not(target_arch = "arm"),
18644    stable(feature = "neon_intrinsics", since = "1.59.0")
18645)]
18646#[cfg_attr(
18647    target_arch = "arm",
18648    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18649)]
18650pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18651    transmute(vld1q_s64_x2(transmute(a)))
18652}
18653#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18655#[doc = "## Safety"]
18656#[doc = "  * Neon instrinsic unsafe"]
18657#[inline]
18658#[cfg(target_endian = "big")]
18659#[target_feature(enable = "neon")]
18660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18662#[cfg_attr(
18663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18664    assert_instr(ld1)
18665)]
18666#[cfg_attr(
18667    not(target_arch = "arm"),
18668    stable(feature = "neon_intrinsics", since = "1.59.0")
18669)]
18670#[cfg_attr(
18671    target_arch = "arm",
18672    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18673)]
18674pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18675    let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
18676    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18677    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18678    ret_val
18679}
18680#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18682#[doc = "## Safety"]
18683#[doc = "  * Neon instrinsic unsafe"]
18684#[inline]
18685#[cfg(target_endian = "little")]
18686#[target_feature(enable = "neon")]
18687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18689#[cfg_attr(
18690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18691    assert_instr(ld1)
18692)]
18693#[cfg_attr(
18694    not(target_arch = "arm"),
18695    stable(feature = "neon_intrinsics", since = "1.59.0")
18696)]
18697#[cfg_attr(
18698    target_arch = "arm",
18699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18700)]
18701pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18702    transmute(vld1q_s64_x3(transmute(a)))
18703}
18704#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18706#[doc = "## Safety"]
18707#[doc = "  * Neon instrinsic unsafe"]
18708#[inline]
18709#[cfg(target_endian = "big")]
18710#[target_feature(enable = "neon")]
18711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18713#[cfg_attr(
18714    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18715    assert_instr(ld1)
18716)]
18717#[cfg_attr(
18718    not(target_arch = "arm"),
18719    stable(feature = "neon_intrinsics", since = "1.59.0")
18720)]
18721#[cfg_attr(
18722    target_arch = "arm",
18723    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18724)]
18725pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18726    let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
18727    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18728    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18729    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18730    ret_val
18731}
18732#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18734#[doc = "## Safety"]
18735#[doc = "  * Neon instrinsic unsafe"]
18736#[inline]
18737#[cfg(target_endian = "little")]
18738#[target_feature(enable = "neon")]
18739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18741#[cfg_attr(
18742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18743    assert_instr(ld1)
18744)]
18745#[cfg_attr(
18746    not(target_arch = "arm"),
18747    stable(feature = "neon_intrinsics", since = "1.59.0")
18748)]
18749#[cfg_attr(
18750    target_arch = "arm",
18751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18752)]
18753pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18754    transmute(vld1q_s64_x4(transmute(a)))
18755}
18756#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18758#[doc = "## Safety"]
18759#[doc = "  * Neon instrinsic unsafe"]
18760#[inline]
18761#[cfg(target_endian = "big")]
18762#[target_feature(enable = "neon")]
18763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18765#[cfg_attr(
18766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18767    assert_instr(ld1)
18768)]
18769#[cfg_attr(
18770    not(target_arch = "arm"),
18771    stable(feature = "neon_intrinsics", since = "1.59.0")
18772)]
18773#[cfg_attr(
18774    target_arch = "arm",
18775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18776)]
18777pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18778    let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
18779    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18780    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18781    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18782    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18783    ret_val
18784}
18785#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18787#[doc = "## Safety"]
18788#[doc = "  * Neon instrinsic unsafe"]
18789#[inline]
18790#[cfg(target_endian = "little")]
18791#[target_feature(enable = "neon")]
18792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18794#[cfg_attr(
18795    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18796    assert_instr(ld1)
18797)]
18798#[cfg_attr(
18799    not(target_arch = "arm"),
18800    stable(feature = "neon_intrinsics", since = "1.59.0")
18801)]
18802#[cfg_attr(
18803    target_arch = "arm",
18804    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18805)]
18806pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18807    transmute(vld1_s8_x2(transmute(a)))
18808}
18809#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18811#[doc = "## Safety"]
18812#[doc = "  * Neon instrinsic unsafe"]
18813#[inline]
18814#[cfg(target_endian = "big")]
18815#[target_feature(enable = "neon")]
18816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18818#[cfg_attr(
18819    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18820    assert_instr(ld1)
18821)]
18822#[cfg_attr(
18823    not(target_arch = "arm"),
18824    stable(feature = "neon_intrinsics", since = "1.59.0")
18825)]
18826#[cfg_attr(
18827    target_arch = "arm",
18828    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18829)]
18830pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18831    let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
18832    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18833    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18834    ret_val
18835}
18836#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18838#[doc = "## Safety"]
18839#[doc = "  * Neon instrinsic unsafe"]
18840#[inline]
18841#[cfg(target_endian = "little")]
18842#[target_feature(enable = "neon")]
18843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18845#[cfg_attr(
18846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18847    assert_instr(ld1)
18848)]
18849#[cfg_attr(
18850    not(target_arch = "arm"),
18851    stable(feature = "neon_intrinsics", since = "1.59.0")
18852)]
18853#[cfg_attr(
18854    target_arch = "arm",
18855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18856)]
18857pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18858    transmute(vld1_s8_x3(transmute(a)))
18859}
18860#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18862#[doc = "## Safety"]
18863#[doc = "  * Neon instrinsic unsafe"]
18864#[inline]
18865#[cfg(target_endian = "big")]
18866#[target_feature(enable = "neon")]
18867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18869#[cfg_attr(
18870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18871    assert_instr(ld1)
18872)]
18873#[cfg_attr(
18874    not(target_arch = "arm"),
18875    stable(feature = "neon_intrinsics", since = "1.59.0")
18876)]
18877#[cfg_attr(
18878    target_arch = "arm",
18879    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18880)]
18881pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18882    let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
18883    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18884    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18885    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18886    ret_val
18887}
18888#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18890#[doc = "## Safety"]
18891#[doc = "  * Neon instrinsic unsafe"]
18892#[inline]
18893#[cfg(target_endian = "little")]
18894#[target_feature(enable = "neon")]
18895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18897#[cfg_attr(
18898    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18899    assert_instr(ld1)
18900)]
18901#[cfg_attr(
18902    not(target_arch = "arm"),
18903    stable(feature = "neon_intrinsics", since = "1.59.0")
18904)]
18905#[cfg_attr(
18906    target_arch = "arm",
18907    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18908)]
18909pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18910    transmute(vld1_s8_x4(transmute(a)))
18911}
18912#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18914#[doc = "## Safety"]
18915#[doc = "  * Neon instrinsic unsafe"]
18916#[inline]
18917#[cfg(target_endian = "big")]
18918#[target_feature(enable = "neon")]
18919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18921#[cfg_attr(
18922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18923    assert_instr(ld1)
18924)]
18925#[cfg_attr(
18926    not(target_arch = "arm"),
18927    stable(feature = "neon_intrinsics", since = "1.59.0")
18928)]
18929#[cfg_attr(
18930    target_arch = "arm",
18931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18932)]
18933pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18934    let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
18935    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18936    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18937    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18938    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18939    ret_val
18940}
18941#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18943#[doc = "## Safety"]
18944#[doc = "  * Neon instrinsic unsafe"]
18945#[inline]
18946#[cfg(target_endian = "little")]
18947#[target_feature(enable = "neon")]
18948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18950#[cfg_attr(
18951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18952    assert_instr(ld1)
18953)]
18954#[cfg_attr(
18955    not(target_arch = "arm"),
18956    stable(feature = "neon_intrinsics", since = "1.59.0")
18957)]
18958#[cfg_attr(
18959    target_arch = "arm",
18960    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18961)]
18962pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18963    transmute(vld1q_s8_x2(transmute(a)))
18964}
18965#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18967#[doc = "## Safety"]
18968#[doc = "  * Neon instrinsic unsafe"]
18969#[inline]
18970#[cfg(target_endian = "big")]
18971#[target_feature(enable = "neon")]
18972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18974#[cfg_attr(
18975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18976    assert_instr(ld1)
18977)]
18978#[cfg_attr(
18979    not(target_arch = "arm"),
18980    stable(feature = "neon_intrinsics", since = "1.59.0")
18981)]
18982#[cfg_attr(
18983    target_arch = "arm",
18984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18985)]
18986pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18987    let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
18988    ret_val.0 = unsafe {
18989        simd_shuffle!(
18990            ret_val.0,
18991            ret_val.0,
18992            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18993        )
18994    };
18995    ret_val.1 = unsafe {
18996        simd_shuffle!(
18997            ret_val.1,
18998            ret_val.1,
18999            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19000        )
19001    };
19002    ret_val
19003}
19004#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
19006#[doc = "## Safety"]
19007#[doc = "  * Neon instrinsic unsafe"]
19008#[inline]
19009#[cfg(target_endian = "little")]
19010#[target_feature(enable = "neon")]
19011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19013#[cfg_attr(
19014    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19015    assert_instr(ld1)
19016)]
19017#[cfg_attr(
19018    not(target_arch = "arm"),
19019    stable(feature = "neon_intrinsics", since = "1.59.0")
19020)]
19021#[cfg_attr(
19022    target_arch = "arm",
19023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19024)]
19025pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
19026    transmute(vld1q_s8_x3(transmute(a)))
19027}
19028#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
19030#[doc = "## Safety"]
19031#[doc = "  * Neon instrinsic unsafe"]
19032#[inline]
19033#[cfg(target_endian = "big")]
19034#[target_feature(enable = "neon")]
19035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19037#[cfg_attr(
19038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19039    assert_instr(ld1)
19040)]
19041#[cfg_attr(
19042    not(target_arch = "arm"),
19043    stable(feature = "neon_intrinsics", since = "1.59.0")
19044)]
19045#[cfg_attr(
19046    target_arch = "arm",
19047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19048)]
19049pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
19050    let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
19051    ret_val.0 = unsafe {
19052        simd_shuffle!(
19053            ret_val.0,
19054            ret_val.0,
19055            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19056        )
19057    };
19058    ret_val.1 = unsafe {
19059        simd_shuffle!(
19060            ret_val.1,
19061            ret_val.1,
19062            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19063        )
19064    };
19065    ret_val.2 = unsafe {
19066        simd_shuffle!(
19067            ret_val.2,
19068            ret_val.2,
19069            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19070        )
19071    };
19072    ret_val
19073}
19074#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
19076#[doc = "## Safety"]
19077#[doc = "  * Neon instrinsic unsafe"]
19078#[inline]
19079#[cfg(target_endian = "little")]
19080#[target_feature(enable = "neon")]
19081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19083#[cfg_attr(
19084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19085    assert_instr(ld1)
19086)]
19087#[cfg_attr(
19088    not(target_arch = "arm"),
19089    stable(feature = "neon_intrinsics", since = "1.59.0")
19090)]
19091#[cfg_attr(
19092    target_arch = "arm",
19093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19094)]
19095pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19096    transmute(vld1q_s8_x4(transmute(a)))
19097}
19098#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
19100#[doc = "## Safety"]
19101#[doc = "  * Neon instrinsic unsafe"]
19102#[inline]
19103#[cfg(target_endian = "big")]
19104#[target_feature(enable = "neon")]
19105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19107#[cfg_attr(
19108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19109    assert_instr(ld1)
19110)]
19111#[cfg_attr(
19112    not(target_arch = "arm"),
19113    stable(feature = "neon_intrinsics", since = "1.59.0")
19114)]
19115#[cfg_attr(
19116    target_arch = "arm",
19117    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19118)]
19119pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19120    let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
19121    ret_val.0 = unsafe {
19122        simd_shuffle!(
19123            ret_val.0,
19124            ret_val.0,
19125            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19126        )
19127    };
19128    ret_val.1 = unsafe {
19129        simd_shuffle!(
19130            ret_val.1,
19131            ret_val.1,
19132            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19133        )
19134    };
19135    ret_val.2 = unsafe {
19136        simd_shuffle!(
19137            ret_val.2,
19138            ret_val.2,
19139            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19140        )
19141    };
19142    ret_val.3 = unsafe {
19143        simd_shuffle!(
19144            ret_val.3,
19145            ret_val.3,
19146            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19147        )
19148    };
19149    ret_val
19150}
19151#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19153#[doc = "## Safety"]
19154#[doc = "  * Neon instrinsic unsafe"]
19155#[inline]
19156#[cfg(target_endian = "little")]
19157#[target_feature(enable = "neon")]
19158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19160#[cfg_attr(
19161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19162    assert_instr(ld1)
19163)]
19164#[cfg_attr(
19165    not(target_arch = "arm"),
19166    stable(feature = "neon_intrinsics", since = "1.59.0")
19167)]
19168#[cfg_attr(
19169    target_arch = "arm",
19170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19171)]
19172pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19173    transmute(vld1_s16_x2(transmute(a)))
19174}
19175#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19177#[doc = "## Safety"]
19178#[doc = "  * Neon instrinsic unsafe"]
19179#[inline]
19180#[cfg(target_endian = "big")]
19181#[target_feature(enable = "neon")]
19182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19184#[cfg_attr(
19185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19186    assert_instr(ld1)
19187)]
19188#[cfg_attr(
19189    not(target_arch = "arm"),
19190    stable(feature = "neon_intrinsics", since = "1.59.0")
19191)]
19192#[cfg_attr(
19193    target_arch = "arm",
19194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19195)]
19196pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19197    let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
19198    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19199    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19200    ret_val
19201}
19202#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19204#[doc = "## Safety"]
19205#[doc = "  * Neon instrinsic unsafe"]
19206#[inline]
19207#[cfg(target_endian = "little")]
19208#[target_feature(enable = "neon")]
19209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19211#[cfg_attr(
19212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19213    assert_instr(ld1)
19214)]
19215#[cfg_attr(
19216    not(target_arch = "arm"),
19217    stable(feature = "neon_intrinsics", since = "1.59.0")
19218)]
19219#[cfg_attr(
19220    target_arch = "arm",
19221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19222)]
19223pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19224    transmute(vld1_s16_x3(transmute(a)))
19225}
19226#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19228#[doc = "## Safety"]
19229#[doc = "  * Neon instrinsic unsafe"]
19230#[inline]
19231#[cfg(target_endian = "big")]
19232#[target_feature(enable = "neon")]
19233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19235#[cfg_attr(
19236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19237    assert_instr(ld1)
19238)]
19239#[cfg_attr(
19240    not(target_arch = "arm"),
19241    stable(feature = "neon_intrinsics", since = "1.59.0")
19242)]
19243#[cfg_attr(
19244    target_arch = "arm",
19245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19246)]
19247pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19248    let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
19249    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19250    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19251    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19252    ret_val
19253}
19254#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19256#[doc = "## Safety"]
19257#[doc = "  * Neon instrinsic unsafe"]
19258#[inline]
19259#[cfg(target_endian = "little")]
19260#[target_feature(enable = "neon")]
19261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19263#[cfg_attr(
19264    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19265    assert_instr(ld1)
19266)]
19267#[cfg_attr(
19268    not(target_arch = "arm"),
19269    stable(feature = "neon_intrinsics", since = "1.59.0")
19270)]
19271#[cfg_attr(
19272    target_arch = "arm",
19273    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19274)]
19275pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19276    transmute(vld1_s16_x4(transmute(a)))
19277}
19278#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19280#[doc = "## Safety"]
19281#[doc = "  * Neon instrinsic unsafe"]
19282#[inline]
19283#[cfg(target_endian = "big")]
19284#[target_feature(enable = "neon")]
19285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19287#[cfg_attr(
19288    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19289    assert_instr(ld1)
19290)]
19291#[cfg_attr(
19292    not(target_arch = "arm"),
19293    stable(feature = "neon_intrinsics", since = "1.59.0")
19294)]
19295#[cfg_attr(
19296    target_arch = "arm",
19297    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19298)]
19299pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19300    let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
19301    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19302    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19303    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19304    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
19305    ret_val
19306}
19307#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19309#[doc = "## Safety"]
19310#[doc = "  * Neon instrinsic unsafe"]
19311#[inline]
19312#[cfg(target_endian = "little")]
19313#[target_feature(enable = "neon")]
19314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19316#[cfg_attr(
19317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19318    assert_instr(ld1)
19319)]
19320#[cfg_attr(
19321    not(target_arch = "arm"),
19322    stable(feature = "neon_intrinsics", since = "1.59.0")
19323)]
19324#[cfg_attr(
19325    target_arch = "arm",
19326    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19327)]
19328pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19329    transmute(vld1q_s16_x2(transmute(a)))
19330}
19331#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19333#[doc = "## Safety"]
19334#[doc = "  * Neon instrinsic unsafe"]
19335#[inline]
19336#[cfg(target_endian = "big")]
19337#[target_feature(enable = "neon")]
19338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19340#[cfg_attr(
19341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19342    assert_instr(ld1)
19343)]
19344#[cfg_attr(
19345    not(target_arch = "arm"),
19346    stable(feature = "neon_intrinsics", since = "1.59.0")
19347)]
19348#[cfg_attr(
19349    target_arch = "arm",
19350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19351)]
19352pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19353    let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
19354    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19355    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19356    ret_val
19357}
19358#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19360#[doc = "## Safety"]
19361#[doc = "  * Neon instrinsic unsafe"]
19362#[inline]
19363#[cfg(target_endian = "little")]
19364#[target_feature(enable = "neon")]
19365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19367#[cfg_attr(
19368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19369    assert_instr(ld1)
19370)]
19371#[cfg_attr(
19372    not(target_arch = "arm"),
19373    stable(feature = "neon_intrinsics", since = "1.59.0")
19374)]
19375#[cfg_attr(
19376    target_arch = "arm",
19377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19378)]
19379pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19380    transmute(vld1q_s16_x3(transmute(a)))
19381}
19382#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19384#[doc = "## Safety"]
19385#[doc = "  * Neon instrinsic unsafe"]
19386#[inline]
19387#[cfg(target_endian = "big")]
19388#[target_feature(enable = "neon")]
19389#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19391#[cfg_attr(
19392    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19393    assert_instr(ld1)
19394)]
19395#[cfg_attr(
19396    not(target_arch = "arm"),
19397    stable(feature = "neon_intrinsics", since = "1.59.0")
19398)]
19399#[cfg_attr(
19400    target_arch = "arm",
19401    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19402)]
19403pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19404    let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
19405    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19406    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19407    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19408    ret_val
19409}
19410#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19412#[doc = "## Safety"]
19413#[doc = "  * Neon instrinsic unsafe"]
19414#[inline]
19415#[cfg(target_endian = "little")]
19416#[target_feature(enable = "neon")]
19417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19419#[cfg_attr(
19420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19421    assert_instr(ld1)
19422)]
19423#[cfg_attr(
19424    not(target_arch = "arm"),
19425    stable(feature = "neon_intrinsics", since = "1.59.0")
19426)]
19427#[cfg_attr(
19428    target_arch = "arm",
19429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19430)]
19431pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19432    transmute(vld1q_s16_x4(transmute(a)))
19433}
19434#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19436#[doc = "## Safety"]
19437#[doc = "  * Neon instrinsic unsafe"]
19438#[inline]
19439#[cfg(target_endian = "big")]
19440#[target_feature(enable = "neon")]
19441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19443#[cfg_attr(
19444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19445    assert_instr(ld1)
19446)]
19447#[cfg_attr(
19448    not(target_arch = "arm"),
19449    stable(feature = "neon_intrinsics", since = "1.59.0")
19450)]
19451#[cfg_attr(
19452    target_arch = "arm",
19453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19454)]
19455pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19456    let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
19457    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19458    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19459    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19460    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
19461    ret_val
19462}
19463#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
19465#[doc = "## Safety"]
19466#[doc = "  * Neon instrinsic unsafe"]
19467#[inline]
19468#[cfg(target_arch = "arm")]
19469#[target_feature(enable = "neon,v7")]
19470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19471unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
19472    unsafe extern "unadjusted" {
19473        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
19474        fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
19475    }
19476    _vld1_v1i64(a, b)
19477}
19478#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
19480#[doc = "## Safety"]
19481#[doc = "  * Neon instrinsic unsafe"]
19482#[inline]
19483#[cfg(target_arch = "arm")]
19484#[target_feature(enable = "neon,v7")]
19485#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19486unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
19487    unsafe extern "unadjusted" {
19488        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
19489        fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
19490    }
19491    _vld1_v2f32(a, b)
19492}
19493#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
19495#[doc = "## Safety"]
19496#[doc = "  * Neon instrinsic unsafe"]
19497#[inline]
19498#[cfg(target_arch = "arm")]
19499#[target_feature(enable = "neon,v7")]
19500#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19501unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
19502    unsafe extern "unadjusted" {
19503        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
19504        fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
19505    }
19506    _vld1_v2i32(a, b)
19507}
19508#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
19510#[doc = "## Safety"]
19511#[doc = "  * Neon instrinsic unsafe"]
19512#[inline]
19513#[cfg(target_arch = "arm")]
19514#[target_feature(enable = "neon,v7")]
19515#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19516unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
19517    unsafe extern "unadjusted" {
19518        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
19519        fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
19520    }
19521    _vld1_v4i16(a, b)
19522}
19523#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
19525#[doc = "## Safety"]
19526#[doc = "  * Neon instrinsic unsafe"]
19527#[inline]
19528#[cfg(target_arch = "arm")]
19529#[target_feature(enable = "neon,v7")]
19530#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19531unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
19532    unsafe extern "unadjusted" {
19533        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
19534        fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
19535    }
19536    _vld1_v8i8(a, b)
19537}
19538#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
19540#[doc = "## Safety"]
19541#[doc = "  * Neon instrinsic unsafe"]
19542#[inline]
19543#[cfg(target_arch = "arm")]
19544#[target_feature(enable = "neon,v7")]
19545#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19546unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
19547    unsafe extern "unadjusted" {
19548        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
19549        fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
19550    }
19551    _vld1q_v16i8(a, b)
19552}
19553#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
19555#[doc = "## Safety"]
19556#[doc = "  * Neon instrinsic unsafe"]
19557#[inline]
19558#[cfg(target_arch = "arm")]
19559#[target_feature(enable = "neon,v7")]
19560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19561unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
19562    unsafe extern "unadjusted" {
19563        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
19564        fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
19565    }
19566    _vld1q_v2i64(a, b)
19567}
19568#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
19570#[doc = "## Safety"]
19571#[doc = "  * Neon instrinsic unsafe"]
19572#[inline]
19573#[cfg(target_arch = "arm")]
19574#[target_feature(enable = "neon,v7")]
19575#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19576unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
19577    unsafe extern "unadjusted" {
19578        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
19579        fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
19580    }
19581    _vld1q_v4f32(a, b)
19582}
19583#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
19585#[doc = "## Safety"]
19586#[doc = "  * Neon instrinsic unsafe"]
19587#[inline]
19588#[cfg(target_arch = "arm")]
19589#[target_feature(enable = "neon,v7")]
19590#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19591unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
19592    unsafe extern "unadjusted" {
19593        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
19594        fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
19595    }
19596    _vld1q_v4i32(a, b)
19597}
19598#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
19600#[doc = "## Safety"]
19601#[doc = "  * Neon instrinsic unsafe"]
19602#[inline]
19603#[cfg(target_arch = "arm")]
19604#[target_feature(enable = "neon,v7")]
19605#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19606unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
19607    unsafe extern "unadjusted" {
19608        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
19609        fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
19610    }
19611    _vld1q_v8i16(a, b)
19612}
19613#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
19615#[doc = "## Safety"]
19616#[doc = "  * Neon instrinsic unsafe"]
19617#[inline]
19618#[cfg(target_arch = "arm")]
19619#[target_feature(enable = "neon,v7")]
19620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19621#[target_feature(enable = "neon,fp16")]
19622#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19623unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
19624    unsafe extern "unadjusted" {
19625        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")]
19626        fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t;
19627    }
19628    _vld1_v4f16(a, b)
19629}
19630#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
19632#[doc = "## Safety"]
19633#[doc = "  * Neon instrinsic unsafe"]
19634#[inline]
19635#[cfg(target_arch = "arm")]
19636#[target_feature(enable = "neon,v7")]
19637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19638#[target_feature(enable = "neon,fp16")]
19639#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19640unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
19641    unsafe extern "unadjusted" {
19642        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")]
19643        fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t;
19644    }
19645    _vld1q_v8f16(a, b)
19646}
19647#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
19648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
19649#[doc = "## Safety"]
19650#[doc = "  * Neon instrinsic unsafe"]
19651#[inline]
19652#[target_feature(enable = "neon,aes")]
19653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
19655#[cfg_attr(
19656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19657    assert_instr(ld1r)
19658)]
19659#[cfg_attr(
19660    not(target_arch = "arm"),
19661    stable(feature = "neon_intrinsics", since = "1.59.0")
19662)]
19663#[cfg_attr(
19664    target_arch = "arm",
19665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19666)]
19667pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
19668    let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0)));
19669    simd_shuffle!(x, x, [0, 0])
19670}
19671#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19673#[doc = "## Safety"]
19674#[doc = "  * Neon instrinsic unsafe"]
19675#[inline]
19676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19677#[cfg(target_arch = "arm")]
19678#[target_feature(enable = "neon,fp16")]
19679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19680#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19681pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19682    unsafe extern "unadjusted" {
19683        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0f16")]
19684        fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
19685    }
19686    _vld2_dup_f16(a as _, 2)
19687}
19688#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19690#[doc = "## Safety"]
19691#[doc = "  * Neon instrinsic unsafe"]
19692#[inline]
19693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19694#[cfg(target_arch = "arm")]
19695#[target_feature(enable = "neon,fp16")]
19696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19697#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19698pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19699    unsafe extern "unadjusted" {
19700        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0f16")]
19701        fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
19702    }
19703    _vld2q_dup_f16(a as _, 2)
19704}
19705#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19707#[doc = "## Safety"]
19708#[doc = "  * Neon instrinsic unsafe"]
19709#[inline]
19710#[cfg(not(target_arch = "arm"))]
19711#[cfg_attr(
19712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19713    assert_instr(ld2r)
19714)]
19715#[target_feature(enable = "neon,fp16")]
19716#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19717pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19718    unsafe extern "unadjusted" {
19719        #[cfg_attr(
19720            any(target_arch = "aarch64", target_arch = "arm64ec"),
19721            link_name = "llvm.aarch64.neon.ld2r.v4f16.p0f16"
19722        )]
19723        fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t;
19724    }
19725    _vld2_dup_f16(a as _)
19726}
19727#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19729#[doc = "## Safety"]
19730#[doc = "  * Neon instrinsic unsafe"]
19731#[inline]
19732#[cfg(not(target_arch = "arm"))]
19733#[cfg_attr(
19734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19735    assert_instr(ld2r)
19736)]
19737#[target_feature(enable = "neon,fp16")]
19738#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19739pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19740    unsafe extern "unadjusted" {
19741        #[cfg_attr(
19742            any(target_arch = "aarch64", target_arch = "arm64ec"),
19743            link_name = "llvm.aarch64.neon.ld2r.v8f16.p0f16"
19744        )]
19745        fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t;
19746    }
19747    _vld2q_dup_f16(a as _)
19748}
19749#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19751#[doc = "## Safety"]
19752#[doc = "  * Neon instrinsic unsafe"]
19753#[inline]
19754#[target_feature(enable = "neon,v7")]
19755#[cfg(target_arch = "arm")]
19756#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19757#[cfg_attr(test, assert_instr(vld2))]
19758pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19759    unsafe extern "unadjusted" {
19760        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")]
19761        fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
19762    }
19763    _vld2_dup_f32(a as *const i8, 4)
19764}
19765#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19767#[doc = "## Safety"]
19768#[doc = "  * Neon instrinsic unsafe"]
19769#[inline]
19770#[target_feature(enable = "neon,v7")]
19771#[cfg(target_arch = "arm")]
19772#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19773#[cfg_attr(test, assert_instr(vld2))]
19774pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19775    unsafe extern "unadjusted" {
19776        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")]
19777        fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
19778    }
19779    _vld2q_dup_f32(a as *const i8, 4)
19780}
19781#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19783#[doc = "## Safety"]
19784#[doc = "  * Neon instrinsic unsafe"]
19785#[inline]
19786#[target_feature(enable = "neon,v7")]
19787#[cfg(target_arch = "arm")]
19788#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19789#[cfg_attr(test, assert_instr(vld2))]
19790pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19791    unsafe extern "unadjusted" {
19792        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")]
19793        fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
19794    }
19795    _vld2_dup_s8(a as *const i8, 1)
19796}
19797#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19799#[doc = "## Safety"]
19800#[doc = "  * Neon instrinsic unsafe"]
19801#[inline]
19802#[target_feature(enable = "neon,v7")]
19803#[cfg(target_arch = "arm")]
19804#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19805#[cfg_attr(test, assert_instr(vld2))]
19806pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19807    unsafe extern "unadjusted" {
19808        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")]
19809        fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
19810    }
19811    _vld2q_dup_s8(a as *const i8, 1)
19812}
19813#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19815#[doc = "## Safety"]
19816#[doc = "  * Neon instrinsic unsafe"]
19817#[inline]
19818#[target_feature(enable = "neon,v7")]
19819#[cfg(target_arch = "arm")]
19820#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19821#[cfg_attr(test, assert_instr(vld2))]
19822pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19823    unsafe extern "unadjusted" {
19824        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")]
19825        fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
19826    }
19827    _vld2_dup_s16(a as *const i8, 2)
19828}
19829#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19831#[doc = "## Safety"]
19832#[doc = "  * Neon instrinsic unsafe"]
19833#[inline]
19834#[target_feature(enable = "neon,v7")]
19835#[cfg(target_arch = "arm")]
19836#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19837#[cfg_attr(test, assert_instr(vld2))]
19838pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19839    unsafe extern "unadjusted" {
19840        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")]
19841        fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
19842    }
19843    _vld2q_dup_s16(a as *const i8, 2)
19844}
19845#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19847#[doc = "## Safety"]
19848#[doc = "  * Neon instrinsic unsafe"]
19849#[inline]
19850#[target_feature(enable = "neon,v7")]
19851#[cfg(target_arch = "arm")]
19852#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19853#[cfg_attr(test, assert_instr(vld2))]
19854pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19855    unsafe extern "unadjusted" {
19856        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")]
19857        fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
19858    }
19859    _vld2_dup_s32(a as *const i8, 4)
19860}
19861#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19863#[doc = "## Safety"]
19864#[doc = "  * Neon instrinsic unsafe"]
19865#[inline]
19866#[target_feature(enable = "neon,v7")]
19867#[cfg(target_arch = "arm")]
19868#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19869#[cfg_attr(test, assert_instr(vld2))]
19870pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19871    unsafe extern "unadjusted" {
19872        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")]
19873        fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
19874    }
19875    _vld2q_dup_s32(a as *const i8, 4)
19876}
19877#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19879#[doc = "## Safety"]
19880#[doc = "  * Neon instrinsic unsafe"]
19881#[inline]
19882#[target_feature(enable = "neon")]
19883#[cfg(not(target_arch = "arm"))]
19884#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19885#[cfg_attr(test, assert_instr(ld2r))]
19886pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19887    unsafe extern "unadjusted" {
19888        #[cfg_attr(
19889            any(target_arch = "aarch64", target_arch = "arm64ec"),
19890            link_name = "llvm.aarch64.neon.ld2r.v2f32.p0"
19891        )]
19892        fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t;
19893    }
19894    _vld2_dup_f32(a as _)
19895}
19896#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19898#[doc = "## Safety"]
19899#[doc = "  * Neon instrinsic unsafe"]
19900#[inline]
19901#[target_feature(enable = "neon")]
19902#[cfg(not(target_arch = "arm"))]
19903#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19904#[cfg_attr(test, assert_instr(ld2r))]
19905pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19906    unsafe extern "unadjusted" {
19907        #[cfg_attr(
19908            any(target_arch = "aarch64", target_arch = "arm64ec"),
19909            link_name = "llvm.aarch64.neon.ld2r.v4f32.p0"
19910        )]
19911        fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t;
19912    }
19913    _vld2q_dup_f32(a as _)
19914}
19915#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19917#[doc = "## Safety"]
19918#[doc = "  * Neon instrinsic unsafe"]
19919#[inline]
19920#[target_feature(enable = "neon")]
19921#[cfg(not(target_arch = "arm"))]
19922#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19923#[cfg_attr(test, assert_instr(ld2r))]
19924pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19925    unsafe extern "unadjusted" {
19926        #[cfg_attr(
19927            any(target_arch = "aarch64", target_arch = "arm64ec"),
19928            link_name = "llvm.aarch64.neon.ld2r.v8i8.p0"
19929        )]
19930        fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t;
19931    }
19932    _vld2_dup_s8(a as _)
19933}
19934#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19936#[doc = "## Safety"]
19937#[doc = "  * Neon instrinsic unsafe"]
19938#[inline]
19939#[target_feature(enable = "neon")]
19940#[cfg(not(target_arch = "arm"))]
19941#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19942#[cfg_attr(test, assert_instr(ld2r))]
19943pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19944    unsafe extern "unadjusted" {
19945        #[cfg_attr(
19946            any(target_arch = "aarch64", target_arch = "arm64ec"),
19947            link_name = "llvm.aarch64.neon.ld2r.v16i8.p0"
19948        )]
19949        fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t;
19950    }
19951    _vld2q_dup_s8(a as _)
19952}
19953#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19955#[doc = "## Safety"]
19956#[doc = "  * Neon instrinsic unsafe"]
19957#[inline]
19958#[target_feature(enable = "neon")]
19959#[cfg(not(target_arch = "arm"))]
19960#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19961#[cfg_attr(test, assert_instr(ld2r))]
19962pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19963    unsafe extern "unadjusted" {
19964        #[cfg_attr(
19965            any(target_arch = "aarch64", target_arch = "arm64ec"),
19966            link_name = "llvm.aarch64.neon.ld2r.v4i16.p0"
19967        )]
19968        fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t;
19969    }
19970    _vld2_dup_s16(a as _)
19971}
19972#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19974#[doc = "## Safety"]
19975#[doc = "  * Neon instrinsic unsafe"]
19976#[inline]
19977#[target_feature(enable = "neon")]
19978#[cfg(not(target_arch = "arm"))]
19979#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19980#[cfg_attr(test, assert_instr(ld2r))]
19981pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19982    unsafe extern "unadjusted" {
19983        #[cfg_attr(
19984            any(target_arch = "aarch64", target_arch = "arm64ec"),
19985            link_name = "llvm.aarch64.neon.ld2r.v8i16.p0"
19986        )]
19987        fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t;
19988    }
19989    _vld2q_dup_s16(a as _)
19990}
19991#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19993#[doc = "## Safety"]
19994#[doc = "  * Neon instrinsic unsafe"]
19995#[inline]
19996#[target_feature(enable = "neon")]
19997#[cfg(not(target_arch = "arm"))]
19998#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19999#[cfg_attr(test, assert_instr(ld2r))]
20000pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
20001    unsafe extern "unadjusted" {
20002        #[cfg_attr(
20003            any(target_arch = "aarch64", target_arch = "arm64ec"),
20004            link_name = "llvm.aarch64.neon.ld2r.v2i32.p0"
20005        )]
20006        fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t;
20007    }
20008    _vld2_dup_s32(a as _)
20009}
20010#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
20012#[doc = "## Safety"]
20013#[doc = "  * Neon instrinsic unsafe"]
20014#[inline]
20015#[target_feature(enable = "neon")]
20016#[cfg(not(target_arch = "arm"))]
20017#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20018#[cfg_attr(test, assert_instr(ld2r))]
20019pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
20020    unsafe extern "unadjusted" {
20021        #[cfg_attr(
20022            any(target_arch = "aarch64", target_arch = "arm64ec"),
20023            link_name = "llvm.aarch64.neon.ld2r.v4i32.p0"
20024        )]
20025        fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t;
20026    }
20027    _vld2q_dup_s32(a as _)
20028}
20029#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
20031#[doc = "## Safety"]
20032#[doc = "  * Neon instrinsic unsafe"]
20033#[inline]
20034#[target_feature(enable = "neon,aes")]
20035#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20037#[cfg_attr(
20038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20039    assert_instr(ld2r)
20040)]
20041#[cfg_attr(
20042    not(target_arch = "arm"),
20043    stable(feature = "neon_intrinsics", since = "1.59.0")
20044)]
20045#[cfg_attr(
20046    target_arch = "arm",
20047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20048)]
20049pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
20050    transmute(vld2_dup_s64(transmute(a)))
20051}
20052#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
20054#[doc = "## Safety"]
20055#[doc = "  * Neon instrinsic unsafe"]
20056#[inline]
20057#[target_feature(enable = "neon,v7")]
20058#[cfg(target_arch = "arm")]
20059#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20060#[cfg_attr(test, assert_instr(nop))]
20061pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
20062    unsafe extern "unadjusted" {
20063        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")]
20064        fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
20065    }
20066    _vld2_dup_s64(a as *const i8, 8)
20067}
20068#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
20070#[doc = "## Safety"]
20071#[doc = "  * Neon instrinsic unsafe"]
20072#[inline]
20073#[target_feature(enable = "neon")]
20074#[cfg(not(target_arch = "arm"))]
20075#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20076#[cfg_attr(test, assert_instr(ld2r))]
20077pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
20078    unsafe extern "unadjusted" {
20079        #[cfg_attr(
20080            any(target_arch = "aarch64", target_arch = "arm64ec"),
20081            link_name = "llvm.aarch64.neon.ld2r.v1i64.p0"
20082        )]
20083        fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t;
20084    }
20085    _vld2_dup_s64(a as _)
20086}
20087#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
20089#[doc = "## Safety"]
20090#[doc = "  * Neon instrinsic unsafe"]
20091#[inline]
20092#[target_feature(enable = "neon")]
20093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20095#[cfg_attr(
20096    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20097    assert_instr(ld2r)
20098)]
20099#[cfg_attr(
20100    not(target_arch = "arm"),
20101    stable(feature = "neon_intrinsics", since = "1.59.0")
20102)]
20103#[cfg_attr(
20104    target_arch = "arm",
20105    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20106)]
20107pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
20108    transmute(vld2_dup_s64(transmute(a)))
20109}
20110#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20112#[doc = "## Safety"]
20113#[doc = "  * Neon instrinsic unsafe"]
20114#[inline]
20115#[cfg(target_endian = "little")]
20116#[target_feature(enable = "neon")]
20117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20119#[cfg_attr(
20120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20121    assert_instr(ld2r)
20122)]
20123#[cfg_attr(
20124    not(target_arch = "arm"),
20125    stable(feature = "neon_intrinsics", since = "1.59.0")
20126)]
20127#[cfg_attr(
20128    target_arch = "arm",
20129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20130)]
20131pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20132    transmute(vld2_dup_s8(transmute(a)))
20133}
20134#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20136#[doc = "## Safety"]
20137#[doc = "  * Neon instrinsic unsafe"]
20138#[inline]
20139#[cfg(target_endian = "big")]
20140#[target_feature(enable = "neon")]
20141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20143#[cfg_attr(
20144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20145    assert_instr(ld2r)
20146)]
20147#[cfg_attr(
20148    not(target_arch = "arm"),
20149    stable(feature = "neon_intrinsics", since = "1.59.0")
20150)]
20151#[cfg_attr(
20152    target_arch = "arm",
20153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20154)]
20155pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20156    let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20157    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20158    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20159    ret_val
20160}
20161#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20163#[doc = "## Safety"]
20164#[doc = "  * Neon instrinsic unsafe"]
20165#[inline]
20166#[cfg(target_endian = "little")]
20167#[target_feature(enable = "neon")]
20168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20170#[cfg_attr(
20171    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20172    assert_instr(ld2r)
20173)]
20174#[cfg_attr(
20175    not(target_arch = "arm"),
20176    stable(feature = "neon_intrinsics", since = "1.59.0")
20177)]
20178#[cfg_attr(
20179    target_arch = "arm",
20180    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20181)]
20182pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20183    transmute(vld2q_dup_s8(transmute(a)))
20184}
20185#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20187#[doc = "## Safety"]
20188#[doc = "  * Neon instrinsic unsafe"]
20189#[inline]
20190#[cfg(target_endian = "big")]
20191#[target_feature(enable = "neon")]
20192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20194#[cfg_attr(
20195    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20196    assert_instr(ld2r)
20197)]
20198#[cfg_attr(
20199    not(target_arch = "arm"),
20200    stable(feature = "neon_intrinsics", since = "1.59.0")
20201)]
20202#[cfg_attr(
20203    target_arch = "arm",
20204    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20205)]
20206pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20207    let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20208    ret_val.0 = unsafe {
20209        simd_shuffle!(
20210            ret_val.0,
20211            ret_val.0,
20212            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20213        )
20214    };
20215    ret_val.1 = unsafe {
20216        simd_shuffle!(
20217            ret_val.1,
20218            ret_val.1,
20219            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20220        )
20221    };
20222    ret_val
20223}
20224#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20226#[doc = "## Safety"]
20227#[doc = "  * Neon instrinsic unsafe"]
20228#[inline]
20229#[cfg(target_endian = "little")]
20230#[target_feature(enable = "neon")]
20231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20233#[cfg_attr(
20234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20235    assert_instr(ld2r)
20236)]
20237#[cfg_attr(
20238    not(target_arch = "arm"),
20239    stable(feature = "neon_intrinsics", since = "1.59.0")
20240)]
20241#[cfg_attr(
20242    target_arch = "arm",
20243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20244)]
20245pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20246    transmute(vld2_dup_s16(transmute(a)))
20247}
20248#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20250#[doc = "## Safety"]
20251#[doc = "  * Neon instrinsic unsafe"]
20252#[inline]
20253#[cfg(target_endian = "big")]
20254#[target_feature(enable = "neon")]
20255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20257#[cfg_attr(
20258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20259    assert_instr(ld2r)
20260)]
20261#[cfg_attr(
20262    not(target_arch = "arm"),
20263    stable(feature = "neon_intrinsics", since = "1.59.0")
20264)]
20265#[cfg_attr(
20266    target_arch = "arm",
20267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20268)]
20269pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20270    let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20271    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20272    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20273    ret_val
20274}
20275#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20277#[doc = "## Safety"]
20278#[doc = "  * Neon instrinsic unsafe"]
20279#[inline]
20280#[cfg(target_endian = "little")]
20281#[target_feature(enable = "neon")]
20282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20284#[cfg_attr(
20285    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20286    assert_instr(ld2r)
20287)]
20288#[cfg_attr(
20289    not(target_arch = "arm"),
20290    stable(feature = "neon_intrinsics", since = "1.59.0")
20291)]
20292#[cfg_attr(
20293    target_arch = "arm",
20294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20295)]
20296pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20297    transmute(vld2q_dup_s16(transmute(a)))
20298}
20299#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20301#[doc = "## Safety"]
20302#[doc = "  * Neon instrinsic unsafe"]
20303#[inline]
20304#[cfg(target_endian = "big")]
20305#[target_feature(enable = "neon")]
20306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20308#[cfg_attr(
20309    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20310    assert_instr(ld2r)
20311)]
20312#[cfg_attr(
20313    not(target_arch = "arm"),
20314    stable(feature = "neon_intrinsics", since = "1.59.0")
20315)]
20316#[cfg_attr(
20317    target_arch = "arm",
20318    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20319)]
20320pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20321    let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20322    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20323    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20324    ret_val
20325}
20326#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20328#[doc = "## Safety"]
20329#[doc = "  * Neon instrinsic unsafe"]
20330#[inline]
20331#[cfg(target_endian = "little")]
20332#[target_feature(enable = "neon")]
20333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20335#[cfg_attr(
20336    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20337    assert_instr(ld2r)
20338)]
20339#[cfg_attr(
20340    not(target_arch = "arm"),
20341    stable(feature = "neon_intrinsics", since = "1.59.0")
20342)]
20343#[cfg_attr(
20344    target_arch = "arm",
20345    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20346)]
20347pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20348    transmute(vld2_dup_s32(transmute(a)))
20349}
20350#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20352#[doc = "## Safety"]
20353#[doc = "  * Neon instrinsic unsafe"]
20354#[inline]
20355#[cfg(target_endian = "big")]
20356#[target_feature(enable = "neon")]
20357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20359#[cfg_attr(
20360    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20361    assert_instr(ld2r)
20362)]
20363#[cfg_attr(
20364    not(target_arch = "arm"),
20365    stable(feature = "neon_intrinsics", since = "1.59.0")
20366)]
20367#[cfg_attr(
20368    target_arch = "arm",
20369    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20370)]
20371pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20372    let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
20373    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
20374    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
20375    ret_val
20376}
20377#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20379#[doc = "## Safety"]
20380#[doc = "  * Neon instrinsic unsafe"]
20381#[inline]
20382#[cfg(target_endian = "little")]
20383#[target_feature(enable = "neon")]
20384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20386#[cfg_attr(
20387    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20388    assert_instr(ld2r)
20389)]
20390#[cfg_attr(
20391    not(target_arch = "arm"),
20392    stable(feature = "neon_intrinsics", since = "1.59.0")
20393)]
20394#[cfg_attr(
20395    target_arch = "arm",
20396    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20397)]
20398pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20399    transmute(vld2q_dup_s32(transmute(a)))
20400}
20401#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20403#[doc = "## Safety"]
20404#[doc = "  * Neon instrinsic unsafe"]
20405#[inline]
20406#[cfg(target_endian = "big")]
20407#[target_feature(enable = "neon")]
20408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20410#[cfg_attr(
20411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20412    assert_instr(ld2r)
20413)]
20414#[cfg_attr(
20415    not(target_arch = "arm"),
20416    stable(feature = "neon_intrinsics", since = "1.59.0")
20417)]
20418#[cfg_attr(
20419    target_arch = "arm",
20420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20421)]
20422pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20423    let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
20424    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20425    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20426    ret_val
20427}
20428#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20430#[doc = "## Safety"]
20431#[doc = "  * Neon instrinsic unsafe"]
20432#[inline]
20433#[cfg(target_endian = "little")]
20434#[target_feature(enable = "neon")]
20435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20437#[cfg_attr(
20438    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20439    assert_instr(ld2r)
20440)]
20441#[cfg_attr(
20442    not(target_arch = "arm"),
20443    stable(feature = "neon_intrinsics", since = "1.59.0")
20444)]
20445#[cfg_attr(
20446    target_arch = "arm",
20447    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20448)]
20449pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20450    transmute(vld2_dup_s8(transmute(a)))
20451}
20452#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20454#[doc = "## Safety"]
20455#[doc = "  * Neon instrinsic unsafe"]
20456#[inline]
20457#[cfg(target_endian = "big")]
20458#[target_feature(enable = "neon")]
20459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20461#[cfg_attr(
20462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20463    assert_instr(ld2r)
20464)]
20465#[cfg_attr(
20466    not(target_arch = "arm"),
20467    stable(feature = "neon_intrinsics", since = "1.59.0")
20468)]
20469#[cfg_attr(
20470    target_arch = "arm",
20471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20472)]
20473pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20474    let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20475    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20476    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20477    ret_val
20478}
20479#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20481#[doc = "## Safety"]
20482#[doc = "  * Neon instrinsic unsafe"]
20483#[inline]
20484#[cfg(target_endian = "little")]
20485#[target_feature(enable = "neon")]
20486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20488#[cfg_attr(
20489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20490    assert_instr(ld2r)
20491)]
20492#[cfg_attr(
20493    not(target_arch = "arm"),
20494    stable(feature = "neon_intrinsics", since = "1.59.0")
20495)]
20496#[cfg_attr(
20497    target_arch = "arm",
20498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20499)]
20500pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20501    transmute(vld2q_dup_s8(transmute(a)))
20502}
20503#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20505#[doc = "## Safety"]
20506#[doc = "  * Neon instrinsic unsafe"]
20507#[inline]
20508#[cfg(target_endian = "big")]
20509#[target_feature(enable = "neon")]
20510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20511#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20512#[cfg_attr(
20513    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20514    assert_instr(ld2r)
20515)]
20516#[cfg_attr(
20517    not(target_arch = "arm"),
20518    stable(feature = "neon_intrinsics", since = "1.59.0")
20519)]
20520#[cfg_attr(
20521    target_arch = "arm",
20522    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20523)]
20524pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20525    let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20526    ret_val.0 = unsafe {
20527        simd_shuffle!(
20528            ret_val.0,
20529            ret_val.0,
20530            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20531        )
20532    };
20533    ret_val.1 = unsafe {
20534        simd_shuffle!(
20535            ret_val.1,
20536            ret_val.1,
20537            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20538        )
20539    };
20540    ret_val
20541}
20542#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20544#[doc = "## Safety"]
20545#[doc = "  * Neon instrinsic unsafe"]
20546#[inline]
20547#[cfg(target_endian = "little")]
20548#[target_feature(enable = "neon")]
20549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20551#[cfg_attr(
20552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20553    assert_instr(ld2r)
20554)]
20555#[cfg_attr(
20556    not(target_arch = "arm"),
20557    stable(feature = "neon_intrinsics", since = "1.59.0")
20558)]
20559#[cfg_attr(
20560    target_arch = "arm",
20561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20562)]
20563pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20564    transmute(vld2_dup_s16(transmute(a)))
20565}
20566#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20568#[doc = "## Safety"]
20569#[doc = "  * Neon instrinsic unsafe"]
20570#[inline]
20571#[cfg(target_endian = "big")]
20572#[target_feature(enable = "neon")]
20573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20575#[cfg_attr(
20576    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20577    assert_instr(ld2r)
20578)]
20579#[cfg_attr(
20580    not(target_arch = "arm"),
20581    stable(feature = "neon_intrinsics", since = "1.59.0")
20582)]
20583#[cfg_attr(
20584    target_arch = "arm",
20585    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20586)]
20587pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20588    let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20589    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20590    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20591    ret_val
20592}
20593#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20595#[doc = "## Safety"]
20596#[doc = "  * Neon instrinsic unsafe"]
20597#[inline]
20598#[cfg(target_endian = "little")]
20599#[target_feature(enable = "neon")]
20600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20602#[cfg_attr(
20603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20604    assert_instr(ld2r)
20605)]
20606#[cfg_attr(
20607    not(target_arch = "arm"),
20608    stable(feature = "neon_intrinsics", since = "1.59.0")
20609)]
20610#[cfg_attr(
20611    target_arch = "arm",
20612    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20613)]
20614pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20615    transmute(vld2q_dup_s16(transmute(a)))
20616}
20617#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20619#[doc = "## Safety"]
20620#[doc = "  * Neon instrinsic unsafe"]
20621#[inline]
20622#[cfg(target_endian = "big")]
20623#[target_feature(enable = "neon")]
20624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20626#[cfg_attr(
20627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20628    assert_instr(ld2r)
20629)]
20630#[cfg_attr(
20631    not(target_arch = "arm"),
20632    stable(feature = "neon_intrinsics", since = "1.59.0")
20633)]
20634#[cfg_attr(
20635    target_arch = "arm",
20636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20637)]
20638pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20639    let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20640    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20641    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20642    ret_val
20643}
20644#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20646#[doc = "## Safety"]
20647#[doc = "  * Neon instrinsic unsafe"]
20648#[inline]
20649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20650#[cfg(target_arch = "arm")]
20651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20652#[target_feature(enable = "neon,fp16")]
20653#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20654pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20655    unsafe extern "unadjusted" {
20656        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0f16")]
20657        fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
20658    }
20659    _vld2_f16(a as _, 2)
20660}
20661#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20663#[doc = "## Safety"]
20664#[doc = "  * Neon instrinsic unsafe"]
20665#[inline]
20666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20667#[cfg(target_arch = "arm")]
20668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20669#[target_feature(enable = "neon,fp16")]
20670#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20671pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20672    unsafe extern "unadjusted" {
20673        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0f16")]
20674        fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
20675    }
20676    _vld2q_f16(a as _, 2)
20677}
20678#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20680#[doc = "## Safety"]
20681#[doc = "  * Neon instrinsic unsafe"]
20682#[inline]
20683#[cfg(not(target_arch = "arm"))]
20684#[cfg_attr(
20685    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20686    assert_instr(ld2)
20687)]
20688#[target_feature(enable = "neon,fp16")]
20689#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20690pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20691    unsafe extern "unadjusted" {
20692        #[cfg_attr(
20693            any(target_arch = "aarch64", target_arch = "arm64ec"),
20694            link_name = "llvm.aarch64.neon.ld2.v4f16.p0f16"
20695        )]
20696        fn _vld2_f16(ptr: *const f16) -> float16x4x2_t;
20697    }
20698    _vld2_f16(a as _)
20699}
20700#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20702#[doc = "## Safety"]
20703#[doc = "  * Neon instrinsic unsafe"]
20704#[inline]
20705#[cfg(not(target_arch = "arm"))]
20706#[cfg_attr(
20707    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20708    assert_instr(ld2)
20709)]
20710#[target_feature(enable = "neon,fp16")]
20711#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20712pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20713    unsafe extern "unadjusted" {
20714        #[cfg_attr(
20715            any(target_arch = "aarch64", target_arch = "arm64ec"),
20716            link_name = "llvm.aarch64.neon.ld2.v8f16.p0f16"
20717        )]
20718        fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t;
20719    }
20720    _vld2q_f16(a as _)
20721}
20722#[doc = "Load multiple 2-element structures to two registers"]
20723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20724#[doc = "## Safety"]
20725#[doc = "  * Neon instrinsic unsafe"]
20726#[inline]
20727#[target_feature(enable = "neon,v7")]
20728#[cfg(target_arch = "arm")]
20729#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20730#[cfg_attr(test, assert_instr(vld2))]
20731pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20732    unsafe extern "unadjusted" {
20733        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")]
20734        fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
20735    }
20736    _vld2_f32(a as *const i8, 4)
20737}
20738#[doc = "Load multiple 2-element structures to two registers"]
20739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20740#[doc = "## Safety"]
20741#[doc = "  * Neon instrinsic unsafe"]
20742#[inline]
20743#[target_feature(enable = "neon,v7")]
20744#[cfg(target_arch = "arm")]
20745#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20746#[cfg_attr(test, assert_instr(vld2))]
20747pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20748    unsafe extern "unadjusted" {
20749        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")]
20750        fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
20751    }
20752    _vld2q_f32(a as *const i8, 4)
20753}
20754#[doc = "Load multiple 2-element structures to two registers"]
20755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20756#[doc = "## Safety"]
20757#[doc = "  * Neon instrinsic unsafe"]
20758#[inline]
20759#[target_feature(enable = "neon,v7")]
20760#[cfg(target_arch = "arm")]
20761#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20762#[cfg_attr(test, assert_instr(vld2))]
20763pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20764    unsafe extern "unadjusted" {
20765        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")]
20766        fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
20767    }
20768    _vld2_s8(a as *const i8, 1)
20769}
20770#[doc = "Load multiple 2-element structures to two registers"]
20771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20772#[doc = "## Safety"]
20773#[doc = "  * Neon instrinsic unsafe"]
20774#[inline]
20775#[target_feature(enable = "neon,v7")]
20776#[cfg(target_arch = "arm")]
20777#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20778#[cfg_attr(test, assert_instr(vld2))]
20779pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20780    unsafe extern "unadjusted" {
20781        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")]
20782        fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
20783    }
20784    _vld2q_s8(a as *const i8, 1)
20785}
20786#[doc = "Load multiple 2-element structures to two registers"]
20787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20788#[doc = "## Safety"]
20789#[doc = "  * Neon instrinsic unsafe"]
20790#[inline]
20791#[target_feature(enable = "neon,v7")]
20792#[cfg(target_arch = "arm")]
20793#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20794#[cfg_attr(test, assert_instr(vld2))]
20795pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20796    unsafe extern "unadjusted" {
20797        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")]
20798        fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
20799    }
20800    _vld2_s16(a as *const i8, 2)
20801}
20802#[doc = "Load multiple 2-element structures to two registers"]
20803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20804#[doc = "## Safety"]
20805#[doc = "  * Neon instrinsic unsafe"]
20806#[inline]
20807#[target_feature(enable = "neon,v7")]
20808#[cfg(target_arch = "arm")]
20809#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20810#[cfg_attr(test, assert_instr(vld2))]
20811pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20812    unsafe extern "unadjusted" {
20813        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")]
20814        fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
20815    }
20816    _vld2q_s16(a as *const i8, 2)
20817}
20818#[doc = "Load multiple 2-element structures to two registers"]
20819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20820#[doc = "## Safety"]
20821#[doc = "  * Neon instrinsic unsafe"]
20822#[inline]
20823#[target_feature(enable = "neon,v7")]
20824#[cfg(target_arch = "arm")]
20825#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20826#[cfg_attr(test, assert_instr(vld2))]
20827pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20828    unsafe extern "unadjusted" {
20829        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")]
20830        fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
20831    }
20832    _vld2_s32(a as *const i8, 4)
20833}
20834#[doc = "Load multiple 2-element structures to two registers"]
20835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20836#[doc = "## Safety"]
20837#[doc = "  * Neon instrinsic unsafe"]
20838#[inline]
20839#[target_feature(enable = "neon,v7")]
20840#[cfg(target_arch = "arm")]
20841#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20842#[cfg_attr(test, assert_instr(vld2))]
20843pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20844    unsafe extern "unadjusted" {
20845        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")]
20846        fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
20847    }
20848    _vld2q_s32(a as *const i8, 4)
20849}
20850#[doc = "Load multiple 2-element structures to two registers"]
20851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20852#[doc = "## Safety"]
20853#[doc = "  * Neon instrinsic unsafe"]
20854#[inline]
20855#[target_feature(enable = "neon")]
20856#[cfg(not(target_arch = "arm"))]
20857#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20858#[cfg_attr(test, assert_instr(ld2))]
20859pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20860    unsafe extern "unadjusted" {
20861        #[cfg_attr(
20862            any(target_arch = "aarch64", target_arch = "arm64ec"),
20863            link_name = "llvm.aarch64.neon.ld2.v2f32.p0"
20864        )]
20865        fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t;
20866    }
20867    _vld2_f32(a as _)
20868}
20869#[doc = "Load multiple 2-element structures to two registers"]
20870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20871#[doc = "## Safety"]
20872#[doc = "  * Neon instrinsic unsafe"]
20873#[inline]
20874#[target_feature(enable = "neon")]
20875#[cfg(not(target_arch = "arm"))]
20876#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20877#[cfg_attr(test, assert_instr(ld2))]
20878pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20879    unsafe extern "unadjusted" {
20880        #[cfg_attr(
20881            any(target_arch = "aarch64", target_arch = "arm64ec"),
20882            link_name = "llvm.aarch64.neon.ld2.v4f32.p0"
20883        )]
20884        fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t;
20885    }
20886    _vld2q_f32(a as _)
20887}
20888#[doc = "Load multiple 2-element structures to two registers"]
20889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20890#[doc = "## Safety"]
20891#[doc = "  * Neon instrinsic unsafe"]
20892#[inline]
20893#[target_feature(enable = "neon")]
20894#[cfg(not(target_arch = "arm"))]
20895#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20896#[cfg_attr(test, assert_instr(ld2))]
20897pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20898    unsafe extern "unadjusted" {
20899        #[cfg_attr(
20900            any(target_arch = "aarch64", target_arch = "arm64ec"),
20901            link_name = "llvm.aarch64.neon.ld2.v8i8.p0"
20902        )]
20903        fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t;
20904    }
20905    _vld2_s8(a as _)
20906}
20907#[doc = "Load multiple 2-element structures to two registers"]
20908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20909#[doc = "## Safety"]
20910#[doc = "  * Neon instrinsic unsafe"]
20911#[inline]
20912#[target_feature(enable = "neon")]
20913#[cfg(not(target_arch = "arm"))]
20914#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20915#[cfg_attr(test, assert_instr(ld2))]
20916pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20917    unsafe extern "unadjusted" {
20918        #[cfg_attr(
20919            any(target_arch = "aarch64", target_arch = "arm64ec"),
20920            link_name = "llvm.aarch64.neon.ld2.v16i8.p0"
20921        )]
20922        fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t;
20923    }
20924    _vld2q_s8(a as _)
20925}
20926#[doc = "Load multiple 2-element structures to two registers"]
20927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20928#[doc = "## Safety"]
20929#[doc = "  * Neon instrinsic unsafe"]
20930#[inline]
20931#[target_feature(enable = "neon")]
20932#[cfg(not(target_arch = "arm"))]
20933#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20934#[cfg_attr(test, assert_instr(ld2))]
20935pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20936    unsafe extern "unadjusted" {
20937        #[cfg_attr(
20938            any(target_arch = "aarch64", target_arch = "arm64ec"),
20939            link_name = "llvm.aarch64.neon.ld2.v4i16.p0"
20940        )]
20941        fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t;
20942    }
20943    _vld2_s16(a as _)
20944}
20945#[doc = "Load multiple 2-element structures to two registers"]
20946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20947#[doc = "## Safety"]
20948#[doc = "  * Neon instrinsic unsafe"]
20949#[inline]
20950#[target_feature(enable = "neon")]
20951#[cfg(not(target_arch = "arm"))]
20952#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20953#[cfg_attr(test, assert_instr(ld2))]
20954pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20955    unsafe extern "unadjusted" {
20956        #[cfg_attr(
20957            any(target_arch = "aarch64", target_arch = "arm64ec"),
20958            link_name = "llvm.aarch64.neon.ld2.v8i16.p0"
20959        )]
20960        fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t;
20961    }
20962    _vld2q_s16(a as _)
20963}
20964#[doc = "Load multiple 2-element structures to two registers"]
20965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20966#[doc = "## Safety"]
20967#[doc = "  * Neon instrinsic unsafe"]
20968#[inline]
20969#[target_feature(enable = "neon")]
20970#[cfg(not(target_arch = "arm"))]
20971#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20972#[cfg_attr(test, assert_instr(ld2))]
20973pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20974    unsafe extern "unadjusted" {
20975        #[cfg_attr(
20976            any(target_arch = "aarch64", target_arch = "arm64ec"),
20977            link_name = "llvm.aarch64.neon.ld2.v2i32.p0"
20978        )]
20979        fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t;
20980    }
20981    _vld2_s32(a as _)
20982}
20983#[doc = "Load multiple 2-element structures to two registers"]
20984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20985#[doc = "## Safety"]
20986#[doc = "  * Neon instrinsic unsafe"]
20987#[inline]
20988#[target_feature(enable = "neon")]
20989#[cfg(not(target_arch = "arm"))]
20990#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20991#[cfg_attr(test, assert_instr(ld2))]
20992pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20993    unsafe extern "unadjusted" {
20994        #[cfg_attr(
20995            any(target_arch = "aarch64", target_arch = "arm64ec"),
20996            link_name = "llvm.aarch64.neon.ld2.v4i32.p0"
20997        )]
20998        fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t;
20999    }
21000    _vld2q_s32(a as _)
21001}
21002#[doc = "Load multiple 2-element structures to two registers"]
21003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
21004#[doc = "## Safety"]
21005#[doc = "  * Neon instrinsic unsafe"]
21006#[inline]
21007#[target_feature(enable = "neon,v7")]
21008#[cfg(target_arch = "arm")]
21009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21010#[rustc_legacy_const_generics(2)]
21011#[target_feature(enable = "neon,fp16")]
21012#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21013pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
21014    static_assert_uimm_bits!(LANE, 2);
21015    unsafe extern "unadjusted" {
21016        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")]
21017        fn _vld2_lane_f16(
21018            ptr: *const f16,
21019            a: float16x4_t,
21020            b: float16x4_t,
21021            n: i32,
21022            size: i32,
21023        ) -> float16x4x2_t;
21024    }
21025    _vld2_lane_f16(a as _, b.0, b.1, LANE, 2)
21026}
21027#[doc = "Load multiple 2-element structures to two registers"]
21028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
21029#[doc = "## Safety"]
21030#[doc = "  * Neon instrinsic unsafe"]
21031#[inline]
21032#[target_feature(enable = "neon,v7")]
21033#[cfg(target_arch = "arm")]
21034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21035#[rustc_legacy_const_generics(2)]
21036#[target_feature(enable = "neon,fp16")]
21037#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21038pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
21039    static_assert_uimm_bits!(LANE, 3);
21040    unsafe extern "unadjusted" {
21041        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")]
21042        fn _vld2q_lane_f16(
21043            ptr: *const f16,
21044            a: float16x8_t,
21045            b: float16x8_t,
21046            n: i32,
21047            size: i32,
21048        ) -> float16x8x2_t;
21049    }
21050    _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2)
21051}
21052#[doc = "Load multiple 2-element structures to two registers"]
21053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
21054#[doc = "## Safety"]
21055#[doc = "  * Neon instrinsic unsafe"]
21056#[inline]
21057#[cfg(not(target_arch = "arm"))]
21058#[cfg_attr(
21059    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21060    assert_instr(ld2, LANE = 0)
21061)]
21062#[rustc_legacy_const_generics(2)]
21063#[target_feature(enable = "neon,fp16")]
21064#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21065pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
21066    static_assert_uimm_bits!(LANE, 2);
21067    unsafe extern "unadjusted" {
21068        #[cfg_attr(
21069            any(target_arch = "aarch64", target_arch = "arm64ec"),
21070            link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0"
21071        )]
21072        fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16)
21073            -> float16x4x2_t;
21074    }
21075    _vld2_lane_f16(b.0, b.1, LANE as i64, a as _)
21076}
21077#[doc = "Load multiple 2-element structures to two registers"]
21078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
21079#[doc = "## Safety"]
21080#[doc = "  * Neon instrinsic unsafe"]
21081#[inline]
21082#[cfg(not(target_arch = "arm"))]
21083#[cfg_attr(
21084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21085    assert_instr(ld2, LANE = 0)
21086)]
21087#[rustc_legacy_const_generics(2)]
21088#[target_feature(enable = "neon,fp16")]
21089#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21090pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
21091    static_assert_uimm_bits!(LANE, 3);
21092    unsafe extern "unadjusted" {
21093        #[cfg_attr(
21094            any(target_arch = "aarch64", target_arch = "arm64ec"),
21095            link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0"
21096        )]
21097        fn _vld2q_lane_f16(
21098            a: float16x8_t,
21099            b: float16x8_t,
21100            n: i64,
21101            ptr: *const f16,
21102        ) -> float16x8x2_t;
21103    }
21104    _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _)
21105}
21106#[doc = "Load multiple 2-element structures to two registers"]
21107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21108#[doc = "## Safety"]
21109#[doc = "  * Neon instrinsic unsafe"]
21110#[inline]
21111#[target_feature(enable = "neon")]
21112#[cfg(not(target_arch = "arm"))]
21113#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21114#[rustc_legacy_const_generics(2)]
21115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21116pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21117    static_assert_uimm_bits!(LANE, 2);
21118    unsafe extern "unadjusted" {
21119        #[cfg_attr(
21120            any(target_arch = "aarch64", target_arch = "arm64ec"),
21121            link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0"
21122        )]
21123        fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t;
21124    }
21125    _vld2_lane_f32(b.0, b.1, LANE as i64, a as _)
21126}
21127#[doc = "Load multiple 2-element structures to two registers"]
21128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21129#[doc = "## Safety"]
21130#[doc = "  * Neon instrinsic unsafe"]
21131#[inline]
21132#[target_feature(enable = "neon")]
21133#[cfg(not(target_arch = "arm"))]
21134#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21135#[rustc_legacy_const_generics(2)]
21136#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21137pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21138    static_assert_uimm_bits!(LANE, 2);
21139    unsafe extern "unadjusted" {
21140        #[cfg_attr(
21141            any(target_arch = "aarch64", target_arch = "arm64ec"),
21142            link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0"
21143        )]
21144        fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8)
21145            -> float32x4x2_t;
21146    }
21147    _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _)
21148}
21149#[doc = "Load multiple 2-element structures to two registers"]
21150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21151#[doc = "## Safety"]
21152#[doc = "  * Neon instrinsic unsafe"]
21153#[inline]
21154#[target_feature(enable = "neon")]
21155#[cfg(not(target_arch = "arm"))]
21156#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21157#[rustc_legacy_const_generics(2)]
21158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21159pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21160    static_assert_uimm_bits!(LANE, 3);
21161    unsafe extern "unadjusted" {
21162        #[cfg_attr(
21163            any(target_arch = "aarch64", target_arch = "arm64ec"),
21164            link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0"
21165        )]
21166        fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t;
21167    }
21168    _vld2_lane_s8(b.0, b.1, LANE as i64, a as _)
21169}
21170#[doc = "Load multiple 2-element structures to two registers"]
21171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21172#[doc = "## Safety"]
21173#[doc = "  * Neon instrinsic unsafe"]
21174#[inline]
21175#[target_feature(enable = "neon")]
21176#[cfg(not(target_arch = "arm"))]
21177#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21178#[rustc_legacy_const_generics(2)]
21179#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21180pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21181    static_assert_uimm_bits!(LANE, 2);
21182    unsafe extern "unadjusted" {
21183        #[cfg_attr(
21184            any(target_arch = "aarch64", target_arch = "arm64ec"),
21185            link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0"
21186        )]
21187        fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t;
21188    }
21189    _vld2_lane_s16(b.0, b.1, LANE as i64, a as _)
21190}
21191#[doc = "Load multiple 2-element structures to two registers"]
21192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21193#[doc = "## Safety"]
21194#[doc = "  * Neon instrinsic unsafe"]
21195#[inline]
21196#[target_feature(enable = "neon")]
21197#[cfg(not(target_arch = "arm"))]
21198#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21199#[rustc_legacy_const_generics(2)]
21200#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21201pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21202    static_assert_uimm_bits!(LANE, 3);
21203    unsafe extern "unadjusted" {
21204        #[cfg_attr(
21205            any(target_arch = "aarch64", target_arch = "arm64ec"),
21206            link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0"
21207        )]
21208        fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t;
21209    }
21210    _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _)
21211}
21212#[doc = "Load multiple 2-element structures to two registers"]
21213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21214#[doc = "## Safety"]
21215#[doc = "  * Neon instrinsic unsafe"]
21216#[inline]
21217#[target_feature(enable = "neon")]
21218#[cfg(not(target_arch = "arm"))]
21219#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21220#[rustc_legacy_const_generics(2)]
21221#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21222pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21223    static_assert_uimm_bits!(LANE, 1);
21224    unsafe extern "unadjusted" {
21225        #[cfg_attr(
21226            any(target_arch = "aarch64", target_arch = "arm64ec"),
21227            link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0"
21228        )]
21229        fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t;
21230    }
21231    _vld2_lane_s32(b.0, b.1, LANE as i64, a as _)
21232}
21233#[doc = "Load multiple 2-element structures to two registers"]
21234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21235#[doc = "## Safety"]
21236#[doc = "  * Neon instrinsic unsafe"]
21237#[inline]
21238#[target_feature(enable = "neon")]
21239#[cfg(not(target_arch = "arm"))]
21240#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21241#[rustc_legacy_const_generics(2)]
21242#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21243pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21244    static_assert_uimm_bits!(LANE, 2);
21245    unsafe extern "unadjusted" {
21246        #[cfg_attr(
21247            any(target_arch = "aarch64", target_arch = "arm64ec"),
21248            link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0"
21249        )]
21250        fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t;
21251    }
21252    _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _)
21253}
21254#[doc = "Load multiple 2-element structures to two registers"]
21255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21256#[doc = "## Safety"]
21257#[doc = "  * Neon instrinsic unsafe"]
21258#[inline]
21259#[target_feature(enable = "neon,v7")]
21260#[cfg(target_arch = "arm")]
21261#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21262#[rustc_legacy_const_generics(2)]
21263#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21264pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21265    static_assert_uimm_bits!(LANE, 1);
21266    unsafe extern "unadjusted" {
21267        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")]
21268        fn _vld2_lane_f32(
21269            ptr: *const i8,
21270            a: float32x2_t,
21271            b: float32x2_t,
21272            n: i32,
21273            size: i32,
21274        ) -> float32x2x2_t;
21275    }
21276    _vld2_lane_f32(a as _, b.0, b.1, LANE, 4)
21277}
21278#[doc = "Load multiple 2-element structures to two registers"]
21279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21280#[doc = "## Safety"]
21281#[doc = "  * Neon instrinsic unsafe"]
21282#[inline]
21283#[target_feature(enable = "neon,v7")]
21284#[cfg(target_arch = "arm")]
21285#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21286#[rustc_legacy_const_generics(2)]
21287#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21288pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21289    static_assert_uimm_bits!(LANE, 2);
21290    unsafe extern "unadjusted" {
21291        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")]
21292        fn _vld2q_lane_f32(
21293            ptr: *const i8,
21294            a: float32x4_t,
21295            b: float32x4_t,
21296            n: i32,
21297            size: i32,
21298        ) -> float32x4x2_t;
21299    }
21300    _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4)
21301}
21302#[doc = "Load multiple 2-element structures to two registers"]
21303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21304#[doc = "## Safety"]
21305#[doc = "  * Neon instrinsic unsafe"]
21306#[inline]
21307#[target_feature(enable = "neon,v7")]
21308#[cfg(target_arch = "arm")]
21309#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21310#[rustc_legacy_const_generics(2)]
21311#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21312pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21313    static_assert_uimm_bits!(LANE, 3);
21314    unsafe extern "unadjusted" {
21315        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")]
21316        fn _vld2q_lane_s16(
21317            ptr: *const i8,
21318            a: int16x8_t,
21319            b: int16x8_t,
21320            n: i32,
21321            size: i32,
21322        ) -> int16x8x2_t;
21323    }
21324    _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2)
21325}
21326#[doc = "Load multiple 2-element structures to two registers"]
21327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21328#[doc = "## Safety"]
21329#[doc = "  * Neon instrinsic unsafe"]
21330#[inline]
21331#[target_feature(enable = "neon,v7")]
21332#[cfg(target_arch = "arm")]
21333#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21334#[rustc_legacy_const_generics(2)]
21335#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21336pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21337    static_assert_uimm_bits!(LANE, 2);
21338    unsafe extern "unadjusted" {
21339        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")]
21340        fn _vld2q_lane_s32(
21341            ptr: *const i8,
21342            a: int32x4_t,
21343            b: int32x4_t,
21344            n: i32,
21345            size: i32,
21346        ) -> int32x4x2_t;
21347    }
21348    _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4)
21349}
21350#[doc = "Load multiple 2-element structures to two registers"]
21351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21352#[doc = "## Safety"]
21353#[doc = "  * Neon instrinsic unsafe"]
21354#[inline]
21355#[target_feature(enable = "neon,v7")]
21356#[cfg(target_arch = "arm")]
21357#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21358#[rustc_legacy_const_generics(2)]
21359#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21360pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21361    static_assert_uimm_bits!(LANE, 3);
21362    unsafe extern "unadjusted" {
21363        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")]
21364        fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32)
21365            -> int8x8x2_t;
21366    }
21367    _vld2_lane_s8(a as _, b.0, b.1, LANE, 1)
21368}
21369#[doc = "Load multiple 2-element structures to two registers"]
21370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21371#[doc = "## Safety"]
21372#[doc = "  * Neon instrinsic unsafe"]
21373#[inline]
21374#[target_feature(enable = "neon,v7")]
21375#[cfg(target_arch = "arm")]
21376#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21377#[rustc_legacy_const_generics(2)]
21378#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21379pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21380    static_assert_uimm_bits!(LANE, 2);
21381    unsafe extern "unadjusted" {
21382        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")]
21383        fn _vld2_lane_s16(
21384            ptr: *const i8,
21385            a: int16x4_t,
21386            b: int16x4_t,
21387            n: i32,
21388            size: i32,
21389        ) -> int16x4x2_t;
21390    }
21391    _vld2_lane_s16(a as _, b.0, b.1, LANE, 2)
21392}
21393#[doc = "Load multiple 2-element structures to two registers"]
21394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21395#[doc = "## Safety"]
21396#[doc = "  * Neon instrinsic unsafe"]
21397#[inline]
21398#[target_feature(enable = "neon,v7")]
21399#[cfg(target_arch = "arm")]
21400#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21401#[rustc_legacy_const_generics(2)]
21402#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21403pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21404    static_assert_uimm_bits!(LANE, 1);
21405    unsafe extern "unadjusted" {
21406        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")]
21407        fn _vld2_lane_s32(
21408            ptr: *const i8,
21409            a: int32x2_t,
21410            b: int32x2_t,
21411            n: i32,
21412            size: i32,
21413        ) -> int32x2x2_t;
21414    }
21415    _vld2_lane_s32(a as _, b.0, b.1, LANE, 4)
21416}
21417#[doc = "Load multiple 2-element structures to two registers"]
21418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
21419#[doc = "## Safety"]
21420#[doc = "  * Neon instrinsic unsafe"]
21421#[inline]
21422#[target_feature(enable = "neon")]
21423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21425#[cfg_attr(
21426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21427    assert_instr(ld2, LANE = 0)
21428)]
21429#[rustc_legacy_const_generics(2)]
21430#[cfg_attr(
21431    not(target_arch = "arm"),
21432    stable(feature = "neon_intrinsics", since = "1.59.0")
21433)]
21434#[cfg_attr(
21435    target_arch = "arm",
21436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21437)]
21438pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t {
21439    static_assert_uimm_bits!(LANE, 3);
21440    transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21441}
21442#[doc = "Load multiple 2-element structures to two registers"]
21443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
21444#[doc = "## Safety"]
21445#[doc = "  * Neon instrinsic unsafe"]
21446#[inline]
21447#[target_feature(enable = "neon")]
21448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21450#[cfg_attr(
21451    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21452    assert_instr(ld2, LANE = 0)
21453)]
21454#[rustc_legacy_const_generics(2)]
21455#[cfg_attr(
21456    not(target_arch = "arm"),
21457    stable(feature = "neon_intrinsics", since = "1.59.0")
21458)]
21459#[cfg_attr(
21460    target_arch = "arm",
21461    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21462)]
21463pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t {
21464    static_assert_uimm_bits!(LANE, 2);
21465    transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21466}
21467#[doc = "Load multiple 2-element structures to two registers"]
21468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
21469#[doc = "## Safety"]
21470#[doc = "  * Neon instrinsic unsafe"]
21471#[inline]
21472#[target_feature(enable = "neon")]
21473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21475#[cfg_attr(
21476    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21477    assert_instr(ld2, LANE = 0)
21478)]
21479#[rustc_legacy_const_generics(2)]
21480#[cfg_attr(
21481    not(target_arch = "arm"),
21482    stable(feature = "neon_intrinsics", since = "1.59.0")
21483)]
21484#[cfg_attr(
21485    target_arch = "arm",
21486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21487)]
21488pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t {
21489    static_assert_uimm_bits!(LANE, 3);
21490    transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21491}
21492#[doc = "Load multiple 2-element structures to two registers"]
21493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
21494#[doc = "## Safety"]
21495#[doc = "  * Neon instrinsic unsafe"]
21496#[inline]
21497#[target_feature(enable = "neon")]
21498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21500#[cfg_attr(
21501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21502    assert_instr(ld2, LANE = 0)
21503)]
21504#[rustc_legacy_const_generics(2)]
21505#[cfg_attr(
21506    not(target_arch = "arm"),
21507    stable(feature = "neon_intrinsics", since = "1.59.0")
21508)]
21509#[cfg_attr(
21510    target_arch = "arm",
21511    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21512)]
21513pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t {
21514    static_assert_uimm_bits!(LANE, 1);
21515    transmute(vld2_lane_s32::<LANE>(transmute(a), transmute(b)))
21516}
21517#[doc = "Load multiple 2-element structures to two registers"]
21518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
21519#[doc = "## Safety"]
21520#[doc = "  * Neon instrinsic unsafe"]
21521#[inline]
21522#[target_feature(enable = "neon")]
21523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21525#[cfg_attr(
21526    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21527    assert_instr(ld2, LANE = 0)
21528)]
21529#[rustc_legacy_const_generics(2)]
21530#[cfg_attr(
21531    not(target_arch = "arm"),
21532    stable(feature = "neon_intrinsics", since = "1.59.0")
21533)]
21534#[cfg_attr(
21535    target_arch = "arm",
21536    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21537)]
21538pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t {
21539    static_assert_uimm_bits!(LANE, 2);
21540    transmute(vld2q_lane_s32::<LANE>(transmute(a), transmute(b)))
21541}
21542#[doc = "Load multiple 2-element structures to two registers"]
21543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
21544#[doc = "## Safety"]
21545#[doc = "  * Neon instrinsic unsafe"]
21546#[inline]
21547#[target_feature(enable = "neon")]
21548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21550#[cfg_attr(
21551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21552    assert_instr(ld2, LANE = 0)
21553)]
21554#[rustc_legacy_const_generics(2)]
21555#[cfg_attr(
21556    not(target_arch = "arm"),
21557    stable(feature = "neon_intrinsics", since = "1.59.0")
21558)]
21559#[cfg_attr(
21560    target_arch = "arm",
21561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21562)]
21563pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t {
21564    static_assert_uimm_bits!(LANE, 3);
21565    transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21566}
21567#[doc = "Load multiple 2-element structures to two registers"]
21568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
21569#[doc = "## Safety"]
21570#[doc = "  * Neon instrinsic unsafe"]
21571#[inline]
21572#[target_feature(enable = "neon")]
21573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21575#[cfg_attr(
21576    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21577    assert_instr(ld2, LANE = 0)
21578)]
21579#[rustc_legacy_const_generics(2)]
21580#[cfg_attr(
21581    not(target_arch = "arm"),
21582    stable(feature = "neon_intrinsics", since = "1.59.0")
21583)]
21584#[cfg_attr(
21585    target_arch = "arm",
21586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21587)]
21588pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t {
21589    static_assert_uimm_bits!(LANE, 2);
21590    transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21591}
21592#[doc = "Load multiple 2-element structures to two registers"]
21593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
21594#[doc = "## Safety"]
21595#[doc = "  * Neon instrinsic unsafe"]
21596#[inline]
21597#[target_feature(enable = "neon")]
21598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21600#[cfg_attr(
21601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21602    assert_instr(ld2, LANE = 0)
21603)]
21604#[rustc_legacy_const_generics(2)]
21605#[cfg_attr(
21606    not(target_arch = "arm"),
21607    stable(feature = "neon_intrinsics", since = "1.59.0")
21608)]
21609#[cfg_attr(
21610    target_arch = "arm",
21611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21612)]
21613pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t {
21614    static_assert_uimm_bits!(LANE, 3);
21615    transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21616}
21617#[doc = "Load multiple 2-element structures to two registers"]
21618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
21619#[doc = "## Safety"]
21620#[doc = "  * Neon instrinsic unsafe"]
21621#[inline]
21622#[target_feature(enable = "neon,aes")]
21623#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
21624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21625#[cfg_attr(
21626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21627    assert_instr(nop)
21628)]
21629#[cfg_attr(
21630    not(target_arch = "arm"),
21631    stable(feature = "neon_intrinsics", since = "1.59.0")
21632)]
21633#[cfg_attr(
21634    target_arch = "arm",
21635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21636)]
21637pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
21638    transmute(vld2_s64(transmute(a)))
21639}
21640#[doc = "Load multiple 2-element structures to two registers"]
21641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21642#[doc = "## Safety"]
21643#[doc = "  * Neon instrinsic unsafe"]
21644#[inline]
21645#[target_feature(enable = "neon,v7")]
21646#[cfg(target_arch = "arm")]
21647#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21648#[cfg_attr(test, assert_instr(nop))]
21649pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21650    unsafe extern "unadjusted" {
21651        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")]
21652        fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
21653    }
21654    _vld2_s64(a as *const i8, 8)
21655}
21656#[doc = "Load multiple 2-element structures to two registers"]
21657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21658#[doc = "## Safety"]
21659#[doc = "  * Neon instrinsic unsafe"]
21660#[inline]
21661#[target_feature(enable = "neon")]
21662#[cfg(not(target_arch = "arm"))]
21663#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21664#[cfg_attr(test, assert_instr(nop))]
21665pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21666    unsafe extern "unadjusted" {
21667        #[cfg_attr(
21668            any(target_arch = "aarch64", target_arch = "arm64ec"),
21669            link_name = "llvm.aarch64.neon.ld2.v1i64.p0"
21670        )]
21671        fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t;
21672    }
21673    _vld2_s64(a as _)
21674}
21675#[doc = "Load multiple 2-element structures to two registers"]
21676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
21677#[doc = "## Safety"]
21678#[doc = "  * Neon instrinsic unsafe"]
21679#[inline]
21680#[target_feature(enable = "neon")]
21681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21683#[cfg_attr(
21684    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21685    assert_instr(nop)
21686)]
21687#[cfg_attr(
21688    not(target_arch = "arm"),
21689    stable(feature = "neon_intrinsics", since = "1.59.0")
21690)]
21691#[cfg_attr(
21692    target_arch = "arm",
21693    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21694)]
21695pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
21696    transmute(vld2_s64(transmute(a)))
21697}
21698#[doc = "Load multiple 2-element structures to two registers"]
21699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21700#[doc = "## Safety"]
21701#[doc = "  * Neon instrinsic unsafe"]
21702#[inline]
21703#[cfg(target_endian = "little")]
21704#[target_feature(enable = "neon")]
21705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21707#[cfg_attr(
21708    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21709    assert_instr(ld2)
21710)]
21711#[cfg_attr(
21712    not(target_arch = "arm"),
21713    stable(feature = "neon_intrinsics", since = "1.59.0")
21714)]
21715#[cfg_attr(
21716    target_arch = "arm",
21717    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21718)]
21719pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21720    transmute(vld2_s8(transmute(a)))
21721}
21722#[doc = "Load multiple 2-element structures to two registers"]
21723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21724#[doc = "## Safety"]
21725#[doc = "  * Neon instrinsic unsafe"]
21726#[inline]
21727#[cfg(target_endian = "big")]
21728#[target_feature(enable = "neon")]
21729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21731#[cfg_attr(
21732    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21733    assert_instr(ld2)
21734)]
21735#[cfg_attr(
21736    not(target_arch = "arm"),
21737    stable(feature = "neon_intrinsics", since = "1.59.0")
21738)]
21739#[cfg_attr(
21740    target_arch = "arm",
21741    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21742)]
21743pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21744    let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
21745    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21746    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21747    ret_val
21748}
21749#[doc = "Load multiple 2-element structures to two registers"]
21750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21751#[doc = "## Safety"]
21752#[doc = "  * Neon instrinsic unsafe"]
21753#[inline]
21754#[cfg(target_endian = "little")]
21755#[target_feature(enable = "neon")]
21756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21758#[cfg_attr(
21759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21760    assert_instr(ld2)
21761)]
21762#[cfg_attr(
21763    not(target_arch = "arm"),
21764    stable(feature = "neon_intrinsics", since = "1.59.0")
21765)]
21766#[cfg_attr(
21767    target_arch = "arm",
21768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21769)]
21770pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21771    transmute(vld2q_s8(transmute(a)))
21772}
21773#[doc = "Load multiple 2-element structures to two registers"]
21774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21775#[doc = "## Safety"]
21776#[doc = "  * Neon instrinsic unsafe"]
21777#[inline]
21778#[cfg(target_endian = "big")]
21779#[target_feature(enable = "neon")]
21780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21782#[cfg_attr(
21783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21784    assert_instr(ld2)
21785)]
21786#[cfg_attr(
21787    not(target_arch = "arm"),
21788    stable(feature = "neon_intrinsics", since = "1.59.0")
21789)]
21790#[cfg_attr(
21791    target_arch = "arm",
21792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21793)]
21794pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21795    let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
21796    ret_val.0 = unsafe {
21797        simd_shuffle!(
21798            ret_val.0,
21799            ret_val.0,
21800            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21801        )
21802    };
21803    ret_val.1 = unsafe {
21804        simd_shuffle!(
21805            ret_val.1,
21806            ret_val.1,
21807            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21808        )
21809    };
21810    ret_val
21811}
21812#[doc = "Load multiple 2-element structures to two registers"]
21813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21814#[doc = "## Safety"]
21815#[doc = "  * Neon instrinsic unsafe"]
21816#[inline]
21817#[cfg(target_endian = "little")]
21818#[target_feature(enable = "neon")]
21819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21821#[cfg_attr(
21822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21823    assert_instr(ld2)
21824)]
21825#[cfg_attr(
21826    not(target_arch = "arm"),
21827    stable(feature = "neon_intrinsics", since = "1.59.0")
21828)]
21829#[cfg_attr(
21830    target_arch = "arm",
21831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21832)]
21833pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21834    transmute(vld2_s16(transmute(a)))
21835}
21836#[doc = "Load multiple 2-element structures to two registers"]
21837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21838#[doc = "## Safety"]
21839#[doc = "  * Neon instrinsic unsafe"]
21840#[inline]
21841#[cfg(target_endian = "big")]
21842#[target_feature(enable = "neon")]
21843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21845#[cfg_attr(
21846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21847    assert_instr(ld2)
21848)]
21849#[cfg_attr(
21850    not(target_arch = "arm"),
21851    stable(feature = "neon_intrinsics", since = "1.59.0")
21852)]
21853#[cfg_attr(
21854    target_arch = "arm",
21855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21856)]
21857pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21858    let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
21859    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21860    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21861    ret_val
21862}
21863#[doc = "Load multiple 2-element structures to two registers"]
21864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21865#[doc = "## Safety"]
21866#[doc = "  * Neon instrinsic unsafe"]
21867#[inline]
21868#[cfg(target_endian = "little")]
21869#[target_feature(enable = "neon")]
21870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21872#[cfg_attr(
21873    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21874    assert_instr(ld2)
21875)]
21876#[cfg_attr(
21877    not(target_arch = "arm"),
21878    stable(feature = "neon_intrinsics", since = "1.59.0")
21879)]
21880#[cfg_attr(
21881    target_arch = "arm",
21882    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21883)]
21884pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21885    transmute(vld2q_s16(transmute(a)))
21886}
21887#[doc = "Load multiple 2-element structures to two registers"]
21888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21889#[doc = "## Safety"]
21890#[doc = "  * Neon instrinsic unsafe"]
21891#[inline]
21892#[cfg(target_endian = "big")]
21893#[target_feature(enable = "neon")]
21894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21896#[cfg_attr(
21897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21898    assert_instr(ld2)
21899)]
21900#[cfg_attr(
21901    not(target_arch = "arm"),
21902    stable(feature = "neon_intrinsics", since = "1.59.0")
21903)]
21904#[cfg_attr(
21905    target_arch = "arm",
21906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21907)]
21908pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21909    let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
21910    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21911    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21912    ret_val
21913}
21914#[doc = "Load multiple 2-element structures to two registers"]
21915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21916#[doc = "## Safety"]
21917#[doc = "  * Neon instrinsic unsafe"]
21918#[inline]
21919#[cfg(target_endian = "little")]
21920#[target_feature(enable = "neon")]
21921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21923#[cfg_attr(
21924    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21925    assert_instr(ld2)
21926)]
21927#[cfg_attr(
21928    not(target_arch = "arm"),
21929    stable(feature = "neon_intrinsics", since = "1.59.0")
21930)]
21931#[cfg_attr(
21932    target_arch = "arm",
21933    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21934)]
21935pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21936    transmute(vld2_s32(transmute(a)))
21937}
21938#[doc = "Load multiple 2-element structures to two registers"]
21939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21940#[doc = "## Safety"]
21941#[doc = "  * Neon instrinsic unsafe"]
21942#[inline]
21943#[cfg(target_endian = "big")]
21944#[target_feature(enable = "neon")]
21945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21947#[cfg_attr(
21948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21949    assert_instr(ld2)
21950)]
21951#[cfg_attr(
21952    not(target_arch = "arm"),
21953    stable(feature = "neon_intrinsics", since = "1.59.0")
21954)]
21955#[cfg_attr(
21956    target_arch = "arm",
21957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21958)]
21959pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21960    let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
21961    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
21962    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
21963    ret_val
21964}
21965#[doc = "Load multiple 2-element structures to two registers"]
21966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21967#[doc = "## Safety"]
21968#[doc = "  * Neon instrinsic unsafe"]
21969#[inline]
21970#[cfg(target_endian = "little")]
21971#[target_feature(enable = "neon")]
21972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21974#[cfg_attr(
21975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21976    assert_instr(ld2)
21977)]
21978#[cfg_attr(
21979    not(target_arch = "arm"),
21980    stable(feature = "neon_intrinsics", since = "1.59.0")
21981)]
21982#[cfg_attr(
21983    target_arch = "arm",
21984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21985)]
21986pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21987    transmute(vld2q_s32(transmute(a)))
21988}
21989#[doc = "Load multiple 2-element structures to two registers"]
21990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21991#[doc = "## Safety"]
21992#[doc = "  * Neon instrinsic unsafe"]
21993#[inline]
21994#[cfg(target_endian = "big")]
21995#[target_feature(enable = "neon")]
21996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21998#[cfg_attr(
21999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22000    assert_instr(ld2)
22001)]
22002#[cfg_attr(
22003    not(target_arch = "arm"),
22004    stable(feature = "neon_intrinsics", since = "1.59.0")
22005)]
22006#[cfg_attr(
22007    target_arch = "arm",
22008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22009)]
22010pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
22011    let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
22012    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22013    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22014    ret_val
22015}
22016#[doc = "Load multiple 2-element structures to two registers"]
22017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
22018#[doc = "## Safety"]
22019#[doc = "  * Neon instrinsic unsafe"]
22020#[inline]
22021#[cfg(target_endian = "little")]
22022#[target_feature(enable = "neon")]
22023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22025#[cfg_attr(
22026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22027    assert_instr(ld2)
22028)]
22029#[cfg_attr(
22030    not(target_arch = "arm"),
22031    stable(feature = "neon_intrinsics", since = "1.59.0")
22032)]
22033#[cfg_attr(
22034    target_arch = "arm",
22035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22036)]
22037pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
22038    transmute(vld2_s8(transmute(a)))
22039}
22040#[doc = "Load multiple 2-element structures to two registers"]
22041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
22042#[doc = "## Safety"]
22043#[doc = "  * Neon instrinsic unsafe"]
22044#[inline]
22045#[cfg(target_endian = "big")]
22046#[target_feature(enable = "neon")]
22047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22049#[cfg_attr(
22050    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22051    assert_instr(ld2)
22052)]
22053#[cfg_attr(
22054    not(target_arch = "arm"),
22055    stable(feature = "neon_intrinsics", since = "1.59.0")
22056)]
22057#[cfg_attr(
22058    target_arch = "arm",
22059    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22060)]
22061pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
22062    let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
22063    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22064    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22065    ret_val
22066}
22067#[doc = "Load multiple 2-element structures to two registers"]
22068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
22069#[doc = "## Safety"]
22070#[doc = "  * Neon instrinsic unsafe"]
22071#[inline]
22072#[cfg(target_endian = "little")]
22073#[target_feature(enable = "neon")]
22074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22076#[cfg_attr(
22077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22078    assert_instr(ld2)
22079)]
22080#[cfg_attr(
22081    not(target_arch = "arm"),
22082    stable(feature = "neon_intrinsics", since = "1.59.0")
22083)]
22084#[cfg_attr(
22085    target_arch = "arm",
22086    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22087)]
22088pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22089    transmute(vld2q_s8(transmute(a)))
22090}
22091#[doc = "Load multiple 2-element structures to two registers"]
22092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
22093#[doc = "## Safety"]
22094#[doc = "  * Neon instrinsic unsafe"]
22095#[inline]
22096#[cfg(target_endian = "big")]
22097#[target_feature(enable = "neon")]
22098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22100#[cfg_attr(
22101    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22102    assert_instr(ld2)
22103)]
22104#[cfg_attr(
22105    not(target_arch = "arm"),
22106    stable(feature = "neon_intrinsics", since = "1.59.0")
22107)]
22108#[cfg_attr(
22109    target_arch = "arm",
22110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22111)]
22112pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22113    let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
22114    ret_val.0 = unsafe {
22115        simd_shuffle!(
22116            ret_val.0,
22117            ret_val.0,
22118            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22119        )
22120    };
22121    ret_val.1 = unsafe {
22122        simd_shuffle!(
22123            ret_val.1,
22124            ret_val.1,
22125            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22126        )
22127    };
22128    ret_val
22129}
22130#[doc = "Load multiple 2-element structures to two registers"]
22131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22132#[doc = "## Safety"]
22133#[doc = "  * Neon instrinsic unsafe"]
22134#[inline]
22135#[cfg(target_endian = "little")]
22136#[target_feature(enable = "neon")]
22137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22139#[cfg_attr(
22140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22141    assert_instr(ld2)
22142)]
22143#[cfg_attr(
22144    not(target_arch = "arm"),
22145    stable(feature = "neon_intrinsics", since = "1.59.0")
22146)]
22147#[cfg_attr(
22148    target_arch = "arm",
22149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22150)]
22151pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22152    transmute(vld2_s16(transmute(a)))
22153}
22154#[doc = "Load multiple 2-element structures to two registers"]
22155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22156#[doc = "## Safety"]
22157#[doc = "  * Neon instrinsic unsafe"]
22158#[inline]
22159#[cfg(target_endian = "big")]
22160#[target_feature(enable = "neon")]
22161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22163#[cfg_attr(
22164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22165    assert_instr(ld2)
22166)]
22167#[cfg_attr(
22168    not(target_arch = "arm"),
22169    stable(feature = "neon_intrinsics", since = "1.59.0")
22170)]
22171#[cfg_attr(
22172    target_arch = "arm",
22173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22174)]
22175pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22176    let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
22177    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22178    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22179    ret_val
22180}
22181#[doc = "Load multiple 2-element structures to two registers"]
22182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22183#[doc = "## Safety"]
22184#[doc = "  * Neon instrinsic unsafe"]
22185#[inline]
22186#[cfg(target_endian = "little")]
22187#[target_feature(enable = "neon")]
22188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22190#[cfg_attr(
22191    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22192    assert_instr(ld2)
22193)]
22194#[cfg_attr(
22195    not(target_arch = "arm"),
22196    stable(feature = "neon_intrinsics", since = "1.59.0")
22197)]
22198#[cfg_attr(
22199    target_arch = "arm",
22200    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22201)]
22202pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22203    transmute(vld2q_s16(transmute(a)))
22204}
22205#[doc = "Load multiple 2-element structures to two registers"]
22206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22207#[doc = "## Safety"]
22208#[doc = "  * Neon instrinsic unsafe"]
22209#[inline]
22210#[cfg(target_endian = "big")]
22211#[target_feature(enable = "neon")]
22212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22214#[cfg_attr(
22215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22216    assert_instr(ld2)
22217)]
22218#[cfg_attr(
22219    not(target_arch = "arm"),
22220    stable(feature = "neon_intrinsics", since = "1.59.0")
22221)]
22222#[cfg_attr(
22223    target_arch = "arm",
22224    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22225)]
22226pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22227    let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
22228    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22229    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22230    ret_val
22231}
22232#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22234#[doc = "## Safety"]
22235#[doc = "  * Neon instrinsic unsafe"]
22236#[inline]
22237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22238#[cfg(target_arch = "arm")]
22239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22240#[target_feature(enable = "neon,fp16")]
22241#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22242pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22243    unsafe extern "unadjusted" {
22244        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0f16")]
22245        fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
22246    }
22247    _vld3_dup_f16(a as _, 2)
22248}
22249#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22251#[doc = "## Safety"]
22252#[doc = "  * Neon instrinsic unsafe"]
22253#[inline]
22254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22255#[cfg(target_arch = "arm")]
22256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22257#[target_feature(enable = "neon,fp16")]
22258#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22259pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22260    unsafe extern "unadjusted" {
22261        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0f16")]
22262        fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
22263    }
22264    _vld3q_dup_f16(a as _, 2)
22265}
22266#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22268#[doc = "## Safety"]
22269#[doc = "  * Neon instrinsic unsafe"]
22270#[inline]
22271#[cfg(not(target_arch = "arm"))]
22272#[cfg_attr(
22273    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22274    assert_instr(ld3r)
22275)]
22276#[target_feature(enable = "neon,fp16")]
22277#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22278pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22279    unsafe extern "unadjusted" {
22280        #[cfg_attr(
22281            any(target_arch = "aarch64", target_arch = "arm64ec"),
22282            link_name = "llvm.aarch64.neon.ld3r.v4f16.p0f16"
22283        )]
22284        fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
22285    }
22286    _vld3_dup_f16(a as _)
22287}
22288#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22290#[doc = "## Safety"]
22291#[doc = "  * Neon instrinsic unsafe"]
22292#[inline]
22293#[cfg(not(target_arch = "arm"))]
22294#[cfg_attr(
22295    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22296    assert_instr(ld3r)
22297)]
22298#[target_feature(enable = "neon,fp16")]
22299#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22300pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22301    unsafe extern "unadjusted" {
22302        #[cfg_attr(
22303            any(target_arch = "aarch64", target_arch = "arm64ec"),
22304            link_name = "llvm.aarch64.neon.ld3r.v8f16.p0f16"
22305        )]
22306        fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
22307    }
22308    _vld3q_dup_f16(a as _)
22309}
22310#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22312#[doc = "## Safety"]
22313#[doc = "  * Neon instrinsic unsafe"]
22314#[inline]
22315#[target_feature(enable = "neon")]
22316#[cfg(not(target_arch = "arm"))]
22317#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22318#[cfg_attr(test, assert_instr(ld3r))]
22319pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22320    unsafe extern "unadjusted" {
22321        #[cfg_attr(
22322            any(target_arch = "aarch64", target_arch = "arm64ec"),
22323            link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
22324        )]
22325        fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
22326    }
22327    _vld3_dup_f32(a as _)
22328}
22329#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22331#[doc = "## Safety"]
22332#[doc = "  * Neon instrinsic unsafe"]
22333#[inline]
22334#[target_feature(enable = "neon")]
22335#[cfg(not(target_arch = "arm"))]
22336#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22337#[cfg_attr(test, assert_instr(ld3r))]
22338pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22339    unsafe extern "unadjusted" {
22340        #[cfg_attr(
22341            any(target_arch = "aarch64", target_arch = "arm64ec"),
22342            link_name = "llvm.aarch64.neon.ld3r.v4f32.p0"
22343        )]
22344        fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t;
22345    }
22346    _vld3q_dup_f32(a as _)
22347}
22348#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22350#[doc = "## Safety"]
22351#[doc = "  * Neon instrinsic unsafe"]
22352#[inline]
22353#[target_feature(enable = "neon")]
22354#[cfg(not(target_arch = "arm"))]
22355#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22356#[cfg_attr(test, assert_instr(ld3r))]
22357pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22358    unsafe extern "unadjusted" {
22359        #[cfg_attr(
22360            any(target_arch = "aarch64", target_arch = "arm64ec"),
22361            link_name = "llvm.aarch64.neon.ld3r.v8i8.p0"
22362        )]
22363        fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t;
22364    }
22365    _vld3_dup_s8(a as _)
22366}
22367#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22369#[doc = "## Safety"]
22370#[doc = "  * Neon instrinsic unsafe"]
22371#[inline]
22372#[target_feature(enable = "neon")]
22373#[cfg(not(target_arch = "arm"))]
22374#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22375#[cfg_attr(test, assert_instr(ld3r))]
22376pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22377    unsafe extern "unadjusted" {
22378        #[cfg_attr(
22379            any(target_arch = "aarch64", target_arch = "arm64ec"),
22380            link_name = "llvm.aarch64.neon.ld3r.v16i8.p0"
22381        )]
22382        fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t;
22383    }
22384    _vld3q_dup_s8(a as _)
22385}
22386#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22388#[doc = "## Safety"]
22389#[doc = "  * Neon instrinsic unsafe"]
22390#[inline]
22391#[target_feature(enable = "neon")]
22392#[cfg(not(target_arch = "arm"))]
22393#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22394#[cfg_attr(test, assert_instr(ld3r))]
22395pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22396    unsafe extern "unadjusted" {
22397        #[cfg_attr(
22398            any(target_arch = "aarch64", target_arch = "arm64ec"),
22399            link_name = "llvm.aarch64.neon.ld3r.v4i16.p0"
22400        )]
22401        fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t;
22402    }
22403    _vld3_dup_s16(a as _)
22404}
22405#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22407#[doc = "## Safety"]
22408#[doc = "  * Neon instrinsic unsafe"]
22409#[inline]
22410#[target_feature(enable = "neon")]
22411#[cfg(not(target_arch = "arm"))]
22412#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22413#[cfg_attr(test, assert_instr(ld3r))]
22414pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22415    unsafe extern "unadjusted" {
22416        #[cfg_attr(
22417            any(target_arch = "aarch64", target_arch = "arm64ec"),
22418            link_name = "llvm.aarch64.neon.ld3r.v8i16.p0"
22419        )]
22420        fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t;
22421    }
22422    _vld3q_dup_s16(a as _)
22423}
22424#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22426#[doc = "## Safety"]
22427#[doc = "  * Neon instrinsic unsafe"]
22428#[inline]
22429#[target_feature(enable = "neon")]
22430#[cfg(not(target_arch = "arm"))]
22431#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22432#[cfg_attr(test, assert_instr(ld3r))]
22433pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22434    unsafe extern "unadjusted" {
22435        #[cfg_attr(
22436            any(target_arch = "aarch64", target_arch = "arm64ec"),
22437            link_name = "llvm.aarch64.neon.ld3r.v2i32.p0"
22438        )]
22439        fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t;
22440    }
22441    _vld3_dup_s32(a as _)
22442}
22443#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22445#[doc = "## Safety"]
22446#[doc = "  * Neon instrinsic unsafe"]
22447#[inline]
22448#[target_feature(enable = "neon")]
22449#[cfg(not(target_arch = "arm"))]
22450#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22451#[cfg_attr(test, assert_instr(ld3r))]
22452pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22453    unsafe extern "unadjusted" {
22454        #[cfg_attr(
22455            any(target_arch = "aarch64", target_arch = "arm64ec"),
22456            link_name = "llvm.aarch64.neon.ld3r.v4i32.p0"
22457        )]
22458        fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t;
22459    }
22460    _vld3q_dup_s32(a as _)
22461}
22462#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22464#[doc = "## Safety"]
22465#[doc = "  * Neon instrinsic unsafe"]
22466#[inline]
22467#[target_feature(enable = "neon")]
22468#[cfg(not(target_arch = "arm"))]
22469#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22470#[cfg_attr(test, assert_instr(ld3r))]
22471pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22472    unsafe extern "unadjusted" {
22473        #[cfg_attr(
22474            any(target_arch = "aarch64", target_arch = "arm64ec"),
22475            link_name = "llvm.aarch64.neon.ld3r.v1i64.p0"
22476        )]
22477        fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t;
22478    }
22479    _vld3_dup_s64(a as _)
22480}
22481#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22483#[doc = "## Safety"]
22484#[doc = "  * Neon instrinsic unsafe"]
22485#[inline]
22486#[target_feature(enable = "neon,v7")]
22487#[cfg(target_arch = "arm")]
22488#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22489#[cfg_attr(test, assert_instr(vld3))]
22490pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22491    unsafe extern "unadjusted" {
22492        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")]
22493        fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
22494    }
22495    _vld3_dup_f32(a as *const i8, 4)
22496}
22497#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22499#[doc = "## Safety"]
22500#[doc = "  * Neon instrinsic unsafe"]
22501#[inline]
22502#[target_feature(enable = "neon,v7")]
22503#[cfg(target_arch = "arm")]
22504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22505#[cfg_attr(test, assert_instr(vld3))]
22506pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22507    unsafe extern "unadjusted" {
22508        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")]
22509        fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
22510    }
22511    _vld3q_dup_f32(a as *const i8, 4)
22512}
22513#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22515#[doc = "## Safety"]
22516#[doc = "  * Neon instrinsic unsafe"]
22517#[inline]
22518#[target_feature(enable = "neon,v7")]
22519#[cfg(target_arch = "arm")]
22520#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22521#[cfg_attr(test, assert_instr(vld3))]
22522pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22523    unsafe extern "unadjusted" {
22524        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")]
22525        fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
22526    }
22527    _vld3_dup_s8(a as *const i8, 1)
22528}
22529#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22531#[doc = "## Safety"]
22532#[doc = "  * Neon instrinsic unsafe"]
22533#[inline]
22534#[target_feature(enable = "neon,v7")]
22535#[cfg(target_arch = "arm")]
22536#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22537#[cfg_attr(test, assert_instr(vld3))]
22538pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22539    unsafe extern "unadjusted" {
22540        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")]
22541        fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
22542    }
22543    _vld3q_dup_s8(a as *const i8, 1)
22544}
22545#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22547#[doc = "## Safety"]
22548#[doc = "  * Neon instrinsic unsafe"]
22549#[inline]
22550#[target_feature(enable = "neon,v7")]
22551#[cfg(target_arch = "arm")]
22552#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22553#[cfg_attr(test, assert_instr(vld3))]
22554pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22555    unsafe extern "unadjusted" {
22556        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")]
22557        fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
22558    }
22559    _vld3_dup_s16(a as *const i8, 2)
22560}
22561#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22563#[doc = "## Safety"]
22564#[doc = "  * Neon instrinsic unsafe"]
22565#[inline]
22566#[target_feature(enable = "neon,v7")]
22567#[cfg(target_arch = "arm")]
22568#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22569#[cfg_attr(test, assert_instr(vld3))]
22570pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22571    unsafe extern "unadjusted" {
22572        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")]
22573        fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
22574    }
22575    _vld3q_dup_s16(a as *const i8, 2)
22576}
22577#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22579#[doc = "## Safety"]
22580#[doc = "  * Neon instrinsic unsafe"]
22581#[inline]
22582#[target_feature(enable = "neon,v7")]
22583#[cfg(target_arch = "arm")]
22584#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22585#[cfg_attr(test, assert_instr(vld3))]
22586pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22587    unsafe extern "unadjusted" {
22588        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")]
22589        fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
22590    }
22591    _vld3_dup_s32(a as *const i8, 4)
22592}
22593#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22595#[doc = "## Safety"]
22596#[doc = "  * Neon instrinsic unsafe"]
22597#[inline]
22598#[target_feature(enable = "neon,v7")]
22599#[cfg(target_arch = "arm")]
22600#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22601#[cfg_attr(test, assert_instr(vld3))]
22602pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22603    unsafe extern "unadjusted" {
22604        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")]
22605        fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
22606    }
22607    _vld3q_dup_s32(a as *const i8, 4)
22608}
22609#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
22611#[doc = "## Safety"]
22612#[doc = "  * Neon instrinsic unsafe"]
22613#[inline]
22614#[target_feature(enable = "neon,aes")]
22615#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22617#[cfg_attr(
22618    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22619    assert_instr(ld3r)
22620)]
22621#[cfg_attr(
22622    not(target_arch = "arm"),
22623    stable(feature = "neon_intrinsics", since = "1.59.0")
22624)]
22625#[cfg_attr(
22626    target_arch = "arm",
22627    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22628)]
22629pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
22630    transmute(vld3_dup_s64(transmute(a)))
22631}
22632#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22634#[doc = "## Safety"]
22635#[doc = "  * Neon instrinsic unsafe"]
22636#[inline]
22637#[cfg(target_arch = "arm")]
22638#[target_feature(enable = "neon,v7")]
22639#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22640#[cfg_attr(test, assert_instr(nop))]
22641pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22642    unsafe extern "unadjusted" {
22643        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")]
22644        fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
22645    }
22646    _vld3_dup_s64(a as *const i8, 8)
22647}
22648#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
22650#[doc = "## Safety"]
22651#[doc = "  * Neon instrinsic unsafe"]
22652#[inline]
22653#[target_feature(enable = "neon")]
22654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22656#[cfg_attr(
22657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22658    assert_instr(ld3r)
22659)]
22660#[cfg_attr(
22661    not(target_arch = "arm"),
22662    stable(feature = "neon_intrinsics", since = "1.59.0")
22663)]
22664#[cfg_attr(
22665    target_arch = "arm",
22666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22667)]
22668pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
22669    transmute(vld3_dup_s64(transmute(a)))
22670}
22671#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22673#[doc = "## Safety"]
22674#[doc = "  * Neon instrinsic unsafe"]
22675#[inline]
22676#[cfg(target_endian = "little")]
22677#[target_feature(enable = "neon")]
22678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22680#[cfg_attr(
22681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22682    assert_instr(ld3r)
22683)]
22684#[cfg_attr(
22685    not(target_arch = "arm"),
22686    stable(feature = "neon_intrinsics", since = "1.59.0")
22687)]
22688#[cfg_attr(
22689    target_arch = "arm",
22690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22691)]
22692pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22693    transmute(vld3_dup_s8(transmute(a)))
22694}
22695#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22697#[doc = "## Safety"]
22698#[doc = "  * Neon instrinsic unsafe"]
22699#[inline]
22700#[cfg(target_endian = "big")]
22701#[target_feature(enable = "neon")]
22702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22704#[cfg_attr(
22705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22706    assert_instr(ld3r)
22707)]
22708#[cfg_attr(
22709    not(target_arch = "arm"),
22710    stable(feature = "neon_intrinsics", since = "1.59.0")
22711)]
22712#[cfg_attr(
22713    target_arch = "arm",
22714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22715)]
22716pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22717    let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22718    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22719    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22720    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22721    ret_val
22722}
22723#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22725#[doc = "## Safety"]
22726#[doc = "  * Neon instrinsic unsafe"]
22727#[inline]
22728#[cfg(target_endian = "little")]
22729#[target_feature(enable = "neon")]
22730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22732#[cfg_attr(
22733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22734    assert_instr(ld3r)
22735)]
22736#[cfg_attr(
22737    not(target_arch = "arm"),
22738    stable(feature = "neon_intrinsics", since = "1.59.0")
22739)]
22740#[cfg_attr(
22741    target_arch = "arm",
22742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22743)]
22744pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22745    transmute(vld3q_dup_s8(transmute(a)))
22746}
22747#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22749#[doc = "## Safety"]
22750#[doc = "  * Neon instrinsic unsafe"]
22751#[inline]
22752#[cfg(target_endian = "big")]
22753#[target_feature(enable = "neon")]
22754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22756#[cfg_attr(
22757    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22758    assert_instr(ld3r)
22759)]
22760#[cfg_attr(
22761    not(target_arch = "arm"),
22762    stable(feature = "neon_intrinsics", since = "1.59.0")
22763)]
22764#[cfg_attr(
22765    target_arch = "arm",
22766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22767)]
22768pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22769    let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
22770    ret_val.0 = unsafe {
22771        simd_shuffle!(
22772            ret_val.0,
22773            ret_val.0,
22774            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22775        )
22776    };
22777    ret_val.1 = unsafe {
22778        simd_shuffle!(
22779            ret_val.1,
22780            ret_val.1,
22781            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22782        )
22783    };
22784    ret_val.2 = unsafe {
22785        simd_shuffle!(
22786            ret_val.2,
22787            ret_val.2,
22788            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22789        )
22790    };
22791    ret_val
22792}
22793#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22795#[doc = "## Safety"]
22796#[doc = "  * Neon instrinsic unsafe"]
22797#[inline]
22798#[cfg(target_endian = "little")]
22799#[target_feature(enable = "neon")]
22800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22802#[cfg_attr(
22803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22804    assert_instr(ld3r)
22805)]
22806#[cfg_attr(
22807    not(target_arch = "arm"),
22808    stable(feature = "neon_intrinsics", since = "1.59.0")
22809)]
22810#[cfg_attr(
22811    target_arch = "arm",
22812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22813)]
22814pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22815    transmute(vld3_dup_s16(transmute(a)))
22816}
22817#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22819#[doc = "## Safety"]
22820#[doc = "  * Neon instrinsic unsafe"]
22821#[inline]
22822#[cfg(target_endian = "big")]
22823#[target_feature(enable = "neon")]
22824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22826#[cfg_attr(
22827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22828    assert_instr(ld3r)
22829)]
22830#[cfg_attr(
22831    not(target_arch = "arm"),
22832    stable(feature = "neon_intrinsics", since = "1.59.0")
22833)]
22834#[cfg_attr(
22835    target_arch = "arm",
22836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22837)]
22838pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22839    let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
22840    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22841    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22842    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22843    ret_val
22844}
22845#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22847#[doc = "## Safety"]
22848#[doc = "  * Neon instrinsic unsafe"]
22849#[inline]
22850#[cfg(target_endian = "little")]
22851#[target_feature(enable = "neon")]
22852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22854#[cfg_attr(
22855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22856    assert_instr(ld3r)
22857)]
22858#[cfg_attr(
22859    not(target_arch = "arm"),
22860    stable(feature = "neon_intrinsics", since = "1.59.0")
22861)]
22862#[cfg_attr(
22863    target_arch = "arm",
22864    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22865)]
22866pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22867    transmute(vld3q_dup_s16(transmute(a)))
22868}
22869#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22871#[doc = "## Safety"]
22872#[doc = "  * Neon instrinsic unsafe"]
22873#[inline]
22874#[cfg(target_endian = "big")]
22875#[target_feature(enable = "neon")]
22876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22878#[cfg_attr(
22879    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22880    assert_instr(ld3r)
22881)]
22882#[cfg_attr(
22883    not(target_arch = "arm"),
22884    stable(feature = "neon_intrinsics", since = "1.59.0")
22885)]
22886#[cfg_attr(
22887    target_arch = "arm",
22888    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22889)]
22890pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22891    let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
22892    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22893    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22894    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22895    ret_val
22896}
22897#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22899#[doc = "## Safety"]
22900#[doc = "  * Neon instrinsic unsafe"]
22901#[inline]
22902#[cfg(target_endian = "little")]
22903#[target_feature(enable = "neon")]
22904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22906#[cfg_attr(
22907    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22908    assert_instr(ld3r)
22909)]
22910#[cfg_attr(
22911    not(target_arch = "arm"),
22912    stable(feature = "neon_intrinsics", since = "1.59.0")
22913)]
22914#[cfg_attr(
22915    target_arch = "arm",
22916    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22917)]
22918pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22919    transmute(vld3_dup_s32(transmute(a)))
22920}
22921#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22923#[doc = "## Safety"]
22924#[doc = "  * Neon instrinsic unsafe"]
22925#[inline]
22926#[cfg(target_endian = "big")]
22927#[target_feature(enable = "neon")]
22928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22930#[cfg_attr(
22931    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22932    assert_instr(ld3r)
22933)]
22934#[cfg_attr(
22935    not(target_arch = "arm"),
22936    stable(feature = "neon_intrinsics", since = "1.59.0")
22937)]
22938#[cfg_attr(
22939    target_arch = "arm",
22940    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22941)]
22942pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22943    let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
22944    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
22945    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
22946    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
22947    ret_val
22948}
22949#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22951#[doc = "## Safety"]
22952#[doc = "  * Neon instrinsic unsafe"]
22953#[inline]
22954#[cfg(target_endian = "little")]
22955#[target_feature(enable = "neon")]
22956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22957#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22958#[cfg_attr(
22959    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22960    assert_instr(ld3r)
22961)]
22962#[cfg_attr(
22963    not(target_arch = "arm"),
22964    stable(feature = "neon_intrinsics", since = "1.59.0")
22965)]
22966#[cfg_attr(
22967    target_arch = "arm",
22968    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22969)]
22970pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22971    transmute(vld3q_dup_s32(transmute(a)))
22972}
22973#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22975#[doc = "## Safety"]
22976#[doc = "  * Neon instrinsic unsafe"]
22977#[inline]
22978#[cfg(target_endian = "big")]
22979#[target_feature(enable = "neon")]
22980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22982#[cfg_attr(
22983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22984    assert_instr(ld3r)
22985)]
22986#[cfg_attr(
22987    not(target_arch = "arm"),
22988    stable(feature = "neon_intrinsics", since = "1.59.0")
22989)]
22990#[cfg_attr(
22991    target_arch = "arm",
22992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22993)]
22994pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22995    let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
22996    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22997    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22998    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22999    ret_val
23000}
23001#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
23003#[doc = "## Safety"]
23004#[doc = "  * Neon instrinsic unsafe"]
23005#[inline]
23006#[cfg(target_endian = "little")]
23007#[target_feature(enable = "neon")]
23008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23010#[cfg_attr(
23011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23012    assert_instr(ld3r)
23013)]
23014#[cfg_attr(
23015    not(target_arch = "arm"),
23016    stable(feature = "neon_intrinsics", since = "1.59.0")
23017)]
23018#[cfg_attr(
23019    target_arch = "arm",
23020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23021)]
23022pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
23023    transmute(vld3_dup_s8(transmute(a)))
23024}
23025#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
23027#[doc = "## Safety"]
23028#[doc = "  * Neon instrinsic unsafe"]
23029#[inline]
23030#[cfg(target_endian = "big")]
23031#[target_feature(enable = "neon")]
23032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23034#[cfg_attr(
23035    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23036    assert_instr(ld3r)
23037)]
23038#[cfg_attr(
23039    not(target_arch = "arm"),
23040    stable(feature = "neon_intrinsics", since = "1.59.0")
23041)]
23042#[cfg_attr(
23043    target_arch = "arm",
23044    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23045)]
23046pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
23047    let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
23048    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23049    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23050    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23051    ret_val
23052}
23053#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
23055#[doc = "## Safety"]
23056#[doc = "  * Neon instrinsic unsafe"]
23057#[inline]
23058#[cfg(target_endian = "little")]
23059#[target_feature(enable = "neon")]
23060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23062#[cfg_attr(
23063    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23064    assert_instr(ld3r)
23065)]
23066#[cfg_attr(
23067    not(target_arch = "arm"),
23068    stable(feature = "neon_intrinsics", since = "1.59.0")
23069)]
23070#[cfg_attr(
23071    target_arch = "arm",
23072    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23073)]
23074pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
23075    transmute(vld3q_dup_s8(transmute(a)))
23076}
23077#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
23079#[doc = "## Safety"]
23080#[doc = "  * Neon instrinsic unsafe"]
23081#[inline]
23082#[cfg(target_endian = "big")]
23083#[target_feature(enable = "neon")]
23084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23086#[cfg_attr(
23087    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23088    assert_instr(ld3r)
23089)]
23090#[cfg_attr(
23091    not(target_arch = "arm"),
23092    stable(feature = "neon_intrinsics", since = "1.59.0")
23093)]
23094#[cfg_attr(
23095    target_arch = "arm",
23096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23097)]
23098pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
23099    let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
23100    ret_val.0 = unsafe {
23101        simd_shuffle!(
23102            ret_val.0,
23103            ret_val.0,
23104            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23105        )
23106    };
23107    ret_val.1 = unsafe {
23108        simd_shuffle!(
23109            ret_val.1,
23110            ret_val.1,
23111            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23112        )
23113    };
23114    ret_val.2 = unsafe {
23115        simd_shuffle!(
23116            ret_val.2,
23117            ret_val.2,
23118            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23119        )
23120    };
23121    ret_val
23122}
23123#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23125#[doc = "## Safety"]
23126#[doc = "  * Neon instrinsic unsafe"]
23127#[inline]
23128#[cfg(target_endian = "little")]
23129#[target_feature(enable = "neon")]
23130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23132#[cfg_attr(
23133    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23134    assert_instr(ld3r)
23135)]
23136#[cfg_attr(
23137    not(target_arch = "arm"),
23138    stable(feature = "neon_intrinsics", since = "1.59.0")
23139)]
23140#[cfg_attr(
23141    target_arch = "arm",
23142    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23143)]
23144pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23145    transmute(vld3_dup_s16(transmute(a)))
23146}
23147#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23149#[doc = "## Safety"]
23150#[doc = "  * Neon instrinsic unsafe"]
23151#[inline]
23152#[cfg(target_endian = "big")]
23153#[target_feature(enable = "neon")]
23154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23156#[cfg_attr(
23157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23158    assert_instr(ld3r)
23159)]
23160#[cfg_attr(
23161    not(target_arch = "arm"),
23162    stable(feature = "neon_intrinsics", since = "1.59.0")
23163)]
23164#[cfg_attr(
23165    target_arch = "arm",
23166    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23167)]
23168pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23169    let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
23170    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
23171    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
23172    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
23173    ret_val
23174}
23175#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23177#[doc = "## Safety"]
23178#[doc = "  * Neon instrinsic unsafe"]
23179#[inline]
23180#[cfg(target_endian = "little")]
23181#[target_feature(enable = "neon")]
23182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23184#[cfg_attr(
23185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23186    assert_instr(ld3r)
23187)]
23188#[cfg_attr(
23189    not(target_arch = "arm"),
23190    stable(feature = "neon_intrinsics", since = "1.59.0")
23191)]
23192#[cfg_attr(
23193    target_arch = "arm",
23194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23195)]
23196pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23197    transmute(vld3q_dup_s16(transmute(a)))
23198}
23199#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23201#[doc = "## Safety"]
23202#[doc = "  * Neon instrinsic unsafe"]
23203#[inline]
23204#[cfg(target_endian = "big")]
23205#[target_feature(enable = "neon")]
23206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23208#[cfg_attr(
23209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23210    assert_instr(ld3r)
23211)]
23212#[cfg_attr(
23213    not(target_arch = "arm"),
23214    stable(feature = "neon_intrinsics", since = "1.59.0")
23215)]
23216#[cfg_attr(
23217    target_arch = "arm",
23218    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23219)]
23220pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23221    let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
23222    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23223    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23224    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23225    ret_val
23226}
23227#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23229#[doc = "## Safety"]
23230#[doc = "  * Neon instrinsic unsafe"]
23231#[inline]
23232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23233#[cfg(target_arch = "arm")]
23234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23235#[target_feature(enable = "neon,fp16")]
23236#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23237pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23238    unsafe extern "unadjusted" {
23239        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0f16")]
23240        fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
23241    }
23242    _vld3_f16(a as _, 2)
23243}
23244#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23246#[doc = "## Safety"]
23247#[doc = "  * Neon instrinsic unsafe"]
23248#[inline]
23249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23250#[cfg(target_arch = "arm")]
23251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23252#[target_feature(enable = "neon,fp16")]
23253#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23254pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23255    unsafe extern "unadjusted" {
23256        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0f16")]
23257        fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
23258    }
23259    _vld3q_f16(a as _, 2)
23260}
23261#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23263#[doc = "## Safety"]
23264#[doc = "  * Neon instrinsic unsafe"]
23265#[inline]
23266#[cfg(not(target_arch = "arm"))]
23267#[cfg_attr(
23268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23269    assert_instr(ld3)
23270)]
23271#[target_feature(enable = "neon,fp16")]
23272#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23273pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23274    unsafe extern "unadjusted" {
23275        #[cfg_attr(
23276            any(target_arch = "aarch64", target_arch = "arm64ec"),
23277            link_name = "llvm.aarch64.neon.ld3.v4f16.p0f16"
23278        )]
23279        fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
23280    }
23281    _vld3_f16(a as _)
23282}
23283#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23285#[doc = "## Safety"]
23286#[doc = "  * Neon instrinsic unsafe"]
23287#[inline]
23288#[cfg(not(target_arch = "arm"))]
23289#[cfg_attr(
23290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23291    assert_instr(ld3)
23292)]
23293#[target_feature(enable = "neon,fp16")]
23294#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23295pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23296    unsafe extern "unadjusted" {
23297        #[cfg_attr(
23298            any(target_arch = "aarch64", target_arch = "arm64ec"),
23299            link_name = "llvm.aarch64.neon.ld3.v8f16.p0f16"
23300        )]
23301        fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
23302    }
23303    _vld3q_f16(a as _)
23304}
23305#[doc = "Load multiple 3-element structures to three registers"]
23306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23307#[doc = "## Safety"]
23308#[doc = "  * Neon instrinsic unsafe"]
23309#[inline]
23310#[target_feature(enable = "neon")]
23311#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23312#[cfg(not(target_arch = "arm"))]
23313#[cfg_attr(test, assert_instr(ld3))]
23314pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23315    unsafe extern "unadjusted" {
23316        #[cfg_attr(
23317            any(target_arch = "aarch64", target_arch = "arm64ec"),
23318            link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
23319        )]
23320        fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
23321    }
23322    _vld3_f32(a as _)
23323}
23324#[doc = "Load multiple 3-element structures to three registers"]
23325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23326#[doc = "## Safety"]
23327#[doc = "  * Neon instrinsic unsafe"]
23328#[inline]
23329#[target_feature(enable = "neon")]
23330#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23331#[cfg(not(target_arch = "arm"))]
23332#[cfg_attr(test, assert_instr(ld3))]
23333pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23334    unsafe extern "unadjusted" {
23335        #[cfg_attr(
23336            any(target_arch = "aarch64", target_arch = "arm64ec"),
23337            link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
23338        )]
23339        fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
23340    }
23341    _vld3q_f32(a as _)
23342}
23343#[doc = "Load multiple 3-element structures to three registers"]
23344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23345#[doc = "## Safety"]
23346#[doc = "  * Neon instrinsic unsafe"]
23347#[inline]
23348#[target_feature(enable = "neon")]
23349#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23350#[cfg(not(target_arch = "arm"))]
23351#[cfg_attr(test, assert_instr(ld3))]
23352pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23353    unsafe extern "unadjusted" {
23354        #[cfg_attr(
23355            any(target_arch = "aarch64", target_arch = "arm64ec"),
23356            link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
23357        )]
23358        fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
23359    }
23360    _vld3_s8(a as _)
23361}
23362#[doc = "Load multiple 3-element structures to three registers"]
23363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23364#[doc = "## Safety"]
23365#[doc = "  * Neon instrinsic unsafe"]
23366#[inline]
23367#[target_feature(enable = "neon")]
23368#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23369#[cfg(not(target_arch = "arm"))]
23370#[cfg_attr(test, assert_instr(ld3))]
23371pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23372    unsafe extern "unadjusted" {
23373        #[cfg_attr(
23374            any(target_arch = "aarch64", target_arch = "arm64ec"),
23375            link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
23376        )]
23377        fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
23378    }
23379    _vld3q_s8(a as _)
23380}
23381#[doc = "Load multiple 3-element structures to three registers"]
23382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23383#[doc = "## Safety"]
23384#[doc = "  * Neon instrinsic unsafe"]
23385#[inline]
23386#[target_feature(enable = "neon")]
23387#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23388#[cfg(not(target_arch = "arm"))]
23389#[cfg_attr(test, assert_instr(ld3))]
23390pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23391    unsafe extern "unadjusted" {
23392        #[cfg_attr(
23393            any(target_arch = "aarch64", target_arch = "arm64ec"),
23394            link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
23395        )]
23396        fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
23397    }
23398    _vld3_s16(a as _)
23399}
23400#[doc = "Load multiple 3-element structures to three registers"]
23401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23402#[doc = "## Safety"]
23403#[doc = "  * Neon instrinsic unsafe"]
23404#[inline]
23405#[target_feature(enable = "neon")]
23406#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23407#[cfg(not(target_arch = "arm"))]
23408#[cfg_attr(test, assert_instr(ld3))]
23409pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23410    unsafe extern "unadjusted" {
23411        #[cfg_attr(
23412            any(target_arch = "aarch64", target_arch = "arm64ec"),
23413            link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
23414        )]
23415        fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
23416    }
23417    _vld3q_s16(a as _)
23418}
23419#[doc = "Load multiple 3-element structures to three registers"]
23420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23421#[doc = "## Safety"]
23422#[doc = "  * Neon instrinsic unsafe"]
23423#[inline]
23424#[target_feature(enable = "neon")]
23425#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23426#[cfg(not(target_arch = "arm"))]
23427#[cfg_attr(test, assert_instr(ld3))]
23428pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23429    unsafe extern "unadjusted" {
23430        #[cfg_attr(
23431            any(target_arch = "aarch64", target_arch = "arm64ec"),
23432            link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
23433        )]
23434        fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
23435    }
23436    _vld3_s32(a as _)
23437}
23438#[doc = "Load multiple 3-element structures to three registers"]
23439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23440#[doc = "## Safety"]
23441#[doc = "  * Neon instrinsic unsafe"]
23442#[inline]
23443#[target_feature(enable = "neon")]
23444#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23445#[cfg(not(target_arch = "arm"))]
23446#[cfg_attr(test, assert_instr(ld3))]
23447pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23448    unsafe extern "unadjusted" {
23449        #[cfg_attr(
23450            any(target_arch = "aarch64", target_arch = "arm64ec"),
23451            link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
23452        )]
23453        fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
23454    }
23455    _vld3q_s32(a as _)
23456}
23457#[doc = "Load multiple 3-element structures to three registers"]
23458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23459#[doc = "## Safety"]
23460#[doc = "  * Neon instrinsic unsafe"]
23461#[inline]
23462#[cfg(target_arch = "arm")]
23463#[target_feature(enable = "neon,v7")]
23464#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23465#[cfg_attr(test, assert_instr(vld3))]
23466pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23467    unsafe extern "unadjusted" {
23468        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")]
23469        fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
23470    }
23471    _vld3_f32(a as *const i8, 4)
23472}
23473#[doc = "Load multiple 3-element structures to three registers"]
23474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23475#[doc = "## Safety"]
23476#[doc = "  * Neon instrinsic unsafe"]
23477#[inline]
23478#[cfg(target_arch = "arm")]
23479#[target_feature(enable = "neon,v7")]
23480#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23481#[cfg_attr(test, assert_instr(vld3))]
23482pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23483    unsafe extern "unadjusted" {
23484        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")]
23485        fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
23486    }
23487    _vld3q_f32(a as *const i8, 4)
23488}
23489#[doc = "Load multiple 3-element structures to three registers"]
23490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23491#[doc = "## Safety"]
23492#[doc = "  * Neon instrinsic unsafe"]
23493#[inline]
23494#[cfg(target_arch = "arm")]
23495#[target_feature(enable = "neon,v7")]
23496#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23497#[cfg_attr(test, assert_instr(vld3))]
23498pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23499    unsafe extern "unadjusted" {
23500        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")]
23501        fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
23502    }
23503    _vld3_s8(a as *const i8, 1)
23504}
23505#[doc = "Load multiple 3-element structures to three registers"]
23506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23507#[doc = "## Safety"]
23508#[doc = "  * Neon instrinsic unsafe"]
23509#[inline]
23510#[cfg(target_arch = "arm")]
23511#[target_feature(enable = "neon,v7")]
23512#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23513#[cfg_attr(test, assert_instr(vld3))]
23514pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23515    unsafe extern "unadjusted" {
23516        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")]
23517        fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
23518    }
23519    _vld3q_s8(a as *const i8, 1)
23520}
23521#[doc = "Load multiple 3-element structures to three registers"]
23522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23523#[doc = "## Safety"]
23524#[doc = "  * Neon instrinsic unsafe"]
23525#[inline]
23526#[cfg(target_arch = "arm")]
23527#[target_feature(enable = "neon,v7")]
23528#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23529#[cfg_attr(test, assert_instr(vld3))]
23530pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23531    unsafe extern "unadjusted" {
23532        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")]
23533        fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
23534    }
23535    _vld3_s16(a as *const i8, 2)
23536}
23537#[doc = "Load multiple 3-element structures to three registers"]
23538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23539#[doc = "## Safety"]
23540#[doc = "  * Neon instrinsic unsafe"]
23541#[inline]
23542#[cfg(target_arch = "arm")]
23543#[target_feature(enable = "neon,v7")]
23544#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23545#[cfg_attr(test, assert_instr(vld3))]
23546pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23547    unsafe extern "unadjusted" {
23548        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")]
23549        fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
23550    }
23551    _vld3q_s16(a as *const i8, 2)
23552}
23553#[doc = "Load multiple 3-element structures to three registers"]
23554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23555#[doc = "## Safety"]
23556#[doc = "  * Neon instrinsic unsafe"]
23557#[inline]
23558#[cfg(target_arch = "arm")]
23559#[target_feature(enable = "neon,v7")]
23560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23561#[cfg_attr(test, assert_instr(vld3))]
23562pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23563    unsafe extern "unadjusted" {
23564        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")]
23565        fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
23566    }
23567    _vld3_s32(a as *const i8, 4)
23568}
23569#[doc = "Load multiple 3-element structures to three registers"]
23570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23571#[doc = "## Safety"]
23572#[doc = "  * Neon instrinsic unsafe"]
23573#[inline]
23574#[cfg(target_arch = "arm")]
23575#[target_feature(enable = "neon,v7")]
23576#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23577#[cfg_attr(test, assert_instr(vld3))]
23578pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23579    unsafe extern "unadjusted" {
23580        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")]
23581        fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
23582    }
23583    _vld3q_s32(a as *const i8, 4)
23584}
23585#[doc = "Load multiple 3-element structures to two registers"]
23586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23587#[doc = "## Safety"]
23588#[doc = "  * Neon instrinsic unsafe"]
23589#[inline]
23590#[target_feature(enable = "neon,v7")]
23591#[cfg(target_arch = "arm")]
23592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23593#[rustc_legacy_const_generics(2)]
23594#[target_feature(enable = "neon,fp16")]
23595#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23596pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23597    static_assert_uimm_bits!(LANE, 2);
23598    unsafe extern "unadjusted" {
23599        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")]
23600        fn _vld3_lane_f16(
23601            ptr: *const f16,
23602            a: float16x4_t,
23603            b: float16x4_t,
23604            c: float16x4_t,
23605            n: i32,
23606            size: i32,
23607        ) -> float16x4x3_t;
23608    }
23609    _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23610}
23611#[doc = "Load multiple 3-element structures to two registers"]
23612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23613#[doc = "## Safety"]
23614#[doc = "  * Neon instrinsic unsafe"]
23615#[inline]
23616#[target_feature(enable = "neon,v7")]
23617#[cfg(target_arch = "arm")]
23618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23619#[rustc_legacy_const_generics(2)]
23620#[target_feature(enable = "neon,fp16")]
23621#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23622pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23623    static_assert_uimm_bits!(LANE, 3);
23624    unsafe extern "unadjusted" {
23625        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")]
23626        fn _vld3q_lane_f16(
23627            ptr: *const f16,
23628            a: float16x8_t,
23629            b: float16x8_t,
23630            c: float16x8_t,
23631            n: i32,
23632            size: i32,
23633        ) -> float16x8x3_t;
23634    }
23635    _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23636}
23637#[doc = "Load multiple 3-element structures to two registers"]
23638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23639#[doc = "## Safety"]
23640#[doc = "  * Neon instrinsic unsafe"]
23641#[inline]
23642#[cfg(not(target_arch = "arm"))]
23643#[cfg_attr(
23644    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23645    assert_instr(ld3, LANE = 0)
23646)]
23647#[rustc_legacy_const_generics(2)]
23648#[target_feature(enable = "neon,fp16")]
23649#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23650pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23651    static_assert_uimm_bits!(LANE, 2);
23652    unsafe extern "unadjusted" {
23653        #[cfg_attr(
23654            any(target_arch = "aarch64", target_arch = "arm64ec"),
23655            link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0"
23656        )]
23657        fn _vld3_lane_f16(
23658            a: float16x4_t,
23659            b: float16x4_t,
23660            c: float16x4_t,
23661            n: i64,
23662            ptr: *const f16,
23663        ) -> float16x4x3_t;
23664    }
23665    _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23666}
23667#[doc = "Load multiple 3-element structures to two registers"]
23668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23669#[doc = "## Safety"]
23670#[doc = "  * Neon instrinsic unsafe"]
23671#[inline]
23672#[cfg(not(target_arch = "arm"))]
23673#[cfg_attr(
23674    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23675    assert_instr(ld3, LANE = 0)
23676)]
23677#[rustc_legacy_const_generics(2)]
23678#[target_feature(enable = "neon,fp16")]
23679#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23680pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23681    static_assert_uimm_bits!(LANE, 3);
23682    unsafe extern "unadjusted" {
23683        #[cfg_attr(
23684            any(target_arch = "aarch64", target_arch = "arm64ec"),
23685            link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0"
23686        )]
23687        fn _vld3q_lane_f16(
23688            a: float16x8_t,
23689            b: float16x8_t,
23690            c: float16x8_t,
23691            n: i64,
23692            ptr: *const f16,
23693        ) -> float16x8x3_t;
23694    }
23695    _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23696}
23697#[doc = "Load multiple 3-element structures to three registers"]
23698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23699#[doc = "## Safety"]
23700#[doc = "  * Neon instrinsic unsafe"]
23701#[inline]
23702#[target_feature(enable = "neon")]
23703#[cfg(not(target_arch = "arm"))]
23704#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23705#[rustc_legacy_const_generics(2)]
23706#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23707pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23708    static_assert_uimm_bits!(LANE, 1);
23709    unsafe extern "unadjusted" {
23710        #[cfg_attr(
23711            any(target_arch = "aarch64", target_arch = "arm64ec"),
23712            link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0"
23713        )]
23714        fn _vld3_lane_f32(
23715            a: float32x2_t,
23716            b: float32x2_t,
23717            c: float32x2_t,
23718            n: i64,
23719            ptr: *const i8,
23720        ) -> float32x2x3_t;
23721    }
23722    _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23723}
23724#[doc = "Load multiple 3-element structures to three registers"]
23725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
23726#[doc = "## Safety"]
23727#[doc = "  * Neon instrinsic unsafe"]
23728#[inline]
23729#[target_feature(enable = "neon")]
23730#[cfg(not(target_arch = "arm"))]
23731#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23732#[rustc_legacy_const_generics(2)]
23733#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23734pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
23735    static_assert_uimm_bits!(LANE, 2);
23736    unsafe extern "unadjusted" {
23737        #[cfg_attr(
23738            any(target_arch = "aarch64", target_arch = "arm64ec"),
23739            link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0"
23740        )]
23741        fn _vld3q_lane_f32(
23742            a: float32x4_t,
23743            b: float32x4_t,
23744            c: float32x4_t,
23745            n: i64,
23746            ptr: *const i8,
23747        ) -> float32x4x3_t;
23748    }
23749    _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23750}
23751#[doc = "Load multiple 3-element structures to three registers"]
23752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23753#[doc = "## Safety"]
23754#[doc = "  * Neon instrinsic unsafe"]
23755#[inline]
23756#[cfg(target_arch = "arm")]
23757#[target_feature(enable = "neon,v7")]
23758#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23759#[rustc_legacy_const_generics(2)]
23760#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23761pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23762    static_assert_uimm_bits!(LANE, 1);
23763    unsafe extern "unadjusted" {
23764        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")]
23765        fn _vld3_lane_f32(
23766            ptr: *const i8,
23767            a: float32x2_t,
23768            b: float32x2_t,
23769            c: float32x2_t,
23770            n: i32,
23771            size: i32,
23772        ) -> float32x2x3_t;
23773    }
23774    _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
23775}
23776#[doc = "Load multiple 3-element structures to two registers"]
23777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23778#[doc = "## Safety"]
23779#[doc = "  * Neon instrinsic unsafe"]
23780#[inline]
23781#[target_feature(enable = "neon")]
23782#[cfg(not(target_arch = "arm"))]
23783#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23784#[rustc_legacy_const_generics(2)]
23785#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23786pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23787    static_assert_uimm_bits!(LANE, 3);
23788    unsafe extern "unadjusted" {
23789        #[cfg_attr(
23790            any(target_arch = "aarch64", target_arch = "arm64ec"),
23791            link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0"
23792        )]
23793        fn _vld3_lane_s8(
23794            a: int8x8_t,
23795            b: int8x8_t,
23796            c: int8x8_t,
23797            n: i64,
23798            ptr: *const i8,
23799        ) -> int8x8x3_t;
23800    }
23801    _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
23802}
23803#[doc = "Load multiple 3-element structures to two registers"]
23804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23805#[doc = "## Safety"]
23806#[doc = "  * Neon instrinsic unsafe"]
23807#[inline]
23808#[target_feature(enable = "neon")]
23809#[cfg(not(target_arch = "arm"))]
23810#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23811#[rustc_legacy_const_generics(2)]
23812#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23813pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23814    static_assert_uimm_bits!(LANE, 2);
23815    unsafe extern "unadjusted" {
23816        #[cfg_attr(
23817            any(target_arch = "aarch64", target_arch = "arm64ec"),
23818            link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0"
23819        )]
23820        fn _vld3_lane_s16(
23821            a: int16x4_t,
23822            b: int16x4_t,
23823            c: int16x4_t,
23824            n: i64,
23825            ptr: *const i8,
23826        ) -> int16x4x3_t;
23827    }
23828    _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23829}
23830#[doc = "Load multiple 3-element structures to two registers"]
23831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23832#[doc = "## Safety"]
23833#[doc = "  * Neon instrinsic unsafe"]
23834#[inline]
23835#[target_feature(enable = "neon")]
23836#[cfg(not(target_arch = "arm"))]
23837#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23838#[rustc_legacy_const_generics(2)]
23839#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23840pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23841    static_assert_uimm_bits!(LANE, 4);
23842    unsafe extern "unadjusted" {
23843        #[cfg_attr(
23844            any(target_arch = "aarch64", target_arch = "arm64ec"),
23845            link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0"
23846        )]
23847        fn _vld3q_lane_s16(
23848            a: int16x8_t,
23849            b: int16x8_t,
23850            c: int16x8_t,
23851            n: i64,
23852            ptr: *const i8,
23853        ) -> int16x8x3_t;
23854    }
23855    _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23856}
23857#[doc = "Load multiple 3-element structures to two registers"]
23858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23859#[doc = "## Safety"]
23860#[doc = "  * Neon instrinsic unsafe"]
23861#[inline]
23862#[target_feature(enable = "neon")]
23863#[cfg(not(target_arch = "arm"))]
23864#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23865#[rustc_legacy_const_generics(2)]
23866#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23867pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23868    static_assert_uimm_bits!(LANE, 1);
23869    unsafe extern "unadjusted" {
23870        #[cfg_attr(
23871            any(target_arch = "aarch64", target_arch = "arm64ec"),
23872            link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0"
23873        )]
23874        fn _vld3_lane_s32(
23875            a: int32x2_t,
23876            b: int32x2_t,
23877            c: int32x2_t,
23878            n: i64,
23879            ptr: *const i8,
23880        ) -> int32x2x3_t;
23881    }
23882    _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23883}
23884#[doc = "Load multiple 3-element structures to two registers"]
23885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23886#[doc = "## Safety"]
23887#[doc = "  * Neon instrinsic unsafe"]
23888#[inline]
23889#[target_feature(enable = "neon")]
23890#[cfg(not(target_arch = "arm"))]
23891#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23892#[rustc_legacy_const_generics(2)]
23893#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23894pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23895    static_assert_uimm_bits!(LANE, 2);
23896    unsafe extern "unadjusted" {
23897        #[cfg_attr(
23898            any(target_arch = "aarch64", target_arch = "arm64ec"),
23899            link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0"
23900        )]
23901        fn _vld3q_lane_s32(
23902            a: int32x4_t,
23903            b: int32x4_t,
23904            c: int32x4_t,
23905            n: i64,
23906            ptr: *const i8,
23907        ) -> int32x4x3_t;
23908    }
23909    _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23910}
23911#[doc = "Load multiple 3-element structures to two registers"]
23912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23913#[doc = "## Safety"]
23914#[doc = "  * Neon instrinsic unsafe"]
23915#[inline]
23916#[cfg(target_arch = "arm")]
23917#[target_feature(enable = "neon,v7")]
23918#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23919#[rustc_legacy_const_generics(2)]
23920#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23921pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23922    static_assert_uimm_bits!(LANE, 3);
23923    unsafe extern "unadjusted" {
23924        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")]
23925        fn _vld3_lane_s8(
23926            ptr: *const i8,
23927            a: int8x8_t,
23928            b: int8x8_t,
23929            c: int8x8_t,
23930            n: i32,
23931            size: i32,
23932        ) -> int8x8x3_t;
23933    }
23934    _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
23935}
23936#[doc = "Load multiple 3-element structures to two registers"]
23937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23938#[doc = "## Safety"]
23939#[doc = "  * Neon instrinsic unsafe"]
23940#[inline]
23941#[cfg(target_arch = "arm")]
23942#[target_feature(enable = "neon,v7")]
23943#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23944#[rustc_legacy_const_generics(2)]
23945#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23946pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23947    static_assert_uimm_bits!(LANE, 2);
23948    unsafe extern "unadjusted" {
23949        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")]
23950        fn _vld3_lane_s16(
23951            ptr: *const i8,
23952            a: int16x4_t,
23953            b: int16x4_t,
23954            c: int16x4_t,
23955            n: i32,
23956            size: i32,
23957        ) -> int16x4x3_t;
23958    }
23959    _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23960}
23961#[doc = "Load multiple 3-element structures to two registers"]
23962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23963#[doc = "## Safety"]
23964#[doc = "  * Neon instrinsic unsafe"]
23965#[inline]
23966#[cfg(target_arch = "arm")]
23967#[target_feature(enable = "neon,v7")]
23968#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23969#[rustc_legacy_const_generics(2)]
23970#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23971pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23972    static_assert_uimm_bits!(LANE, 3);
23973    unsafe extern "unadjusted" {
23974        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")]
23975        fn _vld3q_lane_s16(
23976            ptr: *const i8,
23977            a: int16x8_t,
23978            b: int16x8_t,
23979            c: int16x8_t,
23980            n: i32,
23981            size: i32,
23982        ) -> int16x8x3_t;
23983    }
23984    _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23985}
23986#[doc = "Load multiple 3-element structures to two registers"]
23987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23988#[doc = "## Safety"]
23989#[doc = "  * Neon instrinsic unsafe"]
23990#[inline]
23991#[cfg(target_arch = "arm")]
23992#[target_feature(enable = "neon,v7")]
23993#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23994#[rustc_legacy_const_generics(2)]
23995#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23996pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23997    static_assert_uimm_bits!(LANE, 1);
23998    unsafe extern "unadjusted" {
23999        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")]
24000        fn _vld3_lane_s32(
24001            ptr: *const i8,
24002            a: int32x2_t,
24003            b: int32x2_t,
24004            c: int32x2_t,
24005            n: i32,
24006            size: i32,
24007        ) -> int32x2x3_t;
24008    }
24009    _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
24010}
24011#[doc = "Load multiple 3-element structures to two registers"]
24012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
24013#[doc = "## Safety"]
24014#[doc = "  * Neon instrinsic unsafe"]
24015#[inline]
24016#[cfg(target_arch = "arm")]
24017#[target_feature(enable = "neon,v7")]
24018#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24019#[rustc_legacy_const_generics(2)]
24020#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24021pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
24022    static_assert_uimm_bits!(LANE, 2);
24023    unsafe extern "unadjusted" {
24024        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")]
24025        fn _vld3q_lane_s32(
24026            ptr: *const i8,
24027            a: int32x4_t,
24028            b: int32x4_t,
24029            c: int32x4_t,
24030            n: i32,
24031            size: i32,
24032        ) -> int32x4x3_t;
24033    }
24034    _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
24035}
24036#[doc = "Load multiple 3-element structures to three registers"]
24037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
24038#[doc = "## Safety"]
24039#[doc = "  * Neon instrinsic unsafe"]
24040#[inline]
24041#[target_feature(enable = "neon")]
24042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24044#[cfg_attr(
24045    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24046    assert_instr(ld3, LANE = 0)
24047)]
24048#[rustc_legacy_const_generics(2)]
24049#[cfg_attr(
24050    not(target_arch = "arm"),
24051    stable(feature = "neon_intrinsics", since = "1.59.0")
24052)]
24053#[cfg_attr(
24054    target_arch = "arm",
24055    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24056)]
24057pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t {
24058    static_assert_uimm_bits!(LANE, 3);
24059    transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24060}
24061#[doc = "Load multiple 3-element structures to three registers"]
24062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
24063#[doc = "## Safety"]
24064#[doc = "  * Neon instrinsic unsafe"]
24065#[inline]
24066#[target_feature(enable = "neon")]
24067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24069#[cfg_attr(
24070    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24071    assert_instr(ld3, LANE = 0)
24072)]
24073#[rustc_legacy_const_generics(2)]
24074#[cfg_attr(
24075    not(target_arch = "arm"),
24076    stable(feature = "neon_intrinsics", since = "1.59.0")
24077)]
24078#[cfg_attr(
24079    target_arch = "arm",
24080    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24081)]
24082pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t {
24083    static_assert_uimm_bits!(LANE, 2);
24084    transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24085}
24086#[doc = "Load multiple 3-element structures to three registers"]
24087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
24088#[doc = "## Safety"]
24089#[doc = "  * Neon instrinsic unsafe"]
24090#[inline]
24091#[target_feature(enable = "neon")]
24092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24094#[cfg_attr(
24095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24096    assert_instr(ld3, LANE = 0)
24097)]
24098#[rustc_legacy_const_generics(2)]
24099#[cfg_attr(
24100    not(target_arch = "arm"),
24101    stable(feature = "neon_intrinsics", since = "1.59.0")
24102)]
24103#[cfg_attr(
24104    target_arch = "arm",
24105    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24106)]
24107pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t {
24108    static_assert_uimm_bits!(LANE, 3);
24109    transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24110}
24111#[doc = "Load multiple 3-element structures to three registers"]
24112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
24113#[doc = "## Safety"]
24114#[doc = "  * Neon instrinsic unsafe"]
24115#[inline]
24116#[target_feature(enable = "neon")]
24117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24119#[cfg_attr(
24120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24121    assert_instr(ld3, LANE = 0)
24122)]
24123#[rustc_legacy_const_generics(2)]
24124#[cfg_attr(
24125    not(target_arch = "arm"),
24126    stable(feature = "neon_intrinsics", since = "1.59.0")
24127)]
24128#[cfg_attr(
24129    target_arch = "arm",
24130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24131)]
24132pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t {
24133    static_assert_uimm_bits!(LANE, 1);
24134    transmute(vld3_lane_s32::<LANE>(transmute(a), transmute(b)))
24135}
24136#[doc = "Load multiple 3-element structures to three registers"]
24137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
24138#[doc = "## Safety"]
24139#[doc = "  * Neon instrinsic unsafe"]
24140#[inline]
24141#[target_feature(enable = "neon")]
24142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24144#[cfg_attr(
24145    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24146    assert_instr(ld3, LANE = 0)
24147)]
24148#[rustc_legacy_const_generics(2)]
24149#[cfg_attr(
24150    not(target_arch = "arm"),
24151    stable(feature = "neon_intrinsics", since = "1.59.0")
24152)]
24153#[cfg_attr(
24154    target_arch = "arm",
24155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24156)]
24157pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t {
24158    static_assert_uimm_bits!(LANE, 2);
24159    transmute(vld3q_lane_s32::<LANE>(transmute(a), transmute(b)))
24160}
24161#[doc = "Load multiple 3-element structures to three registers"]
24162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
24163#[doc = "## Safety"]
24164#[doc = "  * Neon instrinsic unsafe"]
24165#[inline]
24166#[target_feature(enable = "neon")]
24167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24169#[cfg_attr(
24170    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24171    assert_instr(ld3, LANE = 0)
24172)]
24173#[rustc_legacy_const_generics(2)]
24174#[cfg_attr(
24175    not(target_arch = "arm"),
24176    stable(feature = "neon_intrinsics", since = "1.59.0")
24177)]
24178#[cfg_attr(
24179    target_arch = "arm",
24180    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24181)]
24182pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t {
24183    static_assert_uimm_bits!(LANE, 3);
24184    transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24185}
24186#[doc = "Load multiple 3-element structures to three registers"]
24187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
24188#[doc = "## Safety"]
24189#[doc = "  * Neon instrinsic unsafe"]
24190#[inline]
24191#[target_feature(enable = "neon")]
24192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24194#[cfg_attr(
24195    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24196    assert_instr(ld3, LANE = 0)
24197)]
24198#[rustc_legacy_const_generics(2)]
24199#[cfg_attr(
24200    not(target_arch = "arm"),
24201    stable(feature = "neon_intrinsics", since = "1.59.0")
24202)]
24203#[cfg_attr(
24204    target_arch = "arm",
24205    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24206)]
24207pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t {
24208    static_assert_uimm_bits!(LANE, 2);
24209    transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24210}
24211#[doc = "Load multiple 3-element structures to three registers"]
24212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
24213#[doc = "## Safety"]
24214#[doc = "  * Neon instrinsic unsafe"]
24215#[inline]
24216#[target_feature(enable = "neon")]
24217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24219#[cfg_attr(
24220    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24221    assert_instr(ld3, LANE = 0)
24222)]
24223#[rustc_legacy_const_generics(2)]
24224#[cfg_attr(
24225    not(target_arch = "arm"),
24226    stable(feature = "neon_intrinsics", since = "1.59.0")
24227)]
24228#[cfg_attr(
24229    target_arch = "arm",
24230    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24231)]
24232pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t {
24233    static_assert_uimm_bits!(LANE, 3);
24234    transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24235}
24236#[doc = "Load multiple 3-element structures to three registers"]
24237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
24238#[doc = "## Safety"]
24239#[doc = "  * Neon instrinsic unsafe"]
24240#[inline]
24241#[target_feature(enable = "neon,aes")]
24242#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
24243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24244#[cfg_attr(
24245    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24246    assert_instr(nop)
24247)]
24248#[cfg_attr(
24249    not(target_arch = "arm"),
24250    stable(feature = "neon_intrinsics", since = "1.59.0")
24251)]
24252#[cfg_attr(
24253    target_arch = "arm",
24254    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24255)]
24256pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
24257    transmute(vld3_s64(transmute(a)))
24258}
24259#[doc = "Load multiple 3-element structures to three registers"]
24260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24261#[doc = "## Safety"]
24262#[doc = "  * Neon instrinsic unsafe"]
24263#[inline]
24264#[target_feature(enable = "neon")]
24265#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24266#[cfg(not(target_arch = "arm"))]
24267#[cfg_attr(test, assert_instr(nop))]
24268pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24269    unsafe extern "unadjusted" {
24270        #[cfg_attr(
24271            any(target_arch = "aarch64", target_arch = "arm64ec"),
24272            link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
24273        )]
24274        fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
24275    }
24276    _vld3_s64(a as _)
24277}
24278#[doc = "Load multiple 3-element structures to three registers"]
24279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24280#[doc = "## Safety"]
24281#[doc = "  * Neon instrinsic unsafe"]
24282#[inline]
24283#[cfg(target_arch = "arm")]
24284#[target_feature(enable = "neon,v7")]
24285#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24286#[cfg_attr(test, assert_instr(nop))]
24287pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24288    unsafe extern "unadjusted" {
24289        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")]
24290        fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
24291    }
24292    _vld3_s64(a as *const i8, 8)
24293}
24294#[doc = "Load multiple 3-element structures to three registers"]
24295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
24296#[doc = "## Safety"]
24297#[doc = "  * Neon instrinsic unsafe"]
24298#[inline]
24299#[target_feature(enable = "neon")]
24300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24302#[cfg_attr(
24303    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24304    assert_instr(nop)
24305)]
24306#[cfg_attr(
24307    not(target_arch = "arm"),
24308    stable(feature = "neon_intrinsics", since = "1.59.0")
24309)]
24310#[cfg_attr(
24311    target_arch = "arm",
24312    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24313)]
24314pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
24315    transmute(vld3_s64(transmute(a)))
24316}
24317#[doc = "Load multiple 3-element structures to three registers"]
24318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24319#[doc = "## Safety"]
24320#[doc = "  * Neon instrinsic unsafe"]
24321#[inline]
24322#[cfg(target_endian = "little")]
24323#[target_feature(enable = "neon")]
24324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24326#[cfg_attr(
24327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24328    assert_instr(ld3)
24329)]
24330#[cfg_attr(
24331    not(target_arch = "arm"),
24332    stable(feature = "neon_intrinsics", since = "1.59.0")
24333)]
24334#[cfg_attr(
24335    target_arch = "arm",
24336    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24337)]
24338pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24339    transmute(vld3_s8(transmute(a)))
24340}
24341#[doc = "Load multiple 3-element structures to three registers"]
24342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24343#[doc = "## Safety"]
24344#[doc = "  * Neon instrinsic unsafe"]
24345#[inline]
24346#[cfg(target_endian = "big")]
24347#[target_feature(enable = "neon")]
24348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24350#[cfg_attr(
24351    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24352    assert_instr(ld3)
24353)]
24354#[cfg_attr(
24355    not(target_arch = "arm"),
24356    stable(feature = "neon_intrinsics", since = "1.59.0")
24357)]
24358#[cfg_attr(
24359    target_arch = "arm",
24360    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24361)]
24362pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24363    let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
24364    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24365    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24366    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24367    ret_val
24368}
24369#[doc = "Load multiple 3-element structures to three registers"]
24370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24371#[doc = "## Safety"]
24372#[doc = "  * Neon instrinsic unsafe"]
24373#[inline]
24374#[cfg(target_endian = "little")]
24375#[target_feature(enable = "neon")]
24376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24378#[cfg_attr(
24379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24380    assert_instr(ld3)
24381)]
24382#[cfg_attr(
24383    not(target_arch = "arm"),
24384    stable(feature = "neon_intrinsics", since = "1.59.0")
24385)]
24386#[cfg_attr(
24387    target_arch = "arm",
24388    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24389)]
24390pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24391    transmute(vld3q_s8(transmute(a)))
24392}
24393#[doc = "Load multiple 3-element structures to three registers"]
24394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24395#[doc = "## Safety"]
24396#[doc = "  * Neon instrinsic unsafe"]
24397#[inline]
24398#[cfg(target_endian = "big")]
24399#[target_feature(enable = "neon")]
24400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24402#[cfg_attr(
24403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24404    assert_instr(ld3)
24405)]
24406#[cfg_attr(
24407    not(target_arch = "arm"),
24408    stable(feature = "neon_intrinsics", since = "1.59.0")
24409)]
24410#[cfg_attr(
24411    target_arch = "arm",
24412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24413)]
24414pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24415    let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
24416    ret_val.0 = unsafe {
24417        simd_shuffle!(
24418            ret_val.0,
24419            ret_val.0,
24420            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24421        )
24422    };
24423    ret_val.1 = unsafe {
24424        simd_shuffle!(
24425            ret_val.1,
24426            ret_val.1,
24427            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24428        )
24429    };
24430    ret_val.2 = unsafe {
24431        simd_shuffle!(
24432            ret_val.2,
24433            ret_val.2,
24434            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24435        )
24436    };
24437    ret_val
24438}
24439#[doc = "Load multiple 3-element structures to three registers"]
24440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24441#[doc = "## Safety"]
24442#[doc = "  * Neon instrinsic unsafe"]
24443#[inline]
24444#[cfg(target_endian = "little")]
24445#[target_feature(enable = "neon")]
24446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24448#[cfg_attr(
24449    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24450    assert_instr(ld3)
24451)]
24452#[cfg_attr(
24453    not(target_arch = "arm"),
24454    stable(feature = "neon_intrinsics", since = "1.59.0")
24455)]
24456#[cfg_attr(
24457    target_arch = "arm",
24458    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24459)]
24460pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24461    transmute(vld3_s16(transmute(a)))
24462}
24463#[doc = "Load multiple 3-element structures to three registers"]
24464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24465#[doc = "## Safety"]
24466#[doc = "  * Neon instrinsic unsafe"]
24467#[inline]
24468#[cfg(target_endian = "big")]
24469#[target_feature(enable = "neon")]
24470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24472#[cfg_attr(
24473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24474    assert_instr(ld3)
24475)]
24476#[cfg_attr(
24477    not(target_arch = "arm"),
24478    stable(feature = "neon_intrinsics", since = "1.59.0")
24479)]
24480#[cfg_attr(
24481    target_arch = "arm",
24482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24483)]
24484pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24485    let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
24486    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24487    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24488    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24489    ret_val
24490}
24491#[doc = "Load multiple 3-element structures to three registers"]
24492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24493#[doc = "## Safety"]
24494#[doc = "  * Neon instrinsic unsafe"]
24495#[inline]
24496#[cfg(target_endian = "little")]
24497#[target_feature(enable = "neon")]
24498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24500#[cfg_attr(
24501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24502    assert_instr(ld3)
24503)]
24504#[cfg_attr(
24505    not(target_arch = "arm"),
24506    stable(feature = "neon_intrinsics", since = "1.59.0")
24507)]
24508#[cfg_attr(
24509    target_arch = "arm",
24510    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24511)]
24512pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24513    transmute(vld3q_s16(transmute(a)))
24514}
24515#[doc = "Load multiple 3-element structures to three registers"]
24516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24517#[doc = "## Safety"]
24518#[doc = "  * Neon instrinsic unsafe"]
24519#[inline]
24520#[cfg(target_endian = "big")]
24521#[target_feature(enable = "neon")]
24522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24524#[cfg_attr(
24525    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24526    assert_instr(ld3)
24527)]
24528#[cfg_attr(
24529    not(target_arch = "arm"),
24530    stable(feature = "neon_intrinsics", since = "1.59.0")
24531)]
24532#[cfg_attr(
24533    target_arch = "arm",
24534    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24535)]
24536pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24537    let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
24538    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24539    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24540    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24541    ret_val
24542}
24543#[doc = "Load multiple 3-element structures to three registers"]
24544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24545#[doc = "## Safety"]
24546#[doc = "  * Neon instrinsic unsafe"]
24547#[inline]
24548#[cfg(target_endian = "little")]
24549#[target_feature(enable = "neon")]
24550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24552#[cfg_attr(
24553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24554    assert_instr(ld3)
24555)]
24556#[cfg_attr(
24557    not(target_arch = "arm"),
24558    stable(feature = "neon_intrinsics", since = "1.59.0")
24559)]
24560#[cfg_attr(
24561    target_arch = "arm",
24562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24563)]
24564pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24565    transmute(vld3_s32(transmute(a)))
24566}
24567#[doc = "Load multiple 3-element structures to three registers"]
24568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24569#[doc = "## Safety"]
24570#[doc = "  * Neon instrinsic unsafe"]
24571#[inline]
24572#[cfg(target_endian = "big")]
24573#[target_feature(enable = "neon")]
24574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24576#[cfg_attr(
24577    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24578    assert_instr(ld3)
24579)]
24580#[cfg_attr(
24581    not(target_arch = "arm"),
24582    stable(feature = "neon_intrinsics", since = "1.59.0")
24583)]
24584#[cfg_attr(
24585    target_arch = "arm",
24586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24587)]
24588pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24589    let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
24590    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
24591    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
24592    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
24593    ret_val
24594}
24595#[doc = "Load multiple 3-element structures to three registers"]
24596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24597#[doc = "## Safety"]
24598#[doc = "  * Neon instrinsic unsafe"]
24599#[inline]
24600#[cfg(target_endian = "little")]
24601#[target_feature(enable = "neon")]
24602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24604#[cfg_attr(
24605    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24606    assert_instr(ld3)
24607)]
24608#[cfg_attr(
24609    not(target_arch = "arm"),
24610    stable(feature = "neon_intrinsics", since = "1.59.0")
24611)]
24612#[cfg_attr(
24613    target_arch = "arm",
24614    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24615)]
24616pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24617    transmute(vld3q_s32(transmute(a)))
24618}
24619#[doc = "Load multiple 3-element structures to three registers"]
24620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24621#[doc = "## Safety"]
24622#[doc = "  * Neon instrinsic unsafe"]
24623#[inline]
24624#[cfg(target_endian = "big")]
24625#[target_feature(enable = "neon")]
24626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24628#[cfg_attr(
24629    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24630    assert_instr(ld3)
24631)]
24632#[cfg_attr(
24633    not(target_arch = "arm"),
24634    stable(feature = "neon_intrinsics", since = "1.59.0")
24635)]
24636#[cfg_attr(
24637    target_arch = "arm",
24638    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24639)]
24640pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24641    let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
24642    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24643    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24644    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24645    ret_val
24646}
24647#[doc = "Load multiple 3-element structures to three registers"]
24648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24649#[doc = "## Safety"]
24650#[doc = "  * Neon instrinsic unsafe"]
24651#[inline]
24652#[cfg(target_endian = "little")]
24653#[target_feature(enable = "neon")]
24654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24656#[cfg_attr(
24657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24658    assert_instr(ld3)
24659)]
24660#[cfg_attr(
24661    not(target_arch = "arm"),
24662    stable(feature = "neon_intrinsics", since = "1.59.0")
24663)]
24664#[cfg_attr(
24665    target_arch = "arm",
24666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24667)]
24668pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24669    transmute(vld3_s8(transmute(a)))
24670}
24671#[doc = "Load multiple 3-element structures to three registers"]
24672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24673#[doc = "## Safety"]
24674#[doc = "  * Neon instrinsic unsafe"]
24675#[inline]
24676#[cfg(target_endian = "big")]
24677#[target_feature(enable = "neon")]
24678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24680#[cfg_attr(
24681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24682    assert_instr(ld3)
24683)]
24684#[cfg_attr(
24685    not(target_arch = "arm"),
24686    stable(feature = "neon_intrinsics", since = "1.59.0")
24687)]
24688#[cfg_attr(
24689    target_arch = "arm",
24690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24691)]
24692pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24693    let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
24694    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24695    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24696    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24697    ret_val
24698}
24699#[doc = "Load multiple 3-element structures to three registers"]
24700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24701#[doc = "## Safety"]
24702#[doc = "  * Neon instrinsic unsafe"]
24703#[inline]
24704#[cfg(target_endian = "little")]
24705#[target_feature(enable = "neon")]
24706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24708#[cfg_attr(
24709    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24710    assert_instr(ld3)
24711)]
24712#[cfg_attr(
24713    not(target_arch = "arm"),
24714    stable(feature = "neon_intrinsics", since = "1.59.0")
24715)]
24716#[cfg_attr(
24717    target_arch = "arm",
24718    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24719)]
24720pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24721    transmute(vld3q_s8(transmute(a)))
24722}
24723#[doc = "Load multiple 3-element structures to three registers"]
24724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24725#[doc = "## Safety"]
24726#[doc = "  * Neon instrinsic unsafe"]
24727#[inline]
24728#[cfg(target_endian = "big")]
24729#[target_feature(enable = "neon")]
24730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24732#[cfg_attr(
24733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24734    assert_instr(ld3)
24735)]
24736#[cfg_attr(
24737    not(target_arch = "arm"),
24738    stable(feature = "neon_intrinsics", since = "1.59.0")
24739)]
24740#[cfg_attr(
24741    target_arch = "arm",
24742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24743)]
24744pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24745    let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
24746    ret_val.0 = unsafe {
24747        simd_shuffle!(
24748            ret_val.0,
24749            ret_val.0,
24750            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24751        )
24752    };
24753    ret_val.1 = unsafe {
24754        simd_shuffle!(
24755            ret_val.1,
24756            ret_val.1,
24757            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24758        )
24759    };
24760    ret_val.2 = unsafe {
24761        simd_shuffle!(
24762            ret_val.2,
24763            ret_val.2,
24764            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24765        )
24766    };
24767    ret_val
24768}
24769#[doc = "Load multiple 3-element structures to three registers"]
24770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24771#[doc = "## Safety"]
24772#[doc = "  * Neon instrinsic unsafe"]
24773#[inline]
24774#[cfg(target_endian = "little")]
24775#[target_feature(enable = "neon")]
24776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24778#[cfg_attr(
24779    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24780    assert_instr(ld3)
24781)]
24782#[cfg_attr(
24783    not(target_arch = "arm"),
24784    stable(feature = "neon_intrinsics", since = "1.59.0")
24785)]
24786#[cfg_attr(
24787    target_arch = "arm",
24788    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24789)]
24790pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24791    transmute(vld3_s16(transmute(a)))
24792}
24793#[doc = "Load multiple 3-element structures to three registers"]
24794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24795#[doc = "## Safety"]
24796#[doc = "  * Neon instrinsic unsafe"]
24797#[inline]
24798#[cfg(target_endian = "big")]
24799#[target_feature(enable = "neon")]
24800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24802#[cfg_attr(
24803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24804    assert_instr(ld3)
24805)]
24806#[cfg_attr(
24807    not(target_arch = "arm"),
24808    stable(feature = "neon_intrinsics", since = "1.59.0")
24809)]
24810#[cfg_attr(
24811    target_arch = "arm",
24812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24813)]
24814pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24815    let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
24816    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24817    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24818    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24819    ret_val
24820}
24821#[doc = "Load multiple 3-element structures to three registers"]
24822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24823#[doc = "## Safety"]
24824#[doc = "  * Neon instrinsic unsafe"]
24825#[inline]
24826#[cfg(target_endian = "little")]
24827#[target_feature(enable = "neon")]
24828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24830#[cfg_attr(
24831    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24832    assert_instr(ld3)
24833)]
24834#[cfg_attr(
24835    not(target_arch = "arm"),
24836    stable(feature = "neon_intrinsics", since = "1.59.0")
24837)]
24838#[cfg_attr(
24839    target_arch = "arm",
24840    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24841)]
24842pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24843    transmute(vld3q_s16(transmute(a)))
24844}
24845#[doc = "Load multiple 3-element structures to three registers"]
24846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24847#[doc = "## Safety"]
24848#[doc = "  * Neon instrinsic unsafe"]
24849#[inline]
24850#[cfg(target_endian = "big")]
24851#[target_feature(enable = "neon")]
24852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24854#[cfg_attr(
24855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24856    assert_instr(ld3)
24857)]
24858#[cfg_attr(
24859    not(target_arch = "arm"),
24860    stable(feature = "neon_intrinsics", since = "1.59.0")
24861)]
24862#[cfg_attr(
24863    target_arch = "arm",
24864    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24865)]
24866pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24867    let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
24868    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24869    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24870    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24871    ret_val
24872}
24873#[doc = "Load multiple 3-element structures to three registers"]
24874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
24875#[doc = "## Safety"]
24876#[doc = "  * Neon instrinsic unsafe"]
24877#[inline]
24878#[cfg(target_arch = "arm")]
24879#[target_feature(enable = "neon,v7")]
24880#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24881#[rustc_legacy_const_generics(2)]
24882#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24883pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
24884    static_assert_uimm_bits!(LANE, 2);
24885    unsafe extern "unadjusted" {
24886        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
24887        fn _vld3q_lane_f32(
24888            ptr: *const i8,
24889            a: float32x4_t,
24890            b: float32x4_t,
24891            c: float32x4_t,
24892            n: i32,
24893            size: i32,
24894        ) -> float32x4x3_t;
24895    }
24896    _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
24897}
24898#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24900#[doc = "## Safety"]
24901#[doc = "  * Neon instrinsic unsafe"]
24902#[inline]
24903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24904#[cfg(target_arch = "arm")]
24905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24906#[target_feature(enable = "neon,fp16")]
24907#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24908pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24909    unsafe extern "unadjusted" {
24910        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0f16")]
24911        fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
24912    }
24913    _vld4_dup_f16(a as _, 2)
24914}
24915#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24917#[doc = "## Safety"]
24918#[doc = "  * Neon instrinsic unsafe"]
24919#[inline]
24920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24921#[cfg(target_arch = "arm")]
24922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24923#[target_feature(enable = "neon,fp16")]
24924#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24925pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24926    unsafe extern "unadjusted" {
24927        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0f16")]
24928        fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
24929    }
24930    _vld4q_dup_f16(a as _, 2)
24931}
24932#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24934#[doc = "## Safety"]
24935#[doc = "  * Neon instrinsic unsafe"]
24936#[inline]
24937#[cfg(not(target_arch = "arm"))]
24938#[cfg_attr(
24939    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24940    assert_instr(ld4r)
24941)]
24942#[target_feature(enable = "neon,fp16")]
24943#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24944pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24945    unsafe extern "unadjusted" {
24946        #[cfg_attr(
24947            any(target_arch = "aarch64", target_arch = "arm64ec"),
24948            link_name = "llvm.aarch64.neon.ld4r.v4f16.p0f16"
24949        )]
24950        fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
24951    }
24952    _vld4_dup_f16(a as _)
24953}
24954#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24956#[doc = "## Safety"]
24957#[doc = "  * Neon instrinsic unsafe"]
24958#[inline]
24959#[cfg(not(target_arch = "arm"))]
24960#[cfg_attr(
24961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24962    assert_instr(ld4r)
24963)]
24964#[target_feature(enable = "neon,fp16")]
24965#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24966pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24967    unsafe extern "unadjusted" {
24968        #[cfg_attr(
24969            any(target_arch = "aarch64", target_arch = "arm64ec"),
24970            link_name = "llvm.aarch64.neon.ld4r.v8f16.p0f16"
24971        )]
24972        fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
24973    }
24974    _vld4q_dup_f16(a as _)
24975}
24976#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
24978#[doc = "## Safety"]
24979#[doc = "  * Neon instrinsic unsafe"]
24980#[inline]
24981#[cfg(target_arch = "arm")]
24982#[target_feature(enable = "neon,v7")]
24983#[cfg_attr(test, assert_instr(vld4))]
24984#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24985pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
24986    unsafe extern "unadjusted" {
24987        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")]
24988        fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
24989    }
24990    _vld4_dup_f32(a as *const i8, 4)
24991}
24992#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
24994#[doc = "## Safety"]
24995#[doc = "  * Neon instrinsic unsafe"]
24996#[inline]
24997#[cfg(target_arch = "arm")]
24998#[target_feature(enable = "neon,v7")]
24999#[cfg_attr(test, assert_instr(vld4))]
25000#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25001pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
25002    unsafe extern "unadjusted" {
25003        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")]
25004        fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
25005    }
25006    _vld4q_dup_f32(a as *const i8, 4)
25007}
25008#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
25010#[doc = "## Safety"]
25011#[doc = "  * Neon instrinsic unsafe"]
25012#[inline]
25013#[cfg(target_arch = "arm")]
25014#[target_feature(enable = "neon,v7")]
25015#[cfg_attr(test, assert_instr(vld4))]
25016#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25017pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25018    unsafe extern "unadjusted" {
25019        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")]
25020        fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
25021    }
25022    _vld4_dup_s8(a as *const i8, 1)
25023}
25024#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25026#[doc = "## Safety"]
25027#[doc = "  * Neon instrinsic unsafe"]
25028#[inline]
25029#[cfg(target_arch = "arm")]
25030#[target_feature(enable = "neon,v7")]
25031#[cfg_attr(test, assert_instr(vld4))]
25032#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25033pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25034    unsafe extern "unadjusted" {
25035        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")]
25036        fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
25037    }
25038    _vld4q_dup_s8(a as *const i8, 1)
25039}
25040#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25042#[doc = "## Safety"]
25043#[doc = "  * Neon instrinsic unsafe"]
25044#[inline]
25045#[cfg(target_arch = "arm")]
25046#[target_feature(enable = "neon,v7")]
25047#[cfg_attr(test, assert_instr(vld4))]
25048#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25049pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25050    unsafe extern "unadjusted" {
25051        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")]
25052        fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
25053    }
25054    _vld4_dup_s16(a as *const i8, 2)
25055}
25056#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25058#[doc = "## Safety"]
25059#[doc = "  * Neon instrinsic unsafe"]
25060#[inline]
25061#[cfg(target_arch = "arm")]
25062#[target_feature(enable = "neon,v7")]
25063#[cfg_attr(test, assert_instr(vld4))]
25064#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25065pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25066    unsafe extern "unadjusted" {
25067        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")]
25068        fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
25069    }
25070    _vld4q_dup_s16(a as *const i8, 2)
25071}
25072#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25074#[doc = "## Safety"]
25075#[doc = "  * Neon instrinsic unsafe"]
25076#[inline]
25077#[cfg(target_arch = "arm")]
25078#[target_feature(enable = "neon,v7")]
25079#[cfg_attr(test, assert_instr(vld4))]
25080#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25081pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25082    unsafe extern "unadjusted" {
25083        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")]
25084        fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
25085    }
25086    _vld4_dup_s32(a as *const i8, 4)
25087}
25088#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25090#[doc = "## Safety"]
25091#[doc = "  * Neon instrinsic unsafe"]
25092#[inline]
25093#[cfg(target_arch = "arm")]
25094#[target_feature(enable = "neon,v7")]
25095#[cfg_attr(test, assert_instr(vld4))]
25096#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25097pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25098    unsafe extern "unadjusted" {
25099        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")]
25100        fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
25101    }
25102    _vld4q_dup_s32(a as *const i8, 4)
25103}
25104#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
25106#[doc = "## Safety"]
25107#[doc = "  * Neon instrinsic unsafe"]
25108#[inline]
25109#[target_feature(enable = "neon")]
25110#[cfg(not(target_arch = "arm"))]
25111#[cfg_attr(test, assert_instr(ld4r))]
25112#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25113pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
25114    unsafe extern "unadjusted" {
25115        #[cfg_attr(
25116            any(target_arch = "aarch64", target_arch = "arm64ec"),
25117            link_name = "llvm.aarch64.neon.ld4r.v2f32.p0f32.p0"
25118        )]
25119        fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t;
25120    }
25121    _vld4_dup_f32(a as _)
25122}
25123#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
25125#[doc = "## Safety"]
25126#[doc = "  * Neon instrinsic unsafe"]
25127#[inline]
25128#[target_feature(enable = "neon")]
25129#[cfg(not(target_arch = "arm"))]
25130#[cfg_attr(test, assert_instr(ld4r))]
25131#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25132pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
25133    unsafe extern "unadjusted" {
25134        #[cfg_attr(
25135            any(target_arch = "aarch64", target_arch = "arm64ec"),
25136            link_name = "llvm.aarch64.neon.ld4r.v4f32.p0f32.p0"
25137        )]
25138        fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t;
25139    }
25140    _vld4q_dup_f32(a as _)
25141}
25142#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
25144#[doc = "## Safety"]
25145#[doc = "  * Neon instrinsic unsafe"]
25146#[inline]
25147#[target_feature(enable = "neon")]
25148#[cfg(not(target_arch = "arm"))]
25149#[cfg_attr(test, assert_instr(ld4r))]
25150#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25151pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25152    unsafe extern "unadjusted" {
25153        #[cfg_attr(
25154            any(target_arch = "aarch64", target_arch = "arm64ec"),
25155            link_name = "llvm.aarch64.neon.ld4r.v8i8.p0i8.p0"
25156        )]
25157        fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t;
25158    }
25159    _vld4_dup_s8(a as _)
25160}
25161#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25163#[doc = "## Safety"]
25164#[doc = "  * Neon instrinsic unsafe"]
25165#[inline]
25166#[target_feature(enable = "neon")]
25167#[cfg(not(target_arch = "arm"))]
25168#[cfg_attr(test, assert_instr(ld4r))]
25169#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25170pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25171    unsafe extern "unadjusted" {
25172        #[cfg_attr(
25173            any(target_arch = "aarch64", target_arch = "arm64ec"),
25174            link_name = "llvm.aarch64.neon.ld4r.v16i8.p0i8.p0"
25175        )]
25176        fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t;
25177    }
25178    _vld4q_dup_s8(a as _)
25179}
25180#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25182#[doc = "## Safety"]
25183#[doc = "  * Neon instrinsic unsafe"]
25184#[inline]
25185#[target_feature(enable = "neon")]
25186#[cfg(not(target_arch = "arm"))]
25187#[cfg_attr(test, assert_instr(ld4r))]
25188#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25189pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25190    unsafe extern "unadjusted" {
25191        #[cfg_attr(
25192            any(target_arch = "aarch64", target_arch = "arm64ec"),
25193            link_name = "llvm.aarch64.neon.ld4r.v4i16.p0i16.p0"
25194        )]
25195        fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t;
25196    }
25197    _vld4_dup_s16(a as _)
25198}
25199#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25201#[doc = "## Safety"]
25202#[doc = "  * Neon instrinsic unsafe"]
25203#[inline]
25204#[target_feature(enable = "neon")]
25205#[cfg(not(target_arch = "arm"))]
25206#[cfg_attr(test, assert_instr(ld4r))]
25207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25208pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25209    unsafe extern "unadjusted" {
25210        #[cfg_attr(
25211            any(target_arch = "aarch64", target_arch = "arm64ec"),
25212            link_name = "llvm.aarch64.neon.ld4r.v8i16.p0i16.p0"
25213        )]
25214        fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t;
25215    }
25216    _vld4q_dup_s16(a as _)
25217}
25218#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25220#[doc = "## Safety"]
25221#[doc = "  * Neon instrinsic unsafe"]
25222#[inline]
25223#[target_feature(enable = "neon")]
25224#[cfg(not(target_arch = "arm"))]
25225#[cfg_attr(test, assert_instr(ld4r))]
25226#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25227pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25228    unsafe extern "unadjusted" {
25229        #[cfg_attr(
25230            any(target_arch = "aarch64", target_arch = "arm64ec"),
25231            link_name = "llvm.aarch64.neon.ld4r.v2i32.p0i32.p0"
25232        )]
25233        fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t;
25234    }
25235    _vld4_dup_s32(a as _)
25236}
25237#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25239#[doc = "## Safety"]
25240#[doc = "  * Neon instrinsic unsafe"]
25241#[inline]
25242#[target_feature(enable = "neon")]
25243#[cfg(not(target_arch = "arm"))]
25244#[cfg_attr(test, assert_instr(ld4r))]
25245#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25246pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25247    unsafe extern "unadjusted" {
25248        #[cfg_attr(
25249            any(target_arch = "aarch64", target_arch = "arm64ec"),
25250            link_name = "llvm.aarch64.neon.ld4r.v4i32.p0i32.p0"
25251        )]
25252        fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t;
25253    }
25254    _vld4q_dup_s32(a as _)
25255}
25256#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25258#[doc = "## Safety"]
25259#[doc = "  * Neon instrinsic unsafe"]
25260#[inline]
25261#[target_feature(enable = "neon")]
25262#[cfg(not(target_arch = "arm"))]
25263#[cfg_attr(test, assert_instr(ld4r))]
25264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25265pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25266    unsafe extern "unadjusted" {
25267        #[cfg_attr(
25268            any(target_arch = "aarch64", target_arch = "arm64ec"),
25269            link_name = "llvm.aarch64.neon.ld4r.v1i64.p0i64.p0"
25270        )]
25271        fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t;
25272    }
25273    _vld4_dup_s64(a as _)
25274}
25275#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
25277#[doc = "## Safety"]
25278#[doc = "  * Neon instrinsic unsafe"]
25279#[inline]
25280#[target_feature(enable = "neon,aes")]
25281#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
25282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25283#[cfg_attr(
25284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25285    assert_instr(ld4r)
25286)]
25287#[cfg_attr(
25288    not(target_arch = "arm"),
25289    stable(feature = "neon_intrinsics", since = "1.59.0")
25290)]
25291#[cfg_attr(
25292    target_arch = "arm",
25293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25294)]
25295pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
25296    transmute(vld4_dup_s64(transmute(a)))
25297}
25298#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25300#[doc = "## Safety"]
25301#[doc = "  * Neon instrinsic unsafe"]
25302#[inline]
25303#[cfg(target_arch = "arm")]
25304#[target_feature(enable = "neon,v7")]
25305#[cfg_attr(test, assert_instr(nop))]
25306#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25307pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25308    unsafe extern "unadjusted" {
25309        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")]
25310        fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
25311    }
25312    _vld4_dup_s64(a as *const i8, 8)
25313}
25314#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
25316#[doc = "## Safety"]
25317#[doc = "  * Neon instrinsic unsafe"]
25318#[inline]
25319#[target_feature(enable = "neon")]
25320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25322#[cfg_attr(
25323    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25324    assert_instr(ld4r)
25325)]
25326#[cfg_attr(
25327    not(target_arch = "arm"),
25328    stable(feature = "neon_intrinsics", since = "1.59.0")
25329)]
25330#[cfg_attr(
25331    target_arch = "arm",
25332    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25333)]
25334pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
25335    transmute(vld4_dup_s64(transmute(a)))
25336}
25337#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25339#[doc = "## Safety"]
25340#[doc = "  * Neon instrinsic unsafe"]
25341#[inline]
25342#[cfg(target_endian = "little")]
25343#[target_feature(enable = "neon")]
25344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25346#[cfg_attr(
25347    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25348    assert_instr(ld4r)
25349)]
25350#[cfg_attr(
25351    not(target_arch = "arm"),
25352    stable(feature = "neon_intrinsics", since = "1.59.0")
25353)]
25354#[cfg_attr(
25355    target_arch = "arm",
25356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25357)]
25358pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25359    transmute(vld4_dup_s8(transmute(a)))
25360}
25361#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25363#[doc = "## Safety"]
25364#[doc = "  * Neon instrinsic unsafe"]
25365#[inline]
25366#[cfg(target_endian = "big")]
25367#[target_feature(enable = "neon")]
25368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25370#[cfg_attr(
25371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25372    assert_instr(ld4r)
25373)]
25374#[cfg_attr(
25375    not(target_arch = "arm"),
25376    stable(feature = "neon_intrinsics", since = "1.59.0")
25377)]
25378#[cfg_attr(
25379    target_arch = "arm",
25380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25381)]
25382pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25383    let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25384    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25385    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25386    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25387    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25388    ret_val
25389}
25390#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25392#[doc = "## Safety"]
25393#[doc = "  * Neon instrinsic unsafe"]
25394#[inline]
25395#[cfg(target_endian = "little")]
25396#[target_feature(enable = "neon")]
25397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25399#[cfg_attr(
25400    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25401    assert_instr(ld4r)
25402)]
25403#[cfg_attr(
25404    not(target_arch = "arm"),
25405    stable(feature = "neon_intrinsics", since = "1.59.0")
25406)]
25407#[cfg_attr(
25408    target_arch = "arm",
25409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25410)]
25411pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25412    transmute(vld4q_dup_s8(transmute(a)))
25413}
25414#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25416#[doc = "## Safety"]
25417#[doc = "  * Neon instrinsic unsafe"]
25418#[inline]
25419#[cfg(target_endian = "big")]
25420#[target_feature(enable = "neon")]
25421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25423#[cfg_attr(
25424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25425    assert_instr(ld4r)
25426)]
25427#[cfg_attr(
25428    not(target_arch = "arm"),
25429    stable(feature = "neon_intrinsics", since = "1.59.0")
25430)]
25431#[cfg_attr(
25432    target_arch = "arm",
25433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25434)]
25435pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25436    let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25437    ret_val.0 = unsafe {
25438        simd_shuffle!(
25439            ret_val.0,
25440            ret_val.0,
25441            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25442        )
25443    };
25444    ret_val.1 = unsafe {
25445        simd_shuffle!(
25446            ret_val.1,
25447            ret_val.1,
25448            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25449        )
25450    };
25451    ret_val.2 = unsafe {
25452        simd_shuffle!(
25453            ret_val.2,
25454            ret_val.2,
25455            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25456        )
25457    };
25458    ret_val.3 = unsafe {
25459        simd_shuffle!(
25460            ret_val.3,
25461            ret_val.3,
25462            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25463        )
25464    };
25465    ret_val
25466}
25467#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25469#[doc = "## Safety"]
25470#[doc = "  * Neon instrinsic unsafe"]
25471#[inline]
25472#[cfg(target_endian = "little")]
25473#[target_feature(enable = "neon")]
25474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25476#[cfg_attr(
25477    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25478    assert_instr(ld4r)
25479)]
25480#[cfg_attr(
25481    not(target_arch = "arm"),
25482    stable(feature = "neon_intrinsics", since = "1.59.0")
25483)]
25484#[cfg_attr(
25485    target_arch = "arm",
25486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25487)]
25488pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25489    transmute(vld4_dup_s16(transmute(a)))
25490}
25491#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25493#[doc = "## Safety"]
25494#[doc = "  * Neon instrinsic unsafe"]
25495#[inline]
25496#[cfg(target_endian = "big")]
25497#[target_feature(enable = "neon")]
25498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25500#[cfg_attr(
25501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25502    assert_instr(ld4r)
25503)]
25504#[cfg_attr(
25505    not(target_arch = "arm"),
25506    stable(feature = "neon_intrinsics", since = "1.59.0")
25507)]
25508#[cfg_attr(
25509    target_arch = "arm",
25510    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25511)]
25512pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25513    let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25514    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25515    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25516    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25517    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25518    ret_val
25519}
25520#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25522#[doc = "## Safety"]
25523#[doc = "  * Neon instrinsic unsafe"]
25524#[inline]
25525#[cfg(target_endian = "little")]
25526#[target_feature(enable = "neon")]
25527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25529#[cfg_attr(
25530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25531    assert_instr(ld4r)
25532)]
25533#[cfg_attr(
25534    not(target_arch = "arm"),
25535    stable(feature = "neon_intrinsics", since = "1.59.0")
25536)]
25537#[cfg_attr(
25538    target_arch = "arm",
25539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25540)]
25541pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25542    transmute(vld4q_dup_s16(transmute(a)))
25543}
25544#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25546#[doc = "## Safety"]
25547#[doc = "  * Neon instrinsic unsafe"]
25548#[inline]
25549#[cfg(target_endian = "big")]
25550#[target_feature(enable = "neon")]
25551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25553#[cfg_attr(
25554    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25555    assert_instr(ld4r)
25556)]
25557#[cfg_attr(
25558    not(target_arch = "arm"),
25559    stable(feature = "neon_intrinsics", since = "1.59.0")
25560)]
25561#[cfg_attr(
25562    target_arch = "arm",
25563    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25564)]
25565pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25566    let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25567    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25568    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25569    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25570    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25571    ret_val
25572}
25573#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25575#[doc = "## Safety"]
25576#[doc = "  * Neon instrinsic unsafe"]
25577#[inline]
25578#[cfg(target_endian = "little")]
25579#[target_feature(enable = "neon")]
25580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25582#[cfg_attr(
25583    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25584    assert_instr(ld4r)
25585)]
25586#[cfg_attr(
25587    not(target_arch = "arm"),
25588    stable(feature = "neon_intrinsics", since = "1.59.0")
25589)]
25590#[cfg_attr(
25591    target_arch = "arm",
25592    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25593)]
25594pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25595    transmute(vld4_dup_s32(transmute(a)))
25596}
25597#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25599#[doc = "## Safety"]
25600#[doc = "  * Neon instrinsic unsafe"]
25601#[inline]
25602#[cfg(target_endian = "big")]
25603#[target_feature(enable = "neon")]
25604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25606#[cfg_attr(
25607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25608    assert_instr(ld4r)
25609)]
25610#[cfg_attr(
25611    not(target_arch = "arm"),
25612    stable(feature = "neon_intrinsics", since = "1.59.0")
25613)]
25614#[cfg_attr(
25615    target_arch = "arm",
25616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25617)]
25618pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25619    let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
25620    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
25621    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
25622    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
25623    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
25624    ret_val
25625}
25626#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25628#[doc = "## Safety"]
25629#[doc = "  * Neon instrinsic unsafe"]
25630#[inline]
25631#[cfg(target_endian = "little")]
25632#[target_feature(enable = "neon")]
25633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25635#[cfg_attr(
25636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25637    assert_instr(ld4r)
25638)]
25639#[cfg_attr(
25640    not(target_arch = "arm"),
25641    stable(feature = "neon_intrinsics", since = "1.59.0")
25642)]
25643#[cfg_attr(
25644    target_arch = "arm",
25645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25646)]
25647pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25648    transmute(vld4q_dup_s32(transmute(a)))
25649}
25650#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25652#[doc = "## Safety"]
25653#[doc = "  * Neon instrinsic unsafe"]
25654#[inline]
25655#[cfg(target_endian = "big")]
25656#[target_feature(enable = "neon")]
25657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25659#[cfg_attr(
25660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25661    assert_instr(ld4r)
25662)]
25663#[cfg_attr(
25664    not(target_arch = "arm"),
25665    stable(feature = "neon_intrinsics", since = "1.59.0")
25666)]
25667#[cfg_attr(
25668    target_arch = "arm",
25669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25670)]
25671pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25672    let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
25673    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25674    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25675    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25676    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25677    ret_val
25678}
25679#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25681#[doc = "## Safety"]
25682#[doc = "  * Neon instrinsic unsafe"]
25683#[inline]
25684#[cfg(target_endian = "little")]
25685#[target_feature(enable = "neon")]
25686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25688#[cfg_attr(
25689    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25690    assert_instr(ld4r)
25691)]
25692#[cfg_attr(
25693    not(target_arch = "arm"),
25694    stable(feature = "neon_intrinsics", since = "1.59.0")
25695)]
25696#[cfg_attr(
25697    target_arch = "arm",
25698    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25699)]
25700pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25701    transmute(vld4_dup_s8(transmute(a)))
25702}
25703#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25705#[doc = "## Safety"]
25706#[doc = "  * Neon instrinsic unsafe"]
25707#[inline]
25708#[cfg(target_endian = "big")]
25709#[target_feature(enable = "neon")]
25710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25712#[cfg_attr(
25713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25714    assert_instr(ld4r)
25715)]
25716#[cfg_attr(
25717    not(target_arch = "arm"),
25718    stable(feature = "neon_intrinsics", since = "1.59.0")
25719)]
25720#[cfg_attr(
25721    target_arch = "arm",
25722    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25723)]
25724pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25725    let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25726    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25727    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25728    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25729    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25730    ret_val
25731}
25732#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25734#[doc = "## Safety"]
25735#[doc = "  * Neon instrinsic unsafe"]
25736#[inline]
25737#[cfg(target_endian = "little")]
25738#[target_feature(enable = "neon")]
25739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25741#[cfg_attr(
25742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25743    assert_instr(ld4r)
25744)]
25745#[cfg_attr(
25746    not(target_arch = "arm"),
25747    stable(feature = "neon_intrinsics", since = "1.59.0")
25748)]
25749#[cfg_attr(
25750    target_arch = "arm",
25751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25752)]
25753pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25754    transmute(vld4q_dup_s8(transmute(a)))
25755}
25756#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25758#[doc = "## Safety"]
25759#[doc = "  * Neon instrinsic unsafe"]
25760#[inline]
25761#[cfg(target_endian = "big")]
25762#[target_feature(enable = "neon")]
25763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25765#[cfg_attr(
25766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25767    assert_instr(ld4r)
25768)]
25769#[cfg_attr(
25770    not(target_arch = "arm"),
25771    stable(feature = "neon_intrinsics", since = "1.59.0")
25772)]
25773#[cfg_attr(
25774    target_arch = "arm",
25775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25776)]
25777pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25778    let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25779    ret_val.0 = unsafe {
25780        simd_shuffle!(
25781            ret_val.0,
25782            ret_val.0,
25783            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25784        )
25785    };
25786    ret_val.1 = unsafe {
25787        simd_shuffle!(
25788            ret_val.1,
25789            ret_val.1,
25790            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25791        )
25792    };
25793    ret_val.2 = unsafe {
25794        simd_shuffle!(
25795            ret_val.2,
25796            ret_val.2,
25797            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25798        )
25799    };
25800    ret_val.3 = unsafe {
25801        simd_shuffle!(
25802            ret_val.3,
25803            ret_val.3,
25804            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25805        )
25806    };
25807    ret_val
25808}
25809#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25811#[doc = "## Safety"]
25812#[doc = "  * Neon instrinsic unsafe"]
25813#[inline]
25814#[cfg(target_endian = "little")]
25815#[target_feature(enable = "neon")]
25816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25818#[cfg_attr(
25819    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25820    assert_instr(ld4r)
25821)]
25822#[cfg_attr(
25823    not(target_arch = "arm"),
25824    stable(feature = "neon_intrinsics", since = "1.59.0")
25825)]
25826#[cfg_attr(
25827    target_arch = "arm",
25828    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25829)]
25830pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25831    transmute(vld4_dup_s16(transmute(a)))
25832}
25833#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25835#[doc = "## Safety"]
25836#[doc = "  * Neon instrinsic unsafe"]
25837#[inline]
25838#[cfg(target_endian = "big")]
25839#[target_feature(enable = "neon")]
25840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25841#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25842#[cfg_attr(
25843    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25844    assert_instr(ld4r)
25845)]
25846#[cfg_attr(
25847    not(target_arch = "arm"),
25848    stable(feature = "neon_intrinsics", since = "1.59.0")
25849)]
25850#[cfg_attr(
25851    target_arch = "arm",
25852    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25853)]
25854pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25855    let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25856    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25857    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25858    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25859    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25860    ret_val
25861}
25862#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25864#[doc = "## Safety"]
25865#[doc = "  * Neon instrinsic unsafe"]
25866#[inline]
25867#[cfg(target_endian = "little")]
25868#[target_feature(enable = "neon")]
25869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25871#[cfg_attr(
25872    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25873    assert_instr(ld4r)
25874)]
25875#[cfg_attr(
25876    not(target_arch = "arm"),
25877    stable(feature = "neon_intrinsics", since = "1.59.0")
25878)]
25879#[cfg_attr(
25880    target_arch = "arm",
25881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25882)]
25883pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25884    transmute(vld4q_dup_s16(transmute(a)))
25885}
25886#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25888#[doc = "## Safety"]
25889#[doc = "  * Neon instrinsic unsafe"]
25890#[inline]
25891#[cfg(target_endian = "big")]
25892#[target_feature(enable = "neon")]
25893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25895#[cfg_attr(
25896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25897    assert_instr(ld4r)
25898)]
25899#[cfg_attr(
25900    not(target_arch = "arm"),
25901    stable(feature = "neon_intrinsics", since = "1.59.0")
25902)]
25903#[cfg_attr(
25904    target_arch = "arm",
25905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25906)]
25907pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25908    let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25909    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25910    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25911    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25912    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25913    ret_val
25914}
25915#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25917#[doc = "## Safety"]
25918#[doc = "  * Neon instrinsic unsafe"]
25919#[inline]
25920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25921#[cfg(target_arch = "arm")]
25922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25923#[target_feature(enable = "neon,fp16")]
25924#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25925pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25926    unsafe extern "unadjusted" {
25927        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0f16")]
25928        fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
25929    }
25930    _vld4_f16(a as _, 2)
25931}
25932#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25934#[doc = "## Safety"]
25935#[doc = "  * Neon instrinsic unsafe"]
25936#[inline]
25937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25938#[cfg(target_arch = "arm")]
25939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25940#[target_feature(enable = "neon,fp16")]
25941#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25942pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25943    unsafe extern "unadjusted" {
25944        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0f16")]
25945        fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
25946    }
25947    _vld4q_f16(a as _, 2)
25948}
25949#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25951#[doc = "## Safety"]
25952#[doc = "  * Neon instrinsic unsafe"]
25953#[inline]
25954#[cfg(not(target_arch = "arm"))]
25955#[cfg_attr(
25956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25957    assert_instr(ld4)
25958)]
25959#[target_feature(enable = "neon,fp16")]
25960#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25961pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25962    unsafe extern "unadjusted" {
25963        #[cfg_attr(
25964            any(target_arch = "aarch64", target_arch = "arm64ec"),
25965            link_name = "llvm.aarch64.neon.ld4.v4f16.p0f16"
25966        )]
25967        fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
25968    }
25969    _vld4_f16(a as _)
25970}
25971#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25973#[doc = "## Safety"]
25974#[doc = "  * Neon instrinsic unsafe"]
25975#[inline]
25976#[cfg(not(target_arch = "arm"))]
25977#[cfg_attr(
25978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25979    assert_instr(ld4)
25980)]
25981#[target_feature(enable = "neon,fp16")]
25982#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25983pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25984    unsafe extern "unadjusted" {
25985        #[cfg_attr(
25986            any(target_arch = "aarch64", target_arch = "arm64ec"),
25987            link_name = "llvm.aarch64.neon.ld4.v8f16.p0f16"
25988        )]
25989        fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
25990    }
25991    _vld4q_f16(a as _)
25992}
25993#[doc = "Load multiple 4-element structures to four registers"]
25994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
25995#[doc = "## Safety"]
25996#[doc = "  * Neon instrinsic unsafe"]
25997#[inline]
25998#[target_feature(enable = "neon")]
25999#[cfg(not(target_arch = "arm"))]
26000#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26001#[cfg_attr(test, assert_instr(ld4))]
26002pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
26003    unsafe extern "unadjusted" {
26004        #[cfg_attr(
26005            any(target_arch = "aarch64", target_arch = "arm64ec"),
26006            link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
26007        )]
26008        fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
26009    }
26010    _vld4_f32(a as _)
26011}
26012#[doc = "Load multiple 4-element structures to four registers"]
26013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26014#[doc = "## Safety"]
26015#[doc = "  * Neon instrinsic unsafe"]
26016#[inline]
26017#[target_feature(enable = "neon")]
26018#[cfg(not(target_arch = "arm"))]
26019#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26020#[cfg_attr(test, assert_instr(ld4))]
26021pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26022    unsafe extern "unadjusted" {
26023        #[cfg_attr(
26024            any(target_arch = "aarch64", target_arch = "arm64ec"),
26025            link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
26026        )]
26027        fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
26028    }
26029    _vld4q_f32(a as _)
26030}
26031#[doc = "Load multiple 4-element structures to four registers"]
26032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26033#[doc = "## Safety"]
26034#[doc = "  * Neon instrinsic unsafe"]
26035#[inline]
26036#[target_feature(enable = "neon")]
26037#[cfg(not(target_arch = "arm"))]
26038#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26039#[cfg_attr(test, assert_instr(ld4))]
26040pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26041    unsafe extern "unadjusted" {
26042        #[cfg_attr(
26043            any(target_arch = "aarch64", target_arch = "arm64ec"),
26044            link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
26045        )]
26046        fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
26047    }
26048    _vld4_s8(a as _)
26049}
26050#[doc = "Load multiple 4-element structures to four registers"]
26051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26052#[doc = "## Safety"]
26053#[doc = "  * Neon instrinsic unsafe"]
26054#[inline]
26055#[target_feature(enable = "neon")]
26056#[cfg(not(target_arch = "arm"))]
26057#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26058#[cfg_attr(test, assert_instr(ld4))]
26059pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26060    unsafe extern "unadjusted" {
26061        #[cfg_attr(
26062            any(target_arch = "aarch64", target_arch = "arm64ec"),
26063            link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
26064        )]
26065        fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
26066    }
26067    _vld4q_s8(a as _)
26068}
26069#[doc = "Load multiple 4-element structures to four registers"]
26070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26071#[doc = "## Safety"]
26072#[doc = "  * Neon instrinsic unsafe"]
26073#[inline]
26074#[target_feature(enable = "neon")]
26075#[cfg(not(target_arch = "arm"))]
26076#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26077#[cfg_attr(test, assert_instr(ld4))]
26078pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26079    unsafe extern "unadjusted" {
26080        #[cfg_attr(
26081            any(target_arch = "aarch64", target_arch = "arm64ec"),
26082            link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
26083        )]
26084        fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
26085    }
26086    _vld4_s16(a as _)
26087}
26088#[doc = "Load multiple 4-element structures to four registers"]
26089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26090#[doc = "## Safety"]
26091#[doc = "  * Neon instrinsic unsafe"]
26092#[inline]
26093#[target_feature(enable = "neon")]
26094#[cfg(not(target_arch = "arm"))]
26095#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26096#[cfg_attr(test, assert_instr(ld4))]
26097pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26098    unsafe extern "unadjusted" {
26099        #[cfg_attr(
26100            any(target_arch = "aarch64", target_arch = "arm64ec"),
26101            link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
26102        )]
26103        fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
26104    }
26105    _vld4q_s16(a as _)
26106}
26107#[doc = "Load multiple 4-element structures to four registers"]
26108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26109#[doc = "## Safety"]
26110#[doc = "  * Neon instrinsic unsafe"]
26111#[inline]
26112#[target_feature(enable = "neon")]
26113#[cfg(not(target_arch = "arm"))]
26114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26115#[cfg_attr(test, assert_instr(ld4))]
26116pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26117    unsafe extern "unadjusted" {
26118        #[cfg_attr(
26119            any(target_arch = "aarch64", target_arch = "arm64ec"),
26120            link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
26121        )]
26122        fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
26123    }
26124    _vld4_s32(a as _)
26125}
26126#[doc = "Load multiple 4-element structures to four registers"]
26127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26128#[doc = "## Safety"]
26129#[doc = "  * Neon instrinsic unsafe"]
26130#[inline]
26131#[target_feature(enable = "neon")]
26132#[cfg(not(target_arch = "arm"))]
26133#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26134#[cfg_attr(test, assert_instr(ld4))]
26135pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26136    unsafe extern "unadjusted" {
26137        #[cfg_attr(
26138            any(target_arch = "aarch64", target_arch = "arm64ec"),
26139            link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
26140        )]
26141        fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
26142    }
26143    _vld4q_s32(a as _)
26144}
26145#[doc = "Load multiple 4-element structures to four registers"]
26146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
26147#[doc = "## Safety"]
26148#[doc = "  * Neon instrinsic unsafe"]
26149#[inline]
26150#[target_feature(enable = "neon,v7")]
26151#[cfg(target_arch = "arm")]
26152#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26153#[cfg_attr(test, assert_instr(vld4))]
26154pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
26155    unsafe extern "unadjusted" {
26156        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")]
26157        fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
26158    }
26159    _vld4_f32(a as *const i8, 4)
26160}
26161#[doc = "Load multiple 4-element structures to four registers"]
26162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26163#[doc = "## Safety"]
26164#[doc = "  * Neon instrinsic unsafe"]
26165#[inline]
26166#[target_feature(enable = "neon,v7")]
26167#[cfg(target_arch = "arm")]
26168#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26169#[cfg_attr(test, assert_instr(vld4))]
26170pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26171    unsafe extern "unadjusted" {
26172        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")]
26173        fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
26174    }
26175    _vld4q_f32(a as *const i8, 4)
26176}
26177#[doc = "Load multiple 4-element structures to four registers"]
26178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26179#[doc = "## Safety"]
26180#[doc = "  * Neon instrinsic unsafe"]
26181#[inline]
26182#[target_feature(enable = "neon,v7")]
26183#[cfg(target_arch = "arm")]
26184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26185#[cfg_attr(test, assert_instr(vld4))]
26186pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26187    unsafe extern "unadjusted" {
26188        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")]
26189        fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
26190    }
26191    _vld4_s8(a as *const i8, 1)
26192}
26193#[doc = "Load multiple 4-element structures to four registers"]
26194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26195#[doc = "## Safety"]
26196#[doc = "  * Neon instrinsic unsafe"]
26197#[inline]
26198#[target_feature(enable = "neon,v7")]
26199#[cfg(target_arch = "arm")]
26200#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26201#[cfg_attr(test, assert_instr(vld4))]
26202pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26203    unsafe extern "unadjusted" {
26204        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")]
26205        fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
26206    }
26207    _vld4q_s8(a as *const i8, 1)
26208}
26209#[doc = "Load multiple 4-element structures to four registers"]
26210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26211#[doc = "## Safety"]
26212#[doc = "  * Neon instrinsic unsafe"]
26213#[inline]
26214#[target_feature(enable = "neon,v7")]
26215#[cfg(target_arch = "arm")]
26216#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26217#[cfg_attr(test, assert_instr(vld4))]
26218pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26219    unsafe extern "unadjusted" {
26220        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")]
26221        fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
26222    }
26223    _vld4_s16(a as *const i8, 2)
26224}
26225#[doc = "Load multiple 4-element structures to four registers"]
26226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26227#[doc = "## Safety"]
26228#[doc = "  * Neon instrinsic unsafe"]
26229#[inline]
26230#[target_feature(enable = "neon,v7")]
26231#[cfg(target_arch = "arm")]
26232#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26233#[cfg_attr(test, assert_instr(vld4))]
26234pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26235    unsafe extern "unadjusted" {
26236        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")]
26237        fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
26238    }
26239    _vld4q_s16(a as *const i8, 2)
26240}
26241#[doc = "Load multiple 4-element structures to four registers"]
26242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26243#[doc = "## Safety"]
26244#[doc = "  * Neon instrinsic unsafe"]
26245#[inline]
26246#[target_feature(enable = "neon,v7")]
26247#[cfg(target_arch = "arm")]
26248#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26249#[cfg_attr(test, assert_instr(vld4))]
26250pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26251    unsafe extern "unadjusted" {
26252        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")]
26253        fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
26254    }
26255    _vld4_s32(a as *const i8, 4)
26256}
26257#[doc = "Load multiple 4-element structures to four registers"]
26258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26259#[doc = "## Safety"]
26260#[doc = "  * Neon instrinsic unsafe"]
26261#[inline]
26262#[target_feature(enable = "neon,v7")]
26263#[cfg(target_arch = "arm")]
26264#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26265#[cfg_attr(test, assert_instr(vld4))]
26266pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26267    unsafe extern "unadjusted" {
26268        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")]
26269        fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
26270    }
26271    _vld4q_s32(a as *const i8, 4)
26272}
26273#[doc = "Load multiple 4-element structures to two registers"]
26274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26275#[doc = "## Safety"]
26276#[doc = "  * Neon instrinsic unsafe"]
26277#[inline]
26278#[target_feature(enable = "neon,v7")]
26279#[cfg(target_arch = "arm")]
26280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26281#[rustc_legacy_const_generics(2)]
26282#[target_feature(enable = "neon,fp16")]
26283#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26284pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26285    static_assert_uimm_bits!(LANE, 2);
26286    unsafe extern "unadjusted" {
26287        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")]
26288        fn _vld4_lane_f16(
26289            ptr: *const f16,
26290            a: float16x4_t,
26291            b: float16x4_t,
26292            c: float16x4_t,
26293            d: float16x4_t,
26294            n: i32,
26295            size: i32,
26296        ) -> float16x4x4_t;
26297    }
26298    _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26299}
26300#[doc = "Load multiple 4-element structures to two registers"]
26301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26302#[doc = "## Safety"]
26303#[doc = "  * Neon instrinsic unsafe"]
26304#[inline]
26305#[target_feature(enable = "neon,v7")]
26306#[cfg(target_arch = "arm")]
26307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26308#[rustc_legacy_const_generics(2)]
26309#[target_feature(enable = "neon,fp16")]
26310#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26311pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26312    static_assert_uimm_bits!(LANE, 3);
26313    unsafe extern "unadjusted" {
26314        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")]
26315        fn _vld4q_lane_f16(
26316            ptr: *const f16,
26317            a: float16x8_t,
26318            b: float16x8_t,
26319            c: float16x8_t,
26320            d: float16x8_t,
26321            n: i32,
26322            size: i32,
26323        ) -> float16x8x4_t;
26324    }
26325    _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26326}
26327#[doc = "Load multiple 4-element structures to two registers"]
26328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26329#[doc = "## Safety"]
26330#[doc = "  * Neon instrinsic unsafe"]
26331#[inline]
26332#[cfg(not(target_arch = "arm"))]
26333#[cfg_attr(
26334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26335    assert_instr(ld4, LANE = 0)
26336)]
26337#[rustc_legacy_const_generics(2)]
26338#[target_feature(enable = "neon,fp16")]
26339#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26340pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26341    static_assert_uimm_bits!(LANE, 2);
26342    unsafe extern "unadjusted" {
26343        #[cfg_attr(
26344            any(target_arch = "aarch64", target_arch = "arm64ec"),
26345            link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0"
26346        )]
26347        fn _vld4_lane_f16(
26348            a: float16x4_t,
26349            b: float16x4_t,
26350            c: float16x4_t,
26351            d: float16x4_t,
26352            n: i64,
26353            ptr: *const f16,
26354        ) -> float16x4x4_t;
26355    }
26356    _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26357}
26358#[doc = "Load multiple 4-element structures to two registers"]
26359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26360#[doc = "## Safety"]
26361#[doc = "  * Neon instrinsic unsafe"]
26362#[inline]
26363#[cfg(not(target_arch = "arm"))]
26364#[cfg_attr(
26365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26366    assert_instr(ld4, LANE = 0)
26367)]
26368#[rustc_legacy_const_generics(2)]
26369#[target_feature(enable = "neon,fp16")]
26370#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26371pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26372    static_assert_uimm_bits!(LANE, 3);
26373    unsafe extern "unadjusted" {
26374        #[cfg_attr(
26375            any(target_arch = "aarch64", target_arch = "arm64ec"),
26376            link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0"
26377        )]
26378        fn _vld4q_lane_f16(
26379            a: float16x8_t,
26380            b: float16x8_t,
26381            c: float16x8_t,
26382            d: float16x8_t,
26383            n: i64,
26384            ptr: *const f16,
26385        ) -> float16x8x4_t;
26386    }
26387    _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26388}
26389#[doc = "Load multiple 4-element structures to four registers"]
26390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26391#[doc = "## Safety"]
26392#[doc = "  * Neon instrinsic unsafe"]
26393#[inline]
26394#[target_feature(enable = "neon")]
26395#[cfg(not(target_arch = "arm"))]
26396#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26397#[rustc_legacy_const_generics(2)]
26398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26399pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26400    static_assert_uimm_bits!(LANE, 1);
26401    unsafe extern "unadjusted" {
26402        #[cfg_attr(
26403            any(target_arch = "aarch64", target_arch = "arm64ec"),
26404            link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0"
26405        )]
26406        fn _vld4_lane_f32(
26407            a: float32x2_t,
26408            b: float32x2_t,
26409            c: float32x2_t,
26410            d: float32x2_t,
26411            n: i64,
26412            ptr: *const i8,
26413        ) -> float32x2x4_t;
26414    }
26415    _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26416}
26417#[doc = "Load multiple 4-element structures to four registers"]
26418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26419#[doc = "## Safety"]
26420#[doc = "  * Neon instrinsic unsafe"]
26421#[inline]
26422#[target_feature(enable = "neon")]
26423#[cfg(not(target_arch = "arm"))]
26424#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26425#[rustc_legacy_const_generics(2)]
26426#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26427pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26428    static_assert_uimm_bits!(LANE, 2);
26429    unsafe extern "unadjusted" {
26430        #[cfg_attr(
26431            any(target_arch = "aarch64", target_arch = "arm64ec"),
26432            link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0"
26433        )]
26434        fn _vld4q_lane_f32(
26435            a: float32x4_t,
26436            b: float32x4_t,
26437            c: float32x4_t,
26438            d: float32x4_t,
26439            n: i64,
26440            ptr: *const i8,
26441        ) -> float32x4x4_t;
26442    }
26443    _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26444}
26445#[doc = "Load multiple 4-element structures to four registers"]
26446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26447#[doc = "## Safety"]
26448#[doc = "  * Neon instrinsic unsafe"]
26449#[inline]
26450#[target_feature(enable = "neon")]
26451#[cfg(not(target_arch = "arm"))]
26452#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26453#[rustc_legacy_const_generics(2)]
26454#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26455pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26456    static_assert_uimm_bits!(LANE, 3);
26457    unsafe extern "unadjusted" {
26458        #[cfg_attr(
26459            any(target_arch = "aarch64", target_arch = "arm64ec"),
26460            link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0"
26461        )]
26462        fn _vld4_lane_s8(
26463            a: int8x8_t,
26464            b: int8x8_t,
26465            c: int8x8_t,
26466            d: int8x8_t,
26467            n: i64,
26468            ptr: *const i8,
26469        ) -> int8x8x4_t;
26470    }
26471    _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26472}
26473#[doc = "Load multiple 4-element structures to four registers"]
26474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26475#[doc = "## Safety"]
26476#[doc = "  * Neon instrinsic unsafe"]
26477#[inline]
26478#[target_feature(enable = "neon")]
26479#[cfg(not(target_arch = "arm"))]
26480#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26481#[rustc_legacy_const_generics(2)]
26482#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26483pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26484    static_assert_uimm_bits!(LANE, 2);
26485    unsafe extern "unadjusted" {
26486        #[cfg_attr(
26487            any(target_arch = "aarch64", target_arch = "arm64ec"),
26488            link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0"
26489        )]
26490        fn _vld4_lane_s16(
26491            a: int16x4_t,
26492            b: int16x4_t,
26493            c: int16x4_t,
26494            d: int16x4_t,
26495            n: i64,
26496            ptr: *const i8,
26497        ) -> int16x4x4_t;
26498    }
26499    _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26500}
26501#[doc = "Load multiple 4-element structures to four registers"]
26502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26503#[doc = "## Safety"]
26504#[doc = "  * Neon instrinsic unsafe"]
26505#[inline]
26506#[target_feature(enable = "neon")]
26507#[cfg(not(target_arch = "arm"))]
26508#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26509#[rustc_legacy_const_generics(2)]
26510#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26511pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26512    static_assert_uimm_bits!(LANE, 3);
26513    unsafe extern "unadjusted" {
26514        #[cfg_attr(
26515            any(target_arch = "aarch64", target_arch = "arm64ec"),
26516            link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0"
26517        )]
26518        fn _vld4q_lane_s16(
26519            a: int16x8_t,
26520            b: int16x8_t,
26521            c: int16x8_t,
26522            d: int16x8_t,
26523            n: i64,
26524            ptr: *const i8,
26525        ) -> int16x8x4_t;
26526    }
26527    _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26528}
26529#[doc = "Load multiple 4-element structures to four registers"]
26530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26531#[doc = "## Safety"]
26532#[doc = "  * Neon instrinsic unsafe"]
26533#[inline]
26534#[target_feature(enable = "neon")]
26535#[cfg(not(target_arch = "arm"))]
26536#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26537#[rustc_legacy_const_generics(2)]
26538#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26539pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26540    static_assert_uimm_bits!(LANE, 1);
26541    unsafe extern "unadjusted" {
26542        #[cfg_attr(
26543            any(target_arch = "aarch64", target_arch = "arm64ec"),
26544            link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0"
26545        )]
26546        fn _vld4_lane_s32(
26547            a: int32x2_t,
26548            b: int32x2_t,
26549            c: int32x2_t,
26550            d: int32x2_t,
26551            n: i64,
26552            ptr: *const i8,
26553        ) -> int32x2x4_t;
26554    }
26555    _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26556}
26557#[doc = "Load multiple 4-element structures to four registers"]
26558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26559#[doc = "## Safety"]
26560#[doc = "  * Neon instrinsic unsafe"]
26561#[inline]
26562#[target_feature(enable = "neon")]
26563#[cfg(not(target_arch = "arm"))]
26564#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26565#[rustc_legacy_const_generics(2)]
26566#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26567pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26568    static_assert_uimm_bits!(LANE, 2);
26569    unsafe extern "unadjusted" {
26570        #[cfg_attr(
26571            any(target_arch = "aarch64", target_arch = "arm64ec"),
26572            link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0"
26573        )]
26574        fn _vld4q_lane_s32(
26575            a: int32x4_t,
26576            b: int32x4_t,
26577            c: int32x4_t,
26578            d: int32x4_t,
26579            n: i64,
26580            ptr: *const i8,
26581        ) -> int32x4x4_t;
26582    }
26583    _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26584}
26585#[doc = "Load multiple 4-element structures to four registers"]
26586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26587#[doc = "## Safety"]
26588#[doc = "  * Neon instrinsic unsafe"]
26589#[inline]
26590#[target_feature(enable = "neon,v7")]
26591#[cfg(target_arch = "arm")]
26592#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26593#[rustc_legacy_const_generics(2)]
26594#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26595pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26596    static_assert_uimm_bits!(LANE, 1);
26597    unsafe extern "unadjusted" {
26598        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")]
26599        fn _vld4_lane_f32(
26600            ptr: *const i8,
26601            a: float32x2_t,
26602            b: float32x2_t,
26603            c: float32x2_t,
26604            d: float32x2_t,
26605            n: i32,
26606            size: i32,
26607        ) -> float32x2x4_t;
26608    }
26609    _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26610}
26611#[doc = "Load multiple 4-element structures to four registers"]
26612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26613#[doc = "## Safety"]
26614#[doc = "  * Neon instrinsic unsafe"]
26615#[inline]
26616#[target_feature(enable = "neon,v7")]
26617#[cfg(target_arch = "arm")]
26618#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26619#[rustc_legacy_const_generics(2)]
26620#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26621pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26622    static_assert_uimm_bits!(LANE, 2);
26623    unsafe extern "unadjusted" {
26624        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")]
26625        fn _vld4q_lane_f32(
26626            ptr: *const i8,
26627            a: float32x4_t,
26628            b: float32x4_t,
26629            c: float32x4_t,
26630            d: float32x4_t,
26631            n: i32,
26632            size: i32,
26633        ) -> float32x4x4_t;
26634    }
26635    _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26636}
26637#[doc = "Load multiple 4-element structures to four registers"]
26638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26639#[doc = "## Safety"]
26640#[doc = "  * Neon instrinsic unsafe"]
26641#[inline]
26642#[target_feature(enable = "neon,v7")]
26643#[cfg(target_arch = "arm")]
26644#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26645#[rustc_legacy_const_generics(2)]
26646#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26647pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26648    static_assert_uimm_bits!(LANE, 3);
26649    unsafe extern "unadjusted" {
26650        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")]
26651        fn _vld4_lane_s8(
26652            ptr: *const i8,
26653            a: int8x8_t,
26654            b: int8x8_t,
26655            c: int8x8_t,
26656            d: int8x8_t,
26657            n: i32,
26658            size: i32,
26659        ) -> int8x8x4_t;
26660    }
26661    _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
26662}
26663#[doc = "Load multiple 4-element structures to four registers"]
26664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26665#[doc = "## Safety"]
26666#[doc = "  * Neon instrinsic unsafe"]
26667#[inline]
26668#[target_feature(enable = "neon,v7")]
26669#[cfg(target_arch = "arm")]
26670#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26671#[rustc_legacy_const_generics(2)]
26672#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26673pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26674    static_assert_uimm_bits!(LANE, 2);
26675    unsafe extern "unadjusted" {
26676        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")]
26677        fn _vld4_lane_s16(
26678            ptr: *const i8,
26679            a: int16x4_t,
26680            b: int16x4_t,
26681            c: int16x4_t,
26682            d: int16x4_t,
26683            n: i32,
26684            size: i32,
26685        ) -> int16x4x4_t;
26686    }
26687    _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26688}
26689#[doc = "Load multiple 4-element structures to four registers"]
26690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26691#[doc = "## Safety"]
26692#[doc = "  * Neon instrinsic unsafe"]
26693#[inline]
26694#[target_feature(enable = "neon,v7")]
26695#[cfg(target_arch = "arm")]
26696#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26697#[rustc_legacy_const_generics(2)]
26698#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26699pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26700    static_assert_uimm_bits!(LANE, 3);
26701    unsafe extern "unadjusted" {
26702        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")]
26703        fn _vld4q_lane_s16(
26704            ptr: *const i8,
26705            a: int16x8_t,
26706            b: int16x8_t,
26707            c: int16x8_t,
26708            d: int16x8_t,
26709            n: i32,
26710            size: i32,
26711        ) -> int16x8x4_t;
26712    }
26713    _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26714}
26715#[doc = "Load multiple 4-element structures to four registers"]
26716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26717#[doc = "## Safety"]
26718#[doc = "  * Neon instrinsic unsafe"]
26719#[inline]
26720#[target_feature(enable = "neon,v7")]
26721#[cfg(target_arch = "arm")]
26722#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26723#[rustc_legacy_const_generics(2)]
26724#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26725pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26726    static_assert_uimm_bits!(LANE, 1);
26727    unsafe extern "unadjusted" {
26728        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")]
26729        fn _vld4_lane_s32(
26730            ptr: *const i8,
26731            a: int32x2_t,
26732            b: int32x2_t,
26733            c: int32x2_t,
26734            d: int32x2_t,
26735            n: i32,
26736            size: i32,
26737        ) -> int32x2x4_t;
26738    }
26739    _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26740}
26741#[doc = "Load multiple 4-element structures to four registers"]
26742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26743#[doc = "## Safety"]
26744#[doc = "  * Neon instrinsic unsafe"]
26745#[inline]
26746#[target_feature(enable = "neon,v7")]
26747#[cfg(target_arch = "arm")]
26748#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26749#[rustc_legacy_const_generics(2)]
26750#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26751pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26752    static_assert_uimm_bits!(LANE, 2);
26753    unsafe extern "unadjusted" {
26754        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")]
26755        fn _vld4q_lane_s32(
26756            ptr: *const i8,
26757            a: int32x4_t,
26758            b: int32x4_t,
26759            c: int32x4_t,
26760            d: int32x4_t,
26761            n: i32,
26762            size: i32,
26763        ) -> int32x4x4_t;
26764    }
26765    _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26766}
26767#[doc = "Load multiple 4-element structures to four registers"]
26768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
26769#[doc = "## Safety"]
26770#[doc = "  * Neon instrinsic unsafe"]
26771#[inline]
26772#[target_feature(enable = "neon")]
26773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26775#[cfg_attr(
26776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26777    assert_instr(ld4, LANE = 0)
26778)]
26779#[rustc_legacy_const_generics(2)]
26780#[cfg_attr(
26781    not(target_arch = "arm"),
26782    stable(feature = "neon_intrinsics", since = "1.59.0")
26783)]
26784#[cfg_attr(
26785    target_arch = "arm",
26786    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26787)]
26788pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t {
26789    static_assert_uimm_bits!(LANE, 3);
26790    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26791}
26792#[doc = "Load multiple 4-element structures to four registers"]
26793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
26794#[doc = "## Safety"]
26795#[doc = "  * Neon instrinsic unsafe"]
26796#[inline]
26797#[target_feature(enable = "neon")]
26798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26800#[cfg_attr(
26801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26802    assert_instr(ld4, LANE = 0)
26803)]
26804#[rustc_legacy_const_generics(2)]
26805#[cfg_attr(
26806    not(target_arch = "arm"),
26807    stable(feature = "neon_intrinsics", since = "1.59.0")
26808)]
26809#[cfg_attr(
26810    target_arch = "arm",
26811    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26812)]
26813pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t {
26814    static_assert_uimm_bits!(LANE, 2);
26815    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26816}
26817#[doc = "Load multiple 4-element structures to four registers"]
26818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
26819#[doc = "## Safety"]
26820#[doc = "  * Neon instrinsic unsafe"]
26821#[inline]
26822#[target_feature(enable = "neon")]
26823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26825#[cfg_attr(
26826    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26827    assert_instr(ld4, LANE = 0)
26828)]
26829#[rustc_legacy_const_generics(2)]
26830#[cfg_attr(
26831    not(target_arch = "arm"),
26832    stable(feature = "neon_intrinsics", since = "1.59.0")
26833)]
26834#[cfg_attr(
26835    target_arch = "arm",
26836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26837)]
26838pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t {
26839    static_assert_uimm_bits!(LANE, 3);
26840    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26841}
26842#[doc = "Load multiple 4-element structures to four registers"]
26843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
26844#[doc = "## Safety"]
26845#[doc = "  * Neon instrinsic unsafe"]
26846#[inline]
26847#[target_feature(enable = "neon")]
26848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26850#[cfg_attr(
26851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26852    assert_instr(ld4, LANE = 0)
26853)]
26854#[rustc_legacy_const_generics(2)]
26855#[cfg_attr(
26856    not(target_arch = "arm"),
26857    stable(feature = "neon_intrinsics", since = "1.59.0")
26858)]
26859#[cfg_attr(
26860    target_arch = "arm",
26861    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26862)]
26863pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
26864    static_assert_uimm_bits!(LANE, 1);
26865    transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
26866}
26867#[doc = "Load multiple 4-element structures to four registers"]
26868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
26869#[doc = "## Safety"]
26870#[doc = "  * Neon instrinsic unsafe"]
26871#[inline]
26872#[target_feature(enable = "neon")]
26873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26875#[cfg_attr(
26876    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26877    assert_instr(ld4, LANE = 0)
26878)]
26879#[rustc_legacy_const_generics(2)]
26880#[cfg_attr(
26881    not(target_arch = "arm"),
26882    stable(feature = "neon_intrinsics", since = "1.59.0")
26883)]
26884#[cfg_attr(
26885    target_arch = "arm",
26886    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26887)]
26888pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
26889    static_assert_uimm_bits!(LANE, 2);
26890    transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
26891}
26892#[doc = "Load multiple 4-element structures to four registers"]
26893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
26894#[doc = "## Safety"]
26895#[doc = "  * Neon instrinsic unsafe"]
26896#[inline]
26897#[target_feature(enable = "neon")]
26898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26900#[cfg_attr(
26901    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26902    assert_instr(ld4, LANE = 0)
26903)]
26904#[rustc_legacy_const_generics(2)]
26905#[cfg_attr(
26906    not(target_arch = "arm"),
26907    stable(feature = "neon_intrinsics", since = "1.59.0")
26908)]
26909#[cfg_attr(
26910    target_arch = "arm",
26911    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26912)]
26913pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
26914    static_assert_uimm_bits!(LANE, 3);
26915    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26916}
26917#[doc = "Load multiple 4-element structures to four registers"]
26918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
26919#[doc = "## Safety"]
26920#[doc = "  * Neon instrinsic unsafe"]
26921#[inline]
26922#[target_feature(enable = "neon")]
26923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26925#[cfg_attr(
26926    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26927    assert_instr(ld4, LANE = 0)
26928)]
26929#[rustc_legacy_const_generics(2)]
26930#[cfg_attr(
26931    not(target_arch = "arm"),
26932    stable(feature = "neon_intrinsics", since = "1.59.0")
26933)]
26934#[cfg_attr(
26935    target_arch = "arm",
26936    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26937)]
26938pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
26939    static_assert_uimm_bits!(LANE, 2);
26940    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26941}
26942#[doc = "Load multiple 4-element structures to four registers"]
26943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
26944#[doc = "## Safety"]
26945#[doc = "  * Neon instrinsic unsafe"]
26946#[inline]
26947#[target_feature(enable = "neon")]
26948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26950#[cfg_attr(
26951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26952    assert_instr(ld4, LANE = 0)
26953)]
26954#[rustc_legacy_const_generics(2)]
26955#[cfg_attr(
26956    not(target_arch = "arm"),
26957    stable(feature = "neon_intrinsics", since = "1.59.0")
26958)]
26959#[cfg_attr(
26960    target_arch = "arm",
26961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26962)]
26963pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
26964    static_assert_uimm_bits!(LANE, 3);
26965    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26966}
26967#[doc = "Load multiple 4-element structures to four registers"]
26968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
26969#[doc = "## Safety"]
26970#[doc = "  * Neon instrinsic unsafe"]
26971#[inline]
26972#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26973#[target_feature(enable = "neon,aes")]
26974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26975#[cfg_attr(
26976    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26977    assert_instr(nop)
26978)]
26979#[cfg_attr(
26980    not(target_arch = "arm"),
26981    stable(feature = "neon_intrinsics", since = "1.59.0")
26982)]
26983#[cfg_attr(
26984    target_arch = "arm",
26985    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26986)]
26987pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
26988    transmute(vld4_s64(transmute(a)))
26989}
26990#[doc = "Load multiple 4-element structures to four registers"]
26991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26992#[doc = "## Safety"]
26993#[doc = "  * Neon instrinsic unsafe"]
26994#[inline]
26995#[target_feature(enable = "neon")]
26996#[cfg(not(target_arch = "arm"))]
26997#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26998#[cfg_attr(test, assert_instr(nop))]
26999pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
27000    unsafe extern "unadjusted" {
27001        #[cfg_attr(
27002            any(target_arch = "aarch64", target_arch = "arm64ec"),
27003            link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
27004        )]
27005        fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
27006    }
27007    _vld4_s64(a as _)
27008}
27009#[doc = "Load multiple 4-element structures to four registers"]
27010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
27011#[doc = "## Safety"]
27012#[doc = "  * Neon instrinsic unsafe"]
27013#[inline]
27014#[target_feature(enable = "neon,v7")]
27015#[cfg(target_arch = "arm")]
27016#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
27017#[cfg_attr(test, assert_instr(nop))]
27018pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
27019    unsafe extern "unadjusted" {
27020        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
27021        fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
27022    }
27023    _vld4_s64(a as *const i8, 8)
27024}
27025#[doc = "Load multiple 4-element structures to four registers"]
27026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
27027#[doc = "## Safety"]
27028#[doc = "  * Neon instrinsic unsafe"]
27029#[inline]
27030#[target_feature(enable = "neon")]
27031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27033#[cfg_attr(
27034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27035    assert_instr(nop)
27036)]
27037#[cfg_attr(
27038    not(target_arch = "arm"),
27039    stable(feature = "neon_intrinsics", since = "1.59.0")
27040)]
27041#[cfg_attr(
27042    target_arch = "arm",
27043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27044)]
27045pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
27046    transmute(vld4_s64(transmute(a)))
27047}
27048#[doc = "Load multiple 4-element structures to four registers"]
27049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
27050#[doc = "## Safety"]
27051#[doc = "  * Neon instrinsic unsafe"]
27052#[inline]
27053#[cfg(target_endian = "little")]
27054#[target_feature(enable = "neon")]
27055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27057#[cfg_attr(
27058    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27059    assert_instr(ld4)
27060)]
27061#[cfg_attr(
27062    not(target_arch = "arm"),
27063    stable(feature = "neon_intrinsics", since = "1.59.0")
27064)]
27065#[cfg_attr(
27066    target_arch = "arm",
27067    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27068)]
27069pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
27070    transmute(vld4_s8(transmute(a)))
27071}
27072#[doc = "Load multiple 4-element structures to four registers"]
27073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
27074#[doc = "## Safety"]
27075#[doc = "  * Neon instrinsic unsafe"]
27076#[inline]
27077#[cfg(target_endian = "big")]
27078#[target_feature(enable = "neon")]
27079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27081#[cfg_attr(
27082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27083    assert_instr(ld4)
27084)]
27085#[cfg_attr(
27086    not(target_arch = "arm"),
27087    stable(feature = "neon_intrinsics", since = "1.59.0")
27088)]
27089#[cfg_attr(
27090    target_arch = "arm",
27091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27092)]
27093pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
27094    let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
27095    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27096    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27097    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27098    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27099    ret_val
27100}
27101#[doc = "Load multiple 4-element structures to four registers"]
27102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27103#[doc = "## Safety"]
27104#[doc = "  * Neon instrinsic unsafe"]
27105#[inline]
27106#[cfg(target_endian = "little")]
27107#[target_feature(enable = "neon")]
27108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27110#[cfg_attr(
27111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27112    assert_instr(ld4)
27113)]
27114#[cfg_attr(
27115    not(target_arch = "arm"),
27116    stable(feature = "neon_intrinsics", since = "1.59.0")
27117)]
27118#[cfg_attr(
27119    target_arch = "arm",
27120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27121)]
27122pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27123    transmute(vld4q_s8(transmute(a)))
27124}
27125#[doc = "Load multiple 4-element structures to four registers"]
27126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27127#[doc = "## Safety"]
27128#[doc = "  * Neon instrinsic unsafe"]
27129#[inline]
27130#[cfg(target_endian = "big")]
27131#[target_feature(enable = "neon")]
27132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27134#[cfg_attr(
27135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27136    assert_instr(ld4)
27137)]
27138#[cfg_attr(
27139    not(target_arch = "arm"),
27140    stable(feature = "neon_intrinsics", since = "1.59.0")
27141)]
27142#[cfg_attr(
27143    target_arch = "arm",
27144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27145)]
27146pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27147    let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
27148    ret_val.0 = unsafe {
27149        simd_shuffle!(
27150            ret_val.0,
27151            ret_val.0,
27152            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27153        )
27154    };
27155    ret_val.1 = unsafe {
27156        simd_shuffle!(
27157            ret_val.1,
27158            ret_val.1,
27159            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27160        )
27161    };
27162    ret_val.2 = unsafe {
27163        simd_shuffle!(
27164            ret_val.2,
27165            ret_val.2,
27166            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27167        )
27168    };
27169    ret_val.3 = unsafe {
27170        simd_shuffle!(
27171            ret_val.3,
27172            ret_val.3,
27173            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27174        )
27175    };
27176    ret_val
27177}
27178#[doc = "Load multiple 4-element structures to four registers"]
27179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27180#[doc = "## Safety"]
27181#[doc = "  * Neon instrinsic unsafe"]
27182#[inline]
27183#[cfg(target_endian = "little")]
27184#[target_feature(enable = "neon")]
27185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27187#[cfg_attr(
27188    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27189    assert_instr(ld4)
27190)]
27191#[cfg_attr(
27192    not(target_arch = "arm"),
27193    stable(feature = "neon_intrinsics", since = "1.59.0")
27194)]
27195#[cfg_attr(
27196    target_arch = "arm",
27197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27198)]
27199pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27200    transmute(vld4_s16(transmute(a)))
27201}
27202#[doc = "Load multiple 4-element structures to four registers"]
27203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27204#[doc = "## Safety"]
27205#[doc = "  * Neon instrinsic unsafe"]
27206#[inline]
27207#[cfg(target_endian = "big")]
27208#[target_feature(enable = "neon")]
27209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27211#[cfg_attr(
27212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27213    assert_instr(ld4)
27214)]
27215#[cfg_attr(
27216    not(target_arch = "arm"),
27217    stable(feature = "neon_intrinsics", since = "1.59.0")
27218)]
27219#[cfg_attr(
27220    target_arch = "arm",
27221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27222)]
27223pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27224    let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
27225    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27226    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27227    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27228    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27229    ret_val
27230}
27231#[doc = "Load multiple 4-element structures to four registers"]
27232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27233#[doc = "## Safety"]
27234#[doc = "  * Neon instrinsic unsafe"]
27235#[inline]
27236#[cfg(target_endian = "little")]
27237#[target_feature(enable = "neon")]
27238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27240#[cfg_attr(
27241    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27242    assert_instr(ld4)
27243)]
27244#[cfg_attr(
27245    not(target_arch = "arm"),
27246    stable(feature = "neon_intrinsics", since = "1.59.0")
27247)]
27248#[cfg_attr(
27249    target_arch = "arm",
27250    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27251)]
27252pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27253    transmute(vld4q_s16(transmute(a)))
27254}
27255#[doc = "Load multiple 4-element structures to four registers"]
27256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27257#[doc = "## Safety"]
27258#[doc = "  * Neon instrinsic unsafe"]
27259#[inline]
27260#[cfg(target_endian = "big")]
27261#[target_feature(enable = "neon")]
27262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27264#[cfg_attr(
27265    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27266    assert_instr(ld4)
27267)]
27268#[cfg_attr(
27269    not(target_arch = "arm"),
27270    stable(feature = "neon_intrinsics", since = "1.59.0")
27271)]
27272#[cfg_attr(
27273    target_arch = "arm",
27274    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27275)]
27276pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27277    let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
27278    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27279    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27280    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27281    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27282    ret_val
27283}
27284#[doc = "Load multiple 4-element structures to four registers"]
27285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27286#[doc = "## Safety"]
27287#[doc = "  * Neon instrinsic unsafe"]
27288#[inline]
27289#[cfg(target_endian = "little")]
27290#[target_feature(enable = "neon")]
27291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27293#[cfg_attr(
27294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27295    assert_instr(ld4)
27296)]
27297#[cfg_attr(
27298    not(target_arch = "arm"),
27299    stable(feature = "neon_intrinsics", since = "1.59.0")
27300)]
27301#[cfg_attr(
27302    target_arch = "arm",
27303    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27304)]
27305pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27306    transmute(vld4_s32(transmute(a)))
27307}
27308#[doc = "Load multiple 4-element structures to four registers"]
27309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27310#[doc = "## Safety"]
27311#[doc = "  * Neon instrinsic unsafe"]
27312#[inline]
27313#[cfg(target_endian = "big")]
27314#[target_feature(enable = "neon")]
27315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27317#[cfg_attr(
27318    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27319    assert_instr(ld4)
27320)]
27321#[cfg_attr(
27322    not(target_arch = "arm"),
27323    stable(feature = "neon_intrinsics", since = "1.59.0")
27324)]
27325#[cfg_attr(
27326    target_arch = "arm",
27327    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27328)]
27329pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27330    let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
27331    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
27332    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
27333    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
27334    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
27335    ret_val
27336}
27337#[doc = "Load multiple 4-element structures to four registers"]
27338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27339#[doc = "## Safety"]
27340#[doc = "  * Neon instrinsic unsafe"]
27341#[inline]
27342#[cfg(target_endian = "little")]
27343#[target_feature(enable = "neon")]
27344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27346#[cfg_attr(
27347    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27348    assert_instr(ld4)
27349)]
27350#[cfg_attr(
27351    not(target_arch = "arm"),
27352    stable(feature = "neon_intrinsics", since = "1.59.0")
27353)]
27354#[cfg_attr(
27355    target_arch = "arm",
27356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27357)]
27358pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27359    transmute(vld4q_s32(transmute(a)))
27360}
27361#[doc = "Load multiple 4-element structures to four registers"]
27362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27363#[doc = "## Safety"]
27364#[doc = "  * Neon instrinsic unsafe"]
27365#[inline]
27366#[cfg(target_endian = "big")]
27367#[target_feature(enable = "neon")]
27368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27370#[cfg_attr(
27371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27372    assert_instr(ld4)
27373)]
27374#[cfg_attr(
27375    not(target_arch = "arm"),
27376    stable(feature = "neon_intrinsics", since = "1.59.0")
27377)]
27378#[cfg_attr(
27379    target_arch = "arm",
27380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27381)]
27382pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27383    let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
27384    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27385    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27386    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27387    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27388    ret_val
27389}
27390#[doc = "Load multiple 4-element structures to four registers"]
27391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27392#[doc = "## Safety"]
27393#[doc = "  * Neon instrinsic unsafe"]
27394#[inline]
27395#[cfg(target_endian = "little")]
27396#[target_feature(enable = "neon")]
27397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27399#[cfg_attr(
27400    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27401    assert_instr(ld4)
27402)]
27403#[cfg_attr(
27404    not(target_arch = "arm"),
27405    stable(feature = "neon_intrinsics", since = "1.59.0")
27406)]
27407#[cfg_attr(
27408    target_arch = "arm",
27409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27410)]
27411pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27412    transmute(vld4_s8(transmute(a)))
27413}
27414#[doc = "Load multiple 4-element structures to four registers"]
27415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27416#[doc = "## Safety"]
27417#[doc = "  * Neon instrinsic unsafe"]
27418#[inline]
27419#[cfg(target_endian = "big")]
27420#[target_feature(enable = "neon")]
27421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27423#[cfg_attr(
27424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27425    assert_instr(ld4)
27426)]
27427#[cfg_attr(
27428    not(target_arch = "arm"),
27429    stable(feature = "neon_intrinsics", since = "1.59.0")
27430)]
27431#[cfg_attr(
27432    target_arch = "arm",
27433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27434)]
27435pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27436    let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
27437    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27438    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27439    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27440    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27441    ret_val
27442}
27443#[doc = "Load multiple 4-element structures to four registers"]
27444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27445#[doc = "## Safety"]
27446#[doc = "  * Neon instrinsic unsafe"]
27447#[inline]
27448#[cfg(target_endian = "little")]
27449#[target_feature(enable = "neon")]
27450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27452#[cfg_attr(
27453    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27454    assert_instr(ld4)
27455)]
27456#[cfg_attr(
27457    not(target_arch = "arm"),
27458    stable(feature = "neon_intrinsics", since = "1.59.0")
27459)]
27460#[cfg_attr(
27461    target_arch = "arm",
27462    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27463)]
27464pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27465    transmute(vld4q_s8(transmute(a)))
27466}
27467#[doc = "Load multiple 4-element structures to four registers"]
27468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27469#[doc = "## Safety"]
27470#[doc = "  * Neon instrinsic unsafe"]
27471#[inline]
27472#[cfg(target_endian = "big")]
27473#[target_feature(enable = "neon")]
27474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27476#[cfg_attr(
27477    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27478    assert_instr(ld4)
27479)]
27480#[cfg_attr(
27481    not(target_arch = "arm"),
27482    stable(feature = "neon_intrinsics", since = "1.59.0")
27483)]
27484#[cfg_attr(
27485    target_arch = "arm",
27486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27487)]
27488pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27489    let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
27490    ret_val.0 = unsafe {
27491        simd_shuffle!(
27492            ret_val.0,
27493            ret_val.0,
27494            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27495        )
27496    };
27497    ret_val.1 = unsafe {
27498        simd_shuffle!(
27499            ret_val.1,
27500            ret_val.1,
27501            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27502        )
27503    };
27504    ret_val.2 = unsafe {
27505        simd_shuffle!(
27506            ret_val.2,
27507            ret_val.2,
27508            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27509        )
27510    };
27511    ret_val.3 = unsafe {
27512        simd_shuffle!(
27513            ret_val.3,
27514            ret_val.3,
27515            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27516        )
27517    };
27518    ret_val
27519}
27520#[doc = "Load multiple 4-element structures to four registers"]
27521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27522#[doc = "## Safety"]
27523#[doc = "  * Neon instrinsic unsafe"]
27524#[inline]
27525#[cfg(target_endian = "little")]
27526#[target_feature(enable = "neon")]
27527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27529#[cfg_attr(
27530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27531    assert_instr(ld4)
27532)]
27533#[cfg_attr(
27534    not(target_arch = "arm"),
27535    stable(feature = "neon_intrinsics", since = "1.59.0")
27536)]
27537#[cfg_attr(
27538    target_arch = "arm",
27539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27540)]
27541pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27542    transmute(vld4_s16(transmute(a)))
27543}
27544#[doc = "Load multiple 4-element structures to four registers"]
27545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27546#[doc = "## Safety"]
27547#[doc = "  * Neon instrinsic unsafe"]
27548#[inline]
27549#[cfg(target_endian = "big")]
27550#[target_feature(enable = "neon")]
27551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27553#[cfg_attr(
27554    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27555    assert_instr(ld4)
27556)]
27557#[cfg_attr(
27558    not(target_arch = "arm"),
27559    stable(feature = "neon_intrinsics", since = "1.59.0")
27560)]
27561#[cfg_attr(
27562    target_arch = "arm",
27563    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27564)]
27565pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27566    let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
27567    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27568    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27569    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27570    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27571    ret_val
27572}
27573#[doc = "Load multiple 4-element structures to four registers"]
27574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27575#[doc = "## Safety"]
27576#[doc = "  * Neon instrinsic unsafe"]
27577#[inline]
27578#[cfg(target_endian = "little")]
27579#[target_feature(enable = "neon")]
27580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27582#[cfg_attr(
27583    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27584    assert_instr(ld4)
27585)]
27586#[cfg_attr(
27587    not(target_arch = "arm"),
27588    stable(feature = "neon_intrinsics", since = "1.59.0")
27589)]
27590#[cfg_attr(
27591    target_arch = "arm",
27592    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27593)]
27594pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27595    transmute(vld4q_s16(transmute(a)))
27596}
27597#[doc = "Load multiple 4-element structures to four registers"]
27598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27599#[doc = "## Safety"]
27600#[doc = "  * Neon instrinsic unsafe"]
27601#[inline]
27602#[cfg(target_endian = "big")]
27603#[target_feature(enable = "neon")]
27604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27606#[cfg_attr(
27607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27608    assert_instr(ld4)
27609)]
27610#[cfg_attr(
27611    not(target_arch = "arm"),
27612    stable(feature = "neon_intrinsics", since = "1.59.0")
27613)]
27614#[cfg_attr(
27615    target_arch = "arm",
27616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27617)]
27618pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27619    let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
27620    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27621    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27622    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27623    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27624    ret_val
27625}
27626#[doc = "Store SIMD&FP register (immediate offset)"]
27627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
27628#[doc = "## Safety"]
27629#[doc = "  * Neon instrinsic unsafe"]
27630#[inline]
27631#[target_feature(enable = "neon")]
27632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27634#[cfg_attr(
27635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27636    assert_instr(nop)
27637)]
27638#[cfg_attr(
27639    not(target_arch = "arm"),
27640    stable(feature = "neon_intrinsics", since = "1.59.0")
27641)]
27642#[cfg_attr(
27643    target_arch = "arm",
27644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27645)]
27646pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
27647    *a
27648}
27649#[doc = "Maximum (vector)"]
27650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
27651#[inline]
27652#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27654#[cfg_attr(
27655    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27656    assert_instr(fmax)
27657)]
27658#[target_feature(enable = "neon,fp16")]
27659#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27660pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27661    unsafe extern "unadjusted" {
27662        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")]
27663        #[cfg_attr(
27664            any(target_arch = "aarch64", target_arch = "arm64ec"),
27665            link_name = "llvm.aarch64.neon.fmax.v4f16"
27666        )]
27667        fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
27668    }
27669    unsafe { _vmax_f16(a, b) }
27670}
27671#[doc = "Maximum (vector)"]
27672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
27673#[inline]
27674#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27675#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27676#[cfg_attr(
27677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27678    assert_instr(fmax)
27679)]
27680#[target_feature(enable = "neon,fp16")]
27681#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27682pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27683    unsafe extern "unadjusted" {
27684        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")]
27685        #[cfg_attr(
27686            any(target_arch = "aarch64", target_arch = "arm64ec"),
27687            link_name = "llvm.aarch64.neon.fmax.v8f16"
27688        )]
27689        fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
27690    }
27691    unsafe { _vmaxq_f16(a, b) }
27692}
27693#[doc = "Maximum (vector)"]
27694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
27695#[inline]
27696#[target_feature(enable = "neon")]
27697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27699#[cfg_attr(
27700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27701    assert_instr(fmax)
27702)]
27703#[cfg_attr(
27704    not(target_arch = "arm"),
27705    stable(feature = "neon_intrinsics", since = "1.59.0")
27706)]
27707#[cfg_attr(
27708    target_arch = "arm",
27709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27710)]
27711pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27712    unsafe extern "unadjusted" {
27713        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")]
27714        #[cfg_attr(
27715            any(target_arch = "aarch64", target_arch = "arm64ec"),
27716            link_name = "llvm.aarch64.neon.fmax.v2f32"
27717        )]
27718        fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
27719    }
27720    unsafe { _vmax_f32(a, b) }
27721}
27722#[doc = "Maximum (vector)"]
27723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
27724#[inline]
27725#[target_feature(enable = "neon")]
27726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27728#[cfg_attr(
27729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27730    assert_instr(fmax)
27731)]
27732#[cfg_attr(
27733    not(target_arch = "arm"),
27734    stable(feature = "neon_intrinsics", since = "1.59.0")
27735)]
27736#[cfg_attr(
27737    target_arch = "arm",
27738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27739)]
27740pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27741    unsafe extern "unadjusted" {
27742        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
27743        #[cfg_attr(
27744            any(target_arch = "aarch64", target_arch = "arm64ec"),
27745            link_name = "llvm.aarch64.neon.fmax.v4f32"
27746        )]
27747        fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
27748    }
27749    unsafe { _vmaxq_f32(a, b) }
27750}
27751#[doc = "Maximum (vector)"]
27752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
27753#[inline]
27754#[target_feature(enable = "neon")]
27755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27756#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27757#[cfg_attr(
27758    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27759    assert_instr(smax)
27760)]
27761#[cfg_attr(
27762    not(target_arch = "arm"),
27763    stable(feature = "neon_intrinsics", since = "1.59.0")
27764)]
27765#[cfg_attr(
27766    target_arch = "arm",
27767    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27768)]
27769pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27770    unsafe extern "unadjusted" {
27771        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")]
27772        #[cfg_attr(
27773            any(target_arch = "aarch64", target_arch = "arm64ec"),
27774            link_name = "llvm.aarch64.neon.smax.v8i8"
27775        )]
27776        fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
27777    }
27778    unsafe { _vmax_s8(a, b) }
27779}
27780#[doc = "Maximum (vector)"]
27781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
27782#[inline]
27783#[target_feature(enable = "neon")]
27784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27786#[cfg_attr(
27787    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27788    assert_instr(smax)
27789)]
27790#[cfg_attr(
27791    not(target_arch = "arm"),
27792    stable(feature = "neon_intrinsics", since = "1.59.0")
27793)]
27794#[cfg_attr(
27795    target_arch = "arm",
27796    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27797)]
27798pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27799    unsafe extern "unadjusted" {
27800        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")]
27801        #[cfg_attr(
27802            any(target_arch = "aarch64", target_arch = "arm64ec"),
27803            link_name = "llvm.aarch64.neon.smax.v16i8"
27804        )]
27805        fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
27806    }
27807    unsafe { _vmaxq_s8(a, b) }
27808}
27809#[doc = "Maximum (vector)"]
27810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
27811#[inline]
27812#[target_feature(enable = "neon")]
27813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27815#[cfg_attr(
27816    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27817    assert_instr(smax)
27818)]
27819#[cfg_attr(
27820    not(target_arch = "arm"),
27821    stable(feature = "neon_intrinsics", since = "1.59.0")
27822)]
27823#[cfg_attr(
27824    target_arch = "arm",
27825    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27826)]
27827pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27828    unsafe extern "unadjusted" {
27829        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")]
27830        #[cfg_attr(
27831            any(target_arch = "aarch64", target_arch = "arm64ec"),
27832            link_name = "llvm.aarch64.neon.smax.v4i16"
27833        )]
27834        fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
27835    }
27836    unsafe { _vmax_s16(a, b) }
27837}
27838#[doc = "Maximum (vector)"]
27839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
27840#[inline]
27841#[target_feature(enable = "neon")]
27842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27844#[cfg_attr(
27845    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27846    assert_instr(smax)
27847)]
27848#[cfg_attr(
27849    not(target_arch = "arm"),
27850    stable(feature = "neon_intrinsics", since = "1.59.0")
27851)]
27852#[cfg_attr(
27853    target_arch = "arm",
27854    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27855)]
27856pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27857    unsafe extern "unadjusted" {
27858        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")]
27859        #[cfg_attr(
27860            any(target_arch = "aarch64", target_arch = "arm64ec"),
27861            link_name = "llvm.aarch64.neon.smax.v8i16"
27862        )]
27863        fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
27864    }
27865    unsafe { _vmaxq_s16(a, b) }
27866}
27867#[doc = "Maximum (vector)"]
27868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
27869#[inline]
27870#[target_feature(enable = "neon")]
27871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27873#[cfg_attr(
27874    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27875    assert_instr(smax)
27876)]
27877#[cfg_attr(
27878    not(target_arch = "arm"),
27879    stable(feature = "neon_intrinsics", since = "1.59.0")
27880)]
27881#[cfg_attr(
27882    target_arch = "arm",
27883    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27884)]
27885pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27886    unsafe extern "unadjusted" {
27887        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")]
27888        #[cfg_attr(
27889            any(target_arch = "aarch64", target_arch = "arm64ec"),
27890            link_name = "llvm.aarch64.neon.smax.v2i32"
27891        )]
27892        fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
27893    }
27894    unsafe { _vmax_s32(a, b) }
27895}
27896#[doc = "Maximum (vector)"]
27897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
27898#[inline]
27899#[target_feature(enable = "neon")]
27900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27901#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27902#[cfg_attr(
27903    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27904    assert_instr(smax)
27905)]
27906#[cfg_attr(
27907    not(target_arch = "arm"),
27908    stable(feature = "neon_intrinsics", since = "1.59.0")
27909)]
27910#[cfg_attr(
27911    target_arch = "arm",
27912    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27913)]
27914pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27915    unsafe extern "unadjusted" {
27916        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")]
27917        #[cfg_attr(
27918            any(target_arch = "aarch64", target_arch = "arm64ec"),
27919            link_name = "llvm.aarch64.neon.smax.v4i32"
27920        )]
27921        fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
27922    }
27923    unsafe { _vmaxq_s32(a, b) }
27924}
27925#[doc = "Maximum (vector)"]
27926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
27927#[inline]
27928#[target_feature(enable = "neon")]
27929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27931#[cfg_attr(
27932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27933    assert_instr(umax)
27934)]
27935#[cfg_attr(
27936    not(target_arch = "arm"),
27937    stable(feature = "neon_intrinsics", since = "1.59.0")
27938)]
27939#[cfg_attr(
27940    target_arch = "arm",
27941    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27942)]
27943pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27944    unsafe extern "unadjusted" {
27945        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")]
27946        #[cfg_attr(
27947            any(target_arch = "aarch64", target_arch = "arm64ec"),
27948            link_name = "llvm.aarch64.neon.umax.v8i8"
27949        )]
27950        fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
27951    }
27952    unsafe { _vmax_u8(a, b) }
27953}
27954#[doc = "Maximum (vector)"]
27955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
27956#[inline]
27957#[target_feature(enable = "neon")]
27958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27960#[cfg_attr(
27961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27962    assert_instr(umax)
27963)]
27964#[cfg_attr(
27965    not(target_arch = "arm"),
27966    stable(feature = "neon_intrinsics", since = "1.59.0")
27967)]
27968#[cfg_attr(
27969    target_arch = "arm",
27970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27971)]
27972pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27973    unsafe extern "unadjusted" {
27974        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")]
27975        #[cfg_attr(
27976            any(target_arch = "aarch64", target_arch = "arm64ec"),
27977            link_name = "llvm.aarch64.neon.umax.v16i8"
27978        )]
27979        fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
27980    }
27981    unsafe { _vmaxq_u8(a, b) }
27982}
27983#[doc = "Maximum (vector)"]
27984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
27985#[inline]
27986#[target_feature(enable = "neon")]
27987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27989#[cfg_attr(
27990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27991    assert_instr(umax)
27992)]
27993#[cfg_attr(
27994    not(target_arch = "arm"),
27995    stable(feature = "neon_intrinsics", since = "1.59.0")
27996)]
27997#[cfg_attr(
27998    target_arch = "arm",
27999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28000)]
28001pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28002    unsafe extern "unadjusted" {
28003        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")]
28004        #[cfg_attr(
28005            any(target_arch = "aarch64", target_arch = "arm64ec"),
28006            link_name = "llvm.aarch64.neon.umax.v4i16"
28007        )]
28008        fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
28009    }
28010    unsafe { _vmax_u16(a, b) }
28011}
28012#[doc = "Maximum (vector)"]
28013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
28014#[inline]
28015#[target_feature(enable = "neon")]
28016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28018#[cfg_attr(
28019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28020    assert_instr(umax)
28021)]
28022#[cfg_attr(
28023    not(target_arch = "arm"),
28024    stable(feature = "neon_intrinsics", since = "1.59.0")
28025)]
28026#[cfg_attr(
28027    target_arch = "arm",
28028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28029)]
28030pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28031    unsafe extern "unadjusted" {
28032        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")]
28033        #[cfg_attr(
28034            any(target_arch = "aarch64", target_arch = "arm64ec"),
28035            link_name = "llvm.aarch64.neon.umax.v8i16"
28036        )]
28037        fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
28038    }
28039    unsafe { _vmaxq_u16(a, b) }
28040}
28041#[doc = "Maximum (vector)"]
28042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
28043#[inline]
28044#[target_feature(enable = "neon")]
28045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28047#[cfg_attr(
28048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28049    assert_instr(umax)
28050)]
28051#[cfg_attr(
28052    not(target_arch = "arm"),
28053    stable(feature = "neon_intrinsics", since = "1.59.0")
28054)]
28055#[cfg_attr(
28056    target_arch = "arm",
28057    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28058)]
28059pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28060    unsafe extern "unadjusted" {
28061        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")]
28062        #[cfg_attr(
28063            any(target_arch = "aarch64", target_arch = "arm64ec"),
28064            link_name = "llvm.aarch64.neon.umax.v2i32"
28065        )]
28066        fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
28067    }
28068    unsafe { _vmax_u32(a, b) }
28069}
28070#[doc = "Maximum (vector)"]
28071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
28072#[inline]
28073#[target_feature(enable = "neon")]
28074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28076#[cfg_attr(
28077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28078    assert_instr(umax)
28079)]
28080#[cfg_attr(
28081    not(target_arch = "arm"),
28082    stable(feature = "neon_intrinsics", since = "1.59.0")
28083)]
28084#[cfg_attr(
28085    target_arch = "arm",
28086    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28087)]
28088pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28089    unsafe extern "unadjusted" {
28090        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")]
28091        #[cfg_attr(
28092            any(target_arch = "aarch64", target_arch = "arm64ec"),
28093            link_name = "llvm.aarch64.neon.umax.v4i32"
28094        )]
28095        fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28096    }
28097    unsafe { _vmaxq_u32(a, b) }
28098}
28099#[doc = "Floating-point Maximum Number (vector)"]
28100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
28101#[inline]
28102#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28104#[cfg_attr(
28105    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28106    assert_instr(fmaxnm)
28107)]
28108#[target_feature(enable = "neon,fp16")]
28109#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28110pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28111    unsafe extern "unadjusted" {
28112        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
28113        #[cfg_attr(
28114            any(target_arch = "aarch64", target_arch = "arm64ec"),
28115            link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
28116        )]
28117        fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28118    }
28119    unsafe { _vmaxnm_f16(a, b) }
28120}
28121#[doc = "Floating-point Maximum Number (vector)"]
28122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
28123#[inline]
28124#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28125#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28126#[cfg_attr(
28127    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28128    assert_instr(fmaxnm)
28129)]
28130#[target_feature(enable = "neon,fp16")]
28131#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28132pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28133    unsafe extern "unadjusted" {
28134        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
28135        #[cfg_attr(
28136            any(target_arch = "aarch64", target_arch = "arm64ec"),
28137            link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
28138        )]
28139        fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28140    }
28141    unsafe { _vmaxnmq_f16(a, b) }
28142}
28143#[doc = "Floating-point Maximum Number (vector)"]
28144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
28145#[inline]
28146#[target_feature(enable = "neon")]
28147#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28149#[cfg_attr(
28150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28151    assert_instr(fmaxnm)
28152)]
28153#[cfg_attr(
28154    not(target_arch = "arm"),
28155    stable(feature = "neon_intrinsics", since = "1.59.0")
28156)]
28157#[cfg_attr(
28158    target_arch = "arm",
28159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28160)]
28161pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28162    unsafe extern "unadjusted" {
28163        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
28164        #[cfg_attr(
28165            any(target_arch = "aarch64", target_arch = "arm64ec"),
28166            link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
28167        )]
28168        fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28169    }
28170    unsafe { _vmaxnm_f32(a, b) }
28171}
28172#[doc = "Floating-point Maximum Number (vector)"]
28173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
28174#[inline]
28175#[target_feature(enable = "neon")]
28176#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28178#[cfg_attr(
28179    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28180    assert_instr(fmaxnm)
28181)]
28182#[cfg_attr(
28183    not(target_arch = "arm"),
28184    stable(feature = "neon_intrinsics", since = "1.59.0")
28185)]
28186#[cfg_attr(
28187    target_arch = "arm",
28188    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28189)]
28190pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28191    unsafe extern "unadjusted" {
28192        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
28193        #[cfg_attr(
28194            any(target_arch = "aarch64", target_arch = "arm64ec"),
28195            link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
28196        )]
28197        fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28198    }
28199    unsafe { _vmaxnmq_f32(a, b) }
28200}
28201#[doc = "Minimum (vector)"]
28202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
28203#[inline]
28204#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28206#[cfg_attr(
28207    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28208    assert_instr(fmin)
28209)]
28210#[target_feature(enable = "neon,fp16")]
28211#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28212pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28213    unsafe extern "unadjusted" {
28214        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")]
28215        #[cfg_attr(
28216            any(target_arch = "aarch64", target_arch = "arm64ec"),
28217            link_name = "llvm.aarch64.neon.fmin.v4f16"
28218        )]
28219        fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28220    }
28221    unsafe { _vmin_f16(a, b) }
28222}
28223#[doc = "Minimum (vector)"]
28224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
28225#[inline]
28226#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28228#[cfg_attr(
28229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28230    assert_instr(fmin)
28231)]
28232#[target_feature(enable = "neon,fp16")]
28233#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28234pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28235    unsafe extern "unadjusted" {
28236        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")]
28237        #[cfg_attr(
28238            any(target_arch = "aarch64", target_arch = "arm64ec"),
28239            link_name = "llvm.aarch64.neon.fmin.v8f16"
28240        )]
28241        fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28242    }
28243    unsafe { _vminq_f16(a, b) }
28244}
28245#[doc = "Minimum (vector)"]
28246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
28247#[inline]
28248#[target_feature(enable = "neon")]
28249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28251#[cfg_attr(
28252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28253    assert_instr(fmin)
28254)]
28255#[cfg_attr(
28256    not(target_arch = "arm"),
28257    stable(feature = "neon_intrinsics", since = "1.59.0")
28258)]
28259#[cfg_attr(
28260    target_arch = "arm",
28261    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28262)]
28263pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28264    unsafe extern "unadjusted" {
28265        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")]
28266        #[cfg_attr(
28267            any(target_arch = "aarch64", target_arch = "arm64ec"),
28268            link_name = "llvm.aarch64.neon.fmin.v2f32"
28269        )]
28270        fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28271    }
28272    unsafe { _vmin_f32(a, b) }
28273}
28274#[doc = "Minimum (vector)"]
28275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
28276#[inline]
28277#[target_feature(enable = "neon")]
28278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28280#[cfg_attr(
28281    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28282    assert_instr(fmin)
28283)]
28284#[cfg_attr(
28285    not(target_arch = "arm"),
28286    stable(feature = "neon_intrinsics", since = "1.59.0")
28287)]
28288#[cfg_attr(
28289    target_arch = "arm",
28290    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28291)]
28292pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28293    unsafe extern "unadjusted" {
28294        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
28295        #[cfg_attr(
28296            any(target_arch = "aarch64", target_arch = "arm64ec"),
28297            link_name = "llvm.aarch64.neon.fmin.v4f32"
28298        )]
28299        fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28300    }
28301    unsafe { _vminq_f32(a, b) }
28302}
28303#[doc = "Minimum (vector)"]
28304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
28305#[inline]
28306#[target_feature(enable = "neon")]
28307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28309#[cfg_attr(
28310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28311    assert_instr(smin)
28312)]
28313#[cfg_attr(
28314    not(target_arch = "arm"),
28315    stable(feature = "neon_intrinsics", since = "1.59.0")
28316)]
28317#[cfg_attr(
28318    target_arch = "arm",
28319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28320)]
28321pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28322    unsafe extern "unadjusted" {
28323        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")]
28324        #[cfg_attr(
28325            any(target_arch = "aarch64", target_arch = "arm64ec"),
28326            link_name = "llvm.aarch64.neon.smin.v8i8"
28327        )]
28328        fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
28329    }
28330    unsafe { _vmin_s8(a, b) }
28331}
28332#[doc = "Minimum (vector)"]
28333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
28334#[inline]
28335#[target_feature(enable = "neon")]
28336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28338#[cfg_attr(
28339    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28340    assert_instr(smin)
28341)]
28342#[cfg_attr(
28343    not(target_arch = "arm"),
28344    stable(feature = "neon_intrinsics", since = "1.59.0")
28345)]
28346#[cfg_attr(
28347    target_arch = "arm",
28348    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28349)]
28350pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28351    unsafe extern "unadjusted" {
28352        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")]
28353        #[cfg_attr(
28354            any(target_arch = "aarch64", target_arch = "arm64ec"),
28355            link_name = "llvm.aarch64.neon.smin.v16i8"
28356        )]
28357        fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
28358    }
28359    unsafe { _vminq_s8(a, b) }
28360}
28361#[doc = "Minimum (vector)"]
28362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
28363#[inline]
28364#[target_feature(enable = "neon")]
28365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28367#[cfg_attr(
28368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28369    assert_instr(smin)
28370)]
28371#[cfg_attr(
28372    not(target_arch = "arm"),
28373    stable(feature = "neon_intrinsics", since = "1.59.0")
28374)]
28375#[cfg_attr(
28376    target_arch = "arm",
28377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28378)]
28379pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28380    unsafe extern "unadjusted" {
28381        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")]
28382        #[cfg_attr(
28383            any(target_arch = "aarch64", target_arch = "arm64ec"),
28384            link_name = "llvm.aarch64.neon.smin.v4i16"
28385        )]
28386        fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
28387    }
28388    unsafe { _vmin_s16(a, b) }
28389}
28390#[doc = "Minimum (vector)"]
28391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
28392#[inline]
28393#[target_feature(enable = "neon")]
28394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28396#[cfg_attr(
28397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28398    assert_instr(smin)
28399)]
28400#[cfg_attr(
28401    not(target_arch = "arm"),
28402    stable(feature = "neon_intrinsics", since = "1.59.0")
28403)]
28404#[cfg_attr(
28405    target_arch = "arm",
28406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28407)]
28408pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28409    unsafe extern "unadjusted" {
28410        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")]
28411        #[cfg_attr(
28412            any(target_arch = "aarch64", target_arch = "arm64ec"),
28413            link_name = "llvm.aarch64.neon.smin.v8i16"
28414        )]
28415        fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
28416    }
28417    unsafe { _vminq_s16(a, b) }
28418}
28419#[doc = "Minimum (vector)"]
28420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
28421#[inline]
28422#[target_feature(enable = "neon")]
28423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28425#[cfg_attr(
28426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28427    assert_instr(smin)
28428)]
28429#[cfg_attr(
28430    not(target_arch = "arm"),
28431    stable(feature = "neon_intrinsics", since = "1.59.0")
28432)]
28433#[cfg_attr(
28434    target_arch = "arm",
28435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28436)]
28437pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28438    unsafe extern "unadjusted" {
28439        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")]
28440        #[cfg_attr(
28441            any(target_arch = "aarch64", target_arch = "arm64ec"),
28442            link_name = "llvm.aarch64.neon.smin.v2i32"
28443        )]
28444        fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
28445    }
28446    unsafe { _vmin_s32(a, b) }
28447}
28448#[doc = "Minimum (vector)"]
28449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
28450#[inline]
28451#[target_feature(enable = "neon")]
28452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28454#[cfg_attr(
28455    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28456    assert_instr(smin)
28457)]
28458#[cfg_attr(
28459    not(target_arch = "arm"),
28460    stable(feature = "neon_intrinsics", since = "1.59.0")
28461)]
28462#[cfg_attr(
28463    target_arch = "arm",
28464    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28465)]
28466pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28467    unsafe extern "unadjusted" {
28468        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")]
28469        #[cfg_attr(
28470            any(target_arch = "aarch64", target_arch = "arm64ec"),
28471            link_name = "llvm.aarch64.neon.smin.v4i32"
28472        )]
28473        fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
28474    }
28475    unsafe { _vminq_s32(a, b) }
28476}
28477#[doc = "Minimum (vector)"]
28478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
28479#[inline]
28480#[target_feature(enable = "neon")]
28481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28483#[cfg_attr(
28484    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28485    assert_instr(umin)
28486)]
28487#[cfg_attr(
28488    not(target_arch = "arm"),
28489    stable(feature = "neon_intrinsics", since = "1.59.0")
28490)]
28491#[cfg_attr(
28492    target_arch = "arm",
28493    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28494)]
28495pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28496    unsafe extern "unadjusted" {
28497        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")]
28498        #[cfg_attr(
28499            any(target_arch = "aarch64", target_arch = "arm64ec"),
28500            link_name = "llvm.aarch64.neon.umin.v8i8"
28501        )]
28502        fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
28503    }
28504    unsafe { _vmin_u8(a, b) }
28505}
28506#[doc = "Minimum (vector)"]
28507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
28508#[inline]
28509#[target_feature(enable = "neon")]
28510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28511#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28512#[cfg_attr(
28513    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28514    assert_instr(umin)
28515)]
28516#[cfg_attr(
28517    not(target_arch = "arm"),
28518    stable(feature = "neon_intrinsics", since = "1.59.0")
28519)]
28520#[cfg_attr(
28521    target_arch = "arm",
28522    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28523)]
28524pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28525    unsafe extern "unadjusted" {
28526        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")]
28527        #[cfg_attr(
28528            any(target_arch = "aarch64", target_arch = "arm64ec"),
28529            link_name = "llvm.aarch64.neon.umin.v16i8"
28530        )]
28531        fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
28532    }
28533    unsafe { _vminq_u8(a, b) }
28534}
28535#[doc = "Minimum (vector)"]
28536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
28537#[inline]
28538#[target_feature(enable = "neon")]
28539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28541#[cfg_attr(
28542    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28543    assert_instr(umin)
28544)]
28545#[cfg_attr(
28546    not(target_arch = "arm"),
28547    stable(feature = "neon_intrinsics", since = "1.59.0")
28548)]
28549#[cfg_attr(
28550    target_arch = "arm",
28551    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28552)]
28553pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28554    unsafe extern "unadjusted" {
28555        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")]
28556        #[cfg_attr(
28557            any(target_arch = "aarch64", target_arch = "arm64ec"),
28558            link_name = "llvm.aarch64.neon.umin.v4i16"
28559        )]
28560        fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
28561    }
28562    unsafe { _vmin_u16(a, b) }
28563}
28564#[doc = "Minimum (vector)"]
28565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
28566#[inline]
28567#[target_feature(enable = "neon")]
28568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28570#[cfg_attr(
28571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28572    assert_instr(umin)
28573)]
28574#[cfg_attr(
28575    not(target_arch = "arm"),
28576    stable(feature = "neon_intrinsics", since = "1.59.0")
28577)]
28578#[cfg_attr(
28579    target_arch = "arm",
28580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28581)]
28582pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28583    unsafe extern "unadjusted" {
28584        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")]
28585        #[cfg_attr(
28586            any(target_arch = "aarch64", target_arch = "arm64ec"),
28587            link_name = "llvm.aarch64.neon.umin.v8i16"
28588        )]
28589        fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
28590    }
28591    unsafe { _vminq_u16(a, b) }
28592}
28593#[doc = "Minimum (vector)"]
28594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
28595#[inline]
28596#[target_feature(enable = "neon")]
28597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28599#[cfg_attr(
28600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28601    assert_instr(umin)
28602)]
28603#[cfg_attr(
28604    not(target_arch = "arm"),
28605    stable(feature = "neon_intrinsics", since = "1.59.0")
28606)]
28607#[cfg_attr(
28608    target_arch = "arm",
28609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28610)]
28611pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28612    unsafe extern "unadjusted" {
28613        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")]
28614        #[cfg_attr(
28615            any(target_arch = "aarch64", target_arch = "arm64ec"),
28616            link_name = "llvm.aarch64.neon.umin.v2i32"
28617        )]
28618        fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
28619    }
28620    unsafe { _vmin_u32(a, b) }
28621}
28622#[doc = "Minimum (vector)"]
28623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
28624#[inline]
28625#[target_feature(enable = "neon")]
28626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28628#[cfg_attr(
28629    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28630    assert_instr(umin)
28631)]
28632#[cfg_attr(
28633    not(target_arch = "arm"),
28634    stable(feature = "neon_intrinsics", since = "1.59.0")
28635)]
28636#[cfg_attr(
28637    target_arch = "arm",
28638    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28639)]
28640pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28641    unsafe extern "unadjusted" {
28642        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")]
28643        #[cfg_attr(
28644            any(target_arch = "aarch64", target_arch = "arm64ec"),
28645            link_name = "llvm.aarch64.neon.umin.v4i32"
28646        )]
28647        fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28648    }
28649    unsafe { _vminq_u32(a, b) }
28650}
28651#[doc = "Floating-point Minimum Number (vector)"]
28652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
28653#[inline]
28654#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28656#[cfg_attr(
28657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28658    assert_instr(fminnm)
28659)]
28660#[target_feature(enable = "neon,fp16")]
28661#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28662pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28663    unsafe extern "unadjusted" {
28664        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
28665        #[cfg_attr(
28666            any(target_arch = "aarch64", target_arch = "arm64ec"),
28667            link_name = "llvm.aarch64.neon.fminnm.v4f16"
28668        )]
28669        fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28670    }
28671    unsafe { _vminnm_f16(a, b) }
28672}
28673#[doc = "Floating-point Minimum Number (vector)"]
28674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
28675#[inline]
28676#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28677#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28678#[cfg_attr(
28679    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28680    assert_instr(fminnm)
28681)]
28682#[target_feature(enable = "neon,fp16")]
28683#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28684pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28685    unsafe extern "unadjusted" {
28686        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
28687        #[cfg_attr(
28688            any(target_arch = "aarch64", target_arch = "arm64ec"),
28689            link_name = "llvm.aarch64.neon.fminnm.v8f16"
28690        )]
28691        fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28692    }
28693    unsafe { _vminnmq_f16(a, b) }
28694}
28695#[doc = "Floating-point Minimum Number (vector)"]
28696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
28697#[inline]
28698#[target_feature(enable = "neon")]
28699#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28701#[cfg_attr(
28702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28703    assert_instr(fminnm)
28704)]
28705#[cfg_attr(
28706    not(target_arch = "arm"),
28707    stable(feature = "neon_intrinsics", since = "1.59.0")
28708)]
28709#[cfg_attr(
28710    target_arch = "arm",
28711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28712)]
28713pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28714    unsafe extern "unadjusted" {
28715        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
28716        #[cfg_attr(
28717            any(target_arch = "aarch64", target_arch = "arm64ec"),
28718            link_name = "llvm.aarch64.neon.fminnm.v2f32"
28719        )]
28720        fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28721    }
28722    unsafe { _vminnm_f32(a, b) }
28723}
28724#[doc = "Floating-point Minimum Number (vector)"]
28725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
28726#[inline]
28727#[target_feature(enable = "neon")]
28728#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28730#[cfg_attr(
28731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28732    assert_instr(fminnm)
28733)]
28734#[cfg_attr(
28735    not(target_arch = "arm"),
28736    stable(feature = "neon_intrinsics", since = "1.59.0")
28737)]
28738#[cfg_attr(
28739    target_arch = "arm",
28740    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28741)]
28742pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28743    unsafe extern "unadjusted" {
28744        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
28745        #[cfg_attr(
28746            any(target_arch = "aarch64", target_arch = "arm64ec"),
28747            link_name = "llvm.aarch64.neon.fminnm.v4f32"
28748        )]
28749        fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28750    }
28751    unsafe { _vminnmq_f32(a, b) }
28752}
28753#[doc = "Floating-point multiply-add to accumulator"]
28754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
28755#[inline]
28756#[target_feature(enable = "neon")]
28757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28759#[cfg_attr(
28760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28761    assert_instr(fmul)
28762)]
28763#[cfg_attr(
28764    not(target_arch = "arm"),
28765    stable(feature = "neon_intrinsics", since = "1.59.0")
28766)]
28767#[cfg_attr(
28768    target_arch = "arm",
28769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28770)]
28771pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
28772    unsafe { simd_add(a, simd_mul(b, c)) }
28773}
28774#[doc = "Floating-point multiply-add to accumulator"]
28775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
28776#[inline]
28777#[target_feature(enable = "neon")]
28778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28780#[cfg_attr(
28781    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28782    assert_instr(fmul)
28783)]
28784#[cfg_attr(
28785    not(target_arch = "arm"),
28786    stable(feature = "neon_intrinsics", since = "1.59.0")
28787)]
28788#[cfg_attr(
28789    target_arch = "arm",
28790    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28791)]
28792pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
28793    unsafe { simd_add(a, simd_mul(b, c)) }
28794}
28795#[doc = "Vector multiply accumulate with scalar"]
28796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
28797#[inline]
28798#[target_feature(enable = "neon")]
28799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28800#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28801#[cfg_attr(
28802    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28803    assert_instr(fmul, LANE = 1)
28804)]
28805#[rustc_legacy_const_generics(3)]
28806#[cfg_attr(
28807    not(target_arch = "arm"),
28808    stable(feature = "neon_intrinsics", since = "1.59.0")
28809)]
28810#[cfg_attr(
28811    target_arch = "arm",
28812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28813)]
28814pub fn vmla_lane_f32<const LANE: i32>(
28815    a: float32x2_t,
28816    b: float32x2_t,
28817    c: float32x2_t,
28818) -> float32x2_t {
28819    static_assert_uimm_bits!(LANE, 1);
28820    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28821}
28822#[doc = "Vector multiply accumulate with scalar"]
28823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
28824#[inline]
28825#[target_feature(enable = "neon")]
28826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28827#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28828#[cfg_attr(
28829    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28830    assert_instr(fmul, LANE = 1)
28831)]
28832#[rustc_legacy_const_generics(3)]
28833#[cfg_attr(
28834    not(target_arch = "arm"),
28835    stable(feature = "neon_intrinsics", since = "1.59.0")
28836)]
28837#[cfg_attr(
28838    target_arch = "arm",
28839    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28840)]
28841pub fn vmla_laneq_f32<const LANE: i32>(
28842    a: float32x2_t,
28843    b: float32x2_t,
28844    c: float32x4_t,
28845) -> float32x2_t {
28846    static_assert_uimm_bits!(LANE, 2);
28847    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28848}
28849#[doc = "Vector multiply accumulate with scalar"]
28850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
28851#[inline]
28852#[target_feature(enable = "neon")]
28853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28854#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28855#[cfg_attr(
28856    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28857    assert_instr(fmul, LANE = 1)
28858)]
28859#[rustc_legacy_const_generics(3)]
28860#[cfg_attr(
28861    not(target_arch = "arm"),
28862    stable(feature = "neon_intrinsics", since = "1.59.0")
28863)]
28864#[cfg_attr(
28865    target_arch = "arm",
28866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28867)]
28868pub fn vmlaq_lane_f32<const LANE: i32>(
28869    a: float32x4_t,
28870    b: float32x4_t,
28871    c: float32x2_t,
28872) -> float32x4_t {
28873    static_assert_uimm_bits!(LANE, 1);
28874    unsafe {
28875        vmlaq_f32(
28876            a,
28877            b,
28878            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28879        )
28880    }
28881}
28882#[doc = "Vector multiply accumulate with scalar"]
28883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
28884#[inline]
28885#[target_feature(enable = "neon")]
28886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28887#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28888#[cfg_attr(
28889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28890    assert_instr(fmul, LANE = 1)
28891)]
28892#[rustc_legacy_const_generics(3)]
28893#[cfg_attr(
28894    not(target_arch = "arm"),
28895    stable(feature = "neon_intrinsics", since = "1.59.0")
28896)]
28897#[cfg_attr(
28898    target_arch = "arm",
28899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28900)]
28901pub fn vmlaq_laneq_f32<const LANE: i32>(
28902    a: float32x4_t,
28903    b: float32x4_t,
28904    c: float32x4_t,
28905) -> float32x4_t {
28906    static_assert_uimm_bits!(LANE, 2);
28907    unsafe {
28908        vmlaq_f32(
28909            a,
28910            b,
28911            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28912        )
28913    }
28914}
28915#[doc = "Vector multiply accumulate with scalar"]
28916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
28917#[inline]
28918#[target_feature(enable = "neon")]
28919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28921#[cfg_attr(
28922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28923    assert_instr(mla, LANE = 1)
28924)]
28925#[rustc_legacy_const_generics(3)]
28926#[cfg_attr(
28927    not(target_arch = "arm"),
28928    stable(feature = "neon_intrinsics", since = "1.59.0")
28929)]
28930#[cfg_attr(
28931    target_arch = "arm",
28932    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28933)]
28934pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
28935    static_assert_uimm_bits!(LANE, 2);
28936    unsafe {
28937        vmla_s16(
28938            a,
28939            b,
28940            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28941        )
28942    }
28943}
28944#[doc = "Vector multiply accumulate with scalar"]
28945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
28946#[inline]
28947#[target_feature(enable = "neon")]
28948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28949#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28950#[cfg_attr(
28951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28952    assert_instr(mla, LANE = 1)
28953)]
28954#[rustc_legacy_const_generics(3)]
28955#[cfg_attr(
28956    not(target_arch = "arm"),
28957    stable(feature = "neon_intrinsics", since = "1.59.0")
28958)]
28959#[cfg_attr(
28960    target_arch = "arm",
28961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28962)]
28963pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
28964    static_assert_uimm_bits!(LANE, 2);
28965    unsafe {
28966        vmla_u16(
28967            a,
28968            b,
28969            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28970        )
28971    }
28972}
28973#[doc = "Vector multiply accumulate with scalar"]
28974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
28975#[inline]
28976#[target_feature(enable = "neon")]
28977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28979#[cfg_attr(
28980    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28981    assert_instr(mla, LANE = 1)
28982)]
28983#[rustc_legacy_const_generics(3)]
28984#[cfg_attr(
28985    not(target_arch = "arm"),
28986    stable(feature = "neon_intrinsics", since = "1.59.0")
28987)]
28988#[cfg_attr(
28989    target_arch = "arm",
28990    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28991)]
28992pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
28993    static_assert_uimm_bits!(LANE, 3);
28994    unsafe {
28995        vmla_s16(
28996            a,
28997            b,
28998            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28999        )
29000    }
29001}
29002#[doc = "Vector multiply accumulate with scalar"]
29003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
29004#[inline]
29005#[target_feature(enable = "neon")]
29006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29008#[cfg_attr(
29009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29010    assert_instr(mla, LANE = 1)
29011)]
29012#[rustc_legacy_const_generics(3)]
29013#[cfg_attr(
29014    not(target_arch = "arm"),
29015    stable(feature = "neon_intrinsics", since = "1.59.0")
29016)]
29017#[cfg_attr(
29018    target_arch = "arm",
29019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29020)]
29021pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
29022    static_assert_uimm_bits!(LANE, 3);
29023    unsafe {
29024        vmla_u16(
29025            a,
29026            b,
29027            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29028        )
29029    }
29030}
29031#[doc = "Vector multiply accumulate with scalar"]
29032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
29033#[inline]
29034#[target_feature(enable = "neon")]
29035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29036#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29037#[cfg_attr(
29038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29039    assert_instr(mla, LANE = 1)
29040)]
29041#[rustc_legacy_const_generics(3)]
29042#[cfg_attr(
29043    not(target_arch = "arm"),
29044    stable(feature = "neon_intrinsics", since = "1.59.0")
29045)]
29046#[cfg_attr(
29047    target_arch = "arm",
29048    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29049)]
29050pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
29051    static_assert_uimm_bits!(LANE, 2);
29052    unsafe {
29053        vmlaq_s16(
29054            a,
29055            b,
29056            simd_shuffle!(
29057                c,
29058                c,
29059                [
29060                    LANE as u32,
29061                    LANE as u32,
29062                    LANE as u32,
29063                    LANE as u32,
29064                    LANE as u32,
29065                    LANE as u32,
29066                    LANE as u32,
29067                    LANE as u32
29068                ]
29069            ),
29070        )
29071    }
29072}
29073#[doc = "Vector multiply accumulate with scalar"]
29074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
29075#[inline]
29076#[target_feature(enable = "neon")]
29077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29078#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29079#[cfg_attr(
29080    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29081    assert_instr(mla, LANE = 1)
29082)]
29083#[rustc_legacy_const_generics(3)]
29084#[cfg_attr(
29085    not(target_arch = "arm"),
29086    stable(feature = "neon_intrinsics", since = "1.59.0")
29087)]
29088#[cfg_attr(
29089    target_arch = "arm",
29090    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29091)]
29092pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
29093    static_assert_uimm_bits!(LANE, 2);
29094    unsafe {
29095        vmlaq_u16(
29096            a,
29097            b,
29098            simd_shuffle!(
29099                c,
29100                c,
29101                [
29102                    LANE as u32,
29103                    LANE as u32,
29104                    LANE as u32,
29105                    LANE as u32,
29106                    LANE as u32,
29107                    LANE as u32,
29108                    LANE as u32,
29109                    LANE as u32
29110                ]
29111            ),
29112        )
29113    }
29114}
29115#[doc = "Vector multiply accumulate with scalar"]
29116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
29117#[inline]
29118#[target_feature(enable = "neon")]
29119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29120#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29121#[cfg_attr(
29122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29123    assert_instr(mla, LANE = 1)
29124)]
29125#[rustc_legacy_const_generics(3)]
29126#[cfg_attr(
29127    not(target_arch = "arm"),
29128    stable(feature = "neon_intrinsics", since = "1.59.0")
29129)]
29130#[cfg_attr(
29131    target_arch = "arm",
29132    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29133)]
29134pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29135    static_assert_uimm_bits!(LANE, 3);
29136    unsafe {
29137        vmlaq_s16(
29138            a,
29139            b,
29140            simd_shuffle!(
29141                c,
29142                c,
29143                [
29144                    LANE as u32,
29145                    LANE as u32,
29146                    LANE as u32,
29147                    LANE as u32,
29148                    LANE as u32,
29149                    LANE as u32,
29150                    LANE as u32,
29151                    LANE as u32
29152                ]
29153            ),
29154        )
29155    }
29156}
29157#[doc = "Vector multiply accumulate with scalar"]
29158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
29159#[inline]
29160#[target_feature(enable = "neon")]
29161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29162#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29163#[cfg_attr(
29164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29165    assert_instr(mla, LANE = 1)
29166)]
29167#[rustc_legacy_const_generics(3)]
29168#[cfg_attr(
29169    not(target_arch = "arm"),
29170    stable(feature = "neon_intrinsics", since = "1.59.0")
29171)]
29172#[cfg_attr(
29173    target_arch = "arm",
29174    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29175)]
29176pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29177    static_assert_uimm_bits!(LANE, 3);
29178    unsafe {
29179        vmlaq_u16(
29180            a,
29181            b,
29182            simd_shuffle!(
29183                c,
29184                c,
29185                [
29186                    LANE as u32,
29187                    LANE as u32,
29188                    LANE as u32,
29189                    LANE as u32,
29190                    LANE as u32,
29191                    LANE as u32,
29192                    LANE as u32,
29193                    LANE as u32
29194                ]
29195            ),
29196        )
29197    }
29198}
29199#[doc = "Vector multiply accumulate with scalar"]
29200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
29201#[inline]
29202#[target_feature(enable = "neon")]
29203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29204#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29205#[cfg_attr(
29206    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29207    assert_instr(mla, LANE = 1)
29208)]
29209#[rustc_legacy_const_generics(3)]
29210#[cfg_attr(
29211    not(target_arch = "arm"),
29212    stable(feature = "neon_intrinsics", since = "1.59.0")
29213)]
29214#[cfg_attr(
29215    target_arch = "arm",
29216    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29217)]
29218pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29219    static_assert_uimm_bits!(LANE, 1);
29220    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29221}
29222#[doc = "Vector multiply accumulate with scalar"]
29223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
29224#[inline]
29225#[target_feature(enable = "neon")]
29226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29228#[cfg_attr(
29229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29230    assert_instr(mla, LANE = 1)
29231)]
29232#[rustc_legacy_const_generics(3)]
29233#[cfg_attr(
29234    not(target_arch = "arm"),
29235    stable(feature = "neon_intrinsics", since = "1.59.0")
29236)]
29237#[cfg_attr(
29238    target_arch = "arm",
29239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29240)]
29241pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29242    static_assert_uimm_bits!(LANE, 1);
29243    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29244}
29245#[doc = "Vector multiply accumulate with scalar"]
29246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
29247#[inline]
29248#[target_feature(enable = "neon")]
29249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29250#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29251#[cfg_attr(
29252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29253    assert_instr(mla, LANE = 1)
29254)]
29255#[rustc_legacy_const_generics(3)]
29256#[cfg_attr(
29257    not(target_arch = "arm"),
29258    stable(feature = "neon_intrinsics", since = "1.59.0")
29259)]
29260#[cfg_attr(
29261    target_arch = "arm",
29262    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29263)]
29264pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
29265    static_assert_uimm_bits!(LANE, 2);
29266    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29267}
29268#[doc = "Vector multiply accumulate with scalar"]
29269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
29270#[inline]
29271#[target_feature(enable = "neon")]
29272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29273#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29274#[cfg_attr(
29275    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29276    assert_instr(mla, LANE = 1)
29277)]
29278#[rustc_legacy_const_generics(3)]
29279#[cfg_attr(
29280    not(target_arch = "arm"),
29281    stable(feature = "neon_intrinsics", since = "1.59.0")
29282)]
29283#[cfg_attr(
29284    target_arch = "arm",
29285    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29286)]
29287pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
29288    static_assert_uimm_bits!(LANE, 2);
29289    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29290}
29291#[doc = "Vector multiply accumulate with scalar"]
29292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
29293#[inline]
29294#[target_feature(enable = "neon")]
29295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29296#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29297#[cfg_attr(
29298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29299    assert_instr(mla, LANE = 1)
29300)]
29301#[rustc_legacy_const_generics(3)]
29302#[cfg_attr(
29303    not(target_arch = "arm"),
29304    stable(feature = "neon_intrinsics", since = "1.59.0")
29305)]
29306#[cfg_attr(
29307    target_arch = "arm",
29308    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29309)]
29310pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
29311    static_assert_uimm_bits!(LANE, 1);
29312    unsafe {
29313        vmlaq_s32(
29314            a,
29315            b,
29316            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29317        )
29318    }
29319}
29320#[doc = "Vector multiply accumulate with scalar"]
29321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
29322#[inline]
29323#[target_feature(enable = "neon")]
29324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29325#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29326#[cfg_attr(
29327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29328    assert_instr(mla, LANE = 1)
29329)]
29330#[rustc_legacy_const_generics(3)]
29331#[cfg_attr(
29332    not(target_arch = "arm"),
29333    stable(feature = "neon_intrinsics", since = "1.59.0")
29334)]
29335#[cfg_attr(
29336    target_arch = "arm",
29337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29338)]
29339pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
29340    static_assert_uimm_bits!(LANE, 1);
29341    unsafe {
29342        vmlaq_u32(
29343            a,
29344            b,
29345            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29346        )
29347    }
29348}
29349#[doc = "Vector multiply accumulate with scalar"]
29350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
29351#[inline]
29352#[target_feature(enable = "neon")]
29353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29354#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29355#[cfg_attr(
29356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29357    assert_instr(mla, LANE = 1)
29358)]
29359#[rustc_legacy_const_generics(3)]
29360#[cfg_attr(
29361    not(target_arch = "arm"),
29362    stable(feature = "neon_intrinsics", since = "1.59.0")
29363)]
29364#[cfg_attr(
29365    target_arch = "arm",
29366    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29367)]
29368pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29369    static_assert_uimm_bits!(LANE, 2);
29370    unsafe {
29371        vmlaq_s32(
29372            a,
29373            b,
29374            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29375        )
29376    }
29377}
29378#[doc = "Vector multiply accumulate with scalar"]
29379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
29380#[inline]
29381#[target_feature(enable = "neon")]
29382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29383#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29384#[cfg_attr(
29385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29386    assert_instr(mla, LANE = 1)
29387)]
29388#[rustc_legacy_const_generics(3)]
29389#[cfg_attr(
29390    not(target_arch = "arm"),
29391    stable(feature = "neon_intrinsics", since = "1.59.0")
29392)]
29393#[cfg_attr(
29394    target_arch = "arm",
29395    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29396)]
29397pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29398    static_assert_uimm_bits!(LANE, 2);
29399    unsafe {
29400        vmlaq_u32(
29401            a,
29402            b,
29403            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29404        )
29405    }
29406}
29407#[doc = "Vector multiply accumulate with scalar"]
29408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
29409#[inline]
29410#[target_feature(enable = "neon")]
29411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29412#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29413#[cfg_attr(
29414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29415    assert_instr(fmul)
29416)]
29417#[cfg_attr(
29418    not(target_arch = "arm"),
29419    stable(feature = "neon_intrinsics", since = "1.59.0")
29420)]
29421#[cfg_attr(
29422    target_arch = "arm",
29423    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29424)]
29425pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
29426    vmla_f32(a, b, vdup_n_f32(c))
29427}
29428#[doc = "Vector multiply accumulate with scalar"]
29429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
29430#[inline]
29431#[target_feature(enable = "neon")]
29432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29433#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29434#[cfg_attr(
29435    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29436    assert_instr(fmul)
29437)]
29438#[cfg_attr(
29439    not(target_arch = "arm"),
29440    stable(feature = "neon_intrinsics", since = "1.59.0")
29441)]
29442#[cfg_attr(
29443    target_arch = "arm",
29444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29445)]
29446pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
29447    vmlaq_f32(a, b, vdupq_n_f32(c))
29448}
29449#[doc = "Vector multiply accumulate with scalar"]
29450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
29451#[inline]
29452#[target_feature(enable = "neon")]
29453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29455#[cfg_attr(
29456    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29457    assert_instr(mla)
29458)]
29459#[cfg_attr(
29460    not(target_arch = "arm"),
29461    stable(feature = "neon_intrinsics", since = "1.59.0")
29462)]
29463#[cfg_attr(
29464    target_arch = "arm",
29465    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29466)]
29467pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
29468    vmla_s16(a, b, vdup_n_s16(c))
29469}
29470#[doc = "Vector multiply accumulate with scalar"]
29471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
29472#[inline]
29473#[target_feature(enable = "neon")]
29474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29475#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29476#[cfg_attr(
29477    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29478    assert_instr(mla)
29479)]
29480#[cfg_attr(
29481    not(target_arch = "arm"),
29482    stable(feature = "neon_intrinsics", since = "1.59.0")
29483)]
29484#[cfg_attr(
29485    target_arch = "arm",
29486    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29487)]
29488pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
29489    vmlaq_s16(a, b, vdupq_n_s16(c))
29490}
29491#[doc = "Vector multiply accumulate with scalar"]
29492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
29493#[inline]
29494#[target_feature(enable = "neon")]
29495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29496#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29497#[cfg_attr(
29498    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29499    assert_instr(mla)
29500)]
29501#[cfg_attr(
29502    not(target_arch = "arm"),
29503    stable(feature = "neon_intrinsics", since = "1.59.0")
29504)]
29505#[cfg_attr(
29506    target_arch = "arm",
29507    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29508)]
29509pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
29510    vmla_u16(a, b, vdup_n_u16(c))
29511}
29512#[doc = "Vector multiply accumulate with scalar"]
29513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
29514#[inline]
29515#[target_feature(enable = "neon")]
29516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29518#[cfg_attr(
29519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29520    assert_instr(mla)
29521)]
29522#[cfg_attr(
29523    not(target_arch = "arm"),
29524    stable(feature = "neon_intrinsics", since = "1.59.0")
29525)]
29526#[cfg_attr(
29527    target_arch = "arm",
29528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29529)]
29530pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
29531    vmlaq_u16(a, b, vdupq_n_u16(c))
29532}
29533#[doc = "Vector multiply accumulate with scalar"]
29534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
29535#[inline]
29536#[target_feature(enable = "neon")]
29537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29539#[cfg_attr(
29540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29541    assert_instr(mla)
29542)]
29543#[cfg_attr(
29544    not(target_arch = "arm"),
29545    stable(feature = "neon_intrinsics", since = "1.59.0")
29546)]
29547#[cfg_attr(
29548    target_arch = "arm",
29549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29550)]
29551pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
29552    vmla_s32(a, b, vdup_n_s32(c))
29553}
29554#[doc = "Vector multiply accumulate with scalar"]
29555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
29556#[inline]
29557#[target_feature(enable = "neon")]
29558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29559#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29560#[cfg_attr(
29561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29562    assert_instr(mla)
29563)]
29564#[cfg_attr(
29565    not(target_arch = "arm"),
29566    stable(feature = "neon_intrinsics", since = "1.59.0")
29567)]
29568#[cfg_attr(
29569    target_arch = "arm",
29570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29571)]
29572pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
29573    vmlaq_s32(a, b, vdupq_n_s32(c))
29574}
29575#[doc = "Vector multiply accumulate with scalar"]
29576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
29577#[inline]
29578#[target_feature(enable = "neon")]
29579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29581#[cfg_attr(
29582    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29583    assert_instr(mla)
29584)]
29585#[cfg_attr(
29586    not(target_arch = "arm"),
29587    stable(feature = "neon_intrinsics", since = "1.59.0")
29588)]
29589#[cfg_attr(
29590    target_arch = "arm",
29591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29592)]
29593pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
29594    vmla_u32(a, b, vdup_n_u32(c))
29595}
29596#[doc = "Vector multiply accumulate with scalar"]
29597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
29598#[inline]
29599#[target_feature(enable = "neon")]
29600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29601#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29602#[cfg_attr(
29603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29604    assert_instr(mla)
29605)]
29606#[cfg_attr(
29607    not(target_arch = "arm"),
29608    stable(feature = "neon_intrinsics", since = "1.59.0")
29609)]
29610#[cfg_attr(
29611    target_arch = "arm",
29612    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29613)]
29614pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
29615    vmlaq_u32(a, b, vdupq_n_u32(c))
29616}
29617#[doc = "Multiply-add to accumulator"]
29618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
29619#[inline]
29620#[target_feature(enable = "neon")]
29621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29622#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29623#[cfg_attr(
29624    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29625    assert_instr(mla)
29626)]
29627#[cfg_attr(
29628    not(target_arch = "arm"),
29629    stable(feature = "neon_intrinsics", since = "1.59.0")
29630)]
29631#[cfg_attr(
29632    target_arch = "arm",
29633    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29634)]
29635pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
29636    unsafe { simd_add(a, simd_mul(b, c)) }
29637}
29638#[doc = "Multiply-add to accumulator"]
29639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
29640#[inline]
29641#[target_feature(enable = "neon")]
29642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29644#[cfg_attr(
29645    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29646    assert_instr(mla)
29647)]
29648#[cfg_attr(
29649    not(target_arch = "arm"),
29650    stable(feature = "neon_intrinsics", since = "1.59.0")
29651)]
29652#[cfg_attr(
29653    target_arch = "arm",
29654    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29655)]
29656pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
29657    unsafe { simd_add(a, simd_mul(b, c)) }
29658}
29659#[doc = "Multiply-add to accumulator"]
29660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
29661#[inline]
29662#[target_feature(enable = "neon")]
29663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29665#[cfg_attr(
29666    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29667    assert_instr(mla)
29668)]
29669#[cfg_attr(
29670    not(target_arch = "arm"),
29671    stable(feature = "neon_intrinsics", since = "1.59.0")
29672)]
29673#[cfg_attr(
29674    target_arch = "arm",
29675    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29676)]
29677pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
29678    unsafe { simd_add(a, simd_mul(b, c)) }
29679}
29680#[doc = "Multiply-add to accumulator"]
29681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
29682#[inline]
29683#[target_feature(enable = "neon")]
29684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29686#[cfg_attr(
29687    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29688    assert_instr(mla)
29689)]
29690#[cfg_attr(
29691    not(target_arch = "arm"),
29692    stable(feature = "neon_intrinsics", since = "1.59.0")
29693)]
29694#[cfg_attr(
29695    target_arch = "arm",
29696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29697)]
29698pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29699    unsafe { simd_add(a, simd_mul(b, c)) }
29700}
29701#[doc = "Multiply-add to accumulator"]
29702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
29703#[inline]
29704#[target_feature(enable = "neon")]
29705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29707#[cfg_attr(
29708    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29709    assert_instr(mla)
29710)]
29711#[cfg_attr(
29712    not(target_arch = "arm"),
29713    stable(feature = "neon_intrinsics", since = "1.59.0")
29714)]
29715#[cfg_attr(
29716    target_arch = "arm",
29717    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29718)]
29719pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29720    unsafe { simd_add(a, simd_mul(b, c)) }
29721}
29722#[doc = "Multiply-add to accumulator"]
29723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
29724#[inline]
29725#[target_feature(enable = "neon")]
29726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29727#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29728#[cfg_attr(
29729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29730    assert_instr(mla)
29731)]
29732#[cfg_attr(
29733    not(target_arch = "arm"),
29734    stable(feature = "neon_intrinsics", since = "1.59.0")
29735)]
29736#[cfg_attr(
29737    target_arch = "arm",
29738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29739)]
29740pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29741    unsafe { simd_add(a, simd_mul(b, c)) }
29742}
29743#[doc = "Multiply-add to accumulator"]
29744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
29745#[inline]
29746#[target_feature(enable = "neon")]
29747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29749#[cfg_attr(
29750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29751    assert_instr(mla)
29752)]
29753#[cfg_attr(
29754    not(target_arch = "arm"),
29755    stable(feature = "neon_intrinsics", since = "1.59.0")
29756)]
29757#[cfg_attr(
29758    target_arch = "arm",
29759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29760)]
29761pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
29762    unsafe { simd_add(a, simd_mul(b, c)) }
29763}
29764#[doc = "Multiply-add to accumulator"]
29765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
29766#[inline]
29767#[target_feature(enable = "neon")]
29768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29770#[cfg_attr(
29771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29772    assert_instr(mla)
29773)]
29774#[cfg_attr(
29775    not(target_arch = "arm"),
29776    stable(feature = "neon_intrinsics", since = "1.59.0")
29777)]
29778#[cfg_attr(
29779    target_arch = "arm",
29780    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29781)]
29782pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
29783    unsafe { simd_add(a, simd_mul(b, c)) }
29784}
29785#[doc = "Multiply-add to accumulator"]
29786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
29787#[inline]
29788#[target_feature(enable = "neon")]
29789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29791#[cfg_attr(
29792    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29793    assert_instr(mla)
29794)]
29795#[cfg_attr(
29796    not(target_arch = "arm"),
29797    stable(feature = "neon_intrinsics", since = "1.59.0")
29798)]
29799#[cfg_attr(
29800    target_arch = "arm",
29801    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29802)]
29803pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
29804    unsafe { simd_add(a, simd_mul(b, c)) }
29805}
29806#[doc = "Multiply-add to accumulator"]
29807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
29808#[inline]
29809#[target_feature(enable = "neon")]
29810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29811#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29812#[cfg_attr(
29813    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29814    assert_instr(mla)
29815)]
29816#[cfg_attr(
29817    not(target_arch = "arm"),
29818    stable(feature = "neon_intrinsics", since = "1.59.0")
29819)]
29820#[cfg_attr(
29821    target_arch = "arm",
29822    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29823)]
29824pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29825    unsafe { simd_add(a, simd_mul(b, c)) }
29826}
29827#[doc = "Multiply-add to accumulator"]
29828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
29829#[inline]
29830#[target_feature(enable = "neon")]
29831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29832#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29833#[cfg_attr(
29834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29835    assert_instr(mla)
29836)]
29837#[cfg_attr(
29838    not(target_arch = "arm"),
29839    stable(feature = "neon_intrinsics", since = "1.59.0")
29840)]
29841#[cfg_attr(
29842    target_arch = "arm",
29843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29844)]
29845pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29846    unsafe { simd_add(a, simd_mul(b, c)) }
29847}
29848#[doc = "Multiply-add to accumulator"]
29849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
29850#[inline]
29851#[target_feature(enable = "neon")]
29852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29853#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29854#[cfg_attr(
29855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29856    assert_instr(mla)
29857)]
29858#[cfg_attr(
29859    not(target_arch = "arm"),
29860    stable(feature = "neon_intrinsics", since = "1.59.0")
29861)]
29862#[cfg_attr(
29863    target_arch = "arm",
29864    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29865)]
29866pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29867    unsafe { simd_add(a, simd_mul(b, c)) }
29868}
29869#[doc = "Vector widening multiply accumulate with scalar"]
29870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
29871#[inline]
29872#[target_feature(enable = "neon")]
29873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29875#[cfg_attr(
29876    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29877    assert_instr(smlal, LANE = 1)
29878)]
29879#[rustc_legacy_const_generics(3)]
29880#[cfg_attr(
29881    not(target_arch = "arm"),
29882    stable(feature = "neon_intrinsics", since = "1.59.0")
29883)]
29884#[cfg_attr(
29885    target_arch = "arm",
29886    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29887)]
29888pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
29889    static_assert_uimm_bits!(LANE, 2);
29890    unsafe {
29891        vmlal_s16(
29892            a,
29893            b,
29894            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29895        )
29896    }
29897}
29898#[doc = "Vector widening multiply accumulate with scalar"]
29899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
29900#[inline]
29901#[target_feature(enable = "neon")]
29902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29903#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29904#[cfg_attr(
29905    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29906    assert_instr(smlal, LANE = 1)
29907)]
29908#[rustc_legacy_const_generics(3)]
29909#[cfg_attr(
29910    not(target_arch = "arm"),
29911    stable(feature = "neon_intrinsics", since = "1.59.0")
29912)]
29913#[cfg_attr(
29914    target_arch = "arm",
29915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29916)]
29917pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
29918    static_assert_uimm_bits!(LANE, 3);
29919    unsafe {
29920        vmlal_s16(
29921            a,
29922            b,
29923            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29924        )
29925    }
29926}
29927#[doc = "Vector widening multiply accumulate with scalar"]
29928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
29929#[inline]
29930#[target_feature(enable = "neon")]
29931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29933#[cfg_attr(
29934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29935    assert_instr(smlal, LANE = 1)
29936)]
29937#[rustc_legacy_const_generics(3)]
29938#[cfg_attr(
29939    not(target_arch = "arm"),
29940    stable(feature = "neon_intrinsics", since = "1.59.0")
29941)]
29942#[cfg_attr(
29943    target_arch = "arm",
29944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29945)]
29946pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
29947    static_assert_uimm_bits!(LANE, 1);
29948    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29949}
29950#[doc = "Vector widening multiply accumulate with scalar"]
29951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
29952#[inline]
29953#[target_feature(enable = "neon")]
29954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29956#[cfg_attr(
29957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29958    assert_instr(smlal, LANE = 1)
29959)]
29960#[rustc_legacy_const_generics(3)]
29961#[cfg_attr(
29962    not(target_arch = "arm"),
29963    stable(feature = "neon_intrinsics", since = "1.59.0")
29964)]
29965#[cfg_attr(
29966    target_arch = "arm",
29967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29968)]
29969pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
29970    static_assert_uimm_bits!(LANE, 2);
29971    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29972}
29973#[doc = "Vector widening multiply accumulate with scalar"]
29974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
29975#[inline]
29976#[target_feature(enable = "neon")]
29977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29979#[cfg_attr(
29980    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29981    assert_instr(umlal, LANE = 1)
29982)]
29983#[rustc_legacy_const_generics(3)]
29984#[cfg_attr(
29985    not(target_arch = "arm"),
29986    stable(feature = "neon_intrinsics", since = "1.59.0")
29987)]
29988#[cfg_attr(
29989    target_arch = "arm",
29990    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29991)]
29992pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
29993    static_assert_uimm_bits!(LANE, 2);
29994    unsafe {
29995        vmlal_u16(
29996            a,
29997            b,
29998            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29999        )
30000    }
30001}
30002#[doc = "Vector widening multiply accumulate with scalar"]
30003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
30004#[inline]
30005#[target_feature(enable = "neon")]
30006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
30008#[cfg_attr(
30009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30010    assert_instr(umlal, LANE = 1)
30011)]
30012#[rustc_legacy_const_generics(3)]
30013#[cfg_attr(
30014    not(target_arch = "arm"),
30015    stable(feature = "neon_intrinsics", since = "1.59.0")
30016)]
30017#[cfg_attr(
30018    target_arch = "arm",
30019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30020)]
30021pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
30022    static_assert_uimm_bits!(LANE, 3);
30023    unsafe {
30024        vmlal_u16(
30025            a,
30026            b,
30027            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30028        )
30029    }
30030}
30031#[doc = "Vector widening multiply accumulate with scalar"]
30032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
30033#[inline]
30034#[target_feature(enable = "neon")]
30035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30036#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
30037#[cfg_attr(
30038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30039    assert_instr(umlal, LANE = 1)
30040)]
30041#[rustc_legacy_const_generics(3)]
30042#[cfg_attr(
30043    not(target_arch = "arm"),
30044    stable(feature = "neon_intrinsics", since = "1.59.0")
30045)]
30046#[cfg_attr(
30047    target_arch = "arm",
30048    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30049)]
30050pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
30051    static_assert_uimm_bits!(LANE, 1);
30052    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30053}
30054#[doc = "Vector widening multiply accumulate with scalar"]
30055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
30056#[inline]
30057#[target_feature(enable = "neon")]
30058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30059#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
30060#[cfg_attr(
30061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30062    assert_instr(umlal, LANE = 1)
30063)]
30064#[rustc_legacy_const_generics(3)]
30065#[cfg_attr(
30066    not(target_arch = "arm"),
30067    stable(feature = "neon_intrinsics", since = "1.59.0")
30068)]
30069#[cfg_attr(
30070    target_arch = "arm",
30071    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30072)]
30073pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
30074    static_assert_uimm_bits!(LANE, 2);
30075    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30076}
30077#[doc = "Vector widening multiply accumulate with scalar"]
30078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
30079#[inline]
30080#[target_feature(enable = "neon")]
30081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30082#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
30083#[cfg_attr(
30084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30085    assert_instr(smlal)
30086)]
30087#[cfg_attr(
30088    not(target_arch = "arm"),
30089    stable(feature = "neon_intrinsics", since = "1.59.0")
30090)]
30091#[cfg_attr(
30092    target_arch = "arm",
30093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30094)]
30095pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
30096    vmlal_s16(a, b, vdup_n_s16(c))
30097}
30098#[doc = "Vector widening multiply accumulate with scalar"]
30099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
30100#[inline]
30101#[target_feature(enable = "neon")]
30102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30103#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30104#[cfg_attr(
30105    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30106    assert_instr(smlal)
30107)]
30108#[cfg_attr(
30109    not(target_arch = "arm"),
30110    stable(feature = "neon_intrinsics", since = "1.59.0")
30111)]
30112#[cfg_attr(
30113    target_arch = "arm",
30114    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30115)]
30116pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
30117    vmlal_s32(a, b, vdup_n_s32(c))
30118}
30119#[doc = "Vector widening multiply accumulate with scalar"]
30120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
30121#[inline]
30122#[target_feature(enable = "neon")]
30123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30124#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30125#[cfg_attr(
30126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30127    assert_instr(umlal)
30128)]
30129#[cfg_attr(
30130    not(target_arch = "arm"),
30131    stable(feature = "neon_intrinsics", since = "1.59.0")
30132)]
30133#[cfg_attr(
30134    target_arch = "arm",
30135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30136)]
30137pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
30138    vmlal_u16(a, b, vdup_n_u16(c))
30139}
30140#[doc = "Vector widening multiply accumulate with scalar"]
30141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
30142#[inline]
30143#[target_feature(enable = "neon")]
30144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30145#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30146#[cfg_attr(
30147    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30148    assert_instr(umlal)
30149)]
30150#[cfg_attr(
30151    not(target_arch = "arm"),
30152    stable(feature = "neon_intrinsics", since = "1.59.0")
30153)]
30154#[cfg_attr(
30155    target_arch = "arm",
30156    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30157)]
30158pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
30159    vmlal_u32(a, b, vdup_n_u32(c))
30160}
30161#[doc = "Signed multiply-add long"]
30162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
30163#[inline]
30164#[target_feature(enable = "neon")]
30165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30166#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
30167#[cfg_attr(
30168    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30169    assert_instr(smlal)
30170)]
30171#[cfg_attr(
30172    not(target_arch = "arm"),
30173    stable(feature = "neon_intrinsics", since = "1.59.0")
30174)]
30175#[cfg_attr(
30176    target_arch = "arm",
30177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30178)]
30179pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
30180    unsafe { simd_add(a, vmull_s8(b, c)) }
30181}
30182#[doc = "Signed multiply-add long"]
30183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
30184#[inline]
30185#[target_feature(enable = "neon")]
30186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30187#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
30188#[cfg_attr(
30189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30190    assert_instr(smlal)
30191)]
30192#[cfg_attr(
30193    not(target_arch = "arm"),
30194    stable(feature = "neon_intrinsics", since = "1.59.0")
30195)]
30196#[cfg_attr(
30197    target_arch = "arm",
30198    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30199)]
30200pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
30201    unsafe { simd_add(a, vmull_s16(b, c)) }
30202}
30203#[doc = "Signed multiply-add long"]
30204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
30205#[inline]
30206#[target_feature(enable = "neon")]
30207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30209#[cfg_attr(
30210    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30211    assert_instr(smlal)
30212)]
30213#[cfg_attr(
30214    not(target_arch = "arm"),
30215    stable(feature = "neon_intrinsics", since = "1.59.0")
30216)]
30217#[cfg_attr(
30218    target_arch = "arm",
30219    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30220)]
30221pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
30222    unsafe { simd_add(a, vmull_s32(b, c)) }
30223}
30224#[doc = "Unsigned multiply-add long"]
30225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
30226#[inline]
30227#[target_feature(enable = "neon")]
30228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30229#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
30230#[cfg_attr(
30231    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30232    assert_instr(umlal)
30233)]
30234#[cfg_attr(
30235    not(target_arch = "arm"),
30236    stable(feature = "neon_intrinsics", since = "1.59.0")
30237)]
30238#[cfg_attr(
30239    target_arch = "arm",
30240    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30241)]
30242pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
30243    unsafe { simd_add(a, vmull_u8(b, c)) }
30244}
30245#[doc = "Unsigned multiply-add long"]
30246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
30247#[inline]
30248#[target_feature(enable = "neon")]
30249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30250#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30251#[cfg_attr(
30252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30253    assert_instr(umlal)
30254)]
30255#[cfg_attr(
30256    not(target_arch = "arm"),
30257    stable(feature = "neon_intrinsics", since = "1.59.0")
30258)]
30259#[cfg_attr(
30260    target_arch = "arm",
30261    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30262)]
30263pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
30264    unsafe { simd_add(a, vmull_u16(b, c)) }
30265}
30266#[doc = "Unsigned multiply-add long"]
30267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
30268#[inline]
30269#[target_feature(enable = "neon")]
30270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30271#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30272#[cfg_attr(
30273    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30274    assert_instr(umlal)
30275)]
30276#[cfg_attr(
30277    not(target_arch = "arm"),
30278    stable(feature = "neon_intrinsics", since = "1.59.0")
30279)]
30280#[cfg_attr(
30281    target_arch = "arm",
30282    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30283)]
30284pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
30285    unsafe { simd_add(a, vmull_u32(b, c)) }
30286}
30287#[doc = "Floating-point multiply-subtract from accumulator"]
30288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
30289#[inline]
30290#[target_feature(enable = "neon")]
30291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30292#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30293#[cfg_attr(
30294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30295    assert_instr(fmul)
30296)]
30297#[cfg_attr(
30298    not(target_arch = "arm"),
30299    stable(feature = "neon_intrinsics", since = "1.59.0")
30300)]
30301#[cfg_attr(
30302    target_arch = "arm",
30303    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30304)]
30305pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
30306    unsafe { simd_sub(a, simd_mul(b, c)) }
30307}
30308#[doc = "Floating-point multiply-subtract from accumulator"]
30309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
30310#[inline]
30311#[target_feature(enable = "neon")]
30312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30313#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30314#[cfg_attr(
30315    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30316    assert_instr(fmul)
30317)]
30318#[cfg_attr(
30319    not(target_arch = "arm"),
30320    stable(feature = "neon_intrinsics", since = "1.59.0")
30321)]
30322#[cfg_attr(
30323    target_arch = "arm",
30324    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30325)]
30326pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
30327    unsafe { simd_sub(a, simd_mul(b, c)) }
30328}
30329#[doc = "Vector multiply subtract with scalar"]
30330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
30331#[inline]
30332#[target_feature(enable = "neon")]
30333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30334#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30335#[cfg_attr(
30336    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30337    assert_instr(fmul, LANE = 1)
30338)]
30339#[rustc_legacy_const_generics(3)]
30340#[cfg_attr(
30341    not(target_arch = "arm"),
30342    stable(feature = "neon_intrinsics", since = "1.59.0")
30343)]
30344#[cfg_attr(
30345    target_arch = "arm",
30346    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30347)]
30348pub fn vmls_lane_f32<const LANE: i32>(
30349    a: float32x2_t,
30350    b: float32x2_t,
30351    c: float32x2_t,
30352) -> float32x2_t {
30353    static_assert_uimm_bits!(LANE, 1);
30354    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30355}
30356#[doc = "Vector multiply subtract with scalar"]
30357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
30358#[inline]
30359#[target_feature(enable = "neon")]
30360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30362#[cfg_attr(
30363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30364    assert_instr(fmul, LANE = 1)
30365)]
30366#[rustc_legacy_const_generics(3)]
30367#[cfg_attr(
30368    not(target_arch = "arm"),
30369    stable(feature = "neon_intrinsics", since = "1.59.0")
30370)]
30371#[cfg_attr(
30372    target_arch = "arm",
30373    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30374)]
30375pub fn vmls_laneq_f32<const LANE: i32>(
30376    a: float32x2_t,
30377    b: float32x2_t,
30378    c: float32x4_t,
30379) -> float32x2_t {
30380    static_assert_uimm_bits!(LANE, 2);
30381    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30382}
30383#[doc = "Vector multiply subtract with scalar"]
30384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
30385#[inline]
30386#[target_feature(enable = "neon")]
30387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30388#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30389#[cfg_attr(
30390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30391    assert_instr(fmul, LANE = 1)
30392)]
30393#[rustc_legacy_const_generics(3)]
30394#[cfg_attr(
30395    not(target_arch = "arm"),
30396    stable(feature = "neon_intrinsics", since = "1.59.0")
30397)]
30398#[cfg_attr(
30399    target_arch = "arm",
30400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30401)]
30402pub fn vmlsq_lane_f32<const LANE: i32>(
30403    a: float32x4_t,
30404    b: float32x4_t,
30405    c: float32x2_t,
30406) -> float32x4_t {
30407    static_assert_uimm_bits!(LANE, 1);
30408    unsafe {
30409        vmlsq_f32(
30410            a,
30411            b,
30412            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30413        )
30414    }
30415}
30416#[doc = "Vector multiply subtract with scalar"]
30417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
30418#[inline]
30419#[target_feature(enable = "neon")]
30420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30421#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30422#[cfg_attr(
30423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30424    assert_instr(fmul, LANE = 1)
30425)]
30426#[rustc_legacy_const_generics(3)]
30427#[cfg_attr(
30428    not(target_arch = "arm"),
30429    stable(feature = "neon_intrinsics", since = "1.59.0")
30430)]
30431#[cfg_attr(
30432    target_arch = "arm",
30433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30434)]
30435pub fn vmlsq_laneq_f32<const LANE: i32>(
30436    a: float32x4_t,
30437    b: float32x4_t,
30438    c: float32x4_t,
30439) -> float32x4_t {
30440    static_assert_uimm_bits!(LANE, 2);
30441    unsafe {
30442        vmlsq_f32(
30443            a,
30444            b,
30445            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30446        )
30447    }
30448}
30449#[doc = "Vector multiply subtract with scalar"]
30450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
30451#[inline]
30452#[target_feature(enable = "neon")]
30453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30455#[cfg_attr(
30456    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30457    assert_instr(mls, LANE = 1)
30458)]
30459#[rustc_legacy_const_generics(3)]
30460#[cfg_attr(
30461    not(target_arch = "arm"),
30462    stable(feature = "neon_intrinsics", since = "1.59.0")
30463)]
30464#[cfg_attr(
30465    target_arch = "arm",
30466    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30467)]
30468pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
30469    static_assert_uimm_bits!(LANE, 2);
30470    unsafe {
30471        vmls_s16(
30472            a,
30473            b,
30474            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30475        )
30476    }
30477}
30478#[doc = "Vector multiply subtract with scalar"]
30479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
30480#[inline]
30481#[target_feature(enable = "neon")]
30482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30483#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30484#[cfg_attr(
30485    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30486    assert_instr(mls, LANE = 1)
30487)]
30488#[rustc_legacy_const_generics(3)]
30489#[cfg_attr(
30490    not(target_arch = "arm"),
30491    stable(feature = "neon_intrinsics", since = "1.59.0")
30492)]
30493#[cfg_attr(
30494    target_arch = "arm",
30495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30496)]
30497pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
30498    static_assert_uimm_bits!(LANE, 2);
30499    unsafe {
30500        vmls_u16(
30501            a,
30502            b,
30503            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30504        )
30505    }
30506}
30507#[doc = "Vector multiply subtract with scalar"]
30508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
30509#[inline]
30510#[target_feature(enable = "neon")]
30511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30512#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30513#[cfg_attr(
30514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30515    assert_instr(mls, LANE = 1)
30516)]
30517#[rustc_legacy_const_generics(3)]
30518#[cfg_attr(
30519    not(target_arch = "arm"),
30520    stable(feature = "neon_intrinsics", since = "1.59.0")
30521)]
30522#[cfg_attr(
30523    target_arch = "arm",
30524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30525)]
30526pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
30527    static_assert_uimm_bits!(LANE, 3);
30528    unsafe {
30529        vmls_s16(
30530            a,
30531            b,
30532            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30533        )
30534    }
30535}
30536#[doc = "Vector multiply subtract with scalar"]
30537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
30538#[inline]
30539#[target_feature(enable = "neon")]
30540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30542#[cfg_attr(
30543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30544    assert_instr(mls, LANE = 1)
30545)]
30546#[rustc_legacy_const_generics(3)]
30547#[cfg_attr(
30548    not(target_arch = "arm"),
30549    stable(feature = "neon_intrinsics", since = "1.59.0")
30550)]
30551#[cfg_attr(
30552    target_arch = "arm",
30553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30554)]
30555pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
30556    static_assert_uimm_bits!(LANE, 3);
30557    unsafe {
30558        vmls_u16(
30559            a,
30560            b,
30561            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30562        )
30563    }
30564}
30565#[doc = "Vector multiply subtract with scalar"]
30566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
30567#[inline]
30568#[target_feature(enable = "neon")]
30569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30571#[cfg_attr(
30572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30573    assert_instr(mls, LANE = 1)
30574)]
30575#[rustc_legacy_const_generics(3)]
30576#[cfg_attr(
30577    not(target_arch = "arm"),
30578    stable(feature = "neon_intrinsics", since = "1.59.0")
30579)]
30580#[cfg_attr(
30581    target_arch = "arm",
30582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30583)]
30584pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
30585    static_assert_uimm_bits!(LANE, 2);
30586    unsafe {
30587        vmlsq_s16(
30588            a,
30589            b,
30590            simd_shuffle!(
30591                c,
30592                c,
30593                [
30594                    LANE as u32,
30595                    LANE as u32,
30596                    LANE as u32,
30597                    LANE as u32,
30598                    LANE as u32,
30599                    LANE as u32,
30600                    LANE as u32,
30601                    LANE as u32
30602                ]
30603            ),
30604        )
30605    }
30606}
30607#[doc = "Vector multiply subtract with scalar"]
30608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
30609#[inline]
30610#[target_feature(enable = "neon")]
30611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30613#[cfg_attr(
30614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30615    assert_instr(mls, LANE = 1)
30616)]
30617#[rustc_legacy_const_generics(3)]
30618#[cfg_attr(
30619    not(target_arch = "arm"),
30620    stable(feature = "neon_intrinsics", since = "1.59.0")
30621)]
30622#[cfg_attr(
30623    target_arch = "arm",
30624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30625)]
30626pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
30627    static_assert_uimm_bits!(LANE, 2);
30628    unsafe {
30629        vmlsq_u16(
30630            a,
30631            b,
30632            simd_shuffle!(
30633                c,
30634                c,
30635                [
30636                    LANE as u32,
30637                    LANE as u32,
30638                    LANE as u32,
30639                    LANE as u32,
30640                    LANE as u32,
30641                    LANE as u32,
30642                    LANE as u32,
30643                    LANE as u32
30644                ]
30645            ),
30646        )
30647    }
30648}
30649#[doc = "Vector multiply subtract with scalar"]
30650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
30651#[inline]
30652#[target_feature(enable = "neon")]
30653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30655#[cfg_attr(
30656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30657    assert_instr(mls, LANE = 1)
30658)]
30659#[rustc_legacy_const_generics(3)]
30660#[cfg_attr(
30661    not(target_arch = "arm"),
30662    stable(feature = "neon_intrinsics", since = "1.59.0")
30663)]
30664#[cfg_attr(
30665    target_arch = "arm",
30666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30667)]
30668pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
30669    static_assert_uimm_bits!(LANE, 3);
30670    unsafe {
30671        vmlsq_s16(
30672            a,
30673            b,
30674            simd_shuffle!(
30675                c,
30676                c,
30677                [
30678                    LANE as u32,
30679                    LANE as u32,
30680                    LANE as u32,
30681                    LANE as u32,
30682                    LANE as u32,
30683                    LANE as u32,
30684                    LANE as u32,
30685                    LANE as u32
30686                ]
30687            ),
30688        )
30689    }
30690}
30691#[doc = "Vector multiply subtract with scalar"]
30692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
30693#[inline]
30694#[target_feature(enable = "neon")]
30695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30696#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30697#[cfg_attr(
30698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30699    assert_instr(mls, LANE = 1)
30700)]
30701#[rustc_legacy_const_generics(3)]
30702#[cfg_attr(
30703    not(target_arch = "arm"),
30704    stable(feature = "neon_intrinsics", since = "1.59.0")
30705)]
30706#[cfg_attr(
30707    target_arch = "arm",
30708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30709)]
30710pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
30711    static_assert_uimm_bits!(LANE, 3);
30712    unsafe {
30713        vmlsq_u16(
30714            a,
30715            b,
30716            simd_shuffle!(
30717                c,
30718                c,
30719                [
30720                    LANE as u32,
30721                    LANE as u32,
30722                    LANE as u32,
30723                    LANE as u32,
30724                    LANE as u32,
30725                    LANE as u32,
30726                    LANE as u32,
30727                    LANE as u32
30728                ]
30729            ),
30730        )
30731    }
30732}
30733#[doc = "Vector multiply subtract with scalar"]
30734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
30735#[inline]
30736#[target_feature(enable = "neon")]
30737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30739#[cfg_attr(
30740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30741    assert_instr(mls, LANE = 1)
30742)]
30743#[rustc_legacy_const_generics(3)]
30744#[cfg_attr(
30745    not(target_arch = "arm"),
30746    stable(feature = "neon_intrinsics", since = "1.59.0")
30747)]
30748#[cfg_attr(
30749    target_arch = "arm",
30750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30751)]
30752pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
30753    static_assert_uimm_bits!(LANE, 1);
30754    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30755}
30756#[doc = "Vector multiply subtract with scalar"]
30757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
30758#[inline]
30759#[target_feature(enable = "neon")]
30760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30761#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30762#[cfg_attr(
30763    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30764    assert_instr(mls, LANE = 1)
30765)]
30766#[rustc_legacy_const_generics(3)]
30767#[cfg_attr(
30768    not(target_arch = "arm"),
30769    stable(feature = "neon_intrinsics", since = "1.59.0")
30770)]
30771#[cfg_attr(
30772    target_arch = "arm",
30773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30774)]
30775pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
30776    static_assert_uimm_bits!(LANE, 1);
30777    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30778}
30779#[doc = "Vector multiply subtract with scalar"]
30780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
30781#[inline]
30782#[target_feature(enable = "neon")]
30783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30785#[cfg_attr(
30786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30787    assert_instr(mls, LANE = 1)
30788)]
30789#[rustc_legacy_const_generics(3)]
30790#[cfg_attr(
30791    not(target_arch = "arm"),
30792    stable(feature = "neon_intrinsics", since = "1.59.0")
30793)]
30794#[cfg_attr(
30795    target_arch = "arm",
30796    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30797)]
30798pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
30799    static_assert_uimm_bits!(LANE, 2);
30800    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30801}
30802#[doc = "Vector multiply subtract with scalar"]
30803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
30804#[inline]
30805#[target_feature(enable = "neon")]
30806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30807#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30808#[cfg_attr(
30809    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30810    assert_instr(mls, LANE = 1)
30811)]
30812#[rustc_legacy_const_generics(3)]
30813#[cfg_attr(
30814    not(target_arch = "arm"),
30815    stable(feature = "neon_intrinsics", since = "1.59.0")
30816)]
30817#[cfg_attr(
30818    target_arch = "arm",
30819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30820)]
30821pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
30822    static_assert_uimm_bits!(LANE, 2);
30823    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30824}
30825#[doc = "Vector multiply subtract with scalar"]
30826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
30827#[inline]
30828#[target_feature(enable = "neon")]
30829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30830#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30831#[cfg_attr(
30832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30833    assert_instr(mls, LANE = 1)
30834)]
30835#[rustc_legacy_const_generics(3)]
30836#[cfg_attr(
30837    not(target_arch = "arm"),
30838    stable(feature = "neon_intrinsics", since = "1.59.0")
30839)]
30840#[cfg_attr(
30841    target_arch = "arm",
30842    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30843)]
30844pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
30845    static_assert_uimm_bits!(LANE, 1);
30846    unsafe {
30847        vmlsq_s32(
30848            a,
30849            b,
30850            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30851        )
30852    }
30853}
30854#[doc = "Vector multiply subtract with scalar"]
30855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
30856#[inline]
30857#[target_feature(enable = "neon")]
30858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30859#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30860#[cfg_attr(
30861    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30862    assert_instr(mls, LANE = 1)
30863)]
30864#[rustc_legacy_const_generics(3)]
30865#[cfg_attr(
30866    not(target_arch = "arm"),
30867    stable(feature = "neon_intrinsics", since = "1.59.0")
30868)]
30869#[cfg_attr(
30870    target_arch = "arm",
30871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30872)]
30873pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
30874    static_assert_uimm_bits!(LANE, 1);
30875    unsafe {
30876        vmlsq_u32(
30877            a,
30878            b,
30879            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30880        )
30881    }
30882}
30883#[doc = "Vector multiply subtract with scalar"]
30884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
30885#[inline]
30886#[target_feature(enable = "neon")]
30887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30888#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30889#[cfg_attr(
30890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30891    assert_instr(mls, LANE = 1)
30892)]
30893#[rustc_legacy_const_generics(3)]
30894#[cfg_attr(
30895    not(target_arch = "arm"),
30896    stable(feature = "neon_intrinsics", since = "1.59.0")
30897)]
30898#[cfg_attr(
30899    target_arch = "arm",
30900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30901)]
30902pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
30903    static_assert_uimm_bits!(LANE, 2);
30904    unsafe {
30905        vmlsq_s32(
30906            a,
30907            b,
30908            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30909        )
30910    }
30911}
30912#[doc = "Vector multiply subtract with scalar"]
30913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
30914#[inline]
30915#[target_feature(enable = "neon")]
30916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30917#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30918#[cfg_attr(
30919    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30920    assert_instr(mls, LANE = 1)
30921)]
30922#[rustc_legacy_const_generics(3)]
30923#[cfg_attr(
30924    not(target_arch = "arm"),
30925    stable(feature = "neon_intrinsics", since = "1.59.0")
30926)]
30927#[cfg_attr(
30928    target_arch = "arm",
30929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30930)]
30931pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
30932    static_assert_uimm_bits!(LANE, 2);
30933    unsafe {
30934        vmlsq_u32(
30935            a,
30936            b,
30937            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30938        )
30939    }
30940}
30941#[doc = "Vector multiply subtract with scalar"]
30942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
30943#[inline]
30944#[target_feature(enable = "neon")]
30945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30946#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30947#[cfg_attr(
30948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30949    assert_instr(fmul)
30950)]
30951#[cfg_attr(
30952    not(target_arch = "arm"),
30953    stable(feature = "neon_intrinsics", since = "1.59.0")
30954)]
30955#[cfg_attr(
30956    target_arch = "arm",
30957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30958)]
30959pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
30960    vmls_f32(a, b, vdup_n_f32(c))
30961}
30962#[doc = "Vector multiply subtract with scalar"]
30963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
30964#[inline]
30965#[target_feature(enable = "neon")]
30966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30967#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30968#[cfg_attr(
30969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30970    assert_instr(fmul)
30971)]
30972#[cfg_attr(
30973    not(target_arch = "arm"),
30974    stable(feature = "neon_intrinsics", since = "1.59.0")
30975)]
30976#[cfg_attr(
30977    target_arch = "arm",
30978    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30979)]
30980pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
30981    vmlsq_f32(a, b, vdupq_n_f32(c))
30982}
30983#[doc = "Vector multiply subtract with scalar"]
30984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
30985#[inline]
30986#[target_feature(enable = "neon")]
30987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30989#[cfg_attr(
30990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30991    assert_instr(mls)
30992)]
30993#[cfg_attr(
30994    not(target_arch = "arm"),
30995    stable(feature = "neon_intrinsics", since = "1.59.0")
30996)]
30997#[cfg_attr(
30998    target_arch = "arm",
30999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31000)]
31001pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
31002    vmls_s16(a, b, vdup_n_s16(c))
31003}
31004#[doc = "Vector multiply subtract with scalar"]
31005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
31006#[inline]
31007#[target_feature(enable = "neon")]
31008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31010#[cfg_attr(
31011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31012    assert_instr(mls)
31013)]
31014#[cfg_attr(
31015    not(target_arch = "arm"),
31016    stable(feature = "neon_intrinsics", since = "1.59.0")
31017)]
31018#[cfg_attr(
31019    target_arch = "arm",
31020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31021)]
31022pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
31023    vmlsq_s16(a, b, vdupq_n_s16(c))
31024}
31025#[doc = "Vector multiply subtract with scalar"]
31026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
31027#[inline]
31028#[target_feature(enable = "neon")]
31029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31030#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31031#[cfg_attr(
31032    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31033    assert_instr(mls)
31034)]
31035#[cfg_attr(
31036    not(target_arch = "arm"),
31037    stable(feature = "neon_intrinsics", since = "1.59.0")
31038)]
31039#[cfg_attr(
31040    target_arch = "arm",
31041    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31042)]
31043pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
31044    vmls_u16(a, b, vdup_n_u16(c))
31045}
31046#[doc = "Vector multiply subtract with scalar"]
31047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
31048#[inline]
31049#[target_feature(enable = "neon")]
31050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31051#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31052#[cfg_attr(
31053    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31054    assert_instr(mls)
31055)]
31056#[cfg_attr(
31057    not(target_arch = "arm"),
31058    stable(feature = "neon_intrinsics", since = "1.59.0")
31059)]
31060#[cfg_attr(
31061    target_arch = "arm",
31062    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31063)]
31064pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
31065    vmlsq_u16(a, b, vdupq_n_u16(c))
31066}
31067#[doc = "Vector multiply subtract with scalar"]
31068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
31069#[inline]
31070#[target_feature(enable = "neon")]
31071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31073#[cfg_attr(
31074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31075    assert_instr(mls)
31076)]
31077#[cfg_attr(
31078    not(target_arch = "arm"),
31079    stable(feature = "neon_intrinsics", since = "1.59.0")
31080)]
31081#[cfg_attr(
31082    target_arch = "arm",
31083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31084)]
31085pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
31086    vmls_s32(a, b, vdup_n_s32(c))
31087}
31088#[doc = "Vector multiply subtract with scalar"]
31089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
31090#[inline]
31091#[target_feature(enable = "neon")]
31092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31093#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31094#[cfg_attr(
31095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31096    assert_instr(mls)
31097)]
31098#[cfg_attr(
31099    not(target_arch = "arm"),
31100    stable(feature = "neon_intrinsics", since = "1.59.0")
31101)]
31102#[cfg_attr(
31103    target_arch = "arm",
31104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31105)]
31106pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
31107    vmlsq_s32(a, b, vdupq_n_s32(c))
31108}
31109#[doc = "Vector multiply subtract with scalar"]
31110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
31111#[inline]
31112#[target_feature(enable = "neon")]
31113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31114#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31115#[cfg_attr(
31116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31117    assert_instr(mls)
31118)]
31119#[cfg_attr(
31120    not(target_arch = "arm"),
31121    stable(feature = "neon_intrinsics", since = "1.59.0")
31122)]
31123#[cfg_attr(
31124    target_arch = "arm",
31125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31126)]
31127pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
31128    vmls_u32(a, b, vdup_n_u32(c))
31129}
31130#[doc = "Vector multiply subtract with scalar"]
31131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
31132#[inline]
31133#[target_feature(enable = "neon")]
31134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31136#[cfg_attr(
31137    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31138    assert_instr(mls)
31139)]
31140#[cfg_attr(
31141    not(target_arch = "arm"),
31142    stable(feature = "neon_intrinsics", since = "1.59.0")
31143)]
31144#[cfg_attr(
31145    target_arch = "arm",
31146    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31147)]
31148pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
31149    vmlsq_u32(a, b, vdupq_n_u32(c))
31150}
31151#[doc = "Multiply-subtract from accumulator"]
31152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
31153#[inline]
31154#[target_feature(enable = "neon")]
31155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31157#[cfg_attr(
31158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31159    assert_instr(mls)
31160)]
31161#[cfg_attr(
31162    not(target_arch = "arm"),
31163    stable(feature = "neon_intrinsics", since = "1.59.0")
31164)]
31165#[cfg_attr(
31166    target_arch = "arm",
31167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31168)]
31169pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
31170    unsafe { simd_sub(a, simd_mul(b, c)) }
31171}
31172#[doc = "Multiply-subtract from accumulator"]
31173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
31174#[inline]
31175#[target_feature(enable = "neon")]
31176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31177#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31178#[cfg_attr(
31179    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31180    assert_instr(mls)
31181)]
31182#[cfg_attr(
31183    not(target_arch = "arm"),
31184    stable(feature = "neon_intrinsics", since = "1.59.0")
31185)]
31186#[cfg_attr(
31187    target_arch = "arm",
31188    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31189)]
31190pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
31191    unsafe { simd_sub(a, simd_mul(b, c)) }
31192}
31193#[doc = "Multiply-subtract from accumulator"]
31194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
31195#[inline]
31196#[target_feature(enable = "neon")]
31197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31199#[cfg_attr(
31200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31201    assert_instr(mls)
31202)]
31203#[cfg_attr(
31204    not(target_arch = "arm"),
31205    stable(feature = "neon_intrinsics", since = "1.59.0")
31206)]
31207#[cfg_attr(
31208    target_arch = "arm",
31209    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31210)]
31211pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
31212    unsafe { simd_sub(a, simd_mul(b, c)) }
31213}
31214#[doc = "Multiply-subtract from accumulator"]
31215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
31216#[inline]
31217#[target_feature(enable = "neon")]
31218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31219#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31220#[cfg_attr(
31221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31222    assert_instr(mls)
31223)]
31224#[cfg_attr(
31225    not(target_arch = "arm"),
31226    stable(feature = "neon_intrinsics", since = "1.59.0")
31227)]
31228#[cfg_attr(
31229    target_arch = "arm",
31230    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31231)]
31232pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
31233    unsafe { simd_sub(a, simd_mul(b, c)) }
31234}
31235#[doc = "Multiply-subtract from accumulator"]
31236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
31237#[inline]
31238#[target_feature(enable = "neon")]
31239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31241#[cfg_attr(
31242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31243    assert_instr(mls)
31244)]
31245#[cfg_attr(
31246    not(target_arch = "arm"),
31247    stable(feature = "neon_intrinsics", since = "1.59.0")
31248)]
31249#[cfg_attr(
31250    target_arch = "arm",
31251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31252)]
31253pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
31254    unsafe { simd_sub(a, simd_mul(b, c)) }
31255}
31256#[doc = "Multiply-subtract from accumulator"]
31257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
31258#[inline]
31259#[target_feature(enable = "neon")]
31260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31261#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31262#[cfg_attr(
31263    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31264    assert_instr(mls)
31265)]
31266#[cfg_attr(
31267    not(target_arch = "arm"),
31268    stable(feature = "neon_intrinsics", since = "1.59.0")
31269)]
31270#[cfg_attr(
31271    target_arch = "arm",
31272    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31273)]
31274pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
31275    unsafe { simd_sub(a, simd_mul(b, c)) }
31276}
31277#[doc = "Multiply-subtract from accumulator"]
31278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
31279#[inline]
31280#[target_feature(enable = "neon")]
31281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31283#[cfg_attr(
31284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31285    assert_instr(mls)
31286)]
31287#[cfg_attr(
31288    not(target_arch = "arm"),
31289    stable(feature = "neon_intrinsics", since = "1.59.0")
31290)]
31291#[cfg_attr(
31292    target_arch = "arm",
31293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31294)]
31295pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
31296    unsafe { simd_sub(a, simd_mul(b, c)) }
31297}
31298#[doc = "Multiply-subtract from accumulator"]
31299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
31300#[inline]
31301#[target_feature(enable = "neon")]
31302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31304#[cfg_attr(
31305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31306    assert_instr(mls)
31307)]
31308#[cfg_attr(
31309    not(target_arch = "arm"),
31310    stable(feature = "neon_intrinsics", since = "1.59.0")
31311)]
31312#[cfg_attr(
31313    target_arch = "arm",
31314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31315)]
31316pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
31317    unsafe { simd_sub(a, simd_mul(b, c)) }
31318}
31319#[doc = "Multiply-subtract from accumulator"]
31320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
31321#[inline]
31322#[target_feature(enable = "neon")]
31323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31325#[cfg_attr(
31326    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31327    assert_instr(mls)
31328)]
31329#[cfg_attr(
31330    not(target_arch = "arm"),
31331    stable(feature = "neon_intrinsics", since = "1.59.0")
31332)]
31333#[cfg_attr(
31334    target_arch = "arm",
31335    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31336)]
31337pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
31338    unsafe { simd_sub(a, simd_mul(b, c)) }
31339}
31340#[doc = "Multiply-subtract from accumulator"]
31341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
31342#[inline]
31343#[target_feature(enable = "neon")]
31344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31345#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31346#[cfg_attr(
31347    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31348    assert_instr(mls)
31349)]
31350#[cfg_attr(
31351    not(target_arch = "arm"),
31352    stable(feature = "neon_intrinsics", since = "1.59.0")
31353)]
31354#[cfg_attr(
31355    target_arch = "arm",
31356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31357)]
31358pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
31359    unsafe { simd_sub(a, simd_mul(b, c)) }
31360}
31361#[doc = "Multiply-subtract from accumulator"]
31362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
31363#[inline]
31364#[target_feature(enable = "neon")]
31365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31366#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31367#[cfg_attr(
31368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31369    assert_instr(mls)
31370)]
31371#[cfg_attr(
31372    not(target_arch = "arm"),
31373    stable(feature = "neon_intrinsics", since = "1.59.0")
31374)]
31375#[cfg_attr(
31376    target_arch = "arm",
31377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31378)]
31379pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
31380    unsafe { simd_sub(a, simd_mul(b, c)) }
31381}
31382#[doc = "Multiply-subtract from accumulator"]
31383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
31384#[inline]
31385#[target_feature(enable = "neon")]
31386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31387#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31388#[cfg_attr(
31389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31390    assert_instr(mls)
31391)]
31392#[cfg_attr(
31393    not(target_arch = "arm"),
31394    stable(feature = "neon_intrinsics", since = "1.59.0")
31395)]
31396#[cfg_attr(
31397    target_arch = "arm",
31398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31399)]
31400pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
31401    unsafe { simd_sub(a, simd_mul(b, c)) }
31402}
31403#[doc = "Vector widening multiply subtract with scalar"]
31404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
31405#[inline]
31406#[target_feature(enable = "neon")]
31407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31408#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31409#[cfg_attr(
31410    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31411    assert_instr(smlsl, LANE = 1)
31412)]
31413#[rustc_legacy_const_generics(3)]
31414#[cfg_attr(
31415    not(target_arch = "arm"),
31416    stable(feature = "neon_intrinsics", since = "1.59.0")
31417)]
31418#[cfg_attr(
31419    target_arch = "arm",
31420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31421)]
31422pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31423    static_assert_uimm_bits!(LANE, 2);
31424    unsafe {
31425        vmlsl_s16(
31426            a,
31427            b,
31428            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31429        )
31430    }
31431}
31432#[doc = "Vector widening multiply subtract with scalar"]
31433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
31434#[inline]
31435#[target_feature(enable = "neon")]
31436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31437#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31438#[cfg_attr(
31439    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31440    assert_instr(smlsl, LANE = 1)
31441)]
31442#[rustc_legacy_const_generics(3)]
31443#[cfg_attr(
31444    not(target_arch = "arm"),
31445    stable(feature = "neon_intrinsics", since = "1.59.0")
31446)]
31447#[cfg_attr(
31448    target_arch = "arm",
31449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31450)]
31451pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
31452    static_assert_uimm_bits!(LANE, 3);
31453    unsafe {
31454        vmlsl_s16(
31455            a,
31456            b,
31457            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31458        )
31459    }
31460}
31461#[doc = "Vector widening multiply subtract with scalar"]
31462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
31463#[inline]
31464#[target_feature(enable = "neon")]
31465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31466#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31467#[cfg_attr(
31468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31469    assert_instr(smlsl, LANE = 1)
31470)]
31471#[rustc_legacy_const_generics(3)]
31472#[cfg_attr(
31473    not(target_arch = "arm"),
31474    stable(feature = "neon_intrinsics", since = "1.59.0")
31475)]
31476#[cfg_attr(
31477    target_arch = "arm",
31478    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31479)]
31480pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31481    static_assert_uimm_bits!(LANE, 1);
31482    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31483}
31484#[doc = "Vector widening multiply subtract with scalar"]
31485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
31486#[inline]
31487#[target_feature(enable = "neon")]
31488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31489#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31490#[cfg_attr(
31491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31492    assert_instr(smlsl, LANE = 1)
31493)]
31494#[rustc_legacy_const_generics(3)]
31495#[cfg_attr(
31496    not(target_arch = "arm"),
31497    stable(feature = "neon_intrinsics", since = "1.59.0")
31498)]
31499#[cfg_attr(
31500    target_arch = "arm",
31501    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31502)]
31503pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
31504    static_assert_uimm_bits!(LANE, 2);
31505    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31506}
31507#[doc = "Vector widening multiply subtract with scalar"]
31508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
31509#[inline]
31510#[target_feature(enable = "neon")]
31511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31512#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31513#[cfg_attr(
31514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31515    assert_instr(umlsl, LANE = 1)
31516)]
31517#[rustc_legacy_const_generics(3)]
31518#[cfg_attr(
31519    not(target_arch = "arm"),
31520    stable(feature = "neon_intrinsics", since = "1.59.0")
31521)]
31522#[cfg_attr(
31523    target_arch = "arm",
31524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31525)]
31526pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31527    static_assert_uimm_bits!(LANE, 2);
31528    unsafe {
31529        vmlsl_u16(
31530            a,
31531            b,
31532            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31533        )
31534    }
31535}
31536#[doc = "Vector widening multiply subtract with scalar"]
31537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
31538#[inline]
31539#[target_feature(enable = "neon")]
31540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31542#[cfg_attr(
31543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31544    assert_instr(umlsl, LANE = 1)
31545)]
31546#[rustc_legacy_const_generics(3)]
31547#[cfg_attr(
31548    not(target_arch = "arm"),
31549    stable(feature = "neon_intrinsics", since = "1.59.0")
31550)]
31551#[cfg_attr(
31552    target_arch = "arm",
31553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31554)]
31555pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
31556    static_assert_uimm_bits!(LANE, 3);
31557    unsafe {
31558        vmlsl_u16(
31559            a,
31560            b,
31561            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31562        )
31563    }
31564}
31565#[doc = "Vector widening multiply subtract with scalar"]
31566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
31567#[inline]
31568#[target_feature(enable = "neon")]
31569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31571#[cfg_attr(
31572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31573    assert_instr(umlsl, LANE = 1)
31574)]
31575#[rustc_legacy_const_generics(3)]
31576#[cfg_attr(
31577    not(target_arch = "arm"),
31578    stable(feature = "neon_intrinsics", since = "1.59.0")
31579)]
31580#[cfg_attr(
31581    target_arch = "arm",
31582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31583)]
31584pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31585    static_assert_uimm_bits!(LANE, 1);
31586    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31587}
31588#[doc = "Vector widening multiply subtract with scalar"]
31589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
31590#[inline]
31591#[target_feature(enable = "neon")]
31592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31593#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31594#[cfg_attr(
31595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31596    assert_instr(umlsl, LANE = 1)
31597)]
31598#[rustc_legacy_const_generics(3)]
31599#[cfg_attr(
31600    not(target_arch = "arm"),
31601    stable(feature = "neon_intrinsics", since = "1.59.0")
31602)]
31603#[cfg_attr(
31604    target_arch = "arm",
31605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31606)]
31607pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
31608    static_assert_uimm_bits!(LANE, 2);
31609    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31610}
31611#[doc = "Vector widening multiply subtract with scalar"]
31612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
31613#[inline]
31614#[target_feature(enable = "neon")]
31615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31616#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31617#[cfg_attr(
31618    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31619    assert_instr(smlsl)
31620)]
31621#[cfg_attr(
31622    not(target_arch = "arm"),
31623    stable(feature = "neon_intrinsics", since = "1.59.0")
31624)]
31625#[cfg_attr(
31626    target_arch = "arm",
31627    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31628)]
31629pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31630    vmlsl_s16(a, b, vdup_n_s16(c))
31631}
31632#[doc = "Vector widening multiply subtract with scalar"]
31633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
31634#[inline]
31635#[target_feature(enable = "neon")]
31636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31637#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31638#[cfg_attr(
31639    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31640    assert_instr(smlsl)
31641)]
31642#[cfg_attr(
31643    not(target_arch = "arm"),
31644    stable(feature = "neon_intrinsics", since = "1.59.0")
31645)]
31646#[cfg_attr(
31647    target_arch = "arm",
31648    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31649)]
31650pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31651    vmlsl_s32(a, b, vdup_n_s32(c))
31652}
31653#[doc = "Vector widening multiply subtract with scalar"]
31654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
31655#[inline]
31656#[target_feature(enable = "neon")]
31657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31658#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31659#[cfg_attr(
31660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31661    assert_instr(umlsl)
31662)]
31663#[cfg_attr(
31664    not(target_arch = "arm"),
31665    stable(feature = "neon_intrinsics", since = "1.59.0")
31666)]
31667#[cfg_attr(
31668    target_arch = "arm",
31669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31670)]
31671pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
31672    vmlsl_u16(a, b, vdup_n_u16(c))
31673}
31674#[doc = "Vector widening multiply subtract with scalar"]
31675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
31676#[inline]
31677#[target_feature(enable = "neon")]
31678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31679#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31680#[cfg_attr(
31681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31682    assert_instr(umlsl)
31683)]
31684#[cfg_attr(
31685    not(target_arch = "arm"),
31686    stable(feature = "neon_intrinsics", since = "1.59.0")
31687)]
31688#[cfg_attr(
31689    target_arch = "arm",
31690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31691)]
31692pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
31693    vmlsl_u32(a, b, vdup_n_u32(c))
31694}
31695#[doc = "Signed multiply-subtract long"]
31696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
31697#[inline]
31698#[target_feature(enable = "neon")]
31699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
31701#[cfg_attr(
31702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31703    assert_instr(smlsl)
31704)]
31705#[cfg_attr(
31706    not(target_arch = "arm"),
31707    stable(feature = "neon_intrinsics", since = "1.59.0")
31708)]
31709#[cfg_attr(
31710    target_arch = "arm",
31711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31712)]
31713pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
31714    unsafe { simd_sub(a, vmull_s8(b, c)) }
31715}
31716#[doc = "Signed multiply-subtract long"]
31717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
31718#[inline]
31719#[target_feature(enable = "neon")]
31720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31722#[cfg_attr(
31723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31724    assert_instr(smlsl)
31725)]
31726#[cfg_attr(
31727    not(target_arch = "arm"),
31728    stable(feature = "neon_intrinsics", since = "1.59.0")
31729)]
31730#[cfg_attr(
31731    target_arch = "arm",
31732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31733)]
31734pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31735    unsafe { simd_sub(a, vmull_s16(b, c)) }
31736}
31737#[doc = "Signed multiply-subtract long"]
31738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
31739#[inline]
31740#[target_feature(enable = "neon")]
31741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31743#[cfg_attr(
31744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31745    assert_instr(smlsl)
31746)]
31747#[cfg_attr(
31748    not(target_arch = "arm"),
31749    stable(feature = "neon_intrinsics", since = "1.59.0")
31750)]
31751#[cfg_attr(
31752    target_arch = "arm",
31753    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31754)]
31755pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31756    unsafe { simd_sub(a, vmull_s32(b, c)) }
31757}
31758#[doc = "Unsigned multiply-subtract long"]
31759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
31760#[inline]
31761#[target_feature(enable = "neon")]
31762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31763#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
31764#[cfg_attr(
31765    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31766    assert_instr(umlsl)
31767)]
31768#[cfg_attr(
31769    not(target_arch = "arm"),
31770    stable(feature = "neon_intrinsics", since = "1.59.0")
31771)]
31772#[cfg_attr(
31773    target_arch = "arm",
31774    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31775)]
31776pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
31777    unsafe { simd_sub(a, vmull_u8(b, c)) }
31778}
31779#[doc = "Unsigned multiply-subtract long"]
31780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
31781#[inline]
31782#[target_feature(enable = "neon")]
31783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31785#[cfg_attr(
31786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31787    assert_instr(umlsl)
31788)]
31789#[cfg_attr(
31790    not(target_arch = "arm"),
31791    stable(feature = "neon_intrinsics", since = "1.59.0")
31792)]
31793#[cfg_attr(
31794    target_arch = "arm",
31795    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31796)]
31797pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31798    unsafe { simd_sub(a, vmull_u16(b, c)) }
31799}
31800#[doc = "Unsigned multiply-subtract long"]
31801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
31802#[inline]
31803#[target_feature(enable = "neon")]
31804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31805#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31806#[cfg_attr(
31807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31808    assert_instr(umlsl)
31809)]
31810#[cfg_attr(
31811    not(target_arch = "arm"),
31812    stable(feature = "neon_intrinsics", since = "1.59.0")
31813)]
31814#[cfg_attr(
31815    target_arch = "arm",
31816    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31817)]
31818pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31819    unsafe { simd_sub(a, vmull_u32(b, c)) }
31820}
31821#[doc = "8-bit integer matrix multiply-accumulate"]
31822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
31823#[inline]
31824#[target_feature(enable = "neon,i8mm")]
31825#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31827#[cfg_attr(
31828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31829    assert_instr(smmla)
31830)]
31831#[cfg_attr(
31832    not(target_arch = "arm"),
31833    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31834)]
31835#[cfg_attr(
31836    target_arch = "arm",
31837    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31838)]
31839pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
31840    unsafe extern "unadjusted" {
31841        #[cfg_attr(
31842            any(target_arch = "aarch64", target_arch = "arm64ec"),
31843            link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8"
31844        )]
31845        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")]
31846        fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
31847    }
31848    unsafe { _vmmlaq_s32(a, b, c) }
31849}
31850#[doc = "8-bit integer matrix multiply-accumulate"]
31851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
31852#[inline]
31853#[target_feature(enable = "neon,i8mm")]
31854#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31856#[cfg_attr(
31857    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31858    assert_instr(ummla)
31859)]
31860#[cfg_attr(
31861    not(target_arch = "arm"),
31862    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31863)]
31864#[cfg_attr(
31865    target_arch = "arm",
31866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31867)]
31868pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
31869    unsafe extern "unadjusted" {
31870        #[cfg_attr(
31871            any(target_arch = "aarch64", target_arch = "arm64ec"),
31872            link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8"
31873        )]
31874        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")]
31875        fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
31876    }
31877    unsafe { _vmmlaq_u32(a, b, c) }
31878}
31879#[doc = "Duplicate element to vector"]
31880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
31881#[inline]
31882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31884#[cfg_attr(
31885    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31886    assert_instr(dup)
31887)]
31888#[target_feature(enable = "neon,fp16")]
31889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31890pub fn vmov_n_f16(a: f16) -> float16x4_t {
31891    vdup_n_f16(a)
31892}
31893#[doc = "Duplicate element to vector"]
31894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
31895#[inline]
31896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31897#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31898#[cfg_attr(
31899    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31900    assert_instr(dup)
31901)]
31902#[target_feature(enable = "neon,fp16")]
31903#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31904pub fn vmovq_n_f16(a: f16) -> float16x8_t {
31905    vdupq_n_f16(a)
31906}
31907#[doc = "Duplicate vector element to vector or scalar"]
31908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
31909#[inline]
31910#[target_feature(enable = "neon")]
31911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31912#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31913#[cfg_attr(
31914    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31915    assert_instr(dup)
31916)]
31917#[cfg_attr(
31918    not(target_arch = "arm"),
31919    stable(feature = "neon_intrinsics", since = "1.59.0")
31920)]
31921#[cfg_attr(
31922    target_arch = "arm",
31923    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31924)]
31925pub fn vmov_n_f32(value: f32) -> float32x2_t {
31926    vdup_n_f32(value)
31927}
31928#[doc = "Duplicate vector element to vector or scalar"]
31929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
31930#[inline]
31931#[target_feature(enable = "neon")]
31932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31933#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31934#[cfg_attr(
31935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31936    assert_instr(dup)
31937)]
31938#[cfg_attr(
31939    not(target_arch = "arm"),
31940    stable(feature = "neon_intrinsics", since = "1.59.0")
31941)]
31942#[cfg_attr(
31943    target_arch = "arm",
31944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31945)]
31946pub fn vmov_n_p16(value: p16) -> poly16x4_t {
31947    vdup_n_p16(value)
31948}
31949#[doc = "Duplicate vector element to vector or scalar"]
31950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
31951#[inline]
31952#[target_feature(enable = "neon")]
31953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31954#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31955#[cfg_attr(
31956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31957    assert_instr(dup)
31958)]
31959#[cfg_attr(
31960    not(target_arch = "arm"),
31961    stable(feature = "neon_intrinsics", since = "1.59.0")
31962)]
31963#[cfg_attr(
31964    target_arch = "arm",
31965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31966)]
31967pub fn vmov_n_p8(value: p8) -> poly8x8_t {
31968    vdup_n_p8(value)
31969}
31970#[doc = "Duplicate vector element to vector or scalar"]
31971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
31972#[inline]
31973#[target_feature(enable = "neon")]
31974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31975#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31976#[cfg_attr(
31977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31978    assert_instr(dup)
31979)]
31980#[cfg_attr(
31981    not(target_arch = "arm"),
31982    stable(feature = "neon_intrinsics", since = "1.59.0")
31983)]
31984#[cfg_attr(
31985    target_arch = "arm",
31986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31987)]
31988pub fn vmov_n_s16(value: i16) -> int16x4_t {
31989    vdup_n_s16(value)
31990}
31991#[doc = "Duplicate vector element to vector or scalar"]
31992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
31993#[inline]
31994#[target_feature(enable = "neon")]
31995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31996#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31997#[cfg_attr(
31998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31999    assert_instr(dup)
32000)]
32001#[cfg_attr(
32002    not(target_arch = "arm"),
32003    stable(feature = "neon_intrinsics", since = "1.59.0")
32004)]
32005#[cfg_attr(
32006    target_arch = "arm",
32007    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32008)]
32009pub fn vmov_n_s32(value: i32) -> int32x2_t {
32010    vdup_n_s32(value)
32011}
32012#[doc = "Duplicate vector element to vector or scalar"]
32013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
32014#[inline]
32015#[target_feature(enable = "neon")]
32016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32018#[cfg_attr(
32019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32020    assert_instr(fmov)
32021)]
32022#[cfg_attr(
32023    not(target_arch = "arm"),
32024    stable(feature = "neon_intrinsics", since = "1.59.0")
32025)]
32026#[cfg_attr(
32027    target_arch = "arm",
32028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32029)]
32030pub fn vmov_n_s64(value: i64) -> int64x1_t {
32031    vdup_n_s64(value)
32032}
32033#[doc = "Duplicate vector element to vector or scalar"]
32034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
32035#[inline]
32036#[target_feature(enable = "neon")]
32037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32038#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32039#[cfg_attr(
32040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32041    assert_instr(dup)
32042)]
32043#[cfg_attr(
32044    not(target_arch = "arm"),
32045    stable(feature = "neon_intrinsics", since = "1.59.0")
32046)]
32047#[cfg_attr(
32048    target_arch = "arm",
32049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32050)]
32051pub fn vmov_n_s8(value: i8) -> int8x8_t {
32052    vdup_n_s8(value)
32053}
32054#[doc = "Duplicate vector element to vector or scalar"]
32055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
32056#[inline]
32057#[target_feature(enable = "neon")]
32058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32059#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32060#[cfg_attr(
32061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32062    assert_instr(dup)
32063)]
32064#[cfg_attr(
32065    not(target_arch = "arm"),
32066    stable(feature = "neon_intrinsics", since = "1.59.0")
32067)]
32068#[cfg_attr(
32069    target_arch = "arm",
32070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32071)]
32072pub fn vmov_n_u16(value: u16) -> uint16x4_t {
32073    vdup_n_u16(value)
32074}
32075#[doc = "Duplicate vector element to vector or scalar"]
32076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
32077#[inline]
32078#[target_feature(enable = "neon")]
32079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32081#[cfg_attr(
32082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32083    assert_instr(dup)
32084)]
32085#[cfg_attr(
32086    not(target_arch = "arm"),
32087    stable(feature = "neon_intrinsics", since = "1.59.0")
32088)]
32089#[cfg_attr(
32090    target_arch = "arm",
32091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32092)]
32093pub fn vmov_n_u32(value: u32) -> uint32x2_t {
32094    vdup_n_u32(value)
32095}
32096#[doc = "Duplicate vector element to vector or scalar"]
32097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
32098#[inline]
32099#[target_feature(enable = "neon")]
32100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32101#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32102#[cfg_attr(
32103    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32104    assert_instr(fmov)
32105)]
32106#[cfg_attr(
32107    not(target_arch = "arm"),
32108    stable(feature = "neon_intrinsics", since = "1.59.0")
32109)]
32110#[cfg_attr(
32111    target_arch = "arm",
32112    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32113)]
32114pub fn vmov_n_u64(value: u64) -> uint64x1_t {
32115    vdup_n_u64(value)
32116}
32117#[doc = "Duplicate vector element to vector or scalar"]
32118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
32119#[inline]
32120#[target_feature(enable = "neon")]
32121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32123#[cfg_attr(
32124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32125    assert_instr(dup)
32126)]
32127#[cfg_attr(
32128    not(target_arch = "arm"),
32129    stable(feature = "neon_intrinsics", since = "1.59.0")
32130)]
32131#[cfg_attr(
32132    target_arch = "arm",
32133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32134)]
32135pub fn vmov_n_u8(value: u8) -> uint8x8_t {
32136    vdup_n_u8(value)
32137}
32138#[doc = "Duplicate vector element to vector or scalar"]
32139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
32140#[inline]
32141#[target_feature(enable = "neon")]
32142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32143#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32144#[cfg_attr(
32145    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32146    assert_instr(dup)
32147)]
32148#[cfg_attr(
32149    not(target_arch = "arm"),
32150    stable(feature = "neon_intrinsics", since = "1.59.0")
32151)]
32152#[cfg_attr(
32153    target_arch = "arm",
32154    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32155)]
32156pub fn vmovq_n_f32(value: f32) -> float32x4_t {
32157    vdupq_n_f32(value)
32158}
32159#[doc = "Duplicate vector element to vector or scalar"]
32160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
32161#[inline]
32162#[target_feature(enable = "neon")]
32163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32164#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32165#[cfg_attr(
32166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32167    assert_instr(dup)
32168)]
32169#[cfg_attr(
32170    not(target_arch = "arm"),
32171    stable(feature = "neon_intrinsics", since = "1.59.0")
32172)]
32173#[cfg_attr(
32174    target_arch = "arm",
32175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32176)]
32177pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
32178    vdupq_n_p16(value)
32179}
32180#[doc = "Duplicate vector element to vector or scalar"]
32181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
32182#[inline]
32183#[target_feature(enable = "neon")]
32184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32186#[cfg_attr(
32187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32188    assert_instr(dup)
32189)]
32190#[cfg_attr(
32191    not(target_arch = "arm"),
32192    stable(feature = "neon_intrinsics", since = "1.59.0")
32193)]
32194#[cfg_attr(
32195    target_arch = "arm",
32196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32197)]
32198pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
32199    vdupq_n_p8(value)
32200}
32201#[doc = "Duplicate vector element to vector or scalar"]
32202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
32203#[inline]
32204#[target_feature(enable = "neon")]
32205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32206#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32207#[cfg_attr(
32208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32209    assert_instr(dup)
32210)]
32211#[cfg_attr(
32212    not(target_arch = "arm"),
32213    stable(feature = "neon_intrinsics", since = "1.59.0")
32214)]
32215#[cfg_attr(
32216    target_arch = "arm",
32217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32218)]
32219pub fn vmovq_n_s16(value: i16) -> int16x8_t {
32220    vdupq_n_s16(value)
32221}
32222#[doc = "Duplicate vector element to vector or scalar"]
32223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
32224#[inline]
32225#[target_feature(enable = "neon")]
32226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32228#[cfg_attr(
32229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32230    assert_instr(dup)
32231)]
32232#[cfg_attr(
32233    not(target_arch = "arm"),
32234    stable(feature = "neon_intrinsics", since = "1.59.0")
32235)]
32236#[cfg_attr(
32237    target_arch = "arm",
32238    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32239)]
32240pub fn vmovq_n_s32(value: i32) -> int32x4_t {
32241    vdupq_n_s32(value)
32242}
32243#[doc = "Duplicate vector element to vector or scalar"]
32244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
32245#[inline]
32246#[target_feature(enable = "neon")]
32247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32248#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32249#[cfg_attr(
32250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32251    assert_instr(dup)
32252)]
32253#[cfg_attr(
32254    not(target_arch = "arm"),
32255    stable(feature = "neon_intrinsics", since = "1.59.0")
32256)]
32257#[cfg_attr(
32258    target_arch = "arm",
32259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32260)]
32261pub fn vmovq_n_s64(value: i64) -> int64x2_t {
32262    vdupq_n_s64(value)
32263}
32264#[doc = "Duplicate vector element to vector or scalar"]
32265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
32266#[inline]
32267#[target_feature(enable = "neon")]
32268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32269#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32270#[cfg_attr(
32271    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32272    assert_instr(dup)
32273)]
32274#[cfg_attr(
32275    not(target_arch = "arm"),
32276    stable(feature = "neon_intrinsics", since = "1.59.0")
32277)]
32278#[cfg_attr(
32279    target_arch = "arm",
32280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32281)]
32282pub fn vmovq_n_s8(value: i8) -> int8x16_t {
32283    vdupq_n_s8(value)
32284}
32285#[doc = "Duplicate vector element to vector or scalar"]
32286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
32287#[inline]
32288#[target_feature(enable = "neon")]
32289#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32290#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32291#[cfg_attr(
32292    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32293    assert_instr(dup)
32294)]
32295#[cfg_attr(
32296    not(target_arch = "arm"),
32297    stable(feature = "neon_intrinsics", since = "1.59.0")
32298)]
32299#[cfg_attr(
32300    target_arch = "arm",
32301    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32302)]
32303pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
32304    vdupq_n_u16(value)
32305}
32306#[doc = "Duplicate vector element to vector or scalar"]
32307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
32308#[inline]
32309#[target_feature(enable = "neon")]
32310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32312#[cfg_attr(
32313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32314    assert_instr(dup)
32315)]
32316#[cfg_attr(
32317    not(target_arch = "arm"),
32318    stable(feature = "neon_intrinsics", since = "1.59.0")
32319)]
32320#[cfg_attr(
32321    target_arch = "arm",
32322    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32323)]
32324pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
32325    vdupq_n_u32(value)
32326}
32327#[doc = "Duplicate vector element to vector or scalar"]
32328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
32329#[inline]
32330#[target_feature(enable = "neon")]
32331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32332#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32333#[cfg_attr(
32334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32335    assert_instr(dup)
32336)]
32337#[cfg_attr(
32338    not(target_arch = "arm"),
32339    stable(feature = "neon_intrinsics", since = "1.59.0")
32340)]
32341#[cfg_attr(
32342    target_arch = "arm",
32343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32344)]
32345pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
32346    vdupq_n_u64(value)
32347}
32348#[doc = "Duplicate vector element to vector or scalar"]
32349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
32350#[inline]
32351#[target_feature(enable = "neon")]
32352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32353#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32354#[cfg_attr(
32355    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32356    assert_instr(dup)
32357)]
32358#[cfg_attr(
32359    not(target_arch = "arm"),
32360    stable(feature = "neon_intrinsics", since = "1.59.0")
32361)]
32362#[cfg_attr(
32363    target_arch = "arm",
32364    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32365)]
32366pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
32367    vdupq_n_u8(value)
32368}
32369#[doc = "Vector long move."]
32370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
32371#[inline]
32372#[target_feature(enable = "neon")]
32373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32375#[cfg_attr(
32376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32377    assert_instr(sxtl)
32378)]
32379#[cfg_attr(
32380    not(target_arch = "arm"),
32381    stable(feature = "neon_intrinsics", since = "1.59.0")
32382)]
32383#[cfg_attr(
32384    target_arch = "arm",
32385    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32386)]
32387pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
32388    unsafe { simd_cast(a) }
32389}
32390#[doc = "Vector long move."]
32391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
32392#[inline]
32393#[target_feature(enable = "neon")]
32394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32396#[cfg_attr(
32397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32398    assert_instr(sxtl)
32399)]
32400#[cfg_attr(
32401    not(target_arch = "arm"),
32402    stable(feature = "neon_intrinsics", since = "1.59.0")
32403)]
32404#[cfg_attr(
32405    target_arch = "arm",
32406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32407)]
32408pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
32409    unsafe { simd_cast(a) }
32410}
32411#[doc = "Vector long move."]
32412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
32413#[inline]
32414#[target_feature(enable = "neon")]
32415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32417#[cfg_attr(
32418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32419    assert_instr(sxtl)
32420)]
32421#[cfg_attr(
32422    not(target_arch = "arm"),
32423    stable(feature = "neon_intrinsics", since = "1.59.0")
32424)]
32425#[cfg_attr(
32426    target_arch = "arm",
32427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32428)]
32429pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
32430    unsafe { simd_cast(a) }
32431}
32432#[doc = "Vector long move."]
32433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
32434#[inline]
32435#[target_feature(enable = "neon")]
32436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32438#[cfg_attr(
32439    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32440    assert_instr(uxtl)
32441)]
32442#[cfg_attr(
32443    not(target_arch = "arm"),
32444    stable(feature = "neon_intrinsics", since = "1.59.0")
32445)]
32446#[cfg_attr(
32447    target_arch = "arm",
32448    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32449)]
32450pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
32451    unsafe { simd_cast(a) }
32452}
32453#[doc = "Vector long move."]
32454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
32455#[inline]
32456#[target_feature(enable = "neon")]
32457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32459#[cfg_attr(
32460    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32461    assert_instr(uxtl)
32462)]
32463#[cfg_attr(
32464    not(target_arch = "arm"),
32465    stable(feature = "neon_intrinsics", since = "1.59.0")
32466)]
32467#[cfg_attr(
32468    target_arch = "arm",
32469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32470)]
32471pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
32472    unsafe { simd_cast(a) }
32473}
32474#[doc = "Vector long move."]
32475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
32476#[inline]
32477#[target_feature(enable = "neon")]
32478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32480#[cfg_attr(
32481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32482    assert_instr(uxtl)
32483)]
32484#[cfg_attr(
32485    not(target_arch = "arm"),
32486    stable(feature = "neon_intrinsics", since = "1.59.0")
32487)]
32488#[cfg_attr(
32489    target_arch = "arm",
32490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32491)]
32492pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
32493    unsafe { simd_cast(a) }
32494}
32495#[doc = "Vector narrow integer."]
32496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
32497#[inline]
32498#[target_feature(enable = "neon")]
32499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32501#[cfg_attr(
32502    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32503    assert_instr(xtn)
32504)]
32505#[cfg_attr(
32506    not(target_arch = "arm"),
32507    stable(feature = "neon_intrinsics", since = "1.59.0")
32508)]
32509#[cfg_attr(
32510    target_arch = "arm",
32511    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32512)]
32513pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
32514    unsafe { simd_cast(a) }
32515}
32516#[doc = "Vector narrow integer."]
32517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
32518#[inline]
32519#[target_feature(enable = "neon")]
32520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32522#[cfg_attr(
32523    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32524    assert_instr(xtn)
32525)]
32526#[cfg_attr(
32527    not(target_arch = "arm"),
32528    stable(feature = "neon_intrinsics", since = "1.59.0")
32529)]
32530#[cfg_attr(
32531    target_arch = "arm",
32532    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32533)]
32534pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
32535    unsafe { simd_cast(a) }
32536}
32537#[doc = "Vector narrow integer."]
32538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
32539#[inline]
32540#[target_feature(enable = "neon")]
32541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32543#[cfg_attr(
32544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32545    assert_instr(xtn)
32546)]
32547#[cfg_attr(
32548    not(target_arch = "arm"),
32549    stable(feature = "neon_intrinsics", since = "1.59.0")
32550)]
32551#[cfg_attr(
32552    target_arch = "arm",
32553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32554)]
32555pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
32556    unsafe { simd_cast(a) }
32557}
32558#[doc = "Vector narrow integer."]
32559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
32560#[inline]
32561#[target_feature(enable = "neon")]
32562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32564#[cfg_attr(
32565    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32566    assert_instr(xtn)
32567)]
32568#[cfg_attr(
32569    not(target_arch = "arm"),
32570    stable(feature = "neon_intrinsics", since = "1.59.0")
32571)]
32572#[cfg_attr(
32573    target_arch = "arm",
32574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32575)]
32576pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
32577    unsafe { simd_cast(a) }
32578}
32579#[doc = "Vector narrow integer."]
32580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
32581#[inline]
32582#[target_feature(enable = "neon")]
32583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32585#[cfg_attr(
32586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32587    assert_instr(xtn)
32588)]
32589#[cfg_attr(
32590    not(target_arch = "arm"),
32591    stable(feature = "neon_intrinsics", since = "1.59.0")
32592)]
32593#[cfg_attr(
32594    target_arch = "arm",
32595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32596)]
32597pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
32598    unsafe { simd_cast(a) }
32599}
32600#[doc = "Vector narrow integer."]
32601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
32602#[inline]
32603#[target_feature(enable = "neon")]
32604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32606#[cfg_attr(
32607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32608    assert_instr(xtn)
32609)]
32610#[cfg_attr(
32611    not(target_arch = "arm"),
32612    stable(feature = "neon_intrinsics", since = "1.59.0")
32613)]
32614#[cfg_attr(
32615    target_arch = "arm",
32616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32617)]
32618pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
32619    unsafe { simd_cast(a) }
32620}
32621#[doc = "Multiply"]
32622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
32623#[inline]
32624#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32626#[cfg_attr(
32627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32628    assert_instr(fmul)
32629)]
32630#[target_feature(enable = "neon,fp16")]
32631#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32632pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
32633    unsafe { simd_mul(a, b) }
32634}
32635#[doc = "Multiply"]
32636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
32637#[inline]
32638#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32639#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32640#[cfg_attr(
32641    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32642    assert_instr(fmul)
32643)]
32644#[target_feature(enable = "neon,fp16")]
32645#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32646pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
32647    unsafe { simd_mul(a, b) }
32648}
32649#[doc = "Multiply"]
32650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
32651#[inline]
32652#[target_feature(enable = "neon")]
32653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32655#[cfg_attr(
32656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32657    assert_instr(fmul)
32658)]
32659#[cfg_attr(
32660    not(target_arch = "arm"),
32661    stable(feature = "neon_intrinsics", since = "1.59.0")
32662)]
32663#[cfg_attr(
32664    target_arch = "arm",
32665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32666)]
32667pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32668    unsafe { simd_mul(a, b) }
32669}
32670#[doc = "Multiply"]
32671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
32672#[inline]
32673#[target_feature(enable = "neon")]
32674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32676#[cfg_attr(
32677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32678    assert_instr(fmul)
32679)]
32680#[cfg_attr(
32681    not(target_arch = "arm"),
32682    stable(feature = "neon_intrinsics", since = "1.59.0")
32683)]
32684#[cfg_attr(
32685    target_arch = "arm",
32686    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32687)]
32688pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32689    unsafe { simd_mul(a, b) }
32690}
32691#[doc = "Multiply"]
32692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
32693#[inline]
32694#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32696#[cfg_attr(
32697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32698    assert_instr(fmul, LANE = 1)
32699)]
32700#[rustc_legacy_const_generics(2)]
32701#[target_feature(enable = "neon,fp16")]
32702#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32703pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
32704    static_assert_uimm_bits!(LANE, 2);
32705    unsafe {
32706        simd_mul(
32707            a,
32708            simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32709        )
32710    }
32711}
32712#[doc = "Multiply"]
32713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
32714#[inline]
32715#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32717#[cfg_attr(
32718    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32719    assert_instr(fmul, LANE = 1)
32720)]
32721#[rustc_legacy_const_generics(2)]
32722#[target_feature(enable = "neon,fp16")]
32723#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32724pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
32725    static_assert_uimm_bits!(LANE, 2);
32726    unsafe {
32727        simd_mul(
32728            a,
32729            simd_shuffle!(
32730                v,
32731                v,
32732                [
32733                    LANE as u32,
32734                    LANE as u32,
32735                    LANE as u32,
32736                    LANE as u32,
32737                    LANE as u32,
32738                    LANE as u32,
32739                    LANE as u32,
32740                    LANE as u32
32741                ]
32742            ),
32743        )
32744    }
32745}
32746#[doc = "Floating-point multiply"]
32747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
32748#[inline]
32749#[target_feature(enable = "neon")]
32750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32752#[cfg_attr(
32753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32754    assert_instr(fmul, LANE = 0)
32755)]
32756#[rustc_legacy_const_generics(2)]
32757#[cfg_attr(
32758    not(target_arch = "arm"),
32759    stable(feature = "neon_intrinsics", since = "1.59.0")
32760)]
32761#[cfg_attr(
32762    target_arch = "arm",
32763    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32764)]
32765pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32766    static_assert_uimm_bits!(LANE, 1);
32767    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32768}
32769#[doc = "Floating-point multiply"]
32770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
32771#[inline]
32772#[target_feature(enable = "neon")]
32773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32775#[cfg_attr(
32776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32777    assert_instr(fmul, LANE = 0)
32778)]
32779#[rustc_legacy_const_generics(2)]
32780#[cfg_attr(
32781    not(target_arch = "arm"),
32782    stable(feature = "neon_intrinsics", since = "1.59.0")
32783)]
32784#[cfg_attr(
32785    target_arch = "arm",
32786    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32787)]
32788pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
32789    static_assert_uimm_bits!(LANE, 2);
32790    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32791}
32792#[doc = "Floating-point multiply"]
32793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
32794#[inline]
32795#[target_feature(enable = "neon")]
32796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32798#[cfg_attr(
32799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32800    assert_instr(fmul, LANE = 0)
32801)]
32802#[rustc_legacy_const_generics(2)]
32803#[cfg_attr(
32804    not(target_arch = "arm"),
32805    stable(feature = "neon_intrinsics", since = "1.59.0")
32806)]
32807#[cfg_attr(
32808    target_arch = "arm",
32809    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32810)]
32811pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
32812    static_assert_uimm_bits!(LANE, 1);
32813    unsafe {
32814        simd_mul(
32815            a,
32816            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32817        )
32818    }
32819}
32820#[doc = "Floating-point multiply"]
32821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
32822#[inline]
32823#[target_feature(enable = "neon")]
32824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32826#[cfg_attr(
32827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32828    assert_instr(fmul, LANE = 0)
32829)]
32830#[rustc_legacy_const_generics(2)]
32831#[cfg_attr(
32832    not(target_arch = "arm"),
32833    stable(feature = "neon_intrinsics", since = "1.59.0")
32834)]
32835#[cfg_attr(
32836    target_arch = "arm",
32837    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32838)]
32839pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32840    static_assert_uimm_bits!(LANE, 2);
32841    unsafe {
32842        simd_mul(
32843            a,
32844            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32845        )
32846    }
32847}
32848#[doc = "Multiply"]
32849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
32850#[inline]
32851#[target_feature(enable = "neon")]
32852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32854#[cfg_attr(
32855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32856    assert_instr(mul, LANE = 1)
32857)]
32858#[rustc_legacy_const_generics(2)]
32859#[cfg_attr(
32860    not(target_arch = "arm"),
32861    stable(feature = "neon_intrinsics", since = "1.59.0")
32862)]
32863#[cfg_attr(
32864    target_arch = "arm",
32865    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32866)]
32867pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32868    static_assert_uimm_bits!(LANE, 2);
32869    unsafe {
32870        simd_mul(
32871            a,
32872            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32873        )
32874    }
32875}
32876#[doc = "Multiply"]
32877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
32878#[inline]
32879#[target_feature(enable = "neon")]
32880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32882#[cfg_attr(
32883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32884    assert_instr(mul, LANE = 1)
32885)]
32886#[rustc_legacy_const_generics(2)]
32887#[cfg_attr(
32888    not(target_arch = "arm"),
32889    stable(feature = "neon_intrinsics", since = "1.59.0")
32890)]
32891#[cfg_attr(
32892    target_arch = "arm",
32893    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32894)]
32895pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
32896    static_assert_uimm_bits!(LANE, 2);
32897    unsafe {
32898        simd_mul(
32899            a,
32900            simd_shuffle!(
32901                b,
32902                b,
32903                [
32904                    LANE as u32,
32905                    LANE as u32,
32906                    LANE as u32,
32907                    LANE as u32,
32908                    LANE as u32,
32909                    LANE as u32,
32910                    LANE as u32,
32911                    LANE as u32
32912                ]
32913            ),
32914        )
32915    }
32916}
32917#[doc = "Multiply"]
32918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
32919#[inline]
32920#[target_feature(enable = "neon")]
32921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32923#[cfg_attr(
32924    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32925    assert_instr(mul, LANE = 1)
32926)]
32927#[rustc_legacy_const_generics(2)]
32928#[cfg_attr(
32929    not(target_arch = "arm"),
32930    stable(feature = "neon_intrinsics", since = "1.59.0")
32931)]
32932#[cfg_attr(
32933    target_arch = "arm",
32934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32935)]
32936pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32937    static_assert_uimm_bits!(LANE, 1);
32938    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32939}
32940#[doc = "Multiply"]
32941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
32942#[inline]
32943#[target_feature(enable = "neon")]
32944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32946#[cfg_attr(
32947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32948    assert_instr(mul, LANE = 1)
32949)]
32950#[rustc_legacy_const_generics(2)]
32951#[cfg_attr(
32952    not(target_arch = "arm"),
32953    stable(feature = "neon_intrinsics", since = "1.59.0")
32954)]
32955#[cfg_attr(
32956    target_arch = "arm",
32957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32958)]
32959pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
32960    static_assert_uimm_bits!(LANE, 1);
32961    unsafe {
32962        simd_mul(
32963            a,
32964            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32965        )
32966    }
32967}
32968#[doc = "Multiply"]
32969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
32970#[inline]
32971#[target_feature(enable = "neon")]
32972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32974#[cfg_attr(
32975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32976    assert_instr(mul, LANE = 1)
32977)]
32978#[rustc_legacy_const_generics(2)]
32979#[cfg_attr(
32980    not(target_arch = "arm"),
32981    stable(feature = "neon_intrinsics", since = "1.59.0")
32982)]
32983#[cfg_attr(
32984    target_arch = "arm",
32985    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32986)]
32987pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
32988    static_assert_uimm_bits!(LANE, 2);
32989    unsafe {
32990        simd_mul(
32991            a,
32992            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32993        )
32994    }
32995}
32996#[doc = "Multiply"]
32997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
32998#[inline]
32999#[target_feature(enable = "neon")]
33000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33002#[cfg_attr(
33003    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33004    assert_instr(mul, LANE = 1)
33005)]
33006#[rustc_legacy_const_generics(2)]
33007#[cfg_attr(
33008    not(target_arch = "arm"),
33009    stable(feature = "neon_intrinsics", since = "1.59.0")
33010)]
33011#[cfg_attr(
33012    target_arch = "arm",
33013    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33014)]
33015pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
33016    static_assert_uimm_bits!(LANE, 2);
33017    unsafe {
33018        simd_mul(
33019            a,
33020            simd_shuffle!(
33021                b,
33022                b,
33023                [
33024                    LANE as u32,
33025                    LANE as u32,
33026                    LANE as u32,
33027                    LANE as u32,
33028                    LANE as u32,
33029                    LANE as u32,
33030                    LANE as u32,
33031                    LANE as u32
33032                ]
33033            ),
33034        )
33035    }
33036}
33037#[doc = "Multiply"]
33038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
33039#[inline]
33040#[target_feature(enable = "neon")]
33041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33043#[cfg_attr(
33044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33045    assert_instr(mul, LANE = 1)
33046)]
33047#[rustc_legacy_const_generics(2)]
33048#[cfg_attr(
33049    not(target_arch = "arm"),
33050    stable(feature = "neon_intrinsics", since = "1.59.0")
33051)]
33052#[cfg_attr(
33053    target_arch = "arm",
33054    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33055)]
33056pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33057    static_assert_uimm_bits!(LANE, 1);
33058    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33059}
33060#[doc = "Multiply"]
33061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
33062#[inline]
33063#[target_feature(enable = "neon")]
33064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33065#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33066#[cfg_attr(
33067    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33068    assert_instr(mul, LANE = 1)
33069)]
33070#[rustc_legacy_const_generics(2)]
33071#[cfg_attr(
33072    not(target_arch = "arm"),
33073    stable(feature = "neon_intrinsics", since = "1.59.0")
33074)]
33075#[cfg_attr(
33076    target_arch = "arm",
33077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33078)]
33079pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
33080    static_assert_uimm_bits!(LANE, 1);
33081    unsafe {
33082        simd_mul(
33083            a,
33084            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33085        )
33086    }
33087}
33088#[doc = "Multiply"]
33089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
33090#[inline]
33091#[target_feature(enable = "neon")]
33092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33094#[cfg_attr(
33095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33096    assert_instr(mul, LANE = 1)
33097)]
33098#[rustc_legacy_const_generics(2)]
33099#[cfg_attr(
33100    not(target_arch = "arm"),
33101    stable(feature = "neon_intrinsics", since = "1.59.0")
33102)]
33103#[cfg_attr(
33104    target_arch = "arm",
33105    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33106)]
33107pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
33108    static_assert_uimm_bits!(LANE, 3);
33109    unsafe {
33110        simd_mul(
33111            a,
33112            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33113        )
33114    }
33115}
33116#[doc = "Multiply"]
33117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
33118#[inline]
33119#[target_feature(enable = "neon")]
33120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33122#[cfg_attr(
33123    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33124    assert_instr(mul, LANE = 1)
33125)]
33126#[rustc_legacy_const_generics(2)]
33127#[cfg_attr(
33128    not(target_arch = "arm"),
33129    stable(feature = "neon_intrinsics", since = "1.59.0")
33130)]
33131#[cfg_attr(
33132    target_arch = "arm",
33133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33134)]
33135pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33136    static_assert_uimm_bits!(LANE, 3);
33137    unsafe {
33138        simd_mul(
33139            a,
33140            simd_shuffle!(
33141                b,
33142                b,
33143                [
33144                    LANE as u32,
33145                    LANE as u32,
33146                    LANE as u32,
33147                    LANE as u32,
33148                    LANE as u32,
33149                    LANE as u32,
33150                    LANE as u32,
33151                    LANE as u32
33152                ]
33153            ),
33154        )
33155    }
33156}
33157#[doc = "Multiply"]
33158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
33159#[inline]
33160#[target_feature(enable = "neon")]
33161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33163#[cfg_attr(
33164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33165    assert_instr(mul, LANE = 1)
33166)]
33167#[rustc_legacy_const_generics(2)]
33168#[cfg_attr(
33169    not(target_arch = "arm"),
33170    stable(feature = "neon_intrinsics", since = "1.59.0")
33171)]
33172#[cfg_attr(
33173    target_arch = "arm",
33174    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33175)]
33176pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
33177    static_assert_uimm_bits!(LANE, 2);
33178    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33179}
33180#[doc = "Multiply"]
33181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
33182#[inline]
33183#[target_feature(enable = "neon")]
33184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33186#[cfg_attr(
33187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33188    assert_instr(mul, LANE = 1)
33189)]
33190#[rustc_legacy_const_generics(2)]
33191#[cfg_attr(
33192    not(target_arch = "arm"),
33193    stable(feature = "neon_intrinsics", since = "1.59.0")
33194)]
33195#[cfg_attr(
33196    target_arch = "arm",
33197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33198)]
33199pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33200    static_assert_uimm_bits!(LANE, 2);
33201    unsafe {
33202        simd_mul(
33203            a,
33204            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33205        )
33206    }
33207}
33208#[doc = "Multiply"]
33209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
33210#[inline]
33211#[target_feature(enable = "neon")]
33212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33214#[cfg_attr(
33215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33216    assert_instr(mul, LANE = 1)
33217)]
33218#[rustc_legacy_const_generics(2)]
33219#[cfg_attr(
33220    not(target_arch = "arm"),
33221    stable(feature = "neon_intrinsics", since = "1.59.0")
33222)]
33223#[cfg_attr(
33224    target_arch = "arm",
33225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33226)]
33227pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
33228    static_assert_uimm_bits!(LANE, 3);
33229    unsafe {
33230        simd_mul(
33231            a,
33232            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33233        )
33234    }
33235}
33236#[doc = "Multiply"]
33237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
33238#[inline]
33239#[target_feature(enable = "neon")]
33240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33241#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33242#[cfg_attr(
33243    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33244    assert_instr(mul, LANE = 1)
33245)]
33246#[rustc_legacy_const_generics(2)]
33247#[cfg_attr(
33248    not(target_arch = "arm"),
33249    stable(feature = "neon_intrinsics", since = "1.59.0")
33250)]
33251#[cfg_attr(
33252    target_arch = "arm",
33253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33254)]
33255pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33256    static_assert_uimm_bits!(LANE, 3);
33257    unsafe {
33258        simd_mul(
33259            a,
33260            simd_shuffle!(
33261                b,
33262                b,
33263                [
33264                    LANE as u32,
33265                    LANE as u32,
33266                    LANE as u32,
33267                    LANE as u32,
33268                    LANE as u32,
33269                    LANE as u32,
33270                    LANE as u32,
33271                    LANE as u32
33272                ]
33273            ),
33274        )
33275    }
33276}
33277#[doc = "Multiply"]
33278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
33279#[inline]
33280#[target_feature(enable = "neon")]
33281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33283#[cfg_attr(
33284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33285    assert_instr(mul, LANE = 1)
33286)]
33287#[rustc_legacy_const_generics(2)]
33288#[cfg_attr(
33289    not(target_arch = "arm"),
33290    stable(feature = "neon_intrinsics", since = "1.59.0")
33291)]
33292#[cfg_attr(
33293    target_arch = "arm",
33294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33295)]
33296pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
33297    static_assert_uimm_bits!(LANE, 2);
33298    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33299}
33300#[doc = "Multiply"]
33301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
33302#[inline]
33303#[target_feature(enable = "neon")]
33304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33306#[cfg_attr(
33307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33308    assert_instr(mul, LANE = 1)
33309)]
33310#[rustc_legacy_const_generics(2)]
33311#[cfg_attr(
33312    not(target_arch = "arm"),
33313    stable(feature = "neon_intrinsics", since = "1.59.0")
33314)]
33315#[cfg_attr(
33316    target_arch = "arm",
33317    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33318)]
33319pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33320    static_assert_uimm_bits!(LANE, 2);
33321    unsafe {
33322        simd_mul(
33323            a,
33324            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33325        )
33326    }
33327}
33328#[doc = "Vector multiply by scalar"]
33329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
33330#[inline]
33331#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33333#[cfg_attr(
33334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33335    assert_instr(fmul)
33336)]
33337#[target_feature(enable = "neon,fp16")]
33338#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33339pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
33340    unsafe { simd_mul(a, vdup_n_f16(b)) }
33341}
33342#[doc = "Vector multiply by scalar"]
33343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
33344#[inline]
33345#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33347#[cfg_attr(
33348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33349    assert_instr(fmul)
33350)]
33351#[target_feature(enable = "neon,fp16")]
33352#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33353pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
33354    unsafe { simd_mul(a, vdupq_n_f16(b)) }
33355}
33356#[doc = "Vector multiply by scalar"]
33357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
33358#[inline]
33359#[target_feature(enable = "neon")]
33360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33362#[cfg_attr(
33363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33364    assert_instr(fmul)
33365)]
33366#[cfg_attr(
33367    not(target_arch = "arm"),
33368    stable(feature = "neon_intrinsics", since = "1.59.0")
33369)]
33370#[cfg_attr(
33371    target_arch = "arm",
33372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33373)]
33374pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
33375    unsafe { simd_mul(a, vdup_n_f32(b)) }
33376}
33377#[doc = "Vector multiply by scalar"]
33378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
33379#[inline]
33380#[target_feature(enable = "neon")]
33381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33383#[cfg_attr(
33384    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33385    assert_instr(fmul)
33386)]
33387#[cfg_attr(
33388    not(target_arch = "arm"),
33389    stable(feature = "neon_intrinsics", since = "1.59.0")
33390)]
33391#[cfg_attr(
33392    target_arch = "arm",
33393    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33394)]
33395pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
33396    unsafe { simd_mul(a, vdupq_n_f32(b)) }
33397}
33398#[doc = "Vector multiply by scalar"]
33399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
33400#[inline]
33401#[target_feature(enable = "neon")]
33402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33404#[cfg_attr(
33405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33406    assert_instr(mul)
33407)]
33408#[cfg_attr(
33409    not(target_arch = "arm"),
33410    stable(feature = "neon_intrinsics", since = "1.59.0")
33411)]
33412#[cfg_attr(
33413    target_arch = "arm",
33414    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33415)]
33416pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
33417    unsafe { simd_mul(a, vdup_n_s16(b)) }
33418}
33419#[doc = "Vector multiply by scalar"]
33420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
33421#[inline]
33422#[target_feature(enable = "neon")]
33423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33425#[cfg_attr(
33426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33427    assert_instr(mul)
33428)]
33429#[cfg_attr(
33430    not(target_arch = "arm"),
33431    stable(feature = "neon_intrinsics", since = "1.59.0")
33432)]
33433#[cfg_attr(
33434    target_arch = "arm",
33435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33436)]
33437pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
33438    unsafe { simd_mul(a, vdupq_n_s16(b)) }
33439}
33440#[doc = "Vector multiply by scalar"]
33441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
33442#[inline]
33443#[target_feature(enable = "neon")]
33444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33446#[cfg_attr(
33447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33448    assert_instr(mul)
33449)]
33450#[cfg_attr(
33451    not(target_arch = "arm"),
33452    stable(feature = "neon_intrinsics", since = "1.59.0")
33453)]
33454#[cfg_attr(
33455    target_arch = "arm",
33456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33457)]
33458pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
33459    unsafe { simd_mul(a, vdup_n_s32(b)) }
33460}
33461#[doc = "Vector multiply by scalar"]
33462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
33463#[inline]
33464#[target_feature(enable = "neon")]
33465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33467#[cfg_attr(
33468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33469    assert_instr(mul)
33470)]
33471#[cfg_attr(
33472    not(target_arch = "arm"),
33473    stable(feature = "neon_intrinsics", since = "1.59.0")
33474)]
33475#[cfg_attr(
33476    target_arch = "arm",
33477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33478)]
33479pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
33480    unsafe { simd_mul(a, vdupq_n_s32(b)) }
33481}
33482#[doc = "Vector multiply by scalar"]
33483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
33484#[inline]
33485#[target_feature(enable = "neon")]
33486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33488#[cfg_attr(
33489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33490    assert_instr(mul)
33491)]
33492#[cfg_attr(
33493    not(target_arch = "arm"),
33494    stable(feature = "neon_intrinsics", since = "1.59.0")
33495)]
33496#[cfg_attr(
33497    target_arch = "arm",
33498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33499)]
33500pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
33501    unsafe { simd_mul(a, vdup_n_u16(b)) }
33502}
33503#[doc = "Vector multiply by scalar"]
33504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
33505#[inline]
33506#[target_feature(enable = "neon")]
33507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33509#[cfg_attr(
33510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33511    assert_instr(mul)
33512)]
33513#[cfg_attr(
33514    not(target_arch = "arm"),
33515    stable(feature = "neon_intrinsics", since = "1.59.0")
33516)]
33517#[cfg_attr(
33518    target_arch = "arm",
33519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33520)]
33521pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
33522    unsafe { simd_mul(a, vdupq_n_u16(b)) }
33523}
33524#[doc = "Vector multiply by scalar"]
33525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
33526#[inline]
33527#[target_feature(enable = "neon")]
33528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33530#[cfg_attr(
33531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33532    assert_instr(mul)
33533)]
33534#[cfg_attr(
33535    not(target_arch = "arm"),
33536    stable(feature = "neon_intrinsics", since = "1.59.0")
33537)]
33538#[cfg_attr(
33539    target_arch = "arm",
33540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33541)]
33542pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
33543    unsafe { simd_mul(a, vdup_n_u32(b)) }
33544}
33545#[doc = "Vector multiply by scalar"]
33546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
33547#[inline]
33548#[target_feature(enable = "neon")]
33549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33551#[cfg_attr(
33552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33553    assert_instr(mul)
33554)]
33555#[cfg_attr(
33556    not(target_arch = "arm"),
33557    stable(feature = "neon_intrinsics", since = "1.59.0")
33558)]
33559#[cfg_attr(
33560    target_arch = "arm",
33561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33562)]
33563pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
33564    unsafe { simd_mul(a, vdupq_n_u32(b)) }
33565}
33566#[doc = "Polynomial multiply"]
33567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
33568#[inline]
33569#[target_feature(enable = "neon")]
33570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33572#[cfg_attr(
33573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33574    assert_instr(pmul)
33575)]
33576#[cfg_attr(
33577    not(target_arch = "arm"),
33578    stable(feature = "neon_intrinsics", since = "1.59.0")
33579)]
33580#[cfg_attr(
33581    target_arch = "arm",
33582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33583)]
33584pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
33585    unsafe extern "unadjusted" {
33586        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
33587        #[cfg_attr(
33588            any(target_arch = "aarch64", target_arch = "arm64ec"),
33589            link_name = "llvm.aarch64.neon.pmul.v8i8"
33590        )]
33591        fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
33592    }
33593    unsafe { _vmul_p8(a, b) }
33594}
33595#[doc = "Polynomial multiply"]
33596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
33597#[inline]
33598#[target_feature(enable = "neon")]
33599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33601#[cfg_attr(
33602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33603    assert_instr(pmul)
33604)]
33605#[cfg_attr(
33606    not(target_arch = "arm"),
33607    stable(feature = "neon_intrinsics", since = "1.59.0")
33608)]
33609#[cfg_attr(
33610    target_arch = "arm",
33611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33612)]
33613pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
33614    unsafe extern "unadjusted" {
33615        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
33616        #[cfg_attr(
33617            any(target_arch = "aarch64", target_arch = "arm64ec"),
33618            link_name = "llvm.aarch64.neon.pmul.v16i8"
33619        )]
33620        fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
33621    }
33622    unsafe { _vmulq_p8(a, b) }
33623}
33624#[doc = "Multiply"]
33625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
33626#[inline]
33627#[target_feature(enable = "neon")]
33628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33630#[cfg_attr(
33631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33632    assert_instr(mul)
33633)]
33634#[cfg_attr(
33635    not(target_arch = "arm"),
33636    stable(feature = "neon_intrinsics", since = "1.59.0")
33637)]
33638#[cfg_attr(
33639    target_arch = "arm",
33640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33641)]
33642pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
33643    unsafe { simd_mul(a, b) }
33644}
33645#[doc = "Multiply"]
33646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
33647#[inline]
33648#[target_feature(enable = "neon")]
33649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33650#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33651#[cfg_attr(
33652    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33653    assert_instr(mul)
33654)]
33655#[cfg_attr(
33656    not(target_arch = "arm"),
33657    stable(feature = "neon_intrinsics", since = "1.59.0")
33658)]
33659#[cfg_attr(
33660    target_arch = "arm",
33661    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33662)]
33663pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33664    unsafe { simd_mul(a, b) }
33665}
33666#[doc = "Multiply"]
33667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
33668#[inline]
33669#[target_feature(enable = "neon")]
33670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33672#[cfg_attr(
33673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33674    assert_instr(mul)
33675)]
33676#[cfg_attr(
33677    not(target_arch = "arm"),
33678    stable(feature = "neon_intrinsics", since = "1.59.0")
33679)]
33680#[cfg_attr(
33681    target_arch = "arm",
33682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33683)]
33684pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
33685    unsafe { simd_mul(a, b) }
33686}
33687#[doc = "Multiply"]
33688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
33689#[inline]
33690#[target_feature(enable = "neon")]
33691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33693#[cfg_attr(
33694    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33695    assert_instr(mul)
33696)]
33697#[cfg_attr(
33698    not(target_arch = "arm"),
33699    stable(feature = "neon_intrinsics", since = "1.59.0")
33700)]
33701#[cfg_attr(
33702    target_arch = "arm",
33703    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33704)]
33705pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33706    unsafe { simd_mul(a, b) }
33707}
33708#[doc = "Multiply"]
33709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
33710#[inline]
33711#[target_feature(enable = "neon")]
33712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33713#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33714#[cfg_attr(
33715    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33716    assert_instr(mul)
33717)]
33718#[cfg_attr(
33719    not(target_arch = "arm"),
33720    stable(feature = "neon_intrinsics", since = "1.59.0")
33721)]
33722#[cfg_attr(
33723    target_arch = "arm",
33724    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33725)]
33726pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
33727    unsafe { simd_mul(a, b) }
33728}
33729#[doc = "Multiply"]
33730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
33731#[inline]
33732#[target_feature(enable = "neon")]
33733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33734#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33735#[cfg_attr(
33736    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33737    assert_instr(mul)
33738)]
33739#[cfg_attr(
33740    not(target_arch = "arm"),
33741    stable(feature = "neon_intrinsics", since = "1.59.0")
33742)]
33743#[cfg_attr(
33744    target_arch = "arm",
33745    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33746)]
33747pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33748    unsafe { simd_mul(a, b) }
33749}
33750#[doc = "Multiply"]
33751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
33752#[inline]
33753#[target_feature(enable = "neon")]
33754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33756#[cfg_attr(
33757    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33758    assert_instr(mul)
33759)]
33760#[cfg_attr(
33761    not(target_arch = "arm"),
33762    stable(feature = "neon_intrinsics", since = "1.59.0")
33763)]
33764#[cfg_attr(
33765    target_arch = "arm",
33766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33767)]
33768pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33769    unsafe { simd_mul(a, b) }
33770}
33771#[doc = "Multiply"]
33772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
33773#[inline]
33774#[target_feature(enable = "neon")]
33775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33776#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33777#[cfg_attr(
33778    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33779    assert_instr(mul)
33780)]
33781#[cfg_attr(
33782    not(target_arch = "arm"),
33783    stable(feature = "neon_intrinsics", since = "1.59.0")
33784)]
33785#[cfg_attr(
33786    target_arch = "arm",
33787    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33788)]
33789pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33790    unsafe { simd_mul(a, b) }
33791}
33792#[doc = "Multiply"]
33793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
33794#[inline]
33795#[target_feature(enable = "neon")]
33796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33797#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33798#[cfg_attr(
33799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33800    assert_instr(mul)
33801)]
33802#[cfg_attr(
33803    not(target_arch = "arm"),
33804    stable(feature = "neon_intrinsics", since = "1.59.0")
33805)]
33806#[cfg_attr(
33807    target_arch = "arm",
33808    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33809)]
33810pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
33811    unsafe { simd_mul(a, b) }
33812}
33813#[doc = "Multiply"]
33814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
33815#[inline]
33816#[target_feature(enable = "neon")]
33817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33818#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33819#[cfg_attr(
33820    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33821    assert_instr(mul)
33822)]
33823#[cfg_attr(
33824    not(target_arch = "arm"),
33825    stable(feature = "neon_intrinsics", since = "1.59.0")
33826)]
33827#[cfg_attr(
33828    target_arch = "arm",
33829    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33830)]
33831pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
33832    unsafe { simd_mul(a, b) }
33833}
33834#[doc = "Multiply"]
33835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
33836#[inline]
33837#[target_feature(enable = "neon")]
33838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33839#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33840#[cfg_attr(
33841    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33842    assert_instr(mul)
33843)]
33844#[cfg_attr(
33845    not(target_arch = "arm"),
33846    stable(feature = "neon_intrinsics", since = "1.59.0")
33847)]
33848#[cfg_attr(
33849    target_arch = "arm",
33850    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33851)]
33852pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
33853    unsafe { simd_mul(a, b) }
33854}
33855#[doc = "Multiply"]
33856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
33857#[inline]
33858#[target_feature(enable = "neon")]
33859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33860#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33861#[cfg_attr(
33862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33863    assert_instr(mul)
33864)]
33865#[cfg_attr(
33866    not(target_arch = "arm"),
33867    stable(feature = "neon_intrinsics", since = "1.59.0")
33868)]
33869#[cfg_attr(
33870    target_arch = "arm",
33871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33872)]
33873pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
33874    unsafe { simd_mul(a, b) }
33875}
33876#[doc = "Vector long multiply by scalar"]
33877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
33878#[inline]
33879#[target_feature(enable = "neon")]
33880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33882#[cfg_attr(
33883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33884    assert_instr(smull, LANE = 1)
33885)]
33886#[rustc_legacy_const_generics(2)]
33887#[cfg_attr(
33888    not(target_arch = "arm"),
33889    stable(feature = "neon_intrinsics", since = "1.59.0")
33890)]
33891#[cfg_attr(
33892    target_arch = "arm",
33893    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33894)]
33895pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
33896    static_assert_uimm_bits!(LANE, 2);
33897    unsafe {
33898        vmull_s16(
33899            a,
33900            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33901        )
33902    }
33903}
33904#[doc = "Vector long multiply by scalar"]
33905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
33906#[inline]
33907#[target_feature(enable = "neon")]
33908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33910#[cfg_attr(
33911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33912    assert_instr(smull, LANE = 1)
33913)]
33914#[rustc_legacy_const_generics(2)]
33915#[cfg_attr(
33916    not(target_arch = "arm"),
33917    stable(feature = "neon_intrinsics", since = "1.59.0")
33918)]
33919#[cfg_attr(
33920    target_arch = "arm",
33921    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33922)]
33923pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
33924    static_assert_uimm_bits!(LANE, 3);
33925    unsafe {
33926        vmull_s16(
33927            a,
33928            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33929        )
33930    }
33931}
33932#[doc = "Vector long multiply by scalar"]
33933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
33934#[inline]
33935#[target_feature(enable = "neon")]
33936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33938#[cfg_attr(
33939    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33940    assert_instr(smull, LANE = 1)
33941)]
33942#[rustc_legacy_const_generics(2)]
33943#[cfg_attr(
33944    not(target_arch = "arm"),
33945    stable(feature = "neon_intrinsics", since = "1.59.0")
33946)]
33947#[cfg_attr(
33948    target_arch = "arm",
33949    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33950)]
33951pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
33952    static_assert_uimm_bits!(LANE, 1);
33953    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33954}
33955#[doc = "Vector long multiply by scalar"]
33956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
33957#[inline]
33958#[target_feature(enable = "neon")]
33959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33961#[cfg_attr(
33962    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33963    assert_instr(smull, LANE = 1)
33964)]
33965#[rustc_legacy_const_generics(2)]
33966#[cfg_attr(
33967    not(target_arch = "arm"),
33968    stable(feature = "neon_intrinsics", since = "1.59.0")
33969)]
33970#[cfg_attr(
33971    target_arch = "arm",
33972    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33973)]
33974pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
33975    static_assert_uimm_bits!(LANE, 2);
33976    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33977}
33978#[doc = "Vector long multiply by scalar"]
33979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
33980#[inline]
33981#[target_feature(enable = "neon")]
33982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33984#[cfg_attr(
33985    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33986    assert_instr(umull, LANE = 1)
33987)]
33988#[rustc_legacy_const_generics(2)]
33989#[cfg_attr(
33990    not(target_arch = "arm"),
33991    stable(feature = "neon_intrinsics", since = "1.59.0")
33992)]
33993#[cfg_attr(
33994    target_arch = "arm",
33995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33996)]
33997pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
33998    static_assert_uimm_bits!(LANE, 2);
33999    unsafe {
34000        vmull_u16(
34001            a,
34002            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
34003        )
34004    }
34005}
34006#[doc = "Vector long multiply by scalar"]
34007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
34008#[inline]
34009#[target_feature(enable = "neon")]
34010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
34012#[cfg_attr(
34013    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34014    assert_instr(umull, LANE = 1)
34015)]
34016#[rustc_legacy_const_generics(2)]
34017#[cfg_attr(
34018    not(target_arch = "arm"),
34019    stable(feature = "neon_intrinsics", since = "1.59.0")
34020)]
34021#[cfg_attr(
34022    target_arch = "arm",
34023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34024)]
34025pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
34026    static_assert_uimm_bits!(LANE, 3);
34027    unsafe {
34028        vmull_u16(
34029            a,
34030            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
34031        )
34032    }
34033}
34034#[doc = "Vector long multiply by scalar"]
34035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
34036#[inline]
34037#[target_feature(enable = "neon")]
34038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
34040#[cfg_attr(
34041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34042    assert_instr(umull, LANE = 1)
34043)]
34044#[rustc_legacy_const_generics(2)]
34045#[cfg_attr(
34046    not(target_arch = "arm"),
34047    stable(feature = "neon_intrinsics", since = "1.59.0")
34048)]
34049#[cfg_attr(
34050    target_arch = "arm",
34051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34052)]
34053pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34054    static_assert_uimm_bits!(LANE, 1);
34055    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
34056}
34057#[doc = "Vector long multiply by scalar"]
34058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
34059#[inline]
34060#[target_feature(enable = "neon")]
34061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
34063#[cfg_attr(
34064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34065    assert_instr(umull, LANE = 1)
34066)]
34067#[rustc_legacy_const_generics(2)]
34068#[cfg_attr(
34069    not(target_arch = "arm"),
34070    stable(feature = "neon_intrinsics", since = "1.59.0")
34071)]
34072#[cfg_attr(
34073    target_arch = "arm",
34074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34075)]
34076pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
34077    static_assert_uimm_bits!(LANE, 2);
34078    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
34079}
34080#[doc = "Vector long multiply with scalar"]
34081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
34082#[inline]
34083#[target_feature(enable = "neon")]
34084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34086#[cfg_attr(
34087    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34088    assert_instr(smull)
34089)]
34090#[cfg_attr(
34091    not(target_arch = "arm"),
34092    stable(feature = "neon_intrinsics", since = "1.59.0")
34093)]
34094#[cfg_attr(
34095    target_arch = "arm",
34096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34097)]
34098pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
34099    vmull_s16(a, vdup_n_s16(b))
34100}
34101#[doc = "Vector long multiply with scalar"]
34102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
34103#[inline]
34104#[target_feature(enable = "neon")]
34105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34107#[cfg_attr(
34108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34109    assert_instr(smull)
34110)]
34111#[cfg_attr(
34112    not(target_arch = "arm"),
34113    stable(feature = "neon_intrinsics", since = "1.59.0")
34114)]
34115#[cfg_attr(
34116    target_arch = "arm",
34117    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34118)]
34119pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
34120    vmull_s32(a, vdup_n_s32(b))
34121}
34122#[doc = "Vector long multiply with scalar"]
34123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
34124#[inline]
34125#[target_feature(enable = "neon")]
34126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34128#[cfg_attr(
34129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34130    assert_instr(umull)
34131)]
34132#[cfg_attr(
34133    not(target_arch = "arm"),
34134    stable(feature = "neon_intrinsics", since = "1.59.0")
34135)]
34136#[cfg_attr(
34137    target_arch = "arm",
34138    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34139)]
34140pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
34141    vmull_u16(a, vdup_n_u16(b))
34142}
34143#[doc = "Vector long multiply with scalar"]
34144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
34145#[inline]
34146#[target_feature(enable = "neon")]
34147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34149#[cfg_attr(
34150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34151    assert_instr(umull)
34152)]
34153#[cfg_attr(
34154    not(target_arch = "arm"),
34155    stable(feature = "neon_intrinsics", since = "1.59.0")
34156)]
34157#[cfg_attr(
34158    target_arch = "arm",
34159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34160)]
34161pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
34162    vmull_u32(a, vdup_n_u32(b))
34163}
34164#[doc = "Polynomial multiply long"]
34165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
34166#[inline]
34167#[target_feature(enable = "neon")]
34168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34169#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
34170#[cfg_attr(
34171    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34172    assert_instr(pmull)
34173)]
34174#[cfg_attr(
34175    not(target_arch = "arm"),
34176    stable(feature = "neon_intrinsics", since = "1.59.0")
34177)]
34178#[cfg_attr(
34179    target_arch = "arm",
34180    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34181)]
34182pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
34183    unsafe extern "unadjusted" {
34184        #[cfg_attr(
34185            any(target_arch = "aarch64", target_arch = "arm64ec"),
34186            link_name = "llvm.aarch64.neon.pmull.v8i16"
34187        )]
34188        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")]
34189        fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t;
34190    }
34191    unsafe { _vmull_p8(a, b) }
34192}
34193#[doc = "Signed multiply long"]
34194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
34195#[inline]
34196#[target_feature(enable = "neon")]
34197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
34199#[cfg_attr(
34200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34201    assert_instr(smull)
34202)]
34203#[cfg_attr(
34204    not(target_arch = "arm"),
34205    stable(feature = "neon_intrinsics", since = "1.59.0")
34206)]
34207#[cfg_attr(
34208    target_arch = "arm",
34209    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34210)]
34211pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
34212    unsafe extern "unadjusted" {
34213        #[cfg_attr(
34214            any(target_arch = "aarch64", target_arch = "arm64ec"),
34215            link_name = "llvm.aarch64.neon.smull.v4i16"
34216        )]
34217        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")]
34218        fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
34219    }
34220    unsafe { _vmull_s16(a, b) }
34221}
34222#[doc = "Signed multiply long"]
34223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
34224#[inline]
34225#[target_feature(enable = "neon")]
34226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
34228#[cfg_attr(
34229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34230    assert_instr(smull)
34231)]
34232#[cfg_attr(
34233    not(target_arch = "arm"),
34234    stable(feature = "neon_intrinsics", since = "1.59.0")
34235)]
34236#[cfg_attr(
34237    target_arch = "arm",
34238    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34239)]
34240pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
34241    unsafe extern "unadjusted" {
34242        #[cfg_attr(
34243            any(target_arch = "aarch64", target_arch = "arm64ec"),
34244            link_name = "llvm.aarch64.neon.smull.v2i32"
34245        )]
34246        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")]
34247        fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
34248    }
34249    unsafe { _vmull_s32(a, b) }
34250}
34251#[doc = "Signed multiply long"]
34252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
34253#[inline]
34254#[target_feature(enable = "neon")]
34255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
34257#[cfg_attr(
34258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34259    assert_instr(smull)
34260)]
34261#[cfg_attr(
34262    not(target_arch = "arm"),
34263    stable(feature = "neon_intrinsics", since = "1.59.0")
34264)]
34265#[cfg_attr(
34266    target_arch = "arm",
34267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34268)]
34269pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
34270    unsafe extern "unadjusted" {
34271        #[cfg_attr(
34272            any(target_arch = "aarch64", target_arch = "arm64ec"),
34273            link_name = "llvm.aarch64.neon.smull.v8i8"
34274        )]
34275        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")]
34276        fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
34277    }
34278    unsafe { _vmull_s8(a, b) }
34279}
34280#[doc = "Unsigned multiply long"]
34281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
34282#[inline]
34283#[target_feature(enable = "neon")]
34284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34285#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
34286#[cfg_attr(
34287    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34288    assert_instr(umull)
34289)]
34290#[cfg_attr(
34291    not(target_arch = "arm"),
34292    stable(feature = "neon_intrinsics", since = "1.59.0")
34293)]
34294#[cfg_attr(
34295    target_arch = "arm",
34296    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34297)]
34298pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
34299    unsafe extern "unadjusted" {
34300        #[cfg_attr(
34301            any(target_arch = "aarch64", target_arch = "arm64ec"),
34302            link_name = "llvm.aarch64.neon.umull.v8i8"
34303        )]
34304        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")]
34305        fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
34306    }
34307    unsafe { _vmull_u8(a, b) }
34308}
34309#[doc = "Unsigned multiply long"]
34310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
34311#[inline]
34312#[target_feature(enable = "neon")]
34313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34314#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
34315#[cfg_attr(
34316    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34317    assert_instr(umull)
34318)]
34319#[cfg_attr(
34320    not(target_arch = "arm"),
34321    stable(feature = "neon_intrinsics", since = "1.59.0")
34322)]
34323#[cfg_attr(
34324    target_arch = "arm",
34325    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34326)]
34327pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
34328    unsafe extern "unadjusted" {
34329        #[cfg_attr(
34330            any(target_arch = "aarch64", target_arch = "arm64ec"),
34331            link_name = "llvm.aarch64.neon.umull.v4i16"
34332        )]
34333        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")]
34334        fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
34335    }
34336    unsafe { _vmull_u16(a, b) }
34337}
34338#[doc = "Unsigned multiply long"]
34339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
34340#[inline]
34341#[target_feature(enable = "neon")]
34342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34343#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
34344#[cfg_attr(
34345    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34346    assert_instr(umull)
34347)]
34348#[cfg_attr(
34349    not(target_arch = "arm"),
34350    stable(feature = "neon_intrinsics", since = "1.59.0")
34351)]
34352#[cfg_attr(
34353    target_arch = "arm",
34354    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34355)]
34356pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34357    unsafe extern "unadjusted" {
34358        #[cfg_attr(
34359            any(target_arch = "aarch64", target_arch = "arm64ec"),
34360            link_name = "llvm.aarch64.neon.umull.v2i32"
34361        )]
34362        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")]
34363        fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
34364    }
34365    unsafe { _vmull_u32(a, b) }
34366}
34367#[doc = "Vector bitwise not."]
34368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
34369#[inline]
34370#[target_feature(enable = "neon")]
34371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34373#[cfg_attr(
34374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34375    assert_instr(mvn)
34376)]
34377#[cfg_attr(
34378    not(target_arch = "arm"),
34379    stable(feature = "neon_intrinsics", since = "1.59.0")
34380)]
34381#[cfg_attr(
34382    target_arch = "arm",
34383    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34384)]
34385pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
34386    let b = poly8x8_t::splat(255);
34387    unsafe { simd_xor(a, b) }
34388}
34389#[doc = "Vector bitwise not."]
34390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
34391#[inline]
34392#[target_feature(enable = "neon")]
34393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34395#[cfg_attr(
34396    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34397    assert_instr(mvn)
34398)]
34399#[cfg_attr(
34400    not(target_arch = "arm"),
34401    stable(feature = "neon_intrinsics", since = "1.59.0")
34402)]
34403#[cfg_attr(
34404    target_arch = "arm",
34405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34406)]
34407pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
34408    let b = int16x4_t::splat(-1);
34409    unsafe { simd_xor(a, b) }
34410}
34411#[doc = "Vector bitwise not."]
34412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
34413#[inline]
34414#[target_feature(enable = "neon")]
34415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34417#[cfg_attr(
34418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34419    assert_instr(mvn)
34420)]
34421#[cfg_attr(
34422    not(target_arch = "arm"),
34423    stable(feature = "neon_intrinsics", since = "1.59.0")
34424)]
34425#[cfg_attr(
34426    target_arch = "arm",
34427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34428)]
34429pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
34430    let b = int32x2_t::splat(-1);
34431    unsafe { simd_xor(a, b) }
34432}
34433#[doc = "Vector bitwise not."]
34434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
34435#[inline]
34436#[target_feature(enable = "neon")]
34437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34439#[cfg_attr(
34440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34441    assert_instr(mvn)
34442)]
34443#[cfg_attr(
34444    not(target_arch = "arm"),
34445    stable(feature = "neon_intrinsics", since = "1.59.0")
34446)]
34447#[cfg_attr(
34448    target_arch = "arm",
34449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34450)]
34451pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
34452    let b = int8x8_t::splat(-1);
34453    unsafe { simd_xor(a, b) }
34454}
34455#[doc = "Vector bitwise not."]
34456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
34457#[inline]
34458#[target_feature(enable = "neon")]
34459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34461#[cfg_attr(
34462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34463    assert_instr(mvn)
34464)]
34465#[cfg_attr(
34466    not(target_arch = "arm"),
34467    stable(feature = "neon_intrinsics", since = "1.59.0")
34468)]
34469#[cfg_attr(
34470    target_arch = "arm",
34471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34472)]
34473pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
34474    let b = uint16x4_t::splat(65_535);
34475    unsafe { simd_xor(a, b) }
34476}
34477#[doc = "Vector bitwise not."]
34478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
34479#[inline]
34480#[target_feature(enable = "neon")]
34481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34483#[cfg_attr(
34484    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34485    assert_instr(mvn)
34486)]
34487#[cfg_attr(
34488    not(target_arch = "arm"),
34489    stable(feature = "neon_intrinsics", since = "1.59.0")
34490)]
34491#[cfg_attr(
34492    target_arch = "arm",
34493    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34494)]
34495pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
34496    let b = uint32x2_t::splat(4_294_967_295);
34497    unsafe { simd_xor(a, b) }
34498}
34499#[doc = "Vector bitwise not."]
34500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
34501#[inline]
34502#[target_feature(enable = "neon")]
34503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34505#[cfg_attr(
34506    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34507    assert_instr(mvn)
34508)]
34509#[cfg_attr(
34510    not(target_arch = "arm"),
34511    stable(feature = "neon_intrinsics", since = "1.59.0")
34512)]
34513#[cfg_attr(
34514    target_arch = "arm",
34515    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34516)]
34517pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
34518    let b = uint8x8_t::splat(255);
34519    unsafe { simd_xor(a, b) }
34520}
34521#[doc = "Vector bitwise not."]
34522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
34523#[inline]
34524#[target_feature(enable = "neon")]
34525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34527#[cfg_attr(
34528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34529    assert_instr(mvn)
34530)]
34531#[cfg_attr(
34532    not(target_arch = "arm"),
34533    stable(feature = "neon_intrinsics", since = "1.59.0")
34534)]
34535#[cfg_attr(
34536    target_arch = "arm",
34537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34538)]
34539pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
34540    let b = poly8x16_t::splat(255);
34541    unsafe { simd_xor(a, b) }
34542}
34543#[doc = "Vector bitwise not."]
34544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
34545#[inline]
34546#[target_feature(enable = "neon")]
34547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34549#[cfg_attr(
34550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34551    assert_instr(mvn)
34552)]
34553#[cfg_attr(
34554    not(target_arch = "arm"),
34555    stable(feature = "neon_intrinsics", since = "1.59.0")
34556)]
34557#[cfg_attr(
34558    target_arch = "arm",
34559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34560)]
34561pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
34562    let b = int16x8_t::splat(-1);
34563    unsafe { simd_xor(a, b) }
34564}
34565#[doc = "Vector bitwise not."]
34566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
34567#[inline]
34568#[target_feature(enable = "neon")]
34569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34571#[cfg_attr(
34572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34573    assert_instr(mvn)
34574)]
34575#[cfg_attr(
34576    not(target_arch = "arm"),
34577    stable(feature = "neon_intrinsics", since = "1.59.0")
34578)]
34579#[cfg_attr(
34580    target_arch = "arm",
34581    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34582)]
34583pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
34584    let b = int32x4_t::splat(-1);
34585    unsafe { simd_xor(a, b) }
34586}
34587#[doc = "Vector bitwise not."]
34588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
34589#[inline]
34590#[target_feature(enable = "neon")]
34591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34593#[cfg_attr(
34594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34595    assert_instr(mvn)
34596)]
34597#[cfg_attr(
34598    not(target_arch = "arm"),
34599    stable(feature = "neon_intrinsics", since = "1.59.0")
34600)]
34601#[cfg_attr(
34602    target_arch = "arm",
34603    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34604)]
34605pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
34606    let b = int8x16_t::splat(-1);
34607    unsafe { simd_xor(a, b) }
34608}
34609#[doc = "Vector bitwise not."]
34610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
34611#[inline]
34612#[target_feature(enable = "neon")]
34613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34615#[cfg_attr(
34616    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34617    assert_instr(mvn)
34618)]
34619#[cfg_attr(
34620    not(target_arch = "arm"),
34621    stable(feature = "neon_intrinsics", since = "1.59.0")
34622)]
34623#[cfg_attr(
34624    target_arch = "arm",
34625    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34626)]
34627pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
34628    let b = uint16x8_t::splat(65_535);
34629    unsafe { simd_xor(a, b) }
34630}
34631#[doc = "Vector bitwise not."]
34632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
34633#[inline]
34634#[target_feature(enable = "neon")]
34635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34637#[cfg_attr(
34638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34639    assert_instr(mvn)
34640)]
34641#[cfg_attr(
34642    not(target_arch = "arm"),
34643    stable(feature = "neon_intrinsics", since = "1.59.0")
34644)]
34645#[cfg_attr(
34646    target_arch = "arm",
34647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34648)]
34649pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
34650    let b = uint32x4_t::splat(4_294_967_295);
34651    unsafe { simd_xor(a, b) }
34652}
34653#[doc = "Vector bitwise not."]
34654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
34655#[inline]
34656#[target_feature(enable = "neon")]
34657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34659#[cfg_attr(
34660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34661    assert_instr(mvn)
34662)]
34663#[cfg_attr(
34664    not(target_arch = "arm"),
34665    stable(feature = "neon_intrinsics", since = "1.59.0")
34666)]
34667#[cfg_attr(
34668    target_arch = "arm",
34669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34670)]
34671pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
34672    let b = uint8x16_t::splat(255);
34673    unsafe { simd_xor(a, b) }
34674}
34675#[doc = "Negate"]
34676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
34677#[inline]
34678#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34679#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34680#[cfg_attr(
34681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34682    assert_instr(fneg)
34683)]
34684#[target_feature(enable = "neon,fp16")]
34685#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34686pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
34687    unsafe { simd_neg(a) }
34688}
34689#[doc = "Negate"]
34690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
34691#[inline]
34692#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34693#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34694#[cfg_attr(
34695    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34696    assert_instr(fneg)
34697)]
34698#[target_feature(enable = "neon,fp16")]
34699#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34700pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
34701    unsafe { simd_neg(a) }
34702}
34703#[doc = "Negate"]
34704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
34705#[inline]
34706#[target_feature(enable = "neon")]
34707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34708#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34709#[cfg_attr(
34710    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34711    assert_instr(fneg)
34712)]
34713#[cfg_attr(
34714    not(target_arch = "arm"),
34715    stable(feature = "neon_intrinsics", since = "1.59.0")
34716)]
34717#[cfg_attr(
34718    target_arch = "arm",
34719    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34720)]
34721pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
34722    unsafe { simd_neg(a) }
34723}
34724#[doc = "Negate"]
34725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
34726#[inline]
34727#[target_feature(enable = "neon")]
34728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34729#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34730#[cfg_attr(
34731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34732    assert_instr(fneg)
34733)]
34734#[cfg_attr(
34735    not(target_arch = "arm"),
34736    stable(feature = "neon_intrinsics", since = "1.59.0")
34737)]
34738#[cfg_attr(
34739    target_arch = "arm",
34740    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34741)]
34742pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
34743    unsafe { simd_neg(a) }
34744}
34745#[doc = "Negate"]
34746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
34747#[inline]
34748#[target_feature(enable = "neon")]
34749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34750#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34751#[cfg_attr(
34752    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34753    assert_instr(neg)
34754)]
34755#[cfg_attr(
34756    not(target_arch = "arm"),
34757    stable(feature = "neon_intrinsics", since = "1.59.0")
34758)]
34759#[cfg_attr(
34760    target_arch = "arm",
34761    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34762)]
34763pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
34764    unsafe { simd_neg(a) }
34765}
34766#[doc = "Negate"]
34767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
34768#[inline]
34769#[target_feature(enable = "neon")]
34770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34771#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34772#[cfg_attr(
34773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34774    assert_instr(neg)
34775)]
34776#[cfg_attr(
34777    not(target_arch = "arm"),
34778    stable(feature = "neon_intrinsics", since = "1.59.0")
34779)]
34780#[cfg_attr(
34781    target_arch = "arm",
34782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34783)]
34784pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
34785    unsafe { simd_neg(a) }
34786}
34787#[doc = "Negate"]
34788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
34789#[inline]
34790#[target_feature(enable = "neon")]
34791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34792#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34793#[cfg_attr(
34794    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34795    assert_instr(neg)
34796)]
34797#[cfg_attr(
34798    not(target_arch = "arm"),
34799    stable(feature = "neon_intrinsics", since = "1.59.0")
34800)]
34801#[cfg_attr(
34802    target_arch = "arm",
34803    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34804)]
34805pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
34806    unsafe { simd_neg(a) }
34807}
34808#[doc = "Negate"]
34809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
34810#[inline]
34811#[target_feature(enable = "neon")]
34812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34813#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34814#[cfg_attr(
34815    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34816    assert_instr(neg)
34817)]
34818#[cfg_attr(
34819    not(target_arch = "arm"),
34820    stable(feature = "neon_intrinsics", since = "1.59.0")
34821)]
34822#[cfg_attr(
34823    target_arch = "arm",
34824    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34825)]
34826pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
34827    unsafe { simd_neg(a) }
34828}
34829#[doc = "Negate"]
34830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
34831#[inline]
34832#[target_feature(enable = "neon")]
34833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34835#[cfg_attr(
34836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34837    assert_instr(neg)
34838)]
34839#[cfg_attr(
34840    not(target_arch = "arm"),
34841    stable(feature = "neon_intrinsics", since = "1.59.0")
34842)]
34843#[cfg_attr(
34844    target_arch = "arm",
34845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34846)]
34847pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
34848    unsafe { simd_neg(a) }
34849}
34850#[doc = "Negate"]
34851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
34852#[inline]
34853#[target_feature(enable = "neon")]
34854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34855#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34856#[cfg_attr(
34857    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34858    assert_instr(neg)
34859)]
34860#[cfg_attr(
34861    not(target_arch = "arm"),
34862    stable(feature = "neon_intrinsics", since = "1.59.0")
34863)]
34864#[cfg_attr(
34865    target_arch = "arm",
34866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34867)]
34868pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
34869    unsafe { simd_neg(a) }
34870}
34871#[doc = "Vector bitwise inclusive OR NOT"]
34872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
34873#[inline]
34874#[target_feature(enable = "neon")]
34875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34877#[cfg_attr(
34878    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34879    assert_instr(orn)
34880)]
34881#[cfg_attr(
34882    not(target_arch = "arm"),
34883    stable(feature = "neon_intrinsics", since = "1.59.0")
34884)]
34885#[cfg_attr(
34886    target_arch = "arm",
34887    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34888)]
34889pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
34890    let c = int16x4_t::splat(-1);
34891    unsafe { simd_or(simd_xor(b, c), a) }
34892}
34893#[doc = "Vector bitwise inclusive OR NOT"]
34894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
34895#[inline]
34896#[target_feature(enable = "neon")]
34897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34899#[cfg_attr(
34900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34901    assert_instr(orn)
34902)]
34903#[cfg_attr(
34904    not(target_arch = "arm"),
34905    stable(feature = "neon_intrinsics", since = "1.59.0")
34906)]
34907#[cfg_attr(
34908    target_arch = "arm",
34909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34910)]
34911pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
34912    let c = int32x2_t::splat(-1);
34913    unsafe { simd_or(simd_xor(b, c), a) }
34914}
34915#[doc = "Vector bitwise inclusive OR NOT"]
34916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
34917#[inline]
34918#[target_feature(enable = "neon")]
34919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34921#[cfg_attr(
34922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34923    assert_instr(orn)
34924)]
34925#[cfg_attr(
34926    not(target_arch = "arm"),
34927    stable(feature = "neon_intrinsics", since = "1.59.0")
34928)]
34929#[cfg_attr(
34930    target_arch = "arm",
34931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34932)]
34933pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
34934    let c = int64x1_t::splat(-1);
34935    unsafe { simd_or(simd_xor(b, c), a) }
34936}
34937#[doc = "Vector bitwise inclusive OR NOT"]
34938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
34939#[inline]
34940#[target_feature(enable = "neon")]
34941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34943#[cfg_attr(
34944    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34945    assert_instr(orn)
34946)]
34947#[cfg_attr(
34948    not(target_arch = "arm"),
34949    stable(feature = "neon_intrinsics", since = "1.59.0")
34950)]
34951#[cfg_attr(
34952    target_arch = "arm",
34953    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34954)]
34955pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
34956    let c = int8x8_t::splat(-1);
34957    unsafe { simd_or(simd_xor(b, c), a) }
34958}
34959#[doc = "Vector bitwise inclusive OR NOT"]
34960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
34961#[inline]
34962#[target_feature(enable = "neon")]
34963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34965#[cfg_attr(
34966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34967    assert_instr(orn)
34968)]
34969#[cfg_attr(
34970    not(target_arch = "arm"),
34971    stable(feature = "neon_intrinsics", since = "1.59.0")
34972)]
34973#[cfg_attr(
34974    target_arch = "arm",
34975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34976)]
34977pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
34978    let c = int16x8_t::splat(-1);
34979    unsafe { simd_or(simd_xor(b, c), a) }
34980}
34981#[doc = "Vector bitwise inclusive OR NOT"]
34982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
34983#[inline]
34984#[target_feature(enable = "neon")]
34985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34987#[cfg_attr(
34988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34989    assert_instr(orn)
34990)]
34991#[cfg_attr(
34992    not(target_arch = "arm"),
34993    stable(feature = "neon_intrinsics", since = "1.59.0")
34994)]
34995#[cfg_attr(
34996    target_arch = "arm",
34997    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34998)]
34999pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35000    let c = int32x4_t::splat(-1);
35001    unsafe { simd_or(simd_xor(b, c), a) }
35002}
35003#[doc = "Vector bitwise inclusive OR NOT"]
35004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
35005#[inline]
35006#[target_feature(enable = "neon")]
35007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35009#[cfg_attr(
35010    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35011    assert_instr(orn)
35012)]
35013#[cfg_attr(
35014    not(target_arch = "arm"),
35015    stable(feature = "neon_intrinsics", since = "1.59.0")
35016)]
35017#[cfg_attr(
35018    target_arch = "arm",
35019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35020)]
35021pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35022    let c = int64x2_t::splat(-1);
35023    unsafe { simd_or(simd_xor(b, c), a) }
35024}
35025#[doc = "Vector bitwise inclusive OR NOT"]
35026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
35027#[inline]
35028#[target_feature(enable = "neon")]
35029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35030#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35031#[cfg_attr(
35032    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35033    assert_instr(orn)
35034)]
35035#[cfg_attr(
35036    not(target_arch = "arm"),
35037    stable(feature = "neon_intrinsics", since = "1.59.0")
35038)]
35039#[cfg_attr(
35040    target_arch = "arm",
35041    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35042)]
35043pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35044    let c = int8x16_t::splat(-1);
35045    unsafe { simd_or(simd_xor(b, c), a) }
35046}
35047#[doc = "Vector bitwise inclusive OR NOT"]
35048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
35049#[inline]
35050#[target_feature(enable = "neon")]
35051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35053#[cfg_attr(
35054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35055    assert_instr(orn)
35056)]
35057#[cfg_attr(
35058    not(target_arch = "arm"),
35059    stable(feature = "neon_intrinsics", since = "1.59.0")
35060)]
35061#[cfg_attr(
35062    target_arch = "arm",
35063    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35064)]
35065pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35066    let c = int16x4_t::splat(-1);
35067    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35068}
35069#[doc = "Vector bitwise inclusive OR NOT"]
35070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
35071#[inline]
35072#[target_feature(enable = "neon")]
35073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35075#[cfg_attr(
35076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35077    assert_instr(orn)
35078)]
35079#[cfg_attr(
35080    not(target_arch = "arm"),
35081    stable(feature = "neon_intrinsics", since = "1.59.0")
35082)]
35083#[cfg_attr(
35084    target_arch = "arm",
35085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35086)]
35087pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35088    let c = int32x2_t::splat(-1);
35089    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35090}
35091#[doc = "Vector bitwise inclusive OR NOT"]
35092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
35093#[inline]
35094#[target_feature(enable = "neon")]
35095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35097#[cfg_attr(
35098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35099    assert_instr(orn)
35100)]
35101#[cfg_attr(
35102    not(target_arch = "arm"),
35103    stable(feature = "neon_intrinsics", since = "1.59.0")
35104)]
35105#[cfg_attr(
35106    target_arch = "arm",
35107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35108)]
35109pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35110    let c = int64x1_t::splat(-1);
35111    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35112}
35113#[doc = "Vector bitwise inclusive OR NOT"]
35114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
35115#[inline]
35116#[target_feature(enable = "neon")]
35117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35119#[cfg_attr(
35120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35121    assert_instr(orn)
35122)]
35123#[cfg_attr(
35124    not(target_arch = "arm"),
35125    stable(feature = "neon_intrinsics", since = "1.59.0")
35126)]
35127#[cfg_attr(
35128    target_arch = "arm",
35129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35130)]
35131pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35132    let c = int8x8_t::splat(-1);
35133    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35134}
35135#[doc = "Vector bitwise inclusive OR NOT"]
35136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
35137#[inline]
35138#[target_feature(enable = "neon")]
35139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35141#[cfg_attr(
35142    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35143    assert_instr(orn)
35144)]
35145#[cfg_attr(
35146    not(target_arch = "arm"),
35147    stable(feature = "neon_intrinsics", since = "1.59.0")
35148)]
35149#[cfg_attr(
35150    target_arch = "arm",
35151    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35152)]
35153pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35154    let c = int16x8_t::splat(-1);
35155    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35156}
35157#[doc = "Vector bitwise inclusive OR NOT"]
35158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
35159#[inline]
35160#[target_feature(enable = "neon")]
35161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35163#[cfg_attr(
35164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35165    assert_instr(orn)
35166)]
35167#[cfg_attr(
35168    not(target_arch = "arm"),
35169    stable(feature = "neon_intrinsics", since = "1.59.0")
35170)]
35171#[cfg_attr(
35172    target_arch = "arm",
35173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35174)]
35175pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35176    let c = int32x4_t::splat(-1);
35177    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35178}
35179#[doc = "Vector bitwise inclusive OR NOT"]
35180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
35181#[inline]
35182#[target_feature(enable = "neon")]
35183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35185#[cfg_attr(
35186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35187    assert_instr(orn)
35188)]
35189#[cfg_attr(
35190    not(target_arch = "arm"),
35191    stable(feature = "neon_intrinsics", since = "1.59.0")
35192)]
35193#[cfg_attr(
35194    target_arch = "arm",
35195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35196)]
35197pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35198    let c = int64x2_t::splat(-1);
35199    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35200}
35201#[doc = "Vector bitwise inclusive OR NOT"]
35202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
35203#[inline]
35204#[target_feature(enable = "neon")]
35205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35207#[cfg_attr(
35208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35209    assert_instr(orn)
35210)]
35211#[cfg_attr(
35212    not(target_arch = "arm"),
35213    stable(feature = "neon_intrinsics", since = "1.59.0")
35214)]
35215#[cfg_attr(
35216    target_arch = "arm",
35217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35218)]
35219pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35220    let c = int8x16_t::splat(-1);
35221    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35222}
35223#[doc = "Vector bitwise or (immediate, inclusive)"]
35224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
35225#[inline]
35226#[target_feature(enable = "neon")]
35227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35229#[cfg_attr(
35230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35231    assert_instr(orr)
35232)]
35233#[cfg_attr(
35234    not(target_arch = "arm"),
35235    stable(feature = "neon_intrinsics", since = "1.59.0")
35236)]
35237#[cfg_attr(
35238    target_arch = "arm",
35239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35240)]
35241pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35242    unsafe { simd_or(a, b) }
35243}
35244#[doc = "Vector bitwise or (immediate, inclusive)"]
35245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
35246#[inline]
35247#[target_feature(enable = "neon")]
35248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35249#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35250#[cfg_attr(
35251    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35252    assert_instr(orr)
35253)]
35254#[cfg_attr(
35255    not(target_arch = "arm"),
35256    stable(feature = "neon_intrinsics", since = "1.59.0")
35257)]
35258#[cfg_attr(
35259    target_arch = "arm",
35260    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35261)]
35262pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35263    unsafe { simd_or(a, b) }
35264}
35265#[doc = "Vector bitwise or (immediate, inclusive)"]
35266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
35267#[inline]
35268#[target_feature(enable = "neon")]
35269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35271#[cfg_attr(
35272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35273    assert_instr(orr)
35274)]
35275#[cfg_attr(
35276    not(target_arch = "arm"),
35277    stable(feature = "neon_intrinsics", since = "1.59.0")
35278)]
35279#[cfg_attr(
35280    target_arch = "arm",
35281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35282)]
35283pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35284    unsafe { simd_or(a, b) }
35285}
35286#[doc = "Vector bitwise or (immediate, inclusive)"]
35287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
35288#[inline]
35289#[target_feature(enable = "neon")]
35290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35292#[cfg_attr(
35293    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35294    assert_instr(orr)
35295)]
35296#[cfg_attr(
35297    not(target_arch = "arm"),
35298    stable(feature = "neon_intrinsics", since = "1.59.0")
35299)]
35300#[cfg_attr(
35301    target_arch = "arm",
35302    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35303)]
35304pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
35305    unsafe { simd_or(a, b) }
35306}
35307#[doc = "Vector bitwise or (immediate, inclusive)"]
35308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
35309#[inline]
35310#[target_feature(enable = "neon")]
35311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35313#[cfg_attr(
35314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35315    assert_instr(orr)
35316)]
35317#[cfg_attr(
35318    not(target_arch = "arm"),
35319    stable(feature = "neon_intrinsics", since = "1.59.0")
35320)]
35321#[cfg_attr(
35322    target_arch = "arm",
35323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35324)]
35325pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35326    unsafe { simd_or(a, b) }
35327}
35328#[doc = "Vector bitwise or (immediate, inclusive)"]
35329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
35330#[inline]
35331#[target_feature(enable = "neon")]
35332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35334#[cfg_attr(
35335    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35336    assert_instr(orr)
35337)]
35338#[cfg_attr(
35339    not(target_arch = "arm"),
35340    stable(feature = "neon_intrinsics", since = "1.59.0")
35341)]
35342#[cfg_attr(
35343    target_arch = "arm",
35344    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35345)]
35346pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35347    unsafe { simd_or(a, b) }
35348}
35349#[doc = "Vector bitwise or (immediate, inclusive)"]
35350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
35351#[inline]
35352#[target_feature(enable = "neon")]
35353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35355#[cfg_attr(
35356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35357    assert_instr(orr)
35358)]
35359#[cfg_attr(
35360    not(target_arch = "arm"),
35361    stable(feature = "neon_intrinsics", since = "1.59.0")
35362)]
35363#[cfg_attr(
35364    target_arch = "arm",
35365    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35366)]
35367pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
35368    unsafe { simd_or(a, b) }
35369}
35370#[doc = "Vector bitwise or (immediate, inclusive)"]
35371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
35372#[inline]
35373#[target_feature(enable = "neon")]
35374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35376#[cfg_attr(
35377    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35378    assert_instr(orr)
35379)]
35380#[cfg_attr(
35381    not(target_arch = "arm"),
35382    stable(feature = "neon_intrinsics", since = "1.59.0")
35383)]
35384#[cfg_attr(
35385    target_arch = "arm",
35386    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35387)]
35388pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35389    unsafe { simd_or(a, b) }
35390}
35391#[doc = "Vector bitwise or (immediate, inclusive)"]
35392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
35393#[inline]
35394#[target_feature(enable = "neon")]
35395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35397#[cfg_attr(
35398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35399    assert_instr(orr)
35400)]
35401#[cfg_attr(
35402    not(target_arch = "arm"),
35403    stable(feature = "neon_intrinsics", since = "1.59.0")
35404)]
35405#[cfg_attr(
35406    target_arch = "arm",
35407    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35408)]
35409pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35410    unsafe { simd_or(a, b) }
35411}
35412#[doc = "Vector bitwise or (immediate, inclusive)"]
35413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
35414#[inline]
35415#[target_feature(enable = "neon")]
35416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35418#[cfg_attr(
35419    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35420    assert_instr(orr)
35421)]
35422#[cfg_attr(
35423    not(target_arch = "arm"),
35424    stable(feature = "neon_intrinsics", since = "1.59.0")
35425)]
35426#[cfg_attr(
35427    target_arch = "arm",
35428    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35429)]
35430pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35431    unsafe { simd_or(a, b) }
35432}
35433#[doc = "Vector bitwise or (immediate, inclusive)"]
35434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
35435#[inline]
35436#[target_feature(enable = "neon")]
35437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35439#[cfg_attr(
35440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35441    assert_instr(orr)
35442)]
35443#[cfg_attr(
35444    not(target_arch = "arm"),
35445    stable(feature = "neon_intrinsics", since = "1.59.0")
35446)]
35447#[cfg_attr(
35448    target_arch = "arm",
35449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35450)]
35451pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35452    unsafe { simd_or(a, b) }
35453}
35454#[doc = "Vector bitwise or (immediate, inclusive)"]
35455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
35456#[inline]
35457#[target_feature(enable = "neon")]
35458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35460#[cfg_attr(
35461    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35462    assert_instr(orr)
35463)]
35464#[cfg_attr(
35465    not(target_arch = "arm"),
35466    stable(feature = "neon_intrinsics", since = "1.59.0")
35467)]
35468#[cfg_attr(
35469    target_arch = "arm",
35470    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35471)]
35472pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35473    unsafe { simd_or(a, b) }
35474}
35475#[doc = "Vector bitwise or (immediate, inclusive)"]
35476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
35477#[inline]
35478#[target_feature(enable = "neon")]
35479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35481#[cfg_attr(
35482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35483    assert_instr(orr)
35484)]
35485#[cfg_attr(
35486    not(target_arch = "arm"),
35487    stable(feature = "neon_intrinsics", since = "1.59.0")
35488)]
35489#[cfg_attr(
35490    target_arch = "arm",
35491    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35492)]
35493pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35494    unsafe { simd_or(a, b) }
35495}
35496#[doc = "Vector bitwise or (immediate, inclusive)"]
35497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
35498#[inline]
35499#[target_feature(enable = "neon")]
35500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35502#[cfg_attr(
35503    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35504    assert_instr(orr)
35505)]
35506#[cfg_attr(
35507    not(target_arch = "arm"),
35508    stable(feature = "neon_intrinsics", since = "1.59.0")
35509)]
35510#[cfg_attr(
35511    target_arch = "arm",
35512    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35513)]
35514pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35515    unsafe { simd_or(a, b) }
35516}
35517#[doc = "Vector bitwise or (immediate, inclusive)"]
35518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
35519#[inline]
35520#[target_feature(enable = "neon")]
35521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35523#[cfg_attr(
35524    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35525    assert_instr(orr)
35526)]
35527#[cfg_attr(
35528    not(target_arch = "arm"),
35529    stable(feature = "neon_intrinsics", since = "1.59.0")
35530)]
35531#[cfg_attr(
35532    target_arch = "arm",
35533    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35534)]
35535pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35536    unsafe { simd_or(a, b) }
35537}
35538#[doc = "Vector bitwise or (immediate, inclusive)"]
35539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
35540#[inline]
35541#[target_feature(enable = "neon")]
35542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35544#[cfg_attr(
35545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35546    assert_instr(orr)
35547)]
35548#[cfg_attr(
35549    not(target_arch = "arm"),
35550    stable(feature = "neon_intrinsics", since = "1.59.0")
35551)]
35552#[cfg_attr(
35553    target_arch = "arm",
35554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35555)]
35556pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35557    unsafe { simd_or(a, b) }
35558}
35559#[doc = "Signed Add and Accumulate Long Pairwise."]
35560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
35561#[inline]
35562#[target_feature(enable = "neon")]
35563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35564#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35565#[cfg_attr(
35566    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35567    assert_instr(sadalp)
35568)]
35569#[cfg_attr(
35570    not(target_arch = "arm"),
35571    stable(feature = "neon_intrinsics", since = "1.59.0")
35572)]
35573#[cfg_attr(
35574    target_arch = "arm",
35575    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35576)]
35577pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
35578    let x: int16x4_t;
35579    #[cfg(target_arch = "arm")]
35580    {
35581        x = priv_vpadal_s8(a, b);
35582    }
35583    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35584    unsafe {
35585        x = simd_add(vpaddl_s8(b), a);
35586    };
35587    x
35588}
35589#[doc = "Signed Add and Accumulate Long Pairwise."]
35590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
35591#[inline]
35592#[target_feature(enable = "neon")]
35593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35595#[cfg_attr(
35596    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35597    assert_instr(sadalp)
35598)]
35599#[cfg_attr(
35600    not(target_arch = "arm"),
35601    stable(feature = "neon_intrinsics", since = "1.59.0")
35602)]
35603#[cfg_attr(
35604    target_arch = "arm",
35605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35606)]
35607pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
35608    let x: int16x8_t;
35609    #[cfg(target_arch = "arm")]
35610    {
35611        x = priv_vpadalq_s8(a, b);
35612    }
35613    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35614    unsafe {
35615        x = simd_add(vpaddlq_s8(b), a);
35616    };
35617    x
35618}
35619#[doc = "Signed Add and Accumulate Long Pairwise."]
35620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
35621#[inline]
35622#[target_feature(enable = "neon")]
35623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35624#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35625#[cfg_attr(
35626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35627    assert_instr(sadalp)
35628)]
35629#[cfg_attr(
35630    not(target_arch = "arm"),
35631    stable(feature = "neon_intrinsics", since = "1.59.0")
35632)]
35633#[cfg_attr(
35634    target_arch = "arm",
35635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35636)]
35637pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
35638    let x: int32x2_t;
35639    #[cfg(target_arch = "arm")]
35640    {
35641        x = priv_vpadal_s16(a, b);
35642    }
35643    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35644    unsafe {
35645        x = simd_add(vpaddl_s16(b), a);
35646    };
35647    x
35648}
35649#[doc = "Signed Add and Accumulate Long Pairwise."]
35650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
35651#[inline]
35652#[target_feature(enable = "neon")]
35653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35655#[cfg_attr(
35656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35657    assert_instr(sadalp)
35658)]
35659#[cfg_attr(
35660    not(target_arch = "arm"),
35661    stable(feature = "neon_intrinsics", since = "1.59.0")
35662)]
35663#[cfg_attr(
35664    target_arch = "arm",
35665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35666)]
35667pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
35668    let x: int32x4_t;
35669    #[cfg(target_arch = "arm")]
35670    {
35671        x = priv_vpadalq_s16(a, b);
35672    }
35673    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35674    unsafe {
35675        x = simd_add(vpaddlq_s16(b), a);
35676    };
35677    x
35678}
35679#[doc = "Signed Add and Accumulate Long Pairwise."]
35680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
35681#[inline]
35682#[target_feature(enable = "neon")]
35683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35684#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35685#[cfg_attr(
35686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35687    assert_instr(sadalp)
35688)]
35689#[cfg_attr(
35690    not(target_arch = "arm"),
35691    stable(feature = "neon_intrinsics", since = "1.59.0")
35692)]
35693#[cfg_attr(
35694    target_arch = "arm",
35695    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35696)]
35697pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
35698    let x: int64x1_t;
35699    #[cfg(target_arch = "arm")]
35700    {
35701        x = priv_vpadal_s32(a, b);
35702    }
35703    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35704    unsafe {
35705        x = simd_add(vpaddl_s32(b), a);
35706    };
35707    x
35708}
35709#[doc = "Signed Add and Accumulate Long Pairwise."]
35710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
35711#[inline]
35712#[target_feature(enable = "neon")]
35713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35714#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35715#[cfg_attr(
35716    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35717    assert_instr(sadalp)
35718)]
35719#[cfg_attr(
35720    not(target_arch = "arm"),
35721    stable(feature = "neon_intrinsics", since = "1.59.0")
35722)]
35723#[cfg_attr(
35724    target_arch = "arm",
35725    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35726)]
35727pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
35728    let x: int64x2_t;
35729    #[cfg(target_arch = "arm")]
35730    {
35731        x = priv_vpadalq_s32(a, b);
35732    }
35733    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35734    unsafe {
35735        x = simd_add(vpaddlq_s32(b), a);
35736    };
35737    x
35738}
35739#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
35741#[inline]
35742#[target_feature(enable = "neon")]
35743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35745#[cfg_attr(
35746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35747    assert_instr(uadalp)
35748)]
35749#[cfg_attr(
35750    not(target_arch = "arm"),
35751    stable(feature = "neon_intrinsics", since = "1.59.0")
35752)]
35753#[cfg_attr(
35754    target_arch = "arm",
35755    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35756)]
35757pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
35758    let x: uint16x4_t;
35759    #[cfg(target_arch = "arm")]
35760    {
35761        x = priv_vpadal_u8(a, b);
35762    }
35763    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35764    unsafe {
35765        x = simd_add(vpaddl_u8(b), a);
35766    };
35767    x
35768}
35769#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
35771#[inline]
35772#[target_feature(enable = "neon")]
35773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35774#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35775#[cfg_attr(
35776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35777    assert_instr(uadalp)
35778)]
35779#[cfg_attr(
35780    not(target_arch = "arm"),
35781    stable(feature = "neon_intrinsics", since = "1.59.0")
35782)]
35783#[cfg_attr(
35784    target_arch = "arm",
35785    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35786)]
35787pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
35788    let x: uint16x8_t;
35789    #[cfg(target_arch = "arm")]
35790    {
35791        x = priv_vpadalq_u8(a, b);
35792    }
35793    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35794    unsafe {
35795        x = simd_add(vpaddlq_u8(b), a);
35796    };
35797    x
35798}
35799#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
35801#[inline]
35802#[target_feature(enable = "neon")]
35803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35805#[cfg_attr(
35806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35807    assert_instr(uadalp)
35808)]
35809#[cfg_attr(
35810    not(target_arch = "arm"),
35811    stable(feature = "neon_intrinsics", since = "1.59.0")
35812)]
35813#[cfg_attr(
35814    target_arch = "arm",
35815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35816)]
35817pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
35818    let x: uint32x2_t;
35819    #[cfg(target_arch = "arm")]
35820    {
35821        x = priv_vpadal_u16(a, b);
35822    }
35823    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35824    unsafe {
35825        x = simd_add(vpaddl_u16(b), a);
35826    };
35827    x
35828}
35829#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
35831#[inline]
35832#[target_feature(enable = "neon")]
35833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35835#[cfg_attr(
35836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35837    assert_instr(uadalp)
35838)]
35839#[cfg_attr(
35840    not(target_arch = "arm"),
35841    stable(feature = "neon_intrinsics", since = "1.59.0")
35842)]
35843#[cfg_attr(
35844    target_arch = "arm",
35845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35846)]
35847pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
35848    let x: uint32x4_t;
35849    #[cfg(target_arch = "arm")]
35850    {
35851        x = priv_vpadalq_u16(a, b);
35852    }
35853    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35854    unsafe {
35855        x = simd_add(vpaddlq_u16(b), a);
35856    };
35857    x
35858}
35859#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
35861#[inline]
35862#[target_feature(enable = "neon")]
35863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35865#[cfg_attr(
35866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35867    assert_instr(uadalp)
35868)]
35869#[cfg_attr(
35870    not(target_arch = "arm"),
35871    stable(feature = "neon_intrinsics", since = "1.59.0")
35872)]
35873#[cfg_attr(
35874    target_arch = "arm",
35875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35876)]
35877pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
35878    let x: uint64x1_t;
35879    #[cfg(target_arch = "arm")]
35880    {
35881        x = priv_vpadal_u32(a, b);
35882    }
35883    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35884    unsafe {
35885        x = simd_add(vpaddl_u32(b), a);
35886    };
35887    x
35888}
35889#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
35891#[inline]
35892#[target_feature(enable = "neon")]
35893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35895#[cfg_attr(
35896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35897    assert_instr(uadalp)
35898)]
35899#[cfg_attr(
35900    not(target_arch = "arm"),
35901    stable(feature = "neon_intrinsics", since = "1.59.0")
35902)]
35903#[cfg_attr(
35904    target_arch = "arm",
35905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35906)]
35907pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
35908    let x: uint64x2_t;
35909    #[cfg(target_arch = "arm")]
35910    {
35911        x = priv_vpadalq_u32(a, b);
35912    }
35913    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35914    unsafe {
35915        x = simd_add(vpaddlq_u32(b), a);
35916    };
35917    x
35918}
35919#[doc = "Floating-point add pairwise"]
35920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
35921#[inline]
35922#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35924#[cfg_attr(
35925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35926    assert_instr(faddp)
35927)]
35928#[target_feature(enable = "neon,fp16")]
35929#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35930pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
35931    unsafe extern "unadjusted" {
35932        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")]
35933        #[cfg_attr(
35934            any(target_arch = "aarch64", target_arch = "arm64ec"),
35935            link_name = "llvm.aarch64.neon.faddp.v4f16"
35936        )]
35937        fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
35938    }
35939    unsafe { _vpadd_f16(a, b) }
35940}
35941#[doc = "Floating-point add pairwise"]
35942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
35943#[inline]
35944#[target_feature(enable = "neon")]
35945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35947#[cfg_attr(
35948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35949    assert_instr(faddp)
35950)]
35951#[cfg_attr(
35952    not(target_arch = "arm"),
35953    stable(feature = "neon_intrinsics", since = "1.59.0")
35954)]
35955#[cfg_attr(
35956    target_arch = "arm",
35957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35958)]
35959pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
35960    unsafe extern "unadjusted" {
35961        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")]
35962        #[cfg_attr(
35963            any(target_arch = "aarch64", target_arch = "arm64ec"),
35964            link_name = "llvm.aarch64.neon.faddp.v2f32"
35965        )]
35966        fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
35967    }
35968    unsafe { _vpadd_f32(a, b) }
35969}
35970#[doc = "Add pairwise."]
35971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
35972#[inline]
35973#[target_feature(enable = "neon")]
35974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35976#[cfg_attr(
35977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35978    assert_instr(addp)
35979)]
35980#[cfg_attr(
35981    not(target_arch = "arm"),
35982    stable(feature = "neon_intrinsics", since = "1.59.0")
35983)]
35984#[cfg_attr(
35985    target_arch = "arm",
35986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35987)]
35988pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35989    unsafe extern "unadjusted" {
35990        #[cfg_attr(
35991            any(target_arch = "aarch64", target_arch = "arm64ec"),
35992            link_name = "llvm.aarch64.neon.addp.v8i8"
35993        )]
35994        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
35995        fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
35996    }
35997    unsafe { _vpadd_s8(a, b) }
35998}
35999#[doc = "Add pairwise."]
36000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
36001#[inline]
36002#[target_feature(enable = "neon")]
36003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36005#[cfg_attr(
36006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36007    assert_instr(addp)
36008)]
36009#[cfg_attr(
36010    not(target_arch = "arm"),
36011    stable(feature = "neon_intrinsics", since = "1.59.0")
36012)]
36013#[cfg_attr(
36014    target_arch = "arm",
36015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36016)]
36017pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36018    unsafe extern "unadjusted" {
36019        #[cfg_attr(
36020            any(target_arch = "aarch64", target_arch = "arm64ec"),
36021            link_name = "llvm.aarch64.neon.addp.v4i16"
36022        )]
36023        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
36024        fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36025    }
36026    unsafe { _vpadd_s16(a, b) }
36027}
36028#[doc = "Add pairwise."]
36029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
36030#[inline]
36031#[target_feature(enable = "neon")]
36032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36034#[cfg_attr(
36035    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36036    assert_instr(addp)
36037)]
36038#[cfg_attr(
36039    not(target_arch = "arm"),
36040    stable(feature = "neon_intrinsics", since = "1.59.0")
36041)]
36042#[cfg_attr(
36043    target_arch = "arm",
36044    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36045)]
36046pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36047    unsafe extern "unadjusted" {
36048        #[cfg_attr(
36049            any(target_arch = "aarch64", target_arch = "arm64ec"),
36050            link_name = "llvm.aarch64.neon.addp.v2i32"
36051        )]
36052        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
36053        fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36054    }
36055    unsafe { _vpadd_s32(a, b) }
36056}
36057#[doc = "Add pairwise."]
36058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
36059#[inline]
36060#[cfg(target_endian = "little")]
36061#[target_feature(enable = "neon")]
36062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36064#[cfg_attr(
36065    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36066    assert_instr(addp)
36067)]
36068#[cfg_attr(
36069    not(target_arch = "arm"),
36070    stable(feature = "neon_intrinsics", since = "1.59.0")
36071)]
36072#[cfg_attr(
36073    target_arch = "arm",
36074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36075)]
36076pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36077    unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
36078}
36079#[doc = "Add pairwise."]
36080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
36081#[inline]
36082#[cfg(target_endian = "big")]
36083#[target_feature(enable = "neon")]
36084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36086#[cfg_attr(
36087    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36088    assert_instr(addp)
36089)]
36090#[cfg_attr(
36091    not(target_arch = "arm"),
36092    stable(feature = "neon_intrinsics", since = "1.59.0")
36093)]
36094#[cfg_attr(
36095    target_arch = "arm",
36096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36097)]
36098pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36099    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36100    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
36101    unsafe {
36102        let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
36103        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36104    }
36105}
36106#[doc = "Add pairwise."]
36107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36108#[inline]
36109#[cfg(target_endian = "little")]
36110#[target_feature(enable = "neon")]
36111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36113#[cfg_attr(
36114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36115    assert_instr(addp)
36116)]
36117#[cfg_attr(
36118    not(target_arch = "arm"),
36119    stable(feature = "neon_intrinsics", since = "1.59.0")
36120)]
36121#[cfg_attr(
36122    target_arch = "arm",
36123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36124)]
36125pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36126    unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
36127}
36128#[doc = "Add pairwise."]
36129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36130#[inline]
36131#[cfg(target_endian = "big")]
36132#[target_feature(enable = "neon")]
36133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36135#[cfg_attr(
36136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36137    assert_instr(addp)
36138)]
36139#[cfg_attr(
36140    not(target_arch = "arm"),
36141    stable(feature = "neon_intrinsics", since = "1.59.0")
36142)]
36143#[cfg_attr(
36144    target_arch = "arm",
36145    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36146)]
36147pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36148    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36149    let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
36150    unsafe {
36151        let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
36152        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36153    }
36154}
36155#[doc = "Add pairwise."]
36156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36157#[inline]
36158#[cfg(target_endian = "little")]
36159#[target_feature(enable = "neon")]
36160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36162#[cfg_attr(
36163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36164    assert_instr(addp)
36165)]
36166#[cfg_attr(
36167    not(target_arch = "arm"),
36168    stable(feature = "neon_intrinsics", since = "1.59.0")
36169)]
36170#[cfg_attr(
36171    target_arch = "arm",
36172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36173)]
36174pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36175    unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
36176}
36177#[doc = "Add pairwise."]
36178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36179#[inline]
36180#[cfg(target_endian = "big")]
36181#[target_feature(enable = "neon")]
36182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36184#[cfg_attr(
36185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36186    assert_instr(addp)
36187)]
36188#[cfg_attr(
36189    not(target_arch = "arm"),
36190    stable(feature = "neon_intrinsics", since = "1.59.0")
36191)]
36192#[cfg_attr(
36193    target_arch = "arm",
36194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36195)]
36196pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36197    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
36198    let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
36199    unsafe {
36200        let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
36201        simd_shuffle!(ret_val, ret_val, [1, 0])
36202    }
36203}
36204#[doc = "Signed Add and Accumulate Long Pairwise."]
36205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
36206#[inline]
36207#[target_feature(enable = "neon")]
36208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36210#[cfg_attr(
36211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36212    assert_instr(saddlp)
36213)]
36214#[cfg_attr(
36215    not(target_arch = "arm"),
36216    stable(feature = "neon_intrinsics", since = "1.59.0")
36217)]
36218#[cfg_attr(
36219    target_arch = "arm",
36220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36221)]
36222pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
36223    unsafe extern "unadjusted" {
36224        #[cfg_attr(
36225            any(target_arch = "aarch64", target_arch = "arm64ec"),
36226            link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8"
36227        )]
36228        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")]
36229        fn _vpaddl_s8(a: int8x8_t) -> int16x4_t;
36230    }
36231    unsafe { _vpaddl_s8(a) }
36232}
36233#[doc = "Signed Add and Accumulate Long Pairwise."]
36234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
36235#[inline]
36236#[target_feature(enable = "neon")]
36237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36239#[cfg_attr(
36240    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36241    assert_instr(saddlp)
36242)]
36243#[cfg_attr(
36244    not(target_arch = "arm"),
36245    stable(feature = "neon_intrinsics", since = "1.59.0")
36246)]
36247#[cfg_attr(
36248    target_arch = "arm",
36249    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36250)]
36251pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
36252    unsafe extern "unadjusted" {
36253        #[cfg_attr(
36254            any(target_arch = "aarch64", target_arch = "arm64ec"),
36255            link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8"
36256        )]
36257        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")]
36258        fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t;
36259    }
36260    unsafe { _vpaddlq_s8(a) }
36261}
36262#[doc = "Signed Add and Accumulate Long Pairwise."]
36263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
36264#[inline]
36265#[target_feature(enable = "neon")]
36266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36267#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36268#[cfg_attr(
36269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36270    assert_instr(saddlp)
36271)]
36272#[cfg_attr(
36273    not(target_arch = "arm"),
36274    stable(feature = "neon_intrinsics", since = "1.59.0")
36275)]
36276#[cfg_attr(
36277    target_arch = "arm",
36278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36279)]
36280pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
36281    unsafe extern "unadjusted" {
36282        #[cfg_attr(
36283            any(target_arch = "aarch64", target_arch = "arm64ec"),
36284            link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16"
36285        )]
36286        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")]
36287        fn _vpaddl_s16(a: int16x4_t) -> int32x2_t;
36288    }
36289    unsafe { _vpaddl_s16(a) }
36290}
36291#[doc = "Signed Add and Accumulate Long Pairwise."]
36292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
36293#[inline]
36294#[target_feature(enable = "neon")]
36295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36296#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36297#[cfg_attr(
36298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36299    assert_instr(saddlp)
36300)]
36301#[cfg_attr(
36302    not(target_arch = "arm"),
36303    stable(feature = "neon_intrinsics", since = "1.59.0")
36304)]
36305#[cfg_attr(
36306    target_arch = "arm",
36307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36308)]
36309pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
36310    unsafe extern "unadjusted" {
36311        #[cfg_attr(
36312            any(target_arch = "aarch64", target_arch = "arm64ec"),
36313            link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16"
36314        )]
36315        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")]
36316        fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t;
36317    }
36318    unsafe { _vpaddlq_s16(a) }
36319}
36320#[doc = "Signed Add and Accumulate Long Pairwise."]
36321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
36322#[inline]
36323#[target_feature(enable = "neon")]
36324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36325#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36326#[cfg_attr(
36327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36328    assert_instr(saddlp)
36329)]
36330#[cfg_attr(
36331    not(target_arch = "arm"),
36332    stable(feature = "neon_intrinsics", since = "1.59.0")
36333)]
36334#[cfg_attr(
36335    target_arch = "arm",
36336    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36337)]
36338pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
36339    unsafe extern "unadjusted" {
36340        #[cfg_attr(
36341            any(target_arch = "aarch64", target_arch = "arm64ec"),
36342            link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32"
36343        )]
36344        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")]
36345        fn _vpaddl_s32(a: int32x2_t) -> int64x1_t;
36346    }
36347    unsafe { _vpaddl_s32(a) }
36348}
36349#[doc = "Signed Add and Accumulate Long Pairwise."]
36350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
36351#[inline]
36352#[target_feature(enable = "neon")]
36353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36354#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36355#[cfg_attr(
36356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36357    assert_instr(saddlp)
36358)]
36359#[cfg_attr(
36360    not(target_arch = "arm"),
36361    stable(feature = "neon_intrinsics", since = "1.59.0")
36362)]
36363#[cfg_attr(
36364    target_arch = "arm",
36365    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36366)]
36367pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
36368    unsafe extern "unadjusted" {
36369        #[cfg_attr(
36370            any(target_arch = "aarch64", target_arch = "arm64ec"),
36371            link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32"
36372        )]
36373        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")]
36374        fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t;
36375    }
36376    unsafe { _vpaddlq_s32(a) }
36377}
36378#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
36380#[inline]
36381#[target_feature(enable = "neon")]
36382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36383#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36384#[cfg_attr(
36385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36386    assert_instr(uaddlp)
36387)]
36388#[cfg_attr(
36389    not(target_arch = "arm"),
36390    stable(feature = "neon_intrinsics", since = "1.59.0")
36391)]
36392#[cfg_attr(
36393    target_arch = "arm",
36394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36395)]
36396pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
36397    unsafe extern "unadjusted" {
36398        #[cfg_attr(
36399            any(target_arch = "aarch64", target_arch = "arm64ec"),
36400            link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8"
36401        )]
36402        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")]
36403        fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t;
36404    }
36405    unsafe { _vpaddl_u8(a) }
36406}
36407#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
36409#[inline]
36410#[target_feature(enable = "neon")]
36411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36412#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36413#[cfg_attr(
36414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36415    assert_instr(uaddlp)
36416)]
36417#[cfg_attr(
36418    not(target_arch = "arm"),
36419    stable(feature = "neon_intrinsics", since = "1.59.0")
36420)]
36421#[cfg_attr(
36422    target_arch = "arm",
36423    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36424)]
36425pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
36426    unsafe extern "unadjusted" {
36427        #[cfg_attr(
36428            any(target_arch = "aarch64", target_arch = "arm64ec"),
36429            link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8"
36430        )]
36431        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")]
36432        fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t;
36433    }
36434    unsafe { _vpaddlq_u8(a) }
36435}
36436#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
36438#[inline]
36439#[target_feature(enable = "neon")]
36440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36441#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36442#[cfg_attr(
36443    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36444    assert_instr(uaddlp)
36445)]
36446#[cfg_attr(
36447    not(target_arch = "arm"),
36448    stable(feature = "neon_intrinsics", since = "1.59.0")
36449)]
36450#[cfg_attr(
36451    target_arch = "arm",
36452    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36453)]
36454pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
36455    unsafe extern "unadjusted" {
36456        #[cfg_attr(
36457            any(target_arch = "aarch64", target_arch = "arm64ec"),
36458            link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16"
36459        )]
36460        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")]
36461        fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t;
36462    }
36463    unsafe { _vpaddl_u16(a) }
36464}
36465#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
36467#[inline]
36468#[target_feature(enable = "neon")]
36469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36470#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36471#[cfg_attr(
36472    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36473    assert_instr(uaddlp)
36474)]
36475#[cfg_attr(
36476    not(target_arch = "arm"),
36477    stable(feature = "neon_intrinsics", since = "1.59.0")
36478)]
36479#[cfg_attr(
36480    target_arch = "arm",
36481    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36482)]
36483pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
36484    unsafe extern "unadjusted" {
36485        #[cfg_attr(
36486            any(target_arch = "aarch64", target_arch = "arm64ec"),
36487            link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16"
36488        )]
36489        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")]
36490        fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t;
36491    }
36492    unsafe { _vpaddlq_u16(a) }
36493}
36494#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
36496#[inline]
36497#[target_feature(enable = "neon")]
36498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36499#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36500#[cfg_attr(
36501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36502    assert_instr(uaddlp)
36503)]
36504#[cfg_attr(
36505    not(target_arch = "arm"),
36506    stable(feature = "neon_intrinsics", since = "1.59.0")
36507)]
36508#[cfg_attr(
36509    target_arch = "arm",
36510    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36511)]
36512pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
36513    unsafe extern "unadjusted" {
36514        #[cfg_attr(
36515            any(target_arch = "aarch64", target_arch = "arm64ec"),
36516            link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32"
36517        )]
36518        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")]
36519        fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t;
36520    }
36521    unsafe { _vpaddl_u32(a) }
36522}
36523#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
36525#[inline]
36526#[target_feature(enable = "neon")]
36527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36529#[cfg_attr(
36530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36531    assert_instr(uaddlp)
36532)]
36533#[cfg_attr(
36534    not(target_arch = "arm"),
36535    stable(feature = "neon_intrinsics", since = "1.59.0")
36536)]
36537#[cfg_attr(
36538    target_arch = "arm",
36539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36540)]
36541pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
36542    unsafe extern "unadjusted" {
36543        #[cfg_attr(
36544            any(target_arch = "aarch64", target_arch = "arm64ec"),
36545            link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32"
36546        )]
36547        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")]
36548        fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t;
36549    }
36550    unsafe { _vpaddlq_u32(a) }
36551}
36552#[doc = "Folding maximum of adjacent pairs"]
36553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
36554#[inline]
36555#[target_feature(enable = "neon")]
36556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36558#[cfg_attr(
36559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36560    assert_instr(fmaxp)
36561)]
36562#[cfg_attr(
36563    not(target_arch = "arm"),
36564    stable(feature = "neon_intrinsics", since = "1.59.0")
36565)]
36566#[cfg_attr(
36567    target_arch = "arm",
36568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36569)]
36570pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36571    unsafe extern "unadjusted" {
36572        #[cfg_attr(
36573            any(target_arch = "aarch64", target_arch = "arm64ec"),
36574            link_name = "llvm.aarch64.neon.fmaxp.v2f32"
36575        )]
36576        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
36577        fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36578    }
36579    unsafe { _vpmax_f32(a, b) }
36580}
36581#[doc = "Folding maximum of adjacent pairs"]
36582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
36583#[inline]
36584#[target_feature(enable = "neon")]
36585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36587#[cfg_attr(
36588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36589    assert_instr(smaxp)
36590)]
36591#[cfg_attr(
36592    not(target_arch = "arm"),
36593    stable(feature = "neon_intrinsics", since = "1.59.0")
36594)]
36595#[cfg_attr(
36596    target_arch = "arm",
36597    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36598)]
36599pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36600    unsafe extern "unadjusted" {
36601        #[cfg_attr(
36602            any(target_arch = "aarch64", target_arch = "arm64ec"),
36603            link_name = "llvm.aarch64.neon.smaxp.v8i8"
36604        )]
36605        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
36606        fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36607    }
36608    unsafe { _vpmax_s8(a, b) }
36609}
36610#[doc = "Folding maximum of adjacent pairs"]
36611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
36612#[inline]
36613#[target_feature(enable = "neon")]
36614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36616#[cfg_attr(
36617    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36618    assert_instr(smaxp)
36619)]
36620#[cfg_attr(
36621    not(target_arch = "arm"),
36622    stable(feature = "neon_intrinsics", since = "1.59.0")
36623)]
36624#[cfg_attr(
36625    target_arch = "arm",
36626    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36627)]
36628pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36629    unsafe extern "unadjusted" {
36630        #[cfg_attr(
36631            any(target_arch = "aarch64", target_arch = "arm64ec"),
36632            link_name = "llvm.aarch64.neon.smaxp.v4i16"
36633        )]
36634        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
36635        fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36636    }
36637    unsafe { _vpmax_s16(a, b) }
36638}
36639#[doc = "Folding maximum of adjacent pairs"]
36640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
36641#[inline]
36642#[target_feature(enable = "neon")]
36643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36645#[cfg_attr(
36646    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36647    assert_instr(smaxp)
36648)]
36649#[cfg_attr(
36650    not(target_arch = "arm"),
36651    stable(feature = "neon_intrinsics", since = "1.59.0")
36652)]
36653#[cfg_attr(
36654    target_arch = "arm",
36655    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36656)]
36657pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36658    unsafe extern "unadjusted" {
36659        #[cfg_attr(
36660            any(target_arch = "aarch64", target_arch = "arm64ec"),
36661            link_name = "llvm.aarch64.neon.smaxp.v2i32"
36662        )]
36663        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
36664        fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36665    }
36666    unsafe { _vpmax_s32(a, b) }
36667}
36668#[doc = "Folding maximum of adjacent pairs"]
36669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
36670#[inline]
36671#[target_feature(enable = "neon")]
36672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36674#[cfg_attr(
36675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36676    assert_instr(umaxp)
36677)]
36678#[cfg_attr(
36679    not(target_arch = "arm"),
36680    stable(feature = "neon_intrinsics", since = "1.59.0")
36681)]
36682#[cfg_attr(
36683    target_arch = "arm",
36684    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36685)]
36686pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36687    unsafe extern "unadjusted" {
36688        #[cfg_attr(
36689            any(target_arch = "aarch64", target_arch = "arm64ec"),
36690            link_name = "llvm.aarch64.neon.umaxp.v8i8"
36691        )]
36692        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
36693        fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36694    }
36695    unsafe { _vpmax_u8(a, b) }
36696}
36697#[doc = "Folding maximum of adjacent pairs"]
36698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
36699#[inline]
36700#[target_feature(enable = "neon")]
36701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36703#[cfg_attr(
36704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36705    assert_instr(umaxp)
36706)]
36707#[cfg_attr(
36708    not(target_arch = "arm"),
36709    stable(feature = "neon_intrinsics", since = "1.59.0")
36710)]
36711#[cfg_attr(
36712    target_arch = "arm",
36713    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36714)]
36715pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36716    unsafe extern "unadjusted" {
36717        #[cfg_attr(
36718            any(target_arch = "aarch64", target_arch = "arm64ec"),
36719            link_name = "llvm.aarch64.neon.umaxp.v4i16"
36720        )]
36721        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
36722        fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36723    }
36724    unsafe { _vpmax_u16(a, b) }
36725}
36726#[doc = "Folding maximum of adjacent pairs"]
36727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
36728#[inline]
36729#[target_feature(enable = "neon")]
36730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36732#[cfg_attr(
36733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36734    assert_instr(umaxp)
36735)]
36736#[cfg_attr(
36737    not(target_arch = "arm"),
36738    stable(feature = "neon_intrinsics", since = "1.59.0")
36739)]
36740#[cfg_attr(
36741    target_arch = "arm",
36742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36743)]
36744pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36745    unsafe extern "unadjusted" {
36746        #[cfg_attr(
36747            any(target_arch = "aarch64", target_arch = "arm64ec"),
36748            link_name = "llvm.aarch64.neon.umaxp.v2i32"
36749        )]
36750        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
36751        fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36752    }
36753    unsafe { _vpmax_u32(a, b) }
36754}
36755#[doc = "Folding minimum of adjacent pairs"]
36756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
36757#[inline]
36758#[target_feature(enable = "neon")]
36759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36761#[cfg_attr(
36762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36763    assert_instr(fminp)
36764)]
36765#[cfg_attr(
36766    not(target_arch = "arm"),
36767    stable(feature = "neon_intrinsics", since = "1.59.0")
36768)]
36769#[cfg_attr(
36770    target_arch = "arm",
36771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36772)]
36773pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36774    unsafe extern "unadjusted" {
36775        #[cfg_attr(
36776            any(target_arch = "aarch64", target_arch = "arm64ec"),
36777            link_name = "llvm.aarch64.neon.fminp.v2f32"
36778        )]
36779        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
36780        fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36781    }
36782    unsafe { _vpmin_f32(a, b) }
36783}
36784#[doc = "Folding minimum of adjacent pairs"]
36785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
36786#[inline]
36787#[target_feature(enable = "neon")]
36788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36790#[cfg_attr(
36791    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36792    assert_instr(sminp)
36793)]
36794#[cfg_attr(
36795    not(target_arch = "arm"),
36796    stable(feature = "neon_intrinsics", since = "1.59.0")
36797)]
36798#[cfg_attr(
36799    target_arch = "arm",
36800    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36801)]
36802pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36803    unsafe extern "unadjusted" {
36804        #[cfg_attr(
36805            any(target_arch = "aarch64", target_arch = "arm64ec"),
36806            link_name = "llvm.aarch64.neon.sminp.v8i8"
36807        )]
36808        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
36809        fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36810    }
36811    unsafe { _vpmin_s8(a, b) }
36812}
36813#[doc = "Folding minimum of adjacent pairs"]
36814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
36815#[inline]
36816#[target_feature(enable = "neon")]
36817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36819#[cfg_attr(
36820    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36821    assert_instr(sminp)
36822)]
36823#[cfg_attr(
36824    not(target_arch = "arm"),
36825    stable(feature = "neon_intrinsics", since = "1.59.0")
36826)]
36827#[cfg_attr(
36828    target_arch = "arm",
36829    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36830)]
36831pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36832    unsafe extern "unadjusted" {
36833        #[cfg_attr(
36834            any(target_arch = "aarch64", target_arch = "arm64ec"),
36835            link_name = "llvm.aarch64.neon.sminp.v4i16"
36836        )]
36837        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
36838        fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36839    }
36840    unsafe { _vpmin_s16(a, b) }
36841}
36842#[doc = "Folding minimum of adjacent pairs"]
36843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
36844#[inline]
36845#[target_feature(enable = "neon")]
36846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36848#[cfg_attr(
36849    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36850    assert_instr(sminp)
36851)]
36852#[cfg_attr(
36853    not(target_arch = "arm"),
36854    stable(feature = "neon_intrinsics", since = "1.59.0")
36855)]
36856#[cfg_attr(
36857    target_arch = "arm",
36858    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36859)]
36860pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36861    unsafe extern "unadjusted" {
36862        #[cfg_attr(
36863            any(target_arch = "aarch64", target_arch = "arm64ec"),
36864            link_name = "llvm.aarch64.neon.sminp.v2i32"
36865        )]
36866        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
36867        fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36868    }
36869    unsafe { _vpmin_s32(a, b) }
36870}
36871#[doc = "Folding minimum of adjacent pairs"]
36872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
36873#[inline]
36874#[target_feature(enable = "neon")]
36875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36877#[cfg_attr(
36878    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36879    assert_instr(uminp)
36880)]
36881#[cfg_attr(
36882    not(target_arch = "arm"),
36883    stable(feature = "neon_intrinsics", since = "1.59.0")
36884)]
36885#[cfg_attr(
36886    target_arch = "arm",
36887    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36888)]
36889pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36890    unsafe extern "unadjusted" {
36891        #[cfg_attr(
36892            any(target_arch = "aarch64", target_arch = "arm64ec"),
36893            link_name = "llvm.aarch64.neon.uminp.v8i8"
36894        )]
36895        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
36896        fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36897    }
36898    unsafe { _vpmin_u8(a, b) }
36899}
36900#[doc = "Folding minimum of adjacent pairs"]
36901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
36902#[inline]
36903#[target_feature(enable = "neon")]
36904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36906#[cfg_attr(
36907    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36908    assert_instr(uminp)
36909)]
36910#[cfg_attr(
36911    not(target_arch = "arm"),
36912    stable(feature = "neon_intrinsics", since = "1.59.0")
36913)]
36914#[cfg_attr(
36915    target_arch = "arm",
36916    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36917)]
36918pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36919    unsafe extern "unadjusted" {
36920        #[cfg_attr(
36921            any(target_arch = "aarch64", target_arch = "arm64ec"),
36922            link_name = "llvm.aarch64.neon.uminp.v4i16"
36923        )]
36924        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
36925        fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36926    }
36927    unsafe { _vpmin_u16(a, b) }
36928}
36929#[doc = "Folding minimum of adjacent pairs"]
36930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
36931#[inline]
36932#[target_feature(enable = "neon")]
36933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36935#[cfg_attr(
36936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36937    assert_instr(uminp)
36938)]
36939#[cfg_attr(
36940    not(target_arch = "arm"),
36941    stable(feature = "neon_intrinsics", since = "1.59.0")
36942)]
36943#[cfg_attr(
36944    target_arch = "arm",
36945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36946)]
36947pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36948    unsafe extern "unadjusted" {
36949        #[cfg_attr(
36950            any(target_arch = "aarch64", target_arch = "arm64ec"),
36951            link_name = "llvm.aarch64.neon.uminp.v2i32"
36952        )]
36953        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
36954        fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36955    }
36956    unsafe { _vpmin_u32(a, b) }
36957}
36958#[doc = "Signed saturating Absolute value"]
36959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
36960#[inline]
36961#[target_feature(enable = "neon")]
36962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36963#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36964#[cfg_attr(
36965    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36966    assert_instr(sqabs)
36967)]
36968#[cfg_attr(
36969    not(target_arch = "arm"),
36970    stable(feature = "neon_intrinsics", since = "1.59.0")
36971)]
36972#[cfg_attr(
36973    target_arch = "arm",
36974    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36975)]
36976pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
36977    unsafe extern "unadjusted" {
36978        #[cfg_attr(
36979            any(target_arch = "aarch64", target_arch = "arm64ec"),
36980            link_name = "llvm.aarch64.neon.sqabs.v8i8"
36981        )]
36982        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")]
36983        fn _vqabs_s8(a: int8x8_t) -> int8x8_t;
36984    }
36985    unsafe { _vqabs_s8(a) }
36986}
36987#[doc = "Signed saturating Absolute value"]
36988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
36989#[inline]
36990#[target_feature(enable = "neon")]
36991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36992#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36993#[cfg_attr(
36994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36995    assert_instr(sqabs)
36996)]
36997#[cfg_attr(
36998    not(target_arch = "arm"),
36999    stable(feature = "neon_intrinsics", since = "1.59.0")
37000)]
37001#[cfg_attr(
37002    target_arch = "arm",
37003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37004)]
37005pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
37006    unsafe extern "unadjusted" {
37007        #[cfg_attr(
37008            any(target_arch = "aarch64", target_arch = "arm64ec"),
37009            link_name = "llvm.aarch64.neon.sqabs.v16i8"
37010        )]
37011        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")]
37012        fn _vqabsq_s8(a: int8x16_t) -> int8x16_t;
37013    }
37014    unsafe { _vqabsq_s8(a) }
37015}
37016#[doc = "Signed saturating Absolute value"]
37017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
37018#[inline]
37019#[target_feature(enable = "neon")]
37020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37021#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
37022#[cfg_attr(
37023    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37024    assert_instr(sqabs)
37025)]
37026#[cfg_attr(
37027    not(target_arch = "arm"),
37028    stable(feature = "neon_intrinsics", since = "1.59.0")
37029)]
37030#[cfg_attr(
37031    target_arch = "arm",
37032    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37033)]
37034pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
37035    unsafe extern "unadjusted" {
37036        #[cfg_attr(
37037            any(target_arch = "aarch64", target_arch = "arm64ec"),
37038            link_name = "llvm.aarch64.neon.sqabs.v4i16"
37039        )]
37040        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")]
37041        fn _vqabs_s16(a: int16x4_t) -> int16x4_t;
37042    }
37043    unsafe { _vqabs_s16(a) }
37044}
37045#[doc = "Signed saturating Absolute value"]
37046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
37047#[inline]
37048#[target_feature(enable = "neon")]
37049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37050#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
37051#[cfg_attr(
37052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37053    assert_instr(sqabs)
37054)]
37055#[cfg_attr(
37056    not(target_arch = "arm"),
37057    stable(feature = "neon_intrinsics", since = "1.59.0")
37058)]
37059#[cfg_attr(
37060    target_arch = "arm",
37061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37062)]
37063pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
37064    unsafe extern "unadjusted" {
37065        #[cfg_attr(
37066            any(target_arch = "aarch64", target_arch = "arm64ec"),
37067            link_name = "llvm.aarch64.neon.sqabs.v8i16"
37068        )]
37069        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")]
37070        fn _vqabsq_s16(a: int16x8_t) -> int16x8_t;
37071    }
37072    unsafe { _vqabsq_s16(a) }
37073}
37074#[doc = "Signed saturating Absolute value"]
37075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
37076#[inline]
37077#[target_feature(enable = "neon")]
37078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37079#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
37080#[cfg_attr(
37081    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37082    assert_instr(sqabs)
37083)]
37084#[cfg_attr(
37085    not(target_arch = "arm"),
37086    stable(feature = "neon_intrinsics", since = "1.59.0")
37087)]
37088#[cfg_attr(
37089    target_arch = "arm",
37090    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37091)]
37092pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
37093    unsafe extern "unadjusted" {
37094        #[cfg_attr(
37095            any(target_arch = "aarch64", target_arch = "arm64ec"),
37096            link_name = "llvm.aarch64.neon.sqabs.v2i32"
37097        )]
37098        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")]
37099        fn _vqabs_s32(a: int32x2_t) -> int32x2_t;
37100    }
37101    unsafe { _vqabs_s32(a) }
37102}
37103#[doc = "Signed saturating Absolute value"]
37104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
37105#[inline]
37106#[target_feature(enable = "neon")]
37107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37108#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
37109#[cfg_attr(
37110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37111    assert_instr(sqabs)
37112)]
37113#[cfg_attr(
37114    not(target_arch = "arm"),
37115    stable(feature = "neon_intrinsics", since = "1.59.0")
37116)]
37117#[cfg_attr(
37118    target_arch = "arm",
37119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37120)]
37121pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
37122    unsafe extern "unadjusted" {
37123        #[cfg_attr(
37124            any(target_arch = "aarch64", target_arch = "arm64ec"),
37125            link_name = "llvm.aarch64.neon.sqabs.v4i32"
37126        )]
37127        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")]
37128        fn _vqabsq_s32(a: int32x4_t) -> int32x4_t;
37129    }
37130    unsafe { _vqabsq_s32(a) }
37131}
37132#[doc = "Saturating add"]
37133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
37134#[inline]
37135#[target_feature(enable = "neon")]
37136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37137#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37138#[cfg_attr(
37139    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37140    assert_instr(sqadd)
37141)]
37142#[cfg_attr(
37143    not(target_arch = "arm"),
37144    stable(feature = "neon_intrinsics", since = "1.59.0")
37145)]
37146#[cfg_attr(
37147    target_arch = "arm",
37148    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37149)]
37150pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
37151    unsafe extern "unadjusted" {
37152        #[cfg_attr(
37153            any(target_arch = "aarch64", target_arch = "arm64ec"),
37154            link_name = "llvm.aarch64.neon.sqadd.v8i8"
37155        )]
37156        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")]
37157        fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
37158    }
37159    unsafe { _vqadd_s8(a, b) }
37160}
37161#[doc = "Saturating add"]
37162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
37163#[inline]
37164#[target_feature(enable = "neon")]
37165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37166#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37167#[cfg_attr(
37168    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37169    assert_instr(sqadd)
37170)]
37171#[cfg_attr(
37172    not(target_arch = "arm"),
37173    stable(feature = "neon_intrinsics", since = "1.59.0")
37174)]
37175#[cfg_attr(
37176    target_arch = "arm",
37177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37178)]
37179pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
37180    unsafe extern "unadjusted" {
37181        #[cfg_attr(
37182            any(target_arch = "aarch64", target_arch = "arm64ec"),
37183            link_name = "llvm.aarch64.neon.sqadd.v16i8"
37184        )]
37185        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")]
37186        fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
37187    }
37188    unsafe { _vqaddq_s8(a, b) }
37189}
37190#[doc = "Saturating add"]
37191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
37192#[inline]
37193#[target_feature(enable = "neon")]
37194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37196#[cfg_attr(
37197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37198    assert_instr(sqadd)
37199)]
37200#[cfg_attr(
37201    not(target_arch = "arm"),
37202    stable(feature = "neon_intrinsics", since = "1.59.0")
37203)]
37204#[cfg_attr(
37205    target_arch = "arm",
37206    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37207)]
37208pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
37209    unsafe extern "unadjusted" {
37210        #[cfg_attr(
37211            any(target_arch = "aarch64", target_arch = "arm64ec"),
37212            link_name = "llvm.aarch64.neon.sqadd.v4i16"
37213        )]
37214        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")]
37215        fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
37216    }
37217    unsafe { _vqadd_s16(a, b) }
37218}
37219#[doc = "Saturating add"]
37220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
37221#[inline]
37222#[target_feature(enable = "neon")]
37223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37225#[cfg_attr(
37226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37227    assert_instr(sqadd)
37228)]
37229#[cfg_attr(
37230    not(target_arch = "arm"),
37231    stable(feature = "neon_intrinsics", since = "1.59.0")
37232)]
37233#[cfg_attr(
37234    target_arch = "arm",
37235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37236)]
37237pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37238    unsafe extern "unadjusted" {
37239        #[cfg_attr(
37240            any(target_arch = "aarch64", target_arch = "arm64ec"),
37241            link_name = "llvm.aarch64.neon.sqadd.v8i16"
37242        )]
37243        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")]
37244        fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
37245    }
37246    unsafe { _vqaddq_s16(a, b) }
37247}
37248#[doc = "Saturating add"]
37249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
37250#[inline]
37251#[target_feature(enable = "neon")]
37252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37253#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37254#[cfg_attr(
37255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37256    assert_instr(sqadd)
37257)]
37258#[cfg_attr(
37259    not(target_arch = "arm"),
37260    stable(feature = "neon_intrinsics", since = "1.59.0")
37261)]
37262#[cfg_attr(
37263    target_arch = "arm",
37264    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37265)]
37266pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
37267    unsafe extern "unadjusted" {
37268        #[cfg_attr(
37269            any(target_arch = "aarch64", target_arch = "arm64ec"),
37270            link_name = "llvm.aarch64.neon.sqadd.v2i32"
37271        )]
37272        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")]
37273        fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
37274    }
37275    unsafe { _vqadd_s32(a, b) }
37276}
37277#[doc = "Saturating add"]
37278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
37279#[inline]
37280#[target_feature(enable = "neon")]
37281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37283#[cfg_attr(
37284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37285    assert_instr(sqadd)
37286)]
37287#[cfg_attr(
37288    not(target_arch = "arm"),
37289    stable(feature = "neon_intrinsics", since = "1.59.0")
37290)]
37291#[cfg_attr(
37292    target_arch = "arm",
37293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37294)]
37295pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37296    unsafe extern "unadjusted" {
37297        #[cfg_attr(
37298            any(target_arch = "aarch64", target_arch = "arm64ec"),
37299            link_name = "llvm.aarch64.neon.sqadd.v4i32"
37300        )]
37301        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")]
37302        fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
37303    }
37304    unsafe { _vqaddq_s32(a, b) }
37305}
37306#[doc = "Saturating add"]
37307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
37308#[inline]
37309#[target_feature(enable = "neon")]
37310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37312#[cfg_attr(
37313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37314    assert_instr(sqadd)
37315)]
37316#[cfg_attr(
37317    not(target_arch = "arm"),
37318    stable(feature = "neon_intrinsics", since = "1.59.0")
37319)]
37320#[cfg_attr(
37321    target_arch = "arm",
37322    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37323)]
37324pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
37325    unsafe extern "unadjusted" {
37326        #[cfg_attr(
37327            any(target_arch = "aarch64", target_arch = "arm64ec"),
37328            link_name = "llvm.aarch64.neon.sqadd.v1i64"
37329        )]
37330        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")]
37331        fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
37332    }
37333    unsafe { _vqadd_s64(a, b) }
37334}
37335#[doc = "Saturating add"]
37336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
37337#[inline]
37338#[target_feature(enable = "neon")]
37339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37341#[cfg_attr(
37342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37343    assert_instr(sqadd)
37344)]
37345#[cfg_attr(
37346    not(target_arch = "arm"),
37347    stable(feature = "neon_intrinsics", since = "1.59.0")
37348)]
37349#[cfg_attr(
37350    target_arch = "arm",
37351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37352)]
37353pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
37354    unsafe extern "unadjusted" {
37355        #[cfg_attr(
37356            any(target_arch = "aarch64", target_arch = "arm64ec"),
37357            link_name = "llvm.aarch64.neon.sqadd.v2i64"
37358        )]
37359        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")]
37360        fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
37361    }
37362    unsafe { _vqaddq_s64(a, b) }
37363}
37364#[doc = "Saturating add"]
37365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
37366#[inline]
37367#[target_feature(enable = "neon")]
37368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37370#[cfg_attr(
37371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37372    assert_instr(uqadd)
37373)]
37374#[cfg_attr(
37375    not(target_arch = "arm"),
37376    stable(feature = "neon_intrinsics", since = "1.59.0")
37377)]
37378#[cfg_attr(
37379    target_arch = "arm",
37380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37381)]
37382pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
37383    unsafe extern "unadjusted" {
37384        #[cfg_attr(
37385            any(target_arch = "aarch64", target_arch = "arm64ec"),
37386            link_name = "llvm.aarch64.neon.uqadd.v8i8"
37387        )]
37388        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")]
37389        fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
37390    }
37391    unsafe { _vqadd_u8(a, b) }
37392}
37393#[doc = "Saturating add"]
37394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
37395#[inline]
37396#[target_feature(enable = "neon")]
37397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37398#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37399#[cfg_attr(
37400    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37401    assert_instr(uqadd)
37402)]
37403#[cfg_attr(
37404    not(target_arch = "arm"),
37405    stable(feature = "neon_intrinsics", since = "1.59.0")
37406)]
37407#[cfg_attr(
37408    target_arch = "arm",
37409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37410)]
37411pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
37412    unsafe extern "unadjusted" {
37413        #[cfg_attr(
37414            any(target_arch = "aarch64", target_arch = "arm64ec"),
37415            link_name = "llvm.aarch64.neon.uqadd.v16i8"
37416        )]
37417        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")]
37418        fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
37419    }
37420    unsafe { _vqaddq_u8(a, b) }
37421}
37422#[doc = "Saturating add"]
37423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
37424#[inline]
37425#[target_feature(enable = "neon")]
37426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37427#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37428#[cfg_attr(
37429    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37430    assert_instr(uqadd)
37431)]
37432#[cfg_attr(
37433    not(target_arch = "arm"),
37434    stable(feature = "neon_intrinsics", since = "1.59.0")
37435)]
37436#[cfg_attr(
37437    target_arch = "arm",
37438    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37439)]
37440pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
37441    unsafe extern "unadjusted" {
37442        #[cfg_attr(
37443            any(target_arch = "aarch64", target_arch = "arm64ec"),
37444            link_name = "llvm.aarch64.neon.uqadd.v4i16"
37445        )]
37446        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")]
37447        fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
37448    }
37449    unsafe { _vqadd_u16(a, b) }
37450}
37451#[doc = "Saturating add"]
37452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
37453#[inline]
37454#[target_feature(enable = "neon")]
37455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37457#[cfg_attr(
37458    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37459    assert_instr(uqadd)
37460)]
37461#[cfg_attr(
37462    not(target_arch = "arm"),
37463    stable(feature = "neon_intrinsics", since = "1.59.0")
37464)]
37465#[cfg_attr(
37466    target_arch = "arm",
37467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37468)]
37469pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
37470    unsafe extern "unadjusted" {
37471        #[cfg_attr(
37472            any(target_arch = "aarch64", target_arch = "arm64ec"),
37473            link_name = "llvm.aarch64.neon.uqadd.v8i16"
37474        )]
37475        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")]
37476        fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
37477    }
37478    unsafe { _vqaddq_u16(a, b) }
37479}
37480#[doc = "Saturating add"]
37481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
37482#[inline]
37483#[target_feature(enable = "neon")]
37484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37486#[cfg_attr(
37487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37488    assert_instr(uqadd)
37489)]
37490#[cfg_attr(
37491    not(target_arch = "arm"),
37492    stable(feature = "neon_intrinsics", since = "1.59.0")
37493)]
37494#[cfg_attr(
37495    target_arch = "arm",
37496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37497)]
37498pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
37499    unsafe extern "unadjusted" {
37500        #[cfg_attr(
37501            any(target_arch = "aarch64", target_arch = "arm64ec"),
37502            link_name = "llvm.aarch64.neon.uqadd.v2i32"
37503        )]
37504        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")]
37505        fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
37506    }
37507    unsafe { _vqadd_u32(a, b) }
37508}
37509#[doc = "Saturating add"]
37510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
37511#[inline]
37512#[target_feature(enable = "neon")]
37513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37515#[cfg_attr(
37516    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37517    assert_instr(uqadd)
37518)]
37519#[cfg_attr(
37520    not(target_arch = "arm"),
37521    stable(feature = "neon_intrinsics", since = "1.59.0")
37522)]
37523#[cfg_attr(
37524    target_arch = "arm",
37525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37526)]
37527pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
37528    unsafe extern "unadjusted" {
37529        #[cfg_attr(
37530            any(target_arch = "aarch64", target_arch = "arm64ec"),
37531            link_name = "llvm.aarch64.neon.uqadd.v4i32"
37532        )]
37533        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")]
37534        fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
37535    }
37536    unsafe { _vqaddq_u32(a, b) }
37537}
37538#[doc = "Saturating add"]
37539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
37540#[inline]
37541#[target_feature(enable = "neon")]
37542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37544#[cfg_attr(
37545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37546    assert_instr(uqadd)
37547)]
37548#[cfg_attr(
37549    not(target_arch = "arm"),
37550    stable(feature = "neon_intrinsics", since = "1.59.0")
37551)]
37552#[cfg_attr(
37553    target_arch = "arm",
37554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37555)]
37556pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
37557    unsafe extern "unadjusted" {
37558        #[cfg_attr(
37559            any(target_arch = "aarch64", target_arch = "arm64ec"),
37560            link_name = "llvm.aarch64.neon.uqadd.v1i64"
37561        )]
37562        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")]
37563        fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
37564    }
37565    unsafe { _vqadd_u64(a, b) }
37566}
37567#[doc = "Saturating add"]
37568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
37569#[inline]
37570#[target_feature(enable = "neon")]
37571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37572#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37573#[cfg_attr(
37574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37575    assert_instr(uqadd)
37576)]
37577#[cfg_attr(
37578    not(target_arch = "arm"),
37579    stable(feature = "neon_intrinsics", since = "1.59.0")
37580)]
37581#[cfg_attr(
37582    target_arch = "arm",
37583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37584)]
37585pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
37586    unsafe extern "unadjusted" {
37587        #[cfg_attr(
37588            any(target_arch = "aarch64", target_arch = "arm64ec"),
37589            link_name = "llvm.aarch64.neon.uqadd.v2i64"
37590        )]
37591        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")]
37592        fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
37593    }
37594    unsafe { _vqaddq_u64(a, b) }
37595}
37596#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
37598#[inline]
37599#[target_feature(enable = "neon")]
37600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
37602#[cfg_attr(
37603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37604    assert_instr(sqdmlal, N = 2)
37605)]
37606#[rustc_legacy_const_generics(3)]
37607#[cfg_attr(
37608    not(target_arch = "arm"),
37609    stable(feature = "neon_intrinsics", since = "1.59.0")
37610)]
37611#[cfg_attr(
37612    target_arch = "arm",
37613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37614)]
37615pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37616    static_assert_uimm_bits!(N, 2);
37617    vqaddq_s32(a, vqdmull_lane_s16::<N>(b, c))
37618}
37619#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
37621#[inline]
37622#[target_feature(enable = "neon")]
37623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
37625#[cfg_attr(
37626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37627    assert_instr(sqdmlal, N = 1)
37628)]
37629#[rustc_legacy_const_generics(3)]
37630#[cfg_attr(
37631    not(target_arch = "arm"),
37632    stable(feature = "neon_intrinsics", since = "1.59.0")
37633)]
37634#[cfg_attr(
37635    target_arch = "arm",
37636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37637)]
37638pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37639    static_assert_uimm_bits!(N, 1);
37640    vqaddq_s64(a, vqdmull_lane_s32::<N>(b, c))
37641}
37642#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
37644#[inline]
37645#[target_feature(enable = "neon")]
37646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37648#[cfg_attr(
37649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37650    assert_instr(sqdmlal)
37651)]
37652#[cfg_attr(
37653    not(target_arch = "arm"),
37654    stable(feature = "neon_intrinsics", since = "1.59.0")
37655)]
37656#[cfg_attr(
37657    target_arch = "arm",
37658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37659)]
37660pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37661    vqaddq_s32(a, vqdmull_n_s16(b, c))
37662}
37663#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
37665#[inline]
37666#[target_feature(enable = "neon")]
37667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37669#[cfg_attr(
37670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37671    assert_instr(sqdmlal)
37672)]
37673#[cfg_attr(
37674    not(target_arch = "arm"),
37675    stable(feature = "neon_intrinsics", since = "1.59.0")
37676)]
37677#[cfg_attr(
37678    target_arch = "arm",
37679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37680)]
37681pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37682    vqaddq_s64(a, vqdmull_n_s32(b, c))
37683}
37684#[doc = "Signed saturating doubling multiply-add long"]
37685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
37686#[inline]
37687#[target_feature(enable = "neon")]
37688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37690#[cfg_attr(
37691    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37692    assert_instr(sqdmlal)
37693)]
37694#[cfg_attr(
37695    not(target_arch = "arm"),
37696    stable(feature = "neon_intrinsics", since = "1.59.0")
37697)]
37698#[cfg_attr(
37699    target_arch = "arm",
37700    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37701)]
37702pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37703    vqaddq_s32(a, vqdmull_s16(b, c))
37704}
37705#[doc = "Signed saturating doubling multiply-add long"]
37706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
37707#[inline]
37708#[target_feature(enable = "neon")]
37709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37711#[cfg_attr(
37712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37713    assert_instr(sqdmlal)
37714)]
37715#[cfg_attr(
37716    not(target_arch = "arm"),
37717    stable(feature = "neon_intrinsics", since = "1.59.0")
37718)]
37719#[cfg_attr(
37720    target_arch = "arm",
37721    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37722)]
37723pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37724    vqaddq_s64(a, vqdmull_s32(b, c))
37725}
37726#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
37728#[inline]
37729#[target_feature(enable = "neon")]
37730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
37732#[cfg_attr(
37733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37734    assert_instr(sqdmlsl, N = 2)
37735)]
37736#[rustc_legacy_const_generics(3)]
37737#[cfg_attr(
37738    not(target_arch = "arm"),
37739    stable(feature = "neon_intrinsics", since = "1.59.0")
37740)]
37741#[cfg_attr(
37742    target_arch = "arm",
37743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37744)]
37745pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37746    static_assert_uimm_bits!(N, 2);
37747    vqsubq_s32(a, vqdmull_lane_s16::<N>(b, c))
37748}
37749#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
37751#[inline]
37752#[target_feature(enable = "neon")]
37753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
37755#[cfg_attr(
37756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37757    assert_instr(sqdmlsl, N = 1)
37758)]
37759#[rustc_legacy_const_generics(3)]
37760#[cfg_attr(
37761    not(target_arch = "arm"),
37762    stable(feature = "neon_intrinsics", since = "1.59.0")
37763)]
37764#[cfg_attr(
37765    target_arch = "arm",
37766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37767)]
37768pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37769    static_assert_uimm_bits!(N, 1);
37770    vqsubq_s64(a, vqdmull_lane_s32::<N>(b, c))
37771}
37772#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
37774#[inline]
37775#[target_feature(enable = "neon")]
37776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37778#[cfg_attr(
37779    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37780    assert_instr(sqdmlsl)
37781)]
37782#[cfg_attr(
37783    not(target_arch = "arm"),
37784    stable(feature = "neon_intrinsics", since = "1.59.0")
37785)]
37786#[cfg_attr(
37787    target_arch = "arm",
37788    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37789)]
37790pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37791    vqsubq_s32(a, vqdmull_n_s16(b, c))
37792}
37793#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
37795#[inline]
37796#[target_feature(enable = "neon")]
37797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37799#[cfg_attr(
37800    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37801    assert_instr(sqdmlsl)
37802)]
37803#[cfg_attr(
37804    not(target_arch = "arm"),
37805    stable(feature = "neon_intrinsics", since = "1.59.0")
37806)]
37807#[cfg_attr(
37808    target_arch = "arm",
37809    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37810)]
37811pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37812    vqsubq_s64(a, vqdmull_n_s32(b, c))
37813}
37814#[doc = "Signed saturating doubling multiply-subtract long"]
37815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
37816#[inline]
37817#[target_feature(enable = "neon")]
37818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37820#[cfg_attr(
37821    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37822    assert_instr(sqdmlsl)
37823)]
37824#[cfg_attr(
37825    not(target_arch = "arm"),
37826    stable(feature = "neon_intrinsics", since = "1.59.0")
37827)]
37828#[cfg_attr(
37829    target_arch = "arm",
37830    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37831)]
37832pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37833    vqsubq_s32(a, vqdmull_s16(b, c))
37834}
37835#[doc = "Signed saturating doubling multiply-subtract long"]
37836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
37837#[inline]
37838#[target_feature(enable = "neon")]
37839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37841#[cfg_attr(
37842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37843    assert_instr(sqdmlsl)
37844)]
37845#[cfg_attr(
37846    not(target_arch = "arm"),
37847    stable(feature = "neon_intrinsics", since = "1.59.0")
37848)]
37849#[cfg_attr(
37850    target_arch = "arm",
37851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37852)]
37853pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37854    vqsubq_s64(a, vqdmull_s32(b, c))
37855}
37856#[doc = "Vector saturating doubling multiply high by scalar"]
37857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
37858#[inline]
37859#[target_feature(enable = "neon")]
37860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37862#[cfg_attr(
37863    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37864    assert_instr(sqdmulh, LANE = 0)
37865)]
37866#[rustc_legacy_const_generics(2)]
37867#[cfg_attr(
37868    not(target_arch = "arm"),
37869    stable(feature = "neon_intrinsics", since = "1.59.0")
37870)]
37871#[cfg_attr(
37872    target_arch = "arm",
37873    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37874)]
37875pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
37876    static_assert_uimm_bits!(LANE, 3);
37877    unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
37878}
37879#[doc = "Vector saturating doubling multiply high by scalar"]
37880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
37881#[inline]
37882#[target_feature(enable = "neon")]
37883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37885#[cfg_attr(
37886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37887    assert_instr(sqdmulh, LANE = 0)
37888)]
37889#[rustc_legacy_const_generics(2)]
37890#[cfg_attr(
37891    not(target_arch = "arm"),
37892    stable(feature = "neon_intrinsics", since = "1.59.0")
37893)]
37894#[cfg_attr(
37895    target_arch = "arm",
37896    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37897)]
37898pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37899    static_assert_uimm_bits!(LANE, 3);
37900    unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
37901}
37902#[doc = "Vector saturating doubling multiply high by scalar"]
37903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
37904#[inline]
37905#[target_feature(enable = "neon")]
37906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37908#[cfg_attr(
37909    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37910    assert_instr(sqdmulh, LANE = 0)
37911)]
37912#[rustc_legacy_const_generics(2)]
37913#[cfg_attr(
37914    not(target_arch = "arm"),
37915    stable(feature = "neon_intrinsics", since = "1.59.0")
37916)]
37917#[cfg_attr(
37918    target_arch = "arm",
37919    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37920)]
37921pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
37922    static_assert_uimm_bits!(LANE, 2);
37923    unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
37924}
37925#[doc = "Vector saturating doubling multiply high by scalar"]
37926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
37927#[inline]
37928#[target_feature(enable = "neon")]
37929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37931#[cfg_attr(
37932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37933    assert_instr(sqdmulh, LANE = 0)
37934)]
37935#[rustc_legacy_const_generics(2)]
37936#[cfg_attr(
37937    not(target_arch = "arm"),
37938    stable(feature = "neon_intrinsics", since = "1.59.0")
37939)]
37940#[cfg_attr(
37941    target_arch = "arm",
37942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37943)]
37944pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37945    static_assert_uimm_bits!(LANE, 2);
37946    unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
37947}
37948#[doc = "Vector saturating doubling multiply high with scalar"]
37949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
37950#[inline]
37951#[target_feature(enable = "neon")]
37952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37954#[cfg_attr(
37955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37956    assert_instr(sqdmulh)
37957)]
37958#[cfg_attr(
37959    not(target_arch = "arm"),
37960    stable(feature = "neon_intrinsics", since = "1.59.0")
37961)]
37962#[cfg_attr(
37963    target_arch = "arm",
37964    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37965)]
37966pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
37967    let b: int16x4_t = vdup_n_s16(b);
37968    vqdmulh_s16(a, b)
37969}
37970#[doc = "Vector saturating doubling multiply high with scalar"]
37971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
37972#[inline]
37973#[target_feature(enable = "neon")]
37974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37976#[cfg_attr(
37977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37978    assert_instr(sqdmulh)
37979)]
37980#[cfg_attr(
37981    not(target_arch = "arm"),
37982    stable(feature = "neon_intrinsics", since = "1.59.0")
37983)]
37984#[cfg_attr(
37985    target_arch = "arm",
37986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37987)]
37988pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
37989    let b: int16x8_t = vdupq_n_s16(b);
37990    vqdmulhq_s16(a, b)
37991}
37992#[doc = "Vector saturating doubling multiply high with scalar"]
37993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
37994#[inline]
37995#[target_feature(enable = "neon")]
37996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37998#[cfg_attr(
37999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38000    assert_instr(sqdmulh)
38001)]
38002#[cfg_attr(
38003    not(target_arch = "arm"),
38004    stable(feature = "neon_intrinsics", since = "1.59.0")
38005)]
38006#[cfg_attr(
38007    target_arch = "arm",
38008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38009)]
38010pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
38011    let b: int32x2_t = vdup_n_s32(b);
38012    vqdmulh_s32(a, b)
38013}
38014#[doc = "Vector saturating doubling multiply high with scalar"]
38015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
38016#[inline]
38017#[target_feature(enable = "neon")]
38018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38020#[cfg_attr(
38021    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38022    assert_instr(sqdmulh)
38023)]
38024#[cfg_attr(
38025    not(target_arch = "arm"),
38026    stable(feature = "neon_intrinsics", since = "1.59.0")
38027)]
38028#[cfg_attr(
38029    target_arch = "arm",
38030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38031)]
38032pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
38033    let b: int32x4_t = vdupq_n_s32(b);
38034    vqdmulhq_s32(a, b)
38035}
38036#[doc = "Signed saturating doubling multiply returning high half"]
38037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
38038#[inline]
38039#[target_feature(enable = "neon")]
38040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38042#[cfg_attr(
38043    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38044    assert_instr(sqdmulh)
38045)]
38046#[cfg_attr(
38047    not(target_arch = "arm"),
38048    stable(feature = "neon_intrinsics", since = "1.59.0")
38049)]
38050#[cfg_attr(
38051    target_arch = "arm",
38052    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38053)]
38054pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38055    unsafe extern "unadjusted" {
38056        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")]
38057        #[cfg_attr(
38058            any(target_arch = "aarch64", target_arch = "arm64ec"),
38059            link_name = "llvm.aarch64.neon.sqdmulh.v4i16"
38060        )]
38061        fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
38062    }
38063    unsafe { _vqdmulh_s16(a, b) }
38064}
38065#[doc = "Signed saturating doubling multiply returning high half"]
38066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
38067#[inline]
38068#[target_feature(enable = "neon")]
38069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38071#[cfg_attr(
38072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38073    assert_instr(sqdmulh)
38074)]
38075#[cfg_attr(
38076    not(target_arch = "arm"),
38077    stable(feature = "neon_intrinsics", since = "1.59.0")
38078)]
38079#[cfg_attr(
38080    target_arch = "arm",
38081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38082)]
38083pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38084    unsafe extern "unadjusted" {
38085        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")]
38086        #[cfg_attr(
38087            any(target_arch = "aarch64", target_arch = "arm64ec"),
38088            link_name = "llvm.aarch64.neon.sqdmulh.v8i16"
38089        )]
38090        fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
38091    }
38092    unsafe { _vqdmulhq_s16(a, b) }
38093}
38094#[doc = "Signed saturating doubling multiply returning high half"]
38095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
38096#[inline]
38097#[target_feature(enable = "neon")]
38098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38100#[cfg_attr(
38101    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38102    assert_instr(sqdmulh)
38103)]
38104#[cfg_attr(
38105    not(target_arch = "arm"),
38106    stable(feature = "neon_intrinsics", since = "1.59.0")
38107)]
38108#[cfg_attr(
38109    target_arch = "arm",
38110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38111)]
38112pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38113    unsafe extern "unadjusted" {
38114        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")]
38115        #[cfg_attr(
38116            any(target_arch = "aarch64", target_arch = "arm64ec"),
38117            link_name = "llvm.aarch64.neon.sqdmulh.v2i32"
38118        )]
38119        fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
38120    }
38121    unsafe { _vqdmulh_s32(a, b) }
38122}
38123#[doc = "Signed saturating doubling multiply returning high half"]
38124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
38125#[inline]
38126#[target_feature(enable = "neon")]
38127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38129#[cfg_attr(
38130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38131    assert_instr(sqdmulh)
38132)]
38133#[cfg_attr(
38134    not(target_arch = "arm"),
38135    stable(feature = "neon_intrinsics", since = "1.59.0")
38136)]
38137#[cfg_attr(
38138    target_arch = "arm",
38139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38140)]
38141pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38142    unsafe extern "unadjusted" {
38143        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")]
38144        #[cfg_attr(
38145            any(target_arch = "aarch64", target_arch = "arm64ec"),
38146            link_name = "llvm.aarch64.neon.sqdmulh.v4i32"
38147        )]
38148        fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
38149    }
38150    unsafe { _vqdmulhq_s32(a, b) }
38151}
38152#[doc = "Vector saturating doubling long multiply by scalar"]
38153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
38154#[inline]
38155#[target_feature(enable = "neon")]
38156#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
38158#[cfg_attr(
38159    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38160    assert_instr(sqdmull, N = 2)
38161)]
38162#[rustc_legacy_const_generics(2)]
38163#[cfg_attr(
38164    not(target_arch = "arm"),
38165    stable(feature = "neon_intrinsics", since = "1.59.0")
38166)]
38167#[cfg_attr(
38168    target_arch = "arm",
38169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38170)]
38171pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38172    static_assert_uimm_bits!(N, 2);
38173    unsafe {
38174        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
38175        vqdmull_s16(a, b)
38176    }
38177}
38178#[doc = "Vector saturating doubling long multiply by scalar"]
38179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
38180#[inline]
38181#[target_feature(enable = "neon")]
38182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
38184#[cfg_attr(
38185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38186    assert_instr(sqdmull, N = 1)
38187)]
38188#[rustc_legacy_const_generics(2)]
38189#[cfg_attr(
38190    not(target_arch = "arm"),
38191    stable(feature = "neon_intrinsics", since = "1.59.0")
38192)]
38193#[cfg_attr(
38194    target_arch = "arm",
38195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38196)]
38197pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38198    static_assert_uimm_bits!(N, 1);
38199    unsafe {
38200        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
38201        vqdmull_s32(a, b)
38202    }
38203}
38204#[doc = "Vector saturating doubling long multiply with scalar"]
38205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
38206#[inline]
38207#[target_feature(enable = "neon")]
38208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38210#[cfg_attr(
38211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38212    assert_instr(sqdmull)
38213)]
38214#[cfg_attr(
38215    not(target_arch = "arm"),
38216    stable(feature = "neon_intrinsics", since = "1.59.0")
38217)]
38218#[cfg_attr(
38219    target_arch = "arm",
38220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38221)]
38222pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
38223    vqdmull_s16(a, vdup_n_s16(b))
38224}
38225#[doc = "Vector saturating doubling long multiply with scalar"]
38226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
38227#[inline]
38228#[target_feature(enable = "neon")]
38229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38231#[cfg_attr(
38232    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38233    assert_instr(sqdmull)
38234)]
38235#[cfg_attr(
38236    not(target_arch = "arm"),
38237    stable(feature = "neon_intrinsics", since = "1.59.0")
38238)]
38239#[cfg_attr(
38240    target_arch = "arm",
38241    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38242)]
38243pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
38244    vqdmull_s32(a, vdup_n_s32(b))
38245}
38246#[doc = "Signed saturating doubling multiply long"]
38247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
38248#[inline]
38249#[target_feature(enable = "neon")]
38250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38252#[cfg_attr(
38253    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38254    assert_instr(sqdmull)
38255)]
38256#[cfg_attr(
38257    not(target_arch = "arm"),
38258    stable(feature = "neon_intrinsics", since = "1.59.0")
38259)]
38260#[cfg_attr(
38261    target_arch = "arm",
38262    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38263)]
38264pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38265    unsafe extern "unadjusted" {
38266        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")]
38267        #[cfg_attr(
38268            any(target_arch = "aarch64", target_arch = "arm64ec"),
38269            link_name = "llvm.aarch64.neon.sqdmull.v4i32"
38270        )]
38271        fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
38272    }
38273    unsafe { _vqdmull_s16(a, b) }
38274}
38275#[doc = "Signed saturating doubling multiply long"]
38276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
38277#[inline]
38278#[target_feature(enable = "neon")]
38279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38281#[cfg_attr(
38282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38283    assert_instr(sqdmull)
38284)]
38285#[cfg_attr(
38286    not(target_arch = "arm"),
38287    stable(feature = "neon_intrinsics", since = "1.59.0")
38288)]
38289#[cfg_attr(
38290    target_arch = "arm",
38291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38292)]
38293pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38294    unsafe extern "unadjusted" {
38295        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")]
38296        #[cfg_attr(
38297            any(target_arch = "aarch64", target_arch = "arm64ec"),
38298            link_name = "llvm.aarch64.neon.sqdmull.v2i64"
38299        )]
38300        fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
38301    }
38302    unsafe { _vqdmull_s32(a, b) }
38303}
38304#[doc = "Signed saturating extract narrow"]
38305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
38306#[inline]
38307#[target_feature(enable = "neon")]
38308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38310#[cfg_attr(
38311    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38312    assert_instr(sqxtn)
38313)]
38314#[cfg_attr(
38315    not(target_arch = "arm"),
38316    stable(feature = "neon_intrinsics", since = "1.59.0")
38317)]
38318#[cfg_attr(
38319    target_arch = "arm",
38320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38321)]
38322pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
38323    unsafe extern "unadjusted" {
38324        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")]
38325        #[cfg_attr(
38326            any(target_arch = "aarch64", target_arch = "arm64ec"),
38327            link_name = "llvm.aarch64.neon.sqxtn.v8i8"
38328        )]
38329        fn _vqmovn_s16(a: int16x8_t) -> int8x8_t;
38330    }
38331    unsafe { _vqmovn_s16(a) }
38332}
38333#[doc = "Signed saturating extract narrow"]
38334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
38335#[inline]
38336#[target_feature(enable = "neon")]
38337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38339#[cfg_attr(
38340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38341    assert_instr(sqxtn)
38342)]
38343#[cfg_attr(
38344    not(target_arch = "arm"),
38345    stable(feature = "neon_intrinsics", since = "1.59.0")
38346)]
38347#[cfg_attr(
38348    target_arch = "arm",
38349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38350)]
38351pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
38352    unsafe extern "unadjusted" {
38353        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")]
38354        #[cfg_attr(
38355            any(target_arch = "aarch64", target_arch = "arm64ec"),
38356            link_name = "llvm.aarch64.neon.sqxtn.v4i16"
38357        )]
38358        fn _vqmovn_s32(a: int32x4_t) -> int16x4_t;
38359    }
38360    unsafe { _vqmovn_s32(a) }
38361}
38362#[doc = "Signed saturating extract narrow"]
38363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
38364#[inline]
38365#[target_feature(enable = "neon")]
38366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38368#[cfg_attr(
38369    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38370    assert_instr(sqxtn)
38371)]
38372#[cfg_attr(
38373    not(target_arch = "arm"),
38374    stable(feature = "neon_intrinsics", since = "1.59.0")
38375)]
38376#[cfg_attr(
38377    target_arch = "arm",
38378    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38379)]
38380pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
38381    unsafe extern "unadjusted" {
38382        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")]
38383        #[cfg_attr(
38384            any(target_arch = "aarch64", target_arch = "arm64ec"),
38385            link_name = "llvm.aarch64.neon.sqxtn.v2i32"
38386        )]
38387        fn _vqmovn_s64(a: int64x2_t) -> int32x2_t;
38388    }
38389    unsafe { _vqmovn_s64(a) }
38390}
38391#[doc = "Unsigned saturating extract narrow"]
38392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
38393#[inline]
38394#[target_feature(enable = "neon")]
38395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38397#[cfg_attr(
38398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38399    assert_instr(uqxtn)
38400)]
38401#[cfg_attr(
38402    not(target_arch = "arm"),
38403    stable(feature = "neon_intrinsics", since = "1.59.0")
38404)]
38405#[cfg_attr(
38406    target_arch = "arm",
38407    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38408)]
38409pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
38410    unsafe extern "unadjusted" {
38411        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")]
38412        #[cfg_attr(
38413            any(target_arch = "aarch64", target_arch = "arm64ec"),
38414            link_name = "llvm.aarch64.neon.uqxtn.v8i8"
38415        )]
38416        fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t;
38417    }
38418    unsafe { _vqmovn_u16(a) }
38419}
38420#[doc = "Unsigned saturating extract narrow"]
38421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
38422#[inline]
38423#[target_feature(enable = "neon")]
38424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38426#[cfg_attr(
38427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38428    assert_instr(uqxtn)
38429)]
38430#[cfg_attr(
38431    not(target_arch = "arm"),
38432    stable(feature = "neon_intrinsics", since = "1.59.0")
38433)]
38434#[cfg_attr(
38435    target_arch = "arm",
38436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38437)]
38438pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
38439    unsafe extern "unadjusted" {
38440        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")]
38441        #[cfg_attr(
38442            any(target_arch = "aarch64", target_arch = "arm64ec"),
38443            link_name = "llvm.aarch64.neon.uqxtn.v4i16"
38444        )]
38445        fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t;
38446    }
38447    unsafe { _vqmovn_u32(a) }
38448}
38449#[doc = "Unsigned saturating extract narrow"]
38450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
38451#[inline]
38452#[target_feature(enable = "neon")]
38453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38455#[cfg_attr(
38456    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38457    assert_instr(uqxtn)
38458)]
38459#[cfg_attr(
38460    not(target_arch = "arm"),
38461    stable(feature = "neon_intrinsics", since = "1.59.0")
38462)]
38463#[cfg_attr(
38464    target_arch = "arm",
38465    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38466)]
38467pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
38468    unsafe extern "unadjusted" {
38469        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
38470        #[cfg_attr(
38471            any(target_arch = "aarch64", target_arch = "arm64ec"),
38472            link_name = "llvm.aarch64.neon.uqxtn.v2i32"
38473        )]
38474        fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t;
38475    }
38476    unsafe { _vqmovn_u64(a) }
38477}
38478#[doc = "Signed saturating extract unsigned narrow"]
38479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
38480#[inline]
38481#[target_feature(enable = "neon")]
38482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38484#[cfg_attr(
38485    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38486    assert_instr(sqxtun)
38487)]
38488#[cfg_attr(
38489    not(target_arch = "arm"),
38490    stable(feature = "neon_intrinsics", since = "1.59.0")
38491)]
38492#[cfg_attr(
38493    target_arch = "arm",
38494    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38495)]
38496pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
38497    unsafe extern "unadjusted" {
38498        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")]
38499        #[cfg_attr(
38500            any(target_arch = "aarch64", target_arch = "arm64ec"),
38501            link_name = "llvm.aarch64.neon.sqxtun.v8i8"
38502        )]
38503        fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t;
38504    }
38505    unsafe { _vqmovun_s16(a) }
38506}
38507#[doc = "Signed saturating extract unsigned narrow"]
38508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
38509#[inline]
38510#[target_feature(enable = "neon")]
38511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38513#[cfg_attr(
38514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38515    assert_instr(sqxtun)
38516)]
38517#[cfg_attr(
38518    not(target_arch = "arm"),
38519    stable(feature = "neon_intrinsics", since = "1.59.0")
38520)]
38521#[cfg_attr(
38522    target_arch = "arm",
38523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38524)]
38525pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
38526    unsafe extern "unadjusted" {
38527        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")]
38528        #[cfg_attr(
38529            any(target_arch = "aarch64", target_arch = "arm64ec"),
38530            link_name = "llvm.aarch64.neon.sqxtun.v4i16"
38531        )]
38532        fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t;
38533    }
38534    unsafe { _vqmovun_s32(a) }
38535}
38536#[doc = "Signed saturating extract unsigned narrow"]
38537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
38538#[inline]
38539#[target_feature(enable = "neon")]
38540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38542#[cfg_attr(
38543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38544    assert_instr(sqxtun)
38545)]
38546#[cfg_attr(
38547    not(target_arch = "arm"),
38548    stable(feature = "neon_intrinsics", since = "1.59.0")
38549)]
38550#[cfg_attr(
38551    target_arch = "arm",
38552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38553)]
38554pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
38555    unsafe extern "unadjusted" {
38556        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")]
38557        #[cfg_attr(
38558            any(target_arch = "aarch64", target_arch = "arm64ec"),
38559            link_name = "llvm.aarch64.neon.sqxtun.v2i32"
38560        )]
38561        fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t;
38562    }
38563    unsafe { _vqmovun_s64(a) }
38564}
38565#[doc = "Signed saturating negate"]
38566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
38567#[inline]
38568#[target_feature(enable = "neon")]
38569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38571#[cfg_attr(
38572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38573    assert_instr(sqneg)
38574)]
38575#[cfg_attr(
38576    not(target_arch = "arm"),
38577    stable(feature = "neon_intrinsics", since = "1.59.0")
38578)]
38579#[cfg_attr(
38580    target_arch = "arm",
38581    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38582)]
38583pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
38584    unsafe extern "unadjusted" {
38585        #[cfg_attr(
38586            any(target_arch = "aarch64", target_arch = "arm64ec"),
38587            link_name = "llvm.aarch64.neon.sqneg.v8i8"
38588        )]
38589        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")]
38590        fn _vqneg_s8(a: int8x8_t) -> int8x8_t;
38591    }
38592    unsafe { _vqneg_s8(a) }
38593}
38594#[doc = "Signed saturating negate"]
38595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
38596#[inline]
38597#[target_feature(enable = "neon")]
38598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38599#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38600#[cfg_attr(
38601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38602    assert_instr(sqneg)
38603)]
38604#[cfg_attr(
38605    not(target_arch = "arm"),
38606    stable(feature = "neon_intrinsics", since = "1.59.0")
38607)]
38608#[cfg_attr(
38609    target_arch = "arm",
38610    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38611)]
38612pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
38613    unsafe extern "unadjusted" {
38614        #[cfg_attr(
38615            any(target_arch = "aarch64", target_arch = "arm64ec"),
38616            link_name = "llvm.aarch64.neon.sqneg.v16i8"
38617        )]
38618        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")]
38619        fn _vqnegq_s8(a: int8x16_t) -> int8x16_t;
38620    }
38621    unsafe { _vqnegq_s8(a) }
38622}
38623#[doc = "Signed saturating negate"]
38624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
38625#[inline]
38626#[target_feature(enable = "neon")]
38627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38628#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38629#[cfg_attr(
38630    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38631    assert_instr(sqneg)
38632)]
38633#[cfg_attr(
38634    not(target_arch = "arm"),
38635    stable(feature = "neon_intrinsics", since = "1.59.0")
38636)]
38637#[cfg_attr(
38638    target_arch = "arm",
38639    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38640)]
38641pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
38642    unsafe extern "unadjusted" {
38643        #[cfg_attr(
38644            any(target_arch = "aarch64", target_arch = "arm64ec"),
38645            link_name = "llvm.aarch64.neon.sqneg.v4i16"
38646        )]
38647        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")]
38648        fn _vqneg_s16(a: int16x4_t) -> int16x4_t;
38649    }
38650    unsafe { _vqneg_s16(a) }
38651}
38652#[doc = "Signed saturating negate"]
38653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
38654#[inline]
38655#[target_feature(enable = "neon")]
38656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38658#[cfg_attr(
38659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38660    assert_instr(sqneg)
38661)]
38662#[cfg_attr(
38663    not(target_arch = "arm"),
38664    stable(feature = "neon_intrinsics", since = "1.59.0")
38665)]
38666#[cfg_attr(
38667    target_arch = "arm",
38668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38669)]
38670pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
38671    unsafe extern "unadjusted" {
38672        #[cfg_attr(
38673            any(target_arch = "aarch64", target_arch = "arm64ec"),
38674            link_name = "llvm.aarch64.neon.sqneg.v8i16"
38675        )]
38676        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")]
38677        fn _vqnegq_s16(a: int16x8_t) -> int16x8_t;
38678    }
38679    unsafe { _vqnegq_s16(a) }
38680}
38681#[doc = "Signed saturating negate"]
38682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
38683#[inline]
38684#[target_feature(enable = "neon")]
38685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38686#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38687#[cfg_attr(
38688    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38689    assert_instr(sqneg)
38690)]
38691#[cfg_attr(
38692    not(target_arch = "arm"),
38693    stable(feature = "neon_intrinsics", since = "1.59.0")
38694)]
38695#[cfg_attr(
38696    target_arch = "arm",
38697    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38698)]
38699pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
38700    unsafe extern "unadjusted" {
38701        #[cfg_attr(
38702            any(target_arch = "aarch64", target_arch = "arm64ec"),
38703            link_name = "llvm.aarch64.neon.sqneg.v2i32"
38704        )]
38705        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")]
38706        fn _vqneg_s32(a: int32x2_t) -> int32x2_t;
38707    }
38708    unsafe { _vqneg_s32(a) }
38709}
38710#[doc = "Signed saturating negate"]
38711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
38712#[inline]
38713#[target_feature(enable = "neon")]
38714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38716#[cfg_attr(
38717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38718    assert_instr(sqneg)
38719)]
38720#[cfg_attr(
38721    not(target_arch = "arm"),
38722    stable(feature = "neon_intrinsics", since = "1.59.0")
38723)]
38724#[cfg_attr(
38725    target_arch = "arm",
38726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38727)]
38728pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
38729    unsafe extern "unadjusted" {
38730        #[cfg_attr(
38731            any(target_arch = "aarch64", target_arch = "arm64ec"),
38732            link_name = "llvm.aarch64.neon.sqneg.v4i32"
38733        )]
38734        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")]
38735        fn _vqnegq_s32(a: int32x4_t) -> int32x4_t;
38736    }
38737    unsafe { _vqnegq_s32(a) }
38738}
38739#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
38741#[inline]
38742#[target_feature(enable = "neon")]
38743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38745#[cfg_attr(
38746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38747    assert_instr(sqrdmulh, LANE = 1)
38748)]
38749#[rustc_legacy_const_generics(2)]
38750#[cfg_attr(
38751    not(target_arch = "arm"),
38752    stable(feature = "neon_intrinsics", since = "1.59.0")
38753)]
38754#[cfg_attr(
38755    target_arch = "arm",
38756    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38757)]
38758pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38759    static_assert_uimm_bits!(LANE, 2);
38760    unsafe {
38761        let b: int16x4_t =
38762            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38763        vqrdmulh_s16(a, b)
38764    }
38765}
38766#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
38768#[inline]
38769#[target_feature(enable = "neon")]
38770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38772#[cfg_attr(
38773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38774    assert_instr(sqrdmulh, LANE = 1)
38775)]
38776#[rustc_legacy_const_generics(2)]
38777#[cfg_attr(
38778    not(target_arch = "arm"),
38779    stable(feature = "neon_intrinsics", since = "1.59.0")
38780)]
38781#[cfg_attr(
38782    target_arch = "arm",
38783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38784)]
38785pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38786    static_assert_uimm_bits!(LANE, 1);
38787    unsafe {
38788        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38789        vqrdmulh_s32(a, b)
38790    }
38791}
38792#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
38794#[inline]
38795#[target_feature(enable = "neon")]
38796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38798#[cfg_attr(
38799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38800    assert_instr(sqrdmulh, LANE = 1)
38801)]
38802#[rustc_legacy_const_generics(2)]
38803#[cfg_attr(
38804    not(target_arch = "arm"),
38805    stable(feature = "neon_intrinsics", since = "1.59.0")
38806)]
38807#[cfg_attr(
38808    target_arch = "arm",
38809    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38810)]
38811pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
38812    static_assert_uimm_bits!(LANE, 3);
38813    unsafe {
38814        let b: int16x4_t =
38815            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38816        vqrdmulh_s16(a, b)
38817    }
38818}
38819#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
38821#[inline]
38822#[target_feature(enable = "neon")]
38823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38825#[cfg_attr(
38826    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38827    assert_instr(sqrdmulh, LANE = 1)
38828)]
38829#[rustc_legacy_const_generics(2)]
38830#[cfg_attr(
38831    not(target_arch = "arm"),
38832    stable(feature = "neon_intrinsics", since = "1.59.0")
38833)]
38834#[cfg_attr(
38835    target_arch = "arm",
38836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38837)]
38838pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
38839    static_assert_uimm_bits!(LANE, 2);
38840    unsafe {
38841        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38842        vqrdmulh_s32(a, b)
38843    }
38844}
38845#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
38847#[inline]
38848#[target_feature(enable = "neon")]
38849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38851#[cfg_attr(
38852    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38853    assert_instr(sqrdmulh, LANE = 1)
38854)]
38855#[rustc_legacy_const_generics(2)]
38856#[cfg_attr(
38857    not(target_arch = "arm"),
38858    stable(feature = "neon_intrinsics", since = "1.59.0")
38859)]
38860#[cfg_attr(
38861    target_arch = "arm",
38862    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38863)]
38864pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
38865    static_assert_uimm_bits!(LANE, 2);
38866    unsafe {
38867        let b: int16x8_t = simd_shuffle!(
38868            b,
38869            b,
38870            [
38871                LANE as u32,
38872                LANE as u32,
38873                LANE as u32,
38874                LANE as u32,
38875                LANE as u32,
38876                LANE as u32,
38877                LANE as u32,
38878                LANE as u32
38879            ]
38880        );
38881        vqrdmulhq_s16(a, b)
38882    }
38883}
38884#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
38886#[inline]
38887#[target_feature(enable = "neon")]
38888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38890#[cfg_attr(
38891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38892    assert_instr(sqrdmulh, LANE = 1)
38893)]
38894#[rustc_legacy_const_generics(2)]
38895#[cfg_attr(
38896    not(target_arch = "arm"),
38897    stable(feature = "neon_intrinsics", since = "1.59.0")
38898)]
38899#[cfg_attr(
38900    target_arch = "arm",
38901    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38902)]
38903pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
38904    static_assert_uimm_bits!(LANE, 1);
38905    unsafe {
38906        let b: int32x4_t =
38907            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38908        vqrdmulhq_s32(a, b)
38909    }
38910}
38911#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
38913#[inline]
38914#[target_feature(enable = "neon")]
38915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38917#[cfg_attr(
38918    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38919    assert_instr(sqrdmulh, LANE = 1)
38920)]
38921#[rustc_legacy_const_generics(2)]
38922#[cfg_attr(
38923    not(target_arch = "arm"),
38924    stable(feature = "neon_intrinsics", since = "1.59.0")
38925)]
38926#[cfg_attr(
38927    target_arch = "arm",
38928    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38929)]
38930pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38931    static_assert_uimm_bits!(LANE, 3);
38932    unsafe {
38933        let b: int16x8_t = simd_shuffle!(
38934            b,
38935            b,
38936            [
38937                LANE as u32,
38938                LANE as u32,
38939                LANE as u32,
38940                LANE as u32,
38941                LANE as u32,
38942                LANE as u32,
38943                LANE as u32,
38944                LANE as u32
38945            ]
38946        );
38947        vqrdmulhq_s16(a, b)
38948    }
38949}
38950#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
38952#[inline]
38953#[target_feature(enable = "neon")]
38954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38956#[cfg_attr(
38957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38958    assert_instr(sqrdmulh, LANE = 1)
38959)]
38960#[rustc_legacy_const_generics(2)]
38961#[cfg_attr(
38962    not(target_arch = "arm"),
38963    stable(feature = "neon_intrinsics", since = "1.59.0")
38964)]
38965#[cfg_attr(
38966    target_arch = "arm",
38967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38968)]
38969pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38970    static_assert_uimm_bits!(LANE, 2);
38971    unsafe {
38972        let b: int32x4_t =
38973            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38974        vqrdmulhq_s32(a, b)
38975    }
38976}
38977#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
38979#[inline]
38980#[target_feature(enable = "neon")]
38981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38983#[cfg_attr(
38984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38985    assert_instr(sqrdmulh)
38986)]
38987#[cfg_attr(
38988    not(target_arch = "arm"),
38989    stable(feature = "neon_intrinsics", since = "1.59.0")
38990)]
38991#[cfg_attr(
38992    target_arch = "arm",
38993    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38994)]
38995pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
38996    vqrdmulh_s16(a, vdup_n_s16(b))
38997}
38998#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
39000#[inline]
39001#[target_feature(enable = "neon")]
39002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39004#[cfg_attr(
39005    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39006    assert_instr(sqrdmulh)
39007)]
39008#[cfg_attr(
39009    not(target_arch = "arm"),
39010    stable(feature = "neon_intrinsics", since = "1.59.0")
39011)]
39012#[cfg_attr(
39013    target_arch = "arm",
39014    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39015)]
39016pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
39017    vqrdmulhq_s16(a, vdupq_n_s16(b))
39018}
39019#[doc = "Vector saturating rounding doubling multiply high with scalar"]
39020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
39021#[inline]
39022#[target_feature(enable = "neon")]
39023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39025#[cfg_attr(
39026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39027    assert_instr(sqrdmulh)
39028)]
39029#[cfg_attr(
39030    not(target_arch = "arm"),
39031    stable(feature = "neon_intrinsics", since = "1.59.0")
39032)]
39033#[cfg_attr(
39034    target_arch = "arm",
39035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39036)]
39037pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
39038    vqrdmulh_s32(a, vdup_n_s32(b))
39039}
39040#[doc = "Vector saturating rounding doubling multiply high with scalar"]
39041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
39042#[inline]
39043#[target_feature(enable = "neon")]
39044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39046#[cfg_attr(
39047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39048    assert_instr(sqrdmulh)
39049)]
39050#[cfg_attr(
39051    not(target_arch = "arm"),
39052    stable(feature = "neon_intrinsics", since = "1.59.0")
39053)]
39054#[cfg_attr(
39055    target_arch = "arm",
39056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39057)]
39058pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
39059    vqrdmulhq_s32(a, vdupq_n_s32(b))
39060}
39061#[doc = "Signed saturating rounding doubling multiply returning high half"]
39062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
39063#[inline]
39064#[target_feature(enable = "neon")]
39065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39067#[cfg_attr(
39068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39069    assert_instr(sqrdmulh)
39070)]
39071#[cfg_attr(
39072    not(target_arch = "arm"),
39073    stable(feature = "neon_intrinsics", since = "1.59.0")
39074)]
39075#[cfg_attr(
39076    target_arch = "arm",
39077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39078)]
39079pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
39080    unsafe extern "unadjusted" {
39081        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")]
39082        #[cfg_attr(
39083            any(target_arch = "aarch64", target_arch = "arm64ec"),
39084            link_name = "llvm.aarch64.neon.sqrdmulh.v4i16"
39085        )]
39086        fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39087    }
39088    unsafe { _vqrdmulh_s16(a, b) }
39089}
39090#[doc = "Signed saturating rounding doubling multiply returning high half"]
39091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
39092#[inline]
39093#[target_feature(enable = "neon")]
39094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39096#[cfg_attr(
39097    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39098    assert_instr(sqrdmulh)
39099)]
39100#[cfg_attr(
39101    not(target_arch = "arm"),
39102    stable(feature = "neon_intrinsics", since = "1.59.0")
39103)]
39104#[cfg_attr(
39105    target_arch = "arm",
39106    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39107)]
39108pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39109    unsafe extern "unadjusted" {
39110        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")]
39111        #[cfg_attr(
39112            any(target_arch = "aarch64", target_arch = "arm64ec"),
39113            link_name = "llvm.aarch64.neon.sqrdmulh.v8i16"
39114        )]
39115        fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39116    }
39117    unsafe { _vqrdmulhq_s16(a, b) }
39118}
39119#[doc = "Signed saturating rounding doubling multiply returning high half"]
39120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
39121#[inline]
39122#[target_feature(enable = "neon")]
39123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39125#[cfg_attr(
39126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39127    assert_instr(sqrdmulh)
39128)]
39129#[cfg_attr(
39130    not(target_arch = "arm"),
39131    stable(feature = "neon_intrinsics", since = "1.59.0")
39132)]
39133#[cfg_attr(
39134    target_arch = "arm",
39135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39136)]
39137pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39138    unsafe extern "unadjusted" {
39139        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")]
39140        #[cfg_attr(
39141            any(target_arch = "aarch64", target_arch = "arm64ec"),
39142            link_name = "llvm.aarch64.neon.sqrdmulh.v2i32"
39143        )]
39144        fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39145    }
39146    unsafe { _vqrdmulh_s32(a, b) }
39147}
39148#[doc = "Signed saturating rounding doubling multiply returning high half"]
39149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
39150#[inline]
39151#[target_feature(enable = "neon")]
39152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39154#[cfg_attr(
39155    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39156    assert_instr(sqrdmulh)
39157)]
39158#[cfg_attr(
39159    not(target_arch = "arm"),
39160    stable(feature = "neon_intrinsics", since = "1.59.0")
39161)]
39162#[cfg_attr(
39163    target_arch = "arm",
39164    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39165)]
39166pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39167    unsafe extern "unadjusted" {
39168        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")]
39169        #[cfg_attr(
39170            any(target_arch = "aarch64", target_arch = "arm64ec"),
39171            link_name = "llvm.aarch64.neon.sqrdmulh.v4i32"
39172        )]
39173        fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39174    }
39175    unsafe { _vqrdmulhq_s32(a, b) }
39176}
39177#[doc = "Signed saturating rounding shift left"]
39178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
39179#[inline]
39180#[target_feature(enable = "neon")]
39181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39183#[cfg_attr(
39184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39185    assert_instr(sqrshl)
39186)]
39187#[cfg_attr(
39188    not(target_arch = "arm"),
39189    stable(feature = "neon_intrinsics", since = "1.59.0")
39190)]
39191#[cfg_attr(
39192    target_arch = "arm",
39193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39194)]
39195pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
39196    unsafe extern "unadjusted" {
39197        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")]
39198        #[cfg_attr(
39199            any(target_arch = "aarch64", target_arch = "arm64ec"),
39200            link_name = "llvm.aarch64.neon.sqrshl.v8i8"
39201        )]
39202        fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
39203    }
39204    unsafe { _vqrshl_s8(a, b) }
39205}
39206#[doc = "Signed saturating rounding shift left"]
39207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
39208#[inline]
39209#[target_feature(enable = "neon")]
39210#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39212#[cfg_attr(
39213    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39214    assert_instr(sqrshl)
39215)]
39216#[cfg_attr(
39217    not(target_arch = "arm"),
39218    stable(feature = "neon_intrinsics", since = "1.59.0")
39219)]
39220#[cfg_attr(
39221    target_arch = "arm",
39222    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39223)]
39224pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
39225    unsafe extern "unadjusted" {
39226        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")]
39227        #[cfg_attr(
39228            any(target_arch = "aarch64", target_arch = "arm64ec"),
39229            link_name = "llvm.aarch64.neon.sqrshl.v16i8"
39230        )]
39231        fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
39232    }
39233    unsafe { _vqrshlq_s8(a, b) }
39234}
39235#[doc = "Signed saturating rounding shift left"]
39236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
39237#[inline]
39238#[target_feature(enable = "neon")]
39239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39241#[cfg_attr(
39242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39243    assert_instr(sqrshl)
39244)]
39245#[cfg_attr(
39246    not(target_arch = "arm"),
39247    stable(feature = "neon_intrinsics", since = "1.59.0")
39248)]
39249#[cfg_attr(
39250    target_arch = "arm",
39251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39252)]
39253pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
39254    unsafe extern "unadjusted" {
39255        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")]
39256        #[cfg_attr(
39257            any(target_arch = "aarch64", target_arch = "arm64ec"),
39258            link_name = "llvm.aarch64.neon.sqrshl.v4i16"
39259        )]
39260        fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39261    }
39262    unsafe { _vqrshl_s16(a, b) }
39263}
39264#[doc = "Signed saturating rounding shift left"]
39265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
39266#[inline]
39267#[target_feature(enable = "neon")]
39268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39270#[cfg_attr(
39271    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39272    assert_instr(sqrshl)
39273)]
39274#[cfg_attr(
39275    not(target_arch = "arm"),
39276    stable(feature = "neon_intrinsics", since = "1.59.0")
39277)]
39278#[cfg_attr(
39279    target_arch = "arm",
39280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39281)]
39282pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39283    unsafe extern "unadjusted" {
39284        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")]
39285        #[cfg_attr(
39286            any(target_arch = "aarch64", target_arch = "arm64ec"),
39287            link_name = "llvm.aarch64.neon.sqrshl.v8i16"
39288        )]
39289        fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39290    }
39291    unsafe { _vqrshlq_s16(a, b) }
39292}
39293#[doc = "Signed saturating rounding shift left"]
39294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
39295#[inline]
39296#[target_feature(enable = "neon")]
39297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39299#[cfg_attr(
39300    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39301    assert_instr(sqrshl)
39302)]
39303#[cfg_attr(
39304    not(target_arch = "arm"),
39305    stable(feature = "neon_intrinsics", since = "1.59.0")
39306)]
39307#[cfg_attr(
39308    target_arch = "arm",
39309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39310)]
39311pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39312    unsafe extern "unadjusted" {
39313        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")]
39314        #[cfg_attr(
39315            any(target_arch = "aarch64", target_arch = "arm64ec"),
39316            link_name = "llvm.aarch64.neon.sqrshl.v2i32"
39317        )]
39318        fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39319    }
39320    unsafe { _vqrshl_s32(a, b) }
39321}
39322#[doc = "Signed saturating rounding shift left"]
39323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
39324#[inline]
39325#[target_feature(enable = "neon")]
39326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39328#[cfg_attr(
39329    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39330    assert_instr(sqrshl)
39331)]
39332#[cfg_attr(
39333    not(target_arch = "arm"),
39334    stable(feature = "neon_intrinsics", since = "1.59.0")
39335)]
39336#[cfg_attr(
39337    target_arch = "arm",
39338    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39339)]
39340pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39341    unsafe extern "unadjusted" {
39342        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")]
39343        #[cfg_attr(
39344            any(target_arch = "aarch64", target_arch = "arm64ec"),
39345            link_name = "llvm.aarch64.neon.sqrshl.v4i32"
39346        )]
39347        fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39348    }
39349    unsafe { _vqrshlq_s32(a, b) }
39350}
39351#[doc = "Signed saturating rounding shift left"]
39352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
39353#[inline]
39354#[target_feature(enable = "neon")]
39355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39357#[cfg_attr(
39358    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39359    assert_instr(sqrshl)
39360)]
39361#[cfg_attr(
39362    not(target_arch = "arm"),
39363    stable(feature = "neon_intrinsics", since = "1.59.0")
39364)]
39365#[cfg_attr(
39366    target_arch = "arm",
39367    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39368)]
39369pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
39370    unsafe extern "unadjusted" {
39371        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")]
39372        #[cfg_attr(
39373            any(target_arch = "aarch64", target_arch = "arm64ec"),
39374            link_name = "llvm.aarch64.neon.sqrshl.v1i64"
39375        )]
39376        fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
39377    }
39378    unsafe { _vqrshl_s64(a, b) }
39379}
39380#[doc = "Signed saturating rounding shift left"]
39381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
39382#[inline]
39383#[target_feature(enable = "neon")]
39384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39386#[cfg_attr(
39387    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39388    assert_instr(sqrshl)
39389)]
39390#[cfg_attr(
39391    not(target_arch = "arm"),
39392    stable(feature = "neon_intrinsics", since = "1.59.0")
39393)]
39394#[cfg_attr(
39395    target_arch = "arm",
39396    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39397)]
39398pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
39399    unsafe extern "unadjusted" {
39400        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")]
39401        #[cfg_attr(
39402            any(target_arch = "aarch64", target_arch = "arm64ec"),
39403            link_name = "llvm.aarch64.neon.sqrshl.v2i64"
39404        )]
39405        fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
39406    }
39407    unsafe { _vqrshlq_s64(a, b) }
39408}
39409#[doc = "Unsigned signed saturating rounding shift left"]
39410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
39411#[inline]
39412#[target_feature(enable = "neon")]
39413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39415#[cfg_attr(
39416    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39417    assert_instr(uqrshl)
39418)]
39419#[cfg_attr(
39420    not(target_arch = "arm"),
39421    stable(feature = "neon_intrinsics", since = "1.59.0")
39422)]
39423#[cfg_attr(
39424    target_arch = "arm",
39425    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39426)]
39427pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
39428    unsafe extern "unadjusted" {
39429        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")]
39430        #[cfg_attr(
39431            any(target_arch = "aarch64", target_arch = "arm64ec"),
39432            link_name = "llvm.aarch64.neon.uqrshl.v8i8"
39433        )]
39434        fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
39435    }
39436    unsafe { _vqrshl_u8(a, b) }
39437}
39438#[doc = "Unsigned signed saturating rounding shift left"]
39439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
39440#[inline]
39441#[target_feature(enable = "neon")]
39442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39444#[cfg_attr(
39445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39446    assert_instr(uqrshl)
39447)]
39448#[cfg_attr(
39449    not(target_arch = "arm"),
39450    stable(feature = "neon_intrinsics", since = "1.59.0")
39451)]
39452#[cfg_attr(
39453    target_arch = "arm",
39454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39455)]
39456pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
39457    unsafe extern "unadjusted" {
39458        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")]
39459        #[cfg_attr(
39460            any(target_arch = "aarch64", target_arch = "arm64ec"),
39461            link_name = "llvm.aarch64.neon.uqrshl.v16i8"
39462        )]
39463        fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
39464    }
39465    unsafe { _vqrshlq_u8(a, b) }
39466}
39467#[doc = "Unsigned signed saturating rounding shift left"]
39468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
39469#[inline]
39470#[target_feature(enable = "neon")]
39471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39473#[cfg_attr(
39474    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39475    assert_instr(uqrshl)
39476)]
39477#[cfg_attr(
39478    not(target_arch = "arm"),
39479    stable(feature = "neon_intrinsics", since = "1.59.0")
39480)]
39481#[cfg_attr(
39482    target_arch = "arm",
39483    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39484)]
39485pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
39486    unsafe extern "unadjusted" {
39487        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")]
39488        #[cfg_attr(
39489            any(target_arch = "aarch64", target_arch = "arm64ec"),
39490            link_name = "llvm.aarch64.neon.uqrshl.v4i16"
39491        )]
39492        fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
39493    }
39494    unsafe { _vqrshl_u16(a, b) }
39495}
39496#[doc = "Unsigned signed saturating rounding shift left"]
39497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
39498#[inline]
39499#[target_feature(enable = "neon")]
39500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39502#[cfg_attr(
39503    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39504    assert_instr(uqrshl)
39505)]
39506#[cfg_attr(
39507    not(target_arch = "arm"),
39508    stable(feature = "neon_intrinsics", since = "1.59.0")
39509)]
39510#[cfg_attr(
39511    target_arch = "arm",
39512    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39513)]
39514pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
39515    unsafe extern "unadjusted" {
39516        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")]
39517        #[cfg_attr(
39518            any(target_arch = "aarch64", target_arch = "arm64ec"),
39519            link_name = "llvm.aarch64.neon.uqrshl.v8i16"
39520        )]
39521        fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
39522    }
39523    unsafe { _vqrshlq_u16(a, b) }
39524}
39525#[doc = "Unsigned signed saturating rounding shift left"]
39526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
39527#[inline]
39528#[target_feature(enable = "neon")]
39529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39531#[cfg_attr(
39532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39533    assert_instr(uqrshl)
39534)]
39535#[cfg_attr(
39536    not(target_arch = "arm"),
39537    stable(feature = "neon_intrinsics", since = "1.59.0")
39538)]
39539#[cfg_attr(
39540    target_arch = "arm",
39541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39542)]
39543pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
39544    unsafe extern "unadjusted" {
39545        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")]
39546        #[cfg_attr(
39547            any(target_arch = "aarch64", target_arch = "arm64ec"),
39548            link_name = "llvm.aarch64.neon.uqrshl.v2i32"
39549        )]
39550        fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
39551    }
39552    unsafe { _vqrshl_u32(a, b) }
39553}
39554#[doc = "Unsigned signed saturating rounding shift left"]
39555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
39556#[inline]
39557#[target_feature(enable = "neon")]
39558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39560#[cfg_attr(
39561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39562    assert_instr(uqrshl)
39563)]
39564#[cfg_attr(
39565    not(target_arch = "arm"),
39566    stable(feature = "neon_intrinsics", since = "1.59.0")
39567)]
39568#[cfg_attr(
39569    target_arch = "arm",
39570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39571)]
39572pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
39573    unsafe extern "unadjusted" {
39574        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")]
39575        #[cfg_attr(
39576            any(target_arch = "aarch64", target_arch = "arm64ec"),
39577            link_name = "llvm.aarch64.neon.uqrshl.v4i32"
39578        )]
39579        fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
39580    }
39581    unsafe { _vqrshlq_u32(a, b) }
39582}
39583#[doc = "Unsigned signed saturating rounding shift left"]
39584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
39585#[inline]
39586#[target_feature(enable = "neon")]
39587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39589#[cfg_attr(
39590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39591    assert_instr(uqrshl)
39592)]
39593#[cfg_attr(
39594    not(target_arch = "arm"),
39595    stable(feature = "neon_intrinsics", since = "1.59.0")
39596)]
39597#[cfg_attr(
39598    target_arch = "arm",
39599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39600)]
39601pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
39602    unsafe extern "unadjusted" {
39603        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")]
39604        #[cfg_attr(
39605            any(target_arch = "aarch64", target_arch = "arm64ec"),
39606            link_name = "llvm.aarch64.neon.uqrshl.v1i64"
39607        )]
39608        fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
39609    }
39610    unsafe { _vqrshl_u64(a, b) }
39611}
39612#[doc = "Unsigned signed saturating rounding shift left"]
39613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
39614#[inline]
39615#[target_feature(enable = "neon")]
39616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39618#[cfg_attr(
39619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39620    assert_instr(uqrshl)
39621)]
39622#[cfg_attr(
39623    not(target_arch = "arm"),
39624    stable(feature = "neon_intrinsics", since = "1.59.0")
39625)]
39626#[cfg_attr(
39627    target_arch = "arm",
39628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39629)]
39630pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
39631    unsafe extern "unadjusted" {
39632        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")]
39633        #[cfg_attr(
39634            any(target_arch = "aarch64", target_arch = "arm64ec"),
39635            link_name = "llvm.aarch64.neon.uqrshl.v2i64"
39636        )]
39637        fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
39638    }
39639    unsafe { _vqrshlq_u64(a, b) }
39640}
39641#[doc = "Signed saturating rounded shift right narrow"]
39642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39643#[inline]
39644#[cfg(target_arch = "arm")]
39645#[target_feature(enable = "neon,v7")]
39646#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39647#[rustc_legacy_const_generics(1)]
39648#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39649pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39650    static_assert!(N >= 1 && N <= 8);
39651    unsafe extern "unadjusted" {
39652        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
39653        fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
39654    }
39655    unsafe {
39656        _vqrshrn_n_s16(
39657            a,
39658            const {
39659                int16x8_t([
39660                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39661                    -N as i16,
39662                ])
39663            },
39664        )
39665    }
39666}
39667#[doc = "Signed saturating rounded shift right narrow"]
39668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39669#[inline]
39670#[cfg(target_arch = "arm")]
39671#[target_feature(enable = "neon,v7")]
39672#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39673#[rustc_legacy_const_generics(1)]
39674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39675pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39676    static_assert!(N >= 1 && N <= 16);
39677    unsafe extern "unadjusted" {
39678        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
39679        fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
39680    }
39681    unsafe {
39682        _vqrshrn_n_s32(
39683            a,
39684            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39685        )
39686    }
39687}
39688#[doc = "Signed saturating rounded shift right narrow"]
39689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39690#[inline]
39691#[cfg(target_arch = "arm")]
39692#[target_feature(enable = "neon,v7")]
39693#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39694#[rustc_legacy_const_generics(1)]
39695#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39696pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39697    static_assert!(N >= 1 && N <= 32);
39698    unsafe extern "unadjusted" {
39699        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
39700        fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
39701    }
39702    unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39703}
39704#[doc = "Signed saturating rounded shift right narrow"]
39705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39706#[inline]
39707#[target_feature(enable = "neon")]
39708#[cfg(not(target_arch = "arm"))]
39709#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39710#[rustc_legacy_const_generics(1)]
39711#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39712pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39713    static_assert!(N >= 1 && N <= 8);
39714    unsafe extern "unadjusted" {
39715        #[cfg_attr(
39716            any(target_arch = "aarch64", target_arch = "arm64ec"),
39717            link_name = "llvm.aarch64.neon.sqrshrn.v8i8"
39718        )]
39719        fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
39720    }
39721    unsafe { _vqrshrn_n_s16(a, N) }
39722}
39723#[doc = "Signed saturating rounded shift right narrow"]
39724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39725#[inline]
39726#[target_feature(enable = "neon")]
39727#[cfg(not(target_arch = "arm"))]
39728#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39729#[rustc_legacy_const_generics(1)]
39730#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39731pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39732    static_assert!(N >= 1 && N <= 16);
39733    unsafe extern "unadjusted" {
39734        #[cfg_attr(
39735            any(target_arch = "aarch64", target_arch = "arm64ec"),
39736            link_name = "llvm.aarch64.neon.sqrshrn.v4i16"
39737        )]
39738        fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
39739    }
39740    unsafe { _vqrshrn_n_s32(a, N) }
39741}
39742#[doc = "Signed saturating rounded shift right narrow"]
39743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39744#[inline]
39745#[target_feature(enable = "neon")]
39746#[cfg(not(target_arch = "arm"))]
39747#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39748#[rustc_legacy_const_generics(1)]
39749#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39750pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39751    static_assert!(N >= 1 && N <= 32);
39752    unsafe extern "unadjusted" {
39753        #[cfg_attr(
39754            any(target_arch = "aarch64", target_arch = "arm64ec"),
39755            link_name = "llvm.aarch64.neon.sqrshrn.v2i32"
39756        )]
39757        fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
39758    }
39759    unsafe { _vqrshrn_n_s64(a, N) }
39760}
39761#[doc = "Unsigned signed saturating rounded shift right narrow"]
39762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39763#[inline]
39764#[cfg(target_arch = "arm")]
39765#[target_feature(enable = "neon,v7")]
39766#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39767#[rustc_legacy_const_generics(1)]
39768#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39769pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39770    static_assert!(N >= 1 && N <= 8);
39771    unsafe extern "unadjusted" {
39772        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
39773        fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
39774    }
39775    unsafe {
39776        _vqrshrn_n_u16(
39777            a,
39778            const {
39779                uint16x8_t([
39780                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
39781                    -N as u16,
39782                ])
39783            },
39784        )
39785    }
39786}
39787#[doc = "Unsigned signed saturating rounded shift right narrow"]
39788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39789#[inline]
39790#[cfg(target_arch = "arm")]
39791#[target_feature(enable = "neon,v7")]
39792#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39793#[rustc_legacy_const_generics(1)]
39794#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39795pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39796    static_assert!(N >= 1 && N <= 16);
39797    unsafe extern "unadjusted" {
39798        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
39799        fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
39800    }
39801    unsafe {
39802        _vqrshrn_n_u32(
39803            a,
39804            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
39805        )
39806    }
39807}
39808#[doc = "Unsigned signed saturating rounded shift right narrow"]
39809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39810#[inline]
39811#[cfg(target_arch = "arm")]
39812#[target_feature(enable = "neon,v7")]
39813#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39814#[rustc_legacy_const_generics(1)]
39815#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39816pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39817    static_assert!(N >= 1 && N <= 32);
39818    unsafe extern "unadjusted" {
39819        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
39820        fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
39821    }
39822    unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
39823}
39824#[doc = "Unsigned signed saturating rounded shift right narrow"]
39825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39826#[inline]
39827#[target_feature(enable = "neon")]
39828#[cfg(not(target_arch = "arm"))]
39829#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39830#[rustc_legacy_const_generics(1)]
39831#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39832pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39833    static_assert!(N >= 1 && N <= 8);
39834    unsafe extern "unadjusted" {
39835        #[cfg_attr(
39836            any(target_arch = "aarch64", target_arch = "arm64ec"),
39837            link_name = "llvm.aarch64.neon.uqrshrn.v8i8"
39838        )]
39839        fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
39840    }
39841    unsafe { _vqrshrn_n_u16(a, N) }
39842}
39843#[doc = "Unsigned signed saturating rounded shift right narrow"]
39844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39845#[inline]
39846#[target_feature(enable = "neon")]
39847#[cfg(not(target_arch = "arm"))]
39848#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39849#[rustc_legacy_const_generics(1)]
39850#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39851pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39852    static_assert!(N >= 1 && N <= 16);
39853    unsafe extern "unadjusted" {
39854        #[cfg_attr(
39855            any(target_arch = "aarch64", target_arch = "arm64ec"),
39856            link_name = "llvm.aarch64.neon.uqrshrn.v4i16"
39857        )]
39858        fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
39859    }
39860    unsafe { _vqrshrn_n_u32(a, N) }
39861}
39862#[doc = "Unsigned signed saturating rounded shift right narrow"]
39863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39864#[inline]
39865#[target_feature(enable = "neon")]
39866#[cfg(not(target_arch = "arm"))]
39867#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39868#[rustc_legacy_const_generics(1)]
39869#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39870pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39871    static_assert!(N >= 1 && N <= 32);
39872    unsafe extern "unadjusted" {
39873        #[cfg_attr(
39874            any(target_arch = "aarch64", target_arch = "arm64ec"),
39875            link_name = "llvm.aarch64.neon.uqrshrn.v2i32"
39876        )]
39877        fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
39878    }
39879    unsafe { _vqrshrn_n_u64(a, N) }
39880}
39881#[doc = "Signed saturating rounded shift right unsigned narrow"]
39882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39883#[inline]
39884#[cfg(target_arch = "arm")]
39885#[target_feature(enable = "neon,v7")]
39886#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39887#[rustc_legacy_const_generics(1)]
39888#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39889pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39890    static_assert!(N >= 1 && N <= 8);
39891    unsafe extern "unadjusted" {
39892        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
39893        fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
39894    }
39895    unsafe {
39896        _vqrshrun_n_s16(
39897            a,
39898            const {
39899                int16x8_t([
39900                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39901                    -N as i16,
39902                ])
39903            },
39904        )
39905    }
39906}
39907#[doc = "Signed saturating rounded shift right unsigned narrow"]
39908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39909#[inline]
39910#[cfg(target_arch = "arm")]
39911#[target_feature(enable = "neon,v7")]
39912#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39913#[rustc_legacy_const_generics(1)]
39914#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39915pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39916    static_assert!(N >= 1 && N <= 16);
39917    unsafe extern "unadjusted" {
39918        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
39919        fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
39920    }
39921    unsafe {
39922        _vqrshrun_n_s32(
39923            a,
39924            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39925        )
39926    }
39927}
39928#[doc = "Signed saturating rounded shift right unsigned narrow"]
39929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39930#[inline]
39931#[cfg(target_arch = "arm")]
39932#[target_feature(enable = "neon,v7")]
39933#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39934#[rustc_legacy_const_generics(1)]
39935#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39936pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39937    static_assert!(N >= 1 && N <= 32);
39938    unsafe extern "unadjusted" {
39939        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
39940        fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
39941    }
39942    unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39943}
39944#[doc = "Signed saturating rounded shift right unsigned narrow"]
39945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39946#[inline]
39947#[target_feature(enable = "neon")]
39948#[cfg(not(target_arch = "arm"))]
39949#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39950#[rustc_legacy_const_generics(1)]
39951#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39952pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39953    static_assert!(N >= 1 && N <= 8);
39954    unsafe extern "unadjusted" {
39955        #[cfg_attr(
39956            any(target_arch = "aarch64", target_arch = "arm64ec"),
39957            link_name = "llvm.aarch64.neon.sqrshrun.v8i8"
39958        )]
39959        fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
39960    }
39961    unsafe { _vqrshrun_n_s16(a, N) }
39962}
39963#[doc = "Signed saturating rounded shift right unsigned narrow"]
39964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39965#[inline]
39966#[target_feature(enable = "neon")]
39967#[cfg(not(target_arch = "arm"))]
39968#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39969#[rustc_legacy_const_generics(1)]
39970#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39971pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39972    static_assert!(N >= 1 && N <= 16);
39973    unsafe extern "unadjusted" {
39974        #[cfg_attr(
39975            any(target_arch = "aarch64", target_arch = "arm64ec"),
39976            link_name = "llvm.aarch64.neon.sqrshrun.v4i16"
39977        )]
39978        fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
39979    }
39980    unsafe { _vqrshrun_n_s32(a, N) }
39981}
39982#[doc = "Signed saturating rounded shift right unsigned narrow"]
39983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39984#[inline]
39985#[target_feature(enable = "neon")]
39986#[cfg(not(target_arch = "arm"))]
39987#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39988#[rustc_legacy_const_generics(1)]
39989#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39990pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39991    static_assert!(N >= 1 && N <= 32);
39992    unsafe extern "unadjusted" {
39993        #[cfg_attr(
39994            any(target_arch = "aarch64", target_arch = "arm64ec"),
39995            link_name = "llvm.aarch64.neon.sqrshrun.v2i32"
39996        )]
39997        fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
39998    }
39999    unsafe { _vqrshrun_n_s64(a, N) }
40000}
40001#[doc = "Signed saturating shift left"]
40002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
40003#[inline]
40004#[target_feature(enable = "neon")]
40005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40007#[cfg_attr(
40008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40009    assert_instr(sqshl, N = 2)
40010)]
40011#[rustc_legacy_const_generics(1)]
40012#[cfg_attr(
40013    not(target_arch = "arm"),
40014    stable(feature = "neon_intrinsics", since = "1.59.0")
40015)]
40016#[cfg_attr(
40017    target_arch = "arm",
40018    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40019)]
40020pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
40021    static_assert_uimm_bits!(N, 3);
40022    vqshl_s8(a, vdup_n_s8(N as _))
40023}
40024#[doc = "Signed saturating shift left"]
40025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
40026#[inline]
40027#[target_feature(enable = "neon")]
40028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40030#[cfg_attr(
40031    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40032    assert_instr(sqshl, N = 2)
40033)]
40034#[rustc_legacy_const_generics(1)]
40035#[cfg_attr(
40036    not(target_arch = "arm"),
40037    stable(feature = "neon_intrinsics", since = "1.59.0")
40038)]
40039#[cfg_attr(
40040    target_arch = "arm",
40041    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40042)]
40043pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
40044    static_assert_uimm_bits!(N, 3);
40045    vqshlq_s8(a, vdupq_n_s8(N as _))
40046}
40047#[doc = "Signed saturating shift left"]
40048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
40049#[inline]
40050#[target_feature(enable = "neon")]
40051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40053#[cfg_attr(
40054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40055    assert_instr(sqshl, N = 2)
40056)]
40057#[rustc_legacy_const_generics(1)]
40058#[cfg_attr(
40059    not(target_arch = "arm"),
40060    stable(feature = "neon_intrinsics", since = "1.59.0")
40061)]
40062#[cfg_attr(
40063    target_arch = "arm",
40064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40065)]
40066pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
40067    static_assert_uimm_bits!(N, 4);
40068    vqshl_s16(a, vdup_n_s16(N as _))
40069}
40070#[doc = "Signed saturating shift left"]
40071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
40072#[inline]
40073#[target_feature(enable = "neon")]
40074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40076#[cfg_attr(
40077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40078    assert_instr(sqshl, N = 2)
40079)]
40080#[rustc_legacy_const_generics(1)]
40081#[cfg_attr(
40082    not(target_arch = "arm"),
40083    stable(feature = "neon_intrinsics", since = "1.59.0")
40084)]
40085#[cfg_attr(
40086    target_arch = "arm",
40087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40088)]
40089pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
40090    static_assert_uimm_bits!(N, 4);
40091    vqshlq_s16(a, vdupq_n_s16(N as _))
40092}
40093#[doc = "Signed saturating shift left"]
40094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
40095#[inline]
40096#[target_feature(enable = "neon")]
40097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40099#[cfg_attr(
40100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40101    assert_instr(sqshl, N = 2)
40102)]
40103#[rustc_legacy_const_generics(1)]
40104#[cfg_attr(
40105    not(target_arch = "arm"),
40106    stable(feature = "neon_intrinsics", since = "1.59.0")
40107)]
40108#[cfg_attr(
40109    target_arch = "arm",
40110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40111)]
40112pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
40113    static_assert_uimm_bits!(N, 5);
40114    vqshl_s32(a, vdup_n_s32(N as _))
40115}
40116#[doc = "Signed saturating shift left"]
40117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
40118#[inline]
40119#[target_feature(enable = "neon")]
40120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40122#[cfg_attr(
40123    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40124    assert_instr(sqshl, N = 2)
40125)]
40126#[rustc_legacy_const_generics(1)]
40127#[cfg_attr(
40128    not(target_arch = "arm"),
40129    stable(feature = "neon_intrinsics", since = "1.59.0")
40130)]
40131#[cfg_attr(
40132    target_arch = "arm",
40133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40134)]
40135pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
40136    static_assert_uimm_bits!(N, 5);
40137    vqshlq_s32(a, vdupq_n_s32(N as _))
40138}
40139#[doc = "Signed saturating shift left"]
40140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
40141#[inline]
40142#[target_feature(enable = "neon")]
40143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40145#[cfg_attr(
40146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40147    assert_instr(sqshl, N = 2)
40148)]
40149#[rustc_legacy_const_generics(1)]
40150#[cfg_attr(
40151    not(target_arch = "arm"),
40152    stable(feature = "neon_intrinsics", since = "1.59.0")
40153)]
40154#[cfg_attr(
40155    target_arch = "arm",
40156    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40157)]
40158pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
40159    static_assert_uimm_bits!(N, 6);
40160    vqshl_s64(a, vdup_n_s64(N as _))
40161}
40162#[doc = "Signed saturating shift left"]
40163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
40164#[inline]
40165#[target_feature(enable = "neon")]
40166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40168#[cfg_attr(
40169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40170    assert_instr(sqshl, N = 2)
40171)]
40172#[rustc_legacy_const_generics(1)]
40173#[cfg_attr(
40174    not(target_arch = "arm"),
40175    stable(feature = "neon_intrinsics", since = "1.59.0")
40176)]
40177#[cfg_attr(
40178    target_arch = "arm",
40179    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40180)]
40181pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
40182    static_assert_uimm_bits!(N, 6);
40183    vqshlq_s64(a, vdupq_n_s64(N as _))
40184}
40185#[doc = "Unsigned saturating shift left"]
40186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
40187#[inline]
40188#[target_feature(enable = "neon")]
40189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40191#[cfg_attr(
40192    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40193    assert_instr(uqshl, N = 2)
40194)]
40195#[rustc_legacy_const_generics(1)]
40196#[cfg_attr(
40197    not(target_arch = "arm"),
40198    stable(feature = "neon_intrinsics", since = "1.59.0")
40199)]
40200#[cfg_attr(
40201    target_arch = "arm",
40202    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40203)]
40204pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
40205    static_assert_uimm_bits!(N, 3);
40206    vqshl_u8(a, vdup_n_s8(N as _))
40207}
40208#[doc = "Unsigned saturating shift left"]
40209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
40210#[inline]
40211#[target_feature(enable = "neon")]
40212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40214#[cfg_attr(
40215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40216    assert_instr(uqshl, N = 2)
40217)]
40218#[rustc_legacy_const_generics(1)]
40219#[cfg_attr(
40220    not(target_arch = "arm"),
40221    stable(feature = "neon_intrinsics", since = "1.59.0")
40222)]
40223#[cfg_attr(
40224    target_arch = "arm",
40225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40226)]
40227pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
40228    static_assert_uimm_bits!(N, 3);
40229    vqshlq_u8(a, vdupq_n_s8(N as _))
40230}
40231#[doc = "Unsigned saturating shift left"]
40232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
40233#[inline]
40234#[target_feature(enable = "neon")]
40235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40237#[cfg_attr(
40238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40239    assert_instr(uqshl, N = 2)
40240)]
40241#[rustc_legacy_const_generics(1)]
40242#[cfg_attr(
40243    not(target_arch = "arm"),
40244    stable(feature = "neon_intrinsics", since = "1.59.0")
40245)]
40246#[cfg_attr(
40247    target_arch = "arm",
40248    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40249)]
40250pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
40251    static_assert_uimm_bits!(N, 4);
40252    vqshl_u16(a, vdup_n_s16(N as _))
40253}
40254#[doc = "Unsigned saturating shift left"]
40255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
40256#[inline]
40257#[target_feature(enable = "neon")]
40258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40260#[cfg_attr(
40261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40262    assert_instr(uqshl, N = 2)
40263)]
40264#[rustc_legacy_const_generics(1)]
40265#[cfg_attr(
40266    not(target_arch = "arm"),
40267    stable(feature = "neon_intrinsics", since = "1.59.0")
40268)]
40269#[cfg_attr(
40270    target_arch = "arm",
40271    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40272)]
40273pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
40274    static_assert_uimm_bits!(N, 4);
40275    vqshlq_u16(a, vdupq_n_s16(N as _))
40276}
40277#[doc = "Unsigned saturating shift left"]
40278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
40279#[inline]
40280#[target_feature(enable = "neon")]
40281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40283#[cfg_attr(
40284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40285    assert_instr(uqshl, N = 2)
40286)]
40287#[rustc_legacy_const_generics(1)]
40288#[cfg_attr(
40289    not(target_arch = "arm"),
40290    stable(feature = "neon_intrinsics", since = "1.59.0")
40291)]
40292#[cfg_attr(
40293    target_arch = "arm",
40294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40295)]
40296pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
40297    static_assert_uimm_bits!(N, 5);
40298    vqshl_u32(a, vdup_n_s32(N as _))
40299}
40300#[doc = "Unsigned saturating shift left"]
40301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
40302#[inline]
40303#[target_feature(enable = "neon")]
40304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40306#[cfg_attr(
40307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40308    assert_instr(uqshl, N = 2)
40309)]
40310#[rustc_legacy_const_generics(1)]
40311#[cfg_attr(
40312    not(target_arch = "arm"),
40313    stable(feature = "neon_intrinsics", since = "1.59.0")
40314)]
40315#[cfg_attr(
40316    target_arch = "arm",
40317    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40318)]
40319pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
40320    static_assert_uimm_bits!(N, 5);
40321    vqshlq_u32(a, vdupq_n_s32(N as _))
40322}
40323#[doc = "Unsigned saturating shift left"]
40324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
40325#[inline]
40326#[target_feature(enable = "neon")]
40327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40329#[cfg_attr(
40330    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40331    assert_instr(uqshl, N = 2)
40332)]
40333#[rustc_legacy_const_generics(1)]
40334#[cfg_attr(
40335    not(target_arch = "arm"),
40336    stable(feature = "neon_intrinsics", since = "1.59.0")
40337)]
40338#[cfg_attr(
40339    target_arch = "arm",
40340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40341)]
40342pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
40343    static_assert_uimm_bits!(N, 6);
40344    vqshl_u64(a, vdup_n_s64(N as _))
40345}
40346#[doc = "Unsigned saturating shift left"]
40347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
40348#[inline]
40349#[target_feature(enable = "neon")]
40350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40352#[cfg_attr(
40353    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40354    assert_instr(uqshl, N = 2)
40355)]
40356#[rustc_legacy_const_generics(1)]
40357#[cfg_attr(
40358    not(target_arch = "arm"),
40359    stable(feature = "neon_intrinsics", since = "1.59.0")
40360)]
40361#[cfg_attr(
40362    target_arch = "arm",
40363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40364)]
40365pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
40366    static_assert_uimm_bits!(N, 6);
40367    vqshlq_u64(a, vdupq_n_s64(N as _))
40368}
40369#[doc = "Signed saturating shift left"]
40370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
40371#[inline]
40372#[target_feature(enable = "neon")]
40373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40375#[cfg_attr(
40376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40377    assert_instr(sqshl)
40378)]
40379#[cfg_attr(
40380    not(target_arch = "arm"),
40381    stable(feature = "neon_intrinsics", since = "1.59.0")
40382)]
40383#[cfg_attr(
40384    target_arch = "arm",
40385    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40386)]
40387pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
40388    unsafe extern "unadjusted" {
40389        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")]
40390        #[cfg_attr(
40391            any(target_arch = "aarch64", target_arch = "arm64ec"),
40392            link_name = "llvm.aarch64.neon.sqshl.v8i8"
40393        )]
40394        fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
40395    }
40396    unsafe { _vqshl_s8(a, b) }
40397}
40398#[doc = "Signed saturating shift left"]
40399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
40400#[inline]
40401#[target_feature(enable = "neon")]
40402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40404#[cfg_attr(
40405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40406    assert_instr(sqshl)
40407)]
40408#[cfg_attr(
40409    not(target_arch = "arm"),
40410    stable(feature = "neon_intrinsics", since = "1.59.0")
40411)]
40412#[cfg_attr(
40413    target_arch = "arm",
40414    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40415)]
40416pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
40417    unsafe extern "unadjusted" {
40418        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")]
40419        #[cfg_attr(
40420            any(target_arch = "aarch64", target_arch = "arm64ec"),
40421            link_name = "llvm.aarch64.neon.sqshl.v16i8"
40422        )]
40423        fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
40424    }
40425    unsafe { _vqshlq_s8(a, b) }
40426}
40427#[doc = "Signed saturating shift left"]
40428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
40429#[inline]
40430#[target_feature(enable = "neon")]
40431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40433#[cfg_attr(
40434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40435    assert_instr(sqshl)
40436)]
40437#[cfg_attr(
40438    not(target_arch = "arm"),
40439    stable(feature = "neon_intrinsics", since = "1.59.0")
40440)]
40441#[cfg_attr(
40442    target_arch = "arm",
40443    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40444)]
40445pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
40446    unsafe extern "unadjusted" {
40447        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")]
40448        #[cfg_attr(
40449            any(target_arch = "aarch64", target_arch = "arm64ec"),
40450            link_name = "llvm.aarch64.neon.sqshl.v4i16"
40451        )]
40452        fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
40453    }
40454    unsafe { _vqshl_s16(a, b) }
40455}
40456#[doc = "Signed saturating shift left"]
40457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
40458#[inline]
40459#[target_feature(enable = "neon")]
40460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40462#[cfg_attr(
40463    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40464    assert_instr(sqshl)
40465)]
40466#[cfg_attr(
40467    not(target_arch = "arm"),
40468    stable(feature = "neon_intrinsics", since = "1.59.0")
40469)]
40470#[cfg_attr(
40471    target_arch = "arm",
40472    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40473)]
40474pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
40475    unsafe extern "unadjusted" {
40476        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")]
40477        #[cfg_attr(
40478            any(target_arch = "aarch64", target_arch = "arm64ec"),
40479            link_name = "llvm.aarch64.neon.sqshl.v8i16"
40480        )]
40481        fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
40482    }
40483    unsafe { _vqshlq_s16(a, b) }
40484}
40485#[doc = "Signed saturating shift left"]
40486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
40487#[inline]
40488#[target_feature(enable = "neon")]
40489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40491#[cfg_attr(
40492    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40493    assert_instr(sqshl)
40494)]
40495#[cfg_attr(
40496    not(target_arch = "arm"),
40497    stable(feature = "neon_intrinsics", since = "1.59.0")
40498)]
40499#[cfg_attr(
40500    target_arch = "arm",
40501    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40502)]
40503pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
40504    unsafe extern "unadjusted" {
40505        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")]
40506        #[cfg_attr(
40507            any(target_arch = "aarch64", target_arch = "arm64ec"),
40508            link_name = "llvm.aarch64.neon.sqshl.v2i32"
40509        )]
40510        fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
40511    }
40512    unsafe { _vqshl_s32(a, b) }
40513}
40514#[doc = "Signed saturating shift left"]
40515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
40516#[inline]
40517#[target_feature(enable = "neon")]
40518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40520#[cfg_attr(
40521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40522    assert_instr(sqshl)
40523)]
40524#[cfg_attr(
40525    not(target_arch = "arm"),
40526    stable(feature = "neon_intrinsics", since = "1.59.0")
40527)]
40528#[cfg_attr(
40529    target_arch = "arm",
40530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40531)]
40532pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
40533    unsafe extern "unadjusted" {
40534        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")]
40535        #[cfg_attr(
40536            any(target_arch = "aarch64", target_arch = "arm64ec"),
40537            link_name = "llvm.aarch64.neon.sqshl.v4i32"
40538        )]
40539        fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
40540    }
40541    unsafe { _vqshlq_s32(a, b) }
40542}
40543#[doc = "Signed saturating shift left"]
40544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
40545#[inline]
40546#[target_feature(enable = "neon")]
40547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40549#[cfg_attr(
40550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40551    assert_instr(sqshl)
40552)]
40553#[cfg_attr(
40554    not(target_arch = "arm"),
40555    stable(feature = "neon_intrinsics", since = "1.59.0")
40556)]
40557#[cfg_attr(
40558    target_arch = "arm",
40559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40560)]
40561pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
40562    unsafe extern "unadjusted" {
40563        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")]
40564        #[cfg_attr(
40565            any(target_arch = "aarch64", target_arch = "arm64ec"),
40566            link_name = "llvm.aarch64.neon.sqshl.v1i64"
40567        )]
40568        fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
40569    }
40570    unsafe { _vqshl_s64(a, b) }
40571}
40572#[doc = "Signed saturating shift left"]
40573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
40574#[inline]
40575#[target_feature(enable = "neon")]
40576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40578#[cfg_attr(
40579    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40580    assert_instr(sqshl)
40581)]
40582#[cfg_attr(
40583    not(target_arch = "arm"),
40584    stable(feature = "neon_intrinsics", since = "1.59.0")
40585)]
40586#[cfg_attr(
40587    target_arch = "arm",
40588    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40589)]
40590pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
40591    unsafe extern "unadjusted" {
40592        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")]
40593        #[cfg_attr(
40594            any(target_arch = "aarch64", target_arch = "arm64ec"),
40595            link_name = "llvm.aarch64.neon.sqshl.v2i64"
40596        )]
40597        fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
40598    }
40599    unsafe { _vqshlq_s64(a, b) }
40600}
40601#[doc = "Unsigned saturating shift left"]
40602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
40603#[inline]
40604#[target_feature(enable = "neon")]
40605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40607#[cfg_attr(
40608    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40609    assert_instr(uqshl)
40610)]
40611#[cfg_attr(
40612    not(target_arch = "arm"),
40613    stable(feature = "neon_intrinsics", since = "1.59.0")
40614)]
40615#[cfg_attr(
40616    target_arch = "arm",
40617    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40618)]
40619pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
40620    unsafe extern "unadjusted" {
40621        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")]
40622        #[cfg_attr(
40623            any(target_arch = "aarch64", target_arch = "arm64ec"),
40624            link_name = "llvm.aarch64.neon.uqshl.v8i8"
40625        )]
40626        fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
40627    }
40628    unsafe { _vqshl_u8(a, b) }
40629}
40630#[doc = "Unsigned saturating shift left"]
40631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
40632#[inline]
40633#[target_feature(enable = "neon")]
40634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40636#[cfg_attr(
40637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40638    assert_instr(uqshl)
40639)]
40640#[cfg_attr(
40641    not(target_arch = "arm"),
40642    stable(feature = "neon_intrinsics", since = "1.59.0")
40643)]
40644#[cfg_attr(
40645    target_arch = "arm",
40646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40647)]
40648pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
40649    unsafe extern "unadjusted" {
40650        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")]
40651        #[cfg_attr(
40652            any(target_arch = "aarch64", target_arch = "arm64ec"),
40653            link_name = "llvm.aarch64.neon.uqshl.v16i8"
40654        )]
40655        fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
40656    }
40657    unsafe { _vqshlq_u8(a, b) }
40658}
40659#[doc = "Unsigned saturating shift left"]
40660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
40661#[inline]
40662#[target_feature(enable = "neon")]
40663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40665#[cfg_attr(
40666    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40667    assert_instr(uqshl)
40668)]
40669#[cfg_attr(
40670    not(target_arch = "arm"),
40671    stable(feature = "neon_intrinsics", since = "1.59.0")
40672)]
40673#[cfg_attr(
40674    target_arch = "arm",
40675    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40676)]
40677pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
40678    unsafe extern "unadjusted" {
40679        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")]
40680        #[cfg_attr(
40681            any(target_arch = "aarch64", target_arch = "arm64ec"),
40682            link_name = "llvm.aarch64.neon.uqshl.v4i16"
40683        )]
40684        fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
40685    }
40686    unsafe { _vqshl_u16(a, b) }
40687}
40688#[doc = "Unsigned saturating shift left"]
40689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
40690#[inline]
40691#[target_feature(enable = "neon")]
40692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40694#[cfg_attr(
40695    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40696    assert_instr(uqshl)
40697)]
40698#[cfg_attr(
40699    not(target_arch = "arm"),
40700    stable(feature = "neon_intrinsics", since = "1.59.0")
40701)]
40702#[cfg_attr(
40703    target_arch = "arm",
40704    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40705)]
40706pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
40707    unsafe extern "unadjusted" {
40708        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")]
40709        #[cfg_attr(
40710            any(target_arch = "aarch64", target_arch = "arm64ec"),
40711            link_name = "llvm.aarch64.neon.uqshl.v8i16"
40712        )]
40713        fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
40714    }
40715    unsafe { _vqshlq_u16(a, b) }
40716}
40717#[doc = "Unsigned saturating shift left"]
40718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
40719#[inline]
40720#[target_feature(enable = "neon")]
40721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40723#[cfg_attr(
40724    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40725    assert_instr(uqshl)
40726)]
40727#[cfg_attr(
40728    not(target_arch = "arm"),
40729    stable(feature = "neon_intrinsics", since = "1.59.0")
40730)]
40731#[cfg_attr(
40732    target_arch = "arm",
40733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40734)]
40735pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
40736    unsafe extern "unadjusted" {
40737        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")]
40738        #[cfg_attr(
40739            any(target_arch = "aarch64", target_arch = "arm64ec"),
40740            link_name = "llvm.aarch64.neon.uqshl.v2i32"
40741        )]
40742        fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
40743    }
40744    unsafe { _vqshl_u32(a, b) }
40745}
40746#[doc = "Unsigned saturating shift left"]
40747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
40748#[inline]
40749#[target_feature(enable = "neon")]
40750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40752#[cfg_attr(
40753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40754    assert_instr(uqshl)
40755)]
40756#[cfg_attr(
40757    not(target_arch = "arm"),
40758    stable(feature = "neon_intrinsics", since = "1.59.0")
40759)]
40760#[cfg_attr(
40761    target_arch = "arm",
40762    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40763)]
40764pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
40765    unsafe extern "unadjusted" {
40766        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")]
40767        #[cfg_attr(
40768            any(target_arch = "aarch64", target_arch = "arm64ec"),
40769            link_name = "llvm.aarch64.neon.uqshl.v4i32"
40770        )]
40771        fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
40772    }
40773    unsafe { _vqshlq_u32(a, b) }
40774}
40775#[doc = "Unsigned saturating shift left"]
40776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
40777#[inline]
40778#[target_feature(enable = "neon")]
40779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40781#[cfg_attr(
40782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40783    assert_instr(uqshl)
40784)]
40785#[cfg_attr(
40786    not(target_arch = "arm"),
40787    stable(feature = "neon_intrinsics", since = "1.59.0")
40788)]
40789#[cfg_attr(
40790    target_arch = "arm",
40791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40792)]
40793pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
40794    unsafe extern "unadjusted" {
40795        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")]
40796        #[cfg_attr(
40797            any(target_arch = "aarch64", target_arch = "arm64ec"),
40798            link_name = "llvm.aarch64.neon.uqshl.v1i64"
40799        )]
40800        fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
40801    }
40802    unsafe { _vqshl_u64(a, b) }
40803}
40804#[doc = "Unsigned saturating shift left"]
40805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
40806#[inline]
40807#[target_feature(enable = "neon")]
40808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40810#[cfg_attr(
40811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40812    assert_instr(uqshl)
40813)]
40814#[cfg_attr(
40815    not(target_arch = "arm"),
40816    stable(feature = "neon_intrinsics", since = "1.59.0")
40817)]
40818#[cfg_attr(
40819    target_arch = "arm",
40820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40821)]
40822pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
40823    unsafe extern "unadjusted" {
40824        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")]
40825        #[cfg_attr(
40826            any(target_arch = "aarch64", target_arch = "arm64ec"),
40827            link_name = "llvm.aarch64.neon.uqshl.v2i64"
40828        )]
40829        fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
40830    }
40831    unsafe { _vqshlq_u64(a, b) }
40832}
40833#[doc = "Signed saturating shift left unsigned"]
40834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40835#[inline]
40836#[cfg(target_arch = "arm")]
40837#[target_feature(enable = "neon,v7")]
40838#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40839#[rustc_legacy_const_generics(1)]
40840#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40841pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40842    static_assert_uimm_bits!(N, 3);
40843    unsafe extern "unadjusted" {
40844        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
40845        fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40846    }
40847    unsafe {
40848        _vqshlu_n_s8(
40849            a,
40850            const {
40851                int8x8_t([
40852                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40853                ])
40854            },
40855        )
40856    }
40857}
40858#[doc = "Signed saturating shift left unsigned"]
40859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40860#[inline]
40861#[cfg(target_arch = "arm")]
40862#[target_feature(enable = "neon,v7")]
40863#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40864#[rustc_legacy_const_generics(1)]
40865#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40866pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40867    static_assert_uimm_bits!(N, 3);
40868    unsafe extern "unadjusted" {
40869        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
40870        fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40871    }
40872    unsafe {
40873        _vqshluq_n_s8(
40874            a,
40875            const {
40876                int8x16_t([
40877                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40878                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40879                ])
40880            },
40881        )
40882    }
40883}
40884#[doc = "Signed saturating shift left unsigned"]
40885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40886#[inline]
40887#[cfg(target_arch = "arm")]
40888#[target_feature(enable = "neon,v7")]
40889#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40890#[rustc_legacy_const_generics(1)]
40891#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40892pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40893    static_assert_uimm_bits!(N, 4);
40894    unsafe extern "unadjusted" {
40895        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
40896        fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40897    }
40898    unsafe {
40899        _vqshlu_n_s16(
40900            a,
40901            const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40902        )
40903    }
40904}
40905#[doc = "Signed saturating shift left unsigned"]
40906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40907#[inline]
40908#[cfg(target_arch = "arm")]
40909#[target_feature(enable = "neon,v7")]
40910#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40911#[rustc_legacy_const_generics(1)]
40912#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40913pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
40914    static_assert_uimm_bits!(N, 4);
40915    unsafe extern "unadjusted" {
40916        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
40917        fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
40918    }
40919    unsafe {
40920        _vqshluq_n_s16(
40921            a,
40922            const {
40923                int16x8_t([
40924                    N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
40925                ])
40926            },
40927        )
40928    }
40929}
40930#[doc = "Signed saturating shift left unsigned"]
40931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
40932#[inline]
40933#[cfg(target_arch = "arm")]
40934#[target_feature(enable = "neon,v7")]
40935#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40936#[rustc_legacy_const_generics(1)]
40937#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40938pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
40939    static_assert_uimm_bits!(N, 5);
40940    unsafe extern "unadjusted" {
40941        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
40942        fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
40943    }
40944    unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
40945}
40946#[doc = "Signed saturating shift left unsigned"]
40947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
40948#[inline]
40949#[cfg(target_arch = "arm")]
40950#[target_feature(enable = "neon,v7")]
40951#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40952#[rustc_legacy_const_generics(1)]
40953#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40954pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
40955    static_assert_uimm_bits!(N, 5);
40956    unsafe extern "unadjusted" {
40957        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
40958        fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
40959    }
40960    unsafe {
40961        _vqshluq_n_s32(
40962            a,
40963            const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
40964        )
40965    }
40966}
40967#[doc = "Signed saturating shift left unsigned"]
40968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
40969#[inline]
40970#[cfg(target_arch = "arm")]
40971#[target_feature(enable = "neon,v7")]
40972#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40973#[rustc_legacy_const_generics(1)]
40974#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40975pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
40976    static_assert_uimm_bits!(N, 6);
40977    unsafe extern "unadjusted" {
40978        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")]
40979        fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
40980    }
40981    unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
40982}
40983#[doc = "Signed saturating shift left unsigned"]
40984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
40985#[inline]
40986#[cfg(target_arch = "arm")]
40987#[target_feature(enable = "neon,v7")]
40988#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40989#[rustc_legacy_const_generics(1)]
40990#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40991pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
40992    static_assert_uimm_bits!(N, 6);
40993    unsafe extern "unadjusted" {
40994        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
40995        fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
40996    }
40997    unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
40998}
40999#[doc = "Signed saturating shift left unsigned"]
41000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
41001#[inline]
41002#[target_feature(enable = "neon")]
41003#[cfg(not(target_arch = "arm"))]
41004#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41005#[rustc_legacy_const_generics(1)]
41006#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41007pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
41008    static_assert_uimm_bits!(N, 3);
41009    unsafe extern "unadjusted" {
41010        #[cfg_attr(
41011            any(target_arch = "aarch64", target_arch = "arm64ec"),
41012            link_name = "llvm.aarch64.neon.sqshlu.v8i8"
41013        )]
41014        fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
41015    }
41016    unsafe {
41017        _vqshlu_n_s8(
41018            a,
41019            const {
41020                int8x8_t([
41021                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41022                ])
41023            },
41024        )
41025    }
41026}
41027#[doc = "Signed saturating shift left unsigned"]
41028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
41029#[inline]
41030#[target_feature(enable = "neon")]
41031#[cfg(not(target_arch = "arm"))]
41032#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41033#[rustc_legacy_const_generics(1)]
41034#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41035pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
41036    static_assert_uimm_bits!(N, 3);
41037    unsafe extern "unadjusted" {
41038        #[cfg_attr(
41039            any(target_arch = "aarch64", target_arch = "arm64ec"),
41040            link_name = "llvm.aarch64.neon.sqshlu.v16i8"
41041        )]
41042        fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
41043    }
41044    unsafe {
41045        _vqshluq_n_s8(
41046            a,
41047            const {
41048                int8x16_t([
41049                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41050                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41051                ])
41052            },
41053        )
41054    }
41055}
41056#[doc = "Signed saturating shift left unsigned"]
41057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
41058#[inline]
41059#[target_feature(enable = "neon")]
41060#[cfg(not(target_arch = "arm"))]
41061#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41062#[rustc_legacy_const_generics(1)]
41063#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41064pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
41065    static_assert_uimm_bits!(N, 4);
41066    unsafe extern "unadjusted" {
41067        #[cfg_attr(
41068            any(target_arch = "aarch64", target_arch = "arm64ec"),
41069            link_name = "llvm.aarch64.neon.sqshlu.v4i16"
41070        )]
41071        fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
41072    }
41073    unsafe {
41074        _vqshlu_n_s16(
41075            a,
41076            const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
41077        )
41078    }
41079}
41080#[doc = "Signed saturating shift left unsigned"]
41081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
41082#[inline]
41083#[target_feature(enable = "neon")]
41084#[cfg(not(target_arch = "arm"))]
41085#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41086#[rustc_legacy_const_generics(1)]
41087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41088pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
41089    static_assert_uimm_bits!(N, 4);
41090    unsafe extern "unadjusted" {
41091        #[cfg_attr(
41092            any(target_arch = "aarch64", target_arch = "arm64ec"),
41093            link_name = "llvm.aarch64.neon.sqshlu.v8i16"
41094        )]
41095        fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
41096    }
41097    unsafe {
41098        _vqshluq_n_s16(
41099            a,
41100            const {
41101                int16x8_t([
41102                    N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
41103                ])
41104            },
41105        )
41106    }
41107}
41108#[doc = "Signed saturating shift left unsigned"]
41109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
41110#[inline]
41111#[target_feature(enable = "neon")]
41112#[cfg(not(target_arch = "arm"))]
41113#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41114#[rustc_legacy_const_generics(1)]
41115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41116pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
41117    static_assert_uimm_bits!(N, 5);
41118    unsafe extern "unadjusted" {
41119        #[cfg_attr(
41120            any(target_arch = "aarch64", target_arch = "arm64ec"),
41121            link_name = "llvm.aarch64.neon.sqshlu.v2i32"
41122        )]
41123        fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
41124    }
41125    unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
41126}
41127#[doc = "Signed saturating shift left unsigned"]
41128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
41129#[inline]
41130#[target_feature(enable = "neon")]
41131#[cfg(not(target_arch = "arm"))]
41132#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41133#[rustc_legacy_const_generics(1)]
41134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41135pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
41136    static_assert_uimm_bits!(N, 5);
41137    unsafe extern "unadjusted" {
41138        #[cfg_attr(
41139            any(target_arch = "aarch64", target_arch = "arm64ec"),
41140            link_name = "llvm.aarch64.neon.sqshlu.v4i32"
41141        )]
41142        fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
41143    }
41144    unsafe {
41145        _vqshluq_n_s32(
41146            a,
41147            const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
41148        )
41149    }
41150}
41151#[doc = "Signed saturating shift left unsigned"]
41152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
41153#[inline]
41154#[target_feature(enable = "neon")]
41155#[cfg(not(target_arch = "arm"))]
41156#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41157#[rustc_legacy_const_generics(1)]
41158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41159pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
41160    static_assert_uimm_bits!(N, 6);
41161    unsafe extern "unadjusted" {
41162        #[cfg_attr(
41163            any(target_arch = "aarch64", target_arch = "arm64ec"),
41164            link_name = "llvm.aarch64.neon.sqshlu.v1i64"
41165        )]
41166        fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
41167    }
41168    unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
41169}
41170#[doc = "Signed saturating shift left unsigned"]
41171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
41172#[inline]
41173#[target_feature(enable = "neon")]
41174#[cfg(not(target_arch = "arm"))]
41175#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41176#[rustc_legacy_const_generics(1)]
41177#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41178pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
41179    static_assert_uimm_bits!(N, 6);
41180    unsafe extern "unadjusted" {
41181        #[cfg_attr(
41182            any(target_arch = "aarch64", target_arch = "arm64ec"),
41183            link_name = "llvm.aarch64.neon.sqshlu.v2i64"
41184        )]
41185        fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
41186    }
41187    unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
41188}
41189#[doc = "Signed saturating shift right narrow"]
41190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41191#[inline]
41192#[cfg(target_arch = "arm")]
41193#[target_feature(enable = "neon,v7")]
41194#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41195#[rustc_legacy_const_generics(1)]
41196#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41197pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41198    static_assert!(N >= 1 && N <= 8);
41199    unsafe extern "unadjusted" {
41200        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
41201        fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
41202    }
41203    unsafe {
41204        _vqshrn_n_s16(
41205            a,
41206            const {
41207                int16x8_t([
41208                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41209                    -N as i16,
41210                ])
41211            },
41212        )
41213    }
41214}
41215#[doc = "Signed saturating shift right narrow"]
41216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41217#[inline]
41218#[cfg(target_arch = "arm")]
41219#[target_feature(enable = "neon,v7")]
41220#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41221#[rustc_legacy_const_generics(1)]
41222#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41223pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41224    static_assert!(N >= 1 && N <= 16);
41225    unsafe extern "unadjusted" {
41226        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
41227        fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
41228    }
41229    unsafe {
41230        _vqshrn_n_s32(
41231            a,
41232            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41233        )
41234    }
41235}
41236#[doc = "Signed saturating shift right narrow"]
41237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41238#[inline]
41239#[cfg(target_arch = "arm")]
41240#[target_feature(enable = "neon,v7")]
41241#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41242#[rustc_legacy_const_generics(1)]
41243#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41244pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41245    static_assert!(N >= 1 && N <= 32);
41246    unsafe extern "unadjusted" {
41247        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
41248        fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
41249    }
41250    unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41251}
41252#[doc = "Signed saturating shift right narrow"]
41253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41254#[inline]
41255#[target_feature(enable = "neon")]
41256#[cfg(not(target_arch = "arm"))]
41257#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41258#[rustc_legacy_const_generics(1)]
41259#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41260pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41261    static_assert!(N >= 1 && N <= 8);
41262    unsafe extern "unadjusted" {
41263        #[cfg_attr(
41264            any(target_arch = "aarch64", target_arch = "arm64ec"),
41265            link_name = "llvm.aarch64.neon.sqshrn.v8i8"
41266        )]
41267        fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
41268    }
41269    unsafe { _vqshrn_n_s16(a, N) }
41270}
41271#[doc = "Signed saturating shift right narrow"]
41272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41273#[inline]
41274#[target_feature(enable = "neon")]
41275#[cfg(not(target_arch = "arm"))]
41276#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41277#[rustc_legacy_const_generics(1)]
41278#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41279pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41280    static_assert!(N >= 1 && N <= 16);
41281    unsafe extern "unadjusted" {
41282        #[cfg_attr(
41283            any(target_arch = "aarch64", target_arch = "arm64ec"),
41284            link_name = "llvm.aarch64.neon.sqshrn.v4i16"
41285        )]
41286        fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
41287    }
41288    unsafe { _vqshrn_n_s32(a, N) }
41289}
41290#[doc = "Signed saturating shift right narrow"]
41291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41292#[inline]
41293#[target_feature(enable = "neon")]
41294#[cfg(not(target_arch = "arm"))]
41295#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41296#[rustc_legacy_const_generics(1)]
41297#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41298pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41299    static_assert!(N >= 1 && N <= 32);
41300    unsafe extern "unadjusted" {
41301        #[cfg_attr(
41302            any(target_arch = "aarch64", target_arch = "arm64ec"),
41303            link_name = "llvm.aarch64.neon.sqshrn.v2i32"
41304        )]
41305        fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
41306    }
41307    unsafe { _vqshrn_n_s64(a, N) }
41308}
41309#[doc = "Unsigned saturating shift right narrow"]
41310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41311#[inline]
41312#[cfg(target_arch = "arm")]
41313#[target_feature(enable = "neon,v7")]
41314#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41315#[rustc_legacy_const_generics(1)]
41316#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41317pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41318    static_assert!(N >= 1 && N <= 8);
41319    unsafe extern "unadjusted" {
41320        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
41321        fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
41322    }
41323    unsafe {
41324        _vqshrn_n_u16(
41325            a,
41326            const {
41327                uint16x8_t([
41328                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
41329                    -N as u16,
41330                ])
41331            },
41332        )
41333    }
41334}
41335#[doc = "Unsigned saturating shift right narrow"]
41336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41337#[inline]
41338#[cfg(target_arch = "arm")]
41339#[target_feature(enable = "neon,v7")]
41340#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41341#[rustc_legacy_const_generics(1)]
41342#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41343pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41344    static_assert!(N >= 1 && N <= 16);
41345    unsafe extern "unadjusted" {
41346        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
41347        fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
41348    }
41349    unsafe {
41350        _vqshrn_n_u32(
41351            a,
41352            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
41353        )
41354    }
41355}
41356#[doc = "Unsigned saturating shift right narrow"]
41357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41358#[inline]
41359#[cfg(target_arch = "arm")]
41360#[target_feature(enable = "neon,v7")]
41361#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41362#[rustc_legacy_const_generics(1)]
41363#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41364pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41365    static_assert!(N >= 1 && N <= 32);
41366    unsafe extern "unadjusted" {
41367        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
41368        fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
41369    }
41370    unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
41371}
41372#[doc = "Unsigned saturating shift right narrow"]
41373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41374#[inline]
41375#[target_feature(enable = "neon")]
41376#[cfg(not(target_arch = "arm"))]
41377#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41378#[rustc_legacy_const_generics(1)]
41379#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41380pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41381    static_assert!(N >= 1 && N <= 8);
41382    unsafe extern "unadjusted" {
41383        #[cfg_attr(
41384            any(target_arch = "aarch64", target_arch = "arm64ec"),
41385            link_name = "llvm.aarch64.neon.uqshrn.v8i8"
41386        )]
41387        fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
41388    }
41389    unsafe { _vqshrn_n_u16(a, N) }
41390}
41391#[doc = "Unsigned saturating shift right narrow"]
41392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41393#[inline]
41394#[target_feature(enable = "neon")]
41395#[cfg(not(target_arch = "arm"))]
41396#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41397#[rustc_legacy_const_generics(1)]
41398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41399pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41400    static_assert!(N >= 1 && N <= 16);
41401    unsafe extern "unadjusted" {
41402        #[cfg_attr(
41403            any(target_arch = "aarch64", target_arch = "arm64ec"),
41404            link_name = "llvm.aarch64.neon.uqshrn.v4i16"
41405        )]
41406        fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
41407    }
41408    unsafe { _vqshrn_n_u32(a, N) }
41409}
41410#[doc = "Unsigned saturating shift right narrow"]
41411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41412#[inline]
41413#[target_feature(enable = "neon")]
41414#[cfg(not(target_arch = "arm"))]
41415#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41416#[rustc_legacy_const_generics(1)]
41417#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41418pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41419    static_assert!(N >= 1 && N <= 32);
41420    unsafe extern "unadjusted" {
41421        #[cfg_attr(
41422            any(target_arch = "aarch64", target_arch = "arm64ec"),
41423            link_name = "llvm.aarch64.neon.uqshrn.v2i32"
41424        )]
41425        fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
41426    }
41427    unsafe { _vqshrn_n_u64(a, N) }
41428}
41429#[doc = "Signed saturating shift right unsigned narrow"]
41430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41431#[inline]
41432#[cfg(target_arch = "arm")]
41433#[target_feature(enable = "neon,v7")]
41434#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41435#[rustc_legacy_const_generics(1)]
41436#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41437pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41438    static_assert!(N >= 1 && N <= 8);
41439    unsafe extern "unadjusted" {
41440        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
41441        fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
41442    }
41443    unsafe {
41444        _vqshrun_n_s16(
41445            a,
41446            const {
41447                int16x8_t([
41448                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41449                    -N as i16,
41450                ])
41451            },
41452        )
41453    }
41454}
41455#[doc = "Signed saturating shift right unsigned narrow"]
41456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41457#[inline]
41458#[cfg(target_arch = "arm")]
41459#[target_feature(enable = "neon,v7")]
41460#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41461#[rustc_legacy_const_generics(1)]
41462#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41463pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41464    static_assert!(N >= 1 && N <= 16);
41465    unsafe extern "unadjusted" {
41466        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
41467        fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
41468    }
41469    unsafe {
41470        _vqshrun_n_s32(
41471            a,
41472            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41473        )
41474    }
41475}
41476#[doc = "Signed saturating shift right unsigned narrow"]
41477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41478#[inline]
41479#[cfg(target_arch = "arm")]
41480#[target_feature(enable = "neon,v7")]
41481#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41482#[rustc_legacy_const_generics(1)]
41483#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41484pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41485    static_assert!(N >= 1 && N <= 32);
41486    unsafe extern "unadjusted" {
41487        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
41488        fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
41489    }
41490    unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41491}
41492#[doc = "Signed saturating shift right unsigned narrow"]
41493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41494#[inline]
41495#[target_feature(enable = "neon")]
41496#[cfg(not(target_arch = "arm"))]
41497#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41498#[rustc_legacy_const_generics(1)]
41499#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41500pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41501    static_assert!(N >= 1 && N <= 8);
41502    unsafe extern "unadjusted" {
41503        #[cfg_attr(
41504            any(target_arch = "aarch64", target_arch = "arm64ec"),
41505            link_name = "llvm.aarch64.neon.sqshrun.v8i8"
41506        )]
41507        fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
41508    }
41509    unsafe { _vqshrun_n_s16(a, N) }
41510}
41511#[doc = "Signed saturating shift right unsigned narrow"]
41512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41513#[inline]
41514#[target_feature(enable = "neon")]
41515#[cfg(not(target_arch = "arm"))]
41516#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41517#[rustc_legacy_const_generics(1)]
41518#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41519pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41520    static_assert!(N >= 1 && N <= 16);
41521    unsafe extern "unadjusted" {
41522        #[cfg_attr(
41523            any(target_arch = "aarch64", target_arch = "arm64ec"),
41524            link_name = "llvm.aarch64.neon.sqshrun.v4i16"
41525        )]
41526        fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
41527    }
41528    unsafe { _vqshrun_n_s32(a, N) }
41529}
41530#[doc = "Signed saturating shift right unsigned narrow"]
41531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41532#[inline]
41533#[target_feature(enable = "neon")]
41534#[cfg(not(target_arch = "arm"))]
41535#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41536#[rustc_legacy_const_generics(1)]
41537#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41538pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41539    static_assert!(N >= 1 && N <= 32);
41540    unsafe extern "unadjusted" {
41541        #[cfg_attr(
41542            any(target_arch = "aarch64", target_arch = "arm64ec"),
41543            link_name = "llvm.aarch64.neon.sqshrun.v2i32"
41544        )]
41545        fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
41546    }
41547    unsafe { _vqshrun_n_s64(a, N) }
41548}
41549#[doc = "Saturating subtract"]
41550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
41551#[inline]
41552#[target_feature(enable = "neon")]
41553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41554#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41555#[cfg_attr(
41556    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41557    assert_instr(sqsub)
41558)]
41559#[cfg_attr(
41560    not(target_arch = "arm"),
41561    stable(feature = "neon_intrinsics", since = "1.59.0")
41562)]
41563#[cfg_attr(
41564    target_arch = "arm",
41565    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41566)]
41567pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
41568    unsafe extern "unadjusted" {
41569        #[cfg_attr(
41570            any(target_arch = "aarch64", target_arch = "arm64ec"),
41571            link_name = "llvm.aarch64.neon.sqsub.v8i8"
41572        )]
41573        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")]
41574        fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
41575    }
41576    unsafe { _vqsub_s8(a, b) }
41577}
41578#[doc = "Saturating subtract"]
41579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
41580#[inline]
41581#[target_feature(enable = "neon")]
41582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41583#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41584#[cfg_attr(
41585    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41586    assert_instr(sqsub)
41587)]
41588#[cfg_attr(
41589    not(target_arch = "arm"),
41590    stable(feature = "neon_intrinsics", since = "1.59.0")
41591)]
41592#[cfg_attr(
41593    target_arch = "arm",
41594    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41595)]
41596pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
41597    unsafe extern "unadjusted" {
41598        #[cfg_attr(
41599            any(target_arch = "aarch64", target_arch = "arm64ec"),
41600            link_name = "llvm.aarch64.neon.sqsub.v16i8"
41601        )]
41602        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")]
41603        fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
41604    }
41605    unsafe { _vqsubq_s8(a, b) }
41606}
41607#[doc = "Saturating subtract"]
41608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
41609#[inline]
41610#[target_feature(enable = "neon")]
41611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41613#[cfg_attr(
41614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41615    assert_instr(sqsub)
41616)]
41617#[cfg_attr(
41618    not(target_arch = "arm"),
41619    stable(feature = "neon_intrinsics", since = "1.59.0")
41620)]
41621#[cfg_attr(
41622    target_arch = "arm",
41623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41624)]
41625pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
41626    unsafe extern "unadjusted" {
41627        #[cfg_attr(
41628            any(target_arch = "aarch64", target_arch = "arm64ec"),
41629            link_name = "llvm.aarch64.neon.sqsub.v4i16"
41630        )]
41631        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")]
41632        fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
41633    }
41634    unsafe { _vqsub_s16(a, b) }
41635}
41636#[doc = "Saturating subtract"]
41637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
41638#[inline]
41639#[target_feature(enable = "neon")]
41640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41641#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41642#[cfg_attr(
41643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41644    assert_instr(sqsub)
41645)]
41646#[cfg_attr(
41647    not(target_arch = "arm"),
41648    stable(feature = "neon_intrinsics", since = "1.59.0")
41649)]
41650#[cfg_attr(
41651    target_arch = "arm",
41652    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41653)]
41654pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
41655    unsafe extern "unadjusted" {
41656        #[cfg_attr(
41657            any(target_arch = "aarch64", target_arch = "arm64ec"),
41658            link_name = "llvm.aarch64.neon.sqsub.v8i16"
41659        )]
41660        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")]
41661        fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
41662    }
41663    unsafe { _vqsubq_s16(a, b) }
41664}
41665#[doc = "Saturating subtract"]
41666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
41667#[inline]
41668#[target_feature(enable = "neon")]
41669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41670#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41671#[cfg_attr(
41672    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41673    assert_instr(sqsub)
41674)]
41675#[cfg_attr(
41676    not(target_arch = "arm"),
41677    stable(feature = "neon_intrinsics", since = "1.59.0")
41678)]
41679#[cfg_attr(
41680    target_arch = "arm",
41681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41682)]
41683pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
41684    unsafe extern "unadjusted" {
41685        #[cfg_attr(
41686            any(target_arch = "aarch64", target_arch = "arm64ec"),
41687            link_name = "llvm.aarch64.neon.sqsub.v2i32"
41688        )]
41689        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")]
41690        fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
41691    }
41692    unsafe { _vqsub_s32(a, b) }
41693}
41694#[doc = "Saturating subtract"]
41695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
41696#[inline]
41697#[target_feature(enable = "neon")]
41698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41700#[cfg_attr(
41701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41702    assert_instr(sqsub)
41703)]
41704#[cfg_attr(
41705    not(target_arch = "arm"),
41706    stable(feature = "neon_intrinsics", since = "1.59.0")
41707)]
41708#[cfg_attr(
41709    target_arch = "arm",
41710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41711)]
41712pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
41713    unsafe extern "unadjusted" {
41714        #[cfg_attr(
41715            any(target_arch = "aarch64", target_arch = "arm64ec"),
41716            link_name = "llvm.aarch64.neon.sqsub.v4i32"
41717        )]
41718        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")]
41719        fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
41720    }
41721    unsafe { _vqsubq_s32(a, b) }
41722}
41723#[doc = "Saturating subtract"]
41724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
41725#[inline]
41726#[target_feature(enable = "neon")]
41727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41728#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41729#[cfg_attr(
41730    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41731    assert_instr(sqsub)
41732)]
41733#[cfg_attr(
41734    not(target_arch = "arm"),
41735    stable(feature = "neon_intrinsics", since = "1.59.0")
41736)]
41737#[cfg_attr(
41738    target_arch = "arm",
41739    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41740)]
41741pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
41742    unsafe extern "unadjusted" {
41743        #[cfg_attr(
41744            any(target_arch = "aarch64", target_arch = "arm64ec"),
41745            link_name = "llvm.aarch64.neon.sqsub.v1i64"
41746        )]
41747        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")]
41748        fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
41749    }
41750    unsafe { _vqsub_s64(a, b) }
41751}
41752#[doc = "Saturating subtract"]
41753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
41754#[inline]
41755#[target_feature(enable = "neon")]
41756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41758#[cfg_attr(
41759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41760    assert_instr(sqsub)
41761)]
41762#[cfg_attr(
41763    not(target_arch = "arm"),
41764    stable(feature = "neon_intrinsics", since = "1.59.0")
41765)]
41766#[cfg_attr(
41767    target_arch = "arm",
41768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41769)]
41770pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
41771    unsafe extern "unadjusted" {
41772        #[cfg_attr(
41773            any(target_arch = "aarch64", target_arch = "arm64ec"),
41774            link_name = "llvm.aarch64.neon.sqsub.v2i64"
41775        )]
41776        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")]
41777        fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
41778    }
41779    unsafe { _vqsubq_s64(a, b) }
41780}
41781#[doc = "Saturating subtract"]
41782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
41783#[inline]
41784#[target_feature(enable = "neon")]
41785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41786#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41787#[cfg_attr(
41788    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41789    assert_instr(uqsub)
41790)]
41791#[cfg_attr(
41792    not(target_arch = "arm"),
41793    stable(feature = "neon_intrinsics", since = "1.59.0")
41794)]
41795#[cfg_attr(
41796    target_arch = "arm",
41797    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41798)]
41799pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
41800    unsafe extern "unadjusted" {
41801        #[cfg_attr(
41802            any(target_arch = "aarch64", target_arch = "arm64ec"),
41803            link_name = "llvm.aarch64.neon.uqsub.v8i8"
41804        )]
41805        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")]
41806        fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
41807    }
41808    unsafe { _vqsub_u8(a, b) }
41809}
41810#[doc = "Saturating subtract"]
41811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
41812#[inline]
41813#[target_feature(enable = "neon")]
41814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41816#[cfg_attr(
41817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41818    assert_instr(uqsub)
41819)]
41820#[cfg_attr(
41821    not(target_arch = "arm"),
41822    stable(feature = "neon_intrinsics", since = "1.59.0")
41823)]
41824#[cfg_attr(
41825    target_arch = "arm",
41826    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41827)]
41828pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
41829    unsafe extern "unadjusted" {
41830        #[cfg_attr(
41831            any(target_arch = "aarch64", target_arch = "arm64ec"),
41832            link_name = "llvm.aarch64.neon.uqsub.v16i8"
41833        )]
41834        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")]
41835        fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
41836    }
41837    unsafe { _vqsubq_u8(a, b) }
41838}
41839#[doc = "Saturating subtract"]
41840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
41841#[inline]
41842#[target_feature(enable = "neon")]
41843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41844#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41845#[cfg_attr(
41846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41847    assert_instr(uqsub)
41848)]
41849#[cfg_attr(
41850    not(target_arch = "arm"),
41851    stable(feature = "neon_intrinsics", since = "1.59.0")
41852)]
41853#[cfg_attr(
41854    target_arch = "arm",
41855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41856)]
41857pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
41858    unsafe extern "unadjusted" {
41859        #[cfg_attr(
41860            any(target_arch = "aarch64", target_arch = "arm64ec"),
41861            link_name = "llvm.aarch64.neon.uqsub.v4i16"
41862        )]
41863        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")]
41864        fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
41865    }
41866    unsafe { _vqsub_u16(a, b) }
41867}
41868#[doc = "Saturating subtract"]
41869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
41870#[inline]
41871#[target_feature(enable = "neon")]
41872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41874#[cfg_attr(
41875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41876    assert_instr(uqsub)
41877)]
41878#[cfg_attr(
41879    not(target_arch = "arm"),
41880    stable(feature = "neon_intrinsics", since = "1.59.0")
41881)]
41882#[cfg_attr(
41883    target_arch = "arm",
41884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41885)]
41886pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
41887    unsafe extern "unadjusted" {
41888        #[cfg_attr(
41889            any(target_arch = "aarch64", target_arch = "arm64ec"),
41890            link_name = "llvm.aarch64.neon.uqsub.v8i16"
41891        )]
41892        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")]
41893        fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
41894    }
41895    unsafe { _vqsubq_u16(a, b) }
41896}
41897#[doc = "Saturating subtract"]
41898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
41899#[inline]
41900#[target_feature(enable = "neon")]
41901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41902#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41903#[cfg_attr(
41904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41905    assert_instr(uqsub)
41906)]
41907#[cfg_attr(
41908    not(target_arch = "arm"),
41909    stable(feature = "neon_intrinsics", since = "1.59.0")
41910)]
41911#[cfg_attr(
41912    target_arch = "arm",
41913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41914)]
41915pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
41916    unsafe extern "unadjusted" {
41917        #[cfg_attr(
41918            any(target_arch = "aarch64", target_arch = "arm64ec"),
41919            link_name = "llvm.aarch64.neon.uqsub.v2i32"
41920        )]
41921        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")]
41922        fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
41923    }
41924    unsafe { _vqsub_u32(a, b) }
41925}
41926#[doc = "Saturating subtract"]
41927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
41928#[inline]
41929#[target_feature(enable = "neon")]
41930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41931#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41932#[cfg_attr(
41933    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41934    assert_instr(uqsub)
41935)]
41936#[cfg_attr(
41937    not(target_arch = "arm"),
41938    stable(feature = "neon_intrinsics", since = "1.59.0")
41939)]
41940#[cfg_attr(
41941    target_arch = "arm",
41942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41943)]
41944pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
41945    unsafe extern "unadjusted" {
41946        #[cfg_attr(
41947            any(target_arch = "aarch64", target_arch = "arm64ec"),
41948            link_name = "llvm.aarch64.neon.uqsub.v4i32"
41949        )]
41950        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")]
41951        fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
41952    }
41953    unsafe { _vqsubq_u32(a, b) }
41954}
41955#[doc = "Saturating subtract"]
41956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
41957#[inline]
41958#[target_feature(enable = "neon")]
41959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41960#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41961#[cfg_attr(
41962    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41963    assert_instr(uqsub)
41964)]
41965#[cfg_attr(
41966    not(target_arch = "arm"),
41967    stable(feature = "neon_intrinsics", since = "1.59.0")
41968)]
41969#[cfg_attr(
41970    target_arch = "arm",
41971    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41972)]
41973pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
41974    unsafe extern "unadjusted" {
41975        #[cfg_attr(
41976            any(target_arch = "aarch64", target_arch = "arm64ec"),
41977            link_name = "llvm.aarch64.neon.uqsub.v1i64"
41978        )]
41979        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")]
41980        fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
41981    }
41982    unsafe { _vqsub_u64(a, b) }
41983}
41984#[doc = "Saturating subtract"]
41985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
41986#[inline]
41987#[target_feature(enable = "neon")]
41988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41989#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41990#[cfg_attr(
41991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41992    assert_instr(uqsub)
41993)]
41994#[cfg_attr(
41995    not(target_arch = "arm"),
41996    stable(feature = "neon_intrinsics", since = "1.59.0")
41997)]
41998#[cfg_attr(
41999    target_arch = "arm",
42000    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42001)]
42002pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
42003    unsafe extern "unadjusted" {
42004        #[cfg_attr(
42005            any(target_arch = "aarch64", target_arch = "arm64ec"),
42006            link_name = "llvm.aarch64.neon.uqsub.v2i64"
42007        )]
42008        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")]
42009        fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
42010    }
42011    unsafe { _vqsubq_u64(a, b) }
42012}
42013#[doc = "Rounding Add returning High Narrow (high half)."]
42014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
42015#[inline]
42016#[target_feature(enable = "neon")]
42017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42018#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42019#[cfg_attr(
42020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42021    assert_instr(raddhn2)
42022)]
42023#[cfg_attr(
42024    not(target_arch = "arm"),
42025    stable(feature = "neon_intrinsics", since = "1.59.0")
42026)]
42027#[cfg_attr(
42028    target_arch = "arm",
42029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42030)]
42031pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
42032    let x = vraddhn_s16(b, c);
42033    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
42034}
42035#[doc = "Rounding Add returning High Narrow (high half)."]
42036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
42037#[inline]
42038#[target_feature(enable = "neon")]
42039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42041#[cfg_attr(
42042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42043    assert_instr(raddhn2)
42044)]
42045#[cfg_attr(
42046    not(target_arch = "arm"),
42047    stable(feature = "neon_intrinsics", since = "1.59.0")
42048)]
42049#[cfg_attr(
42050    target_arch = "arm",
42051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42052)]
42053pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
42054    let x = vraddhn_s32(b, c);
42055    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
42056}
42057#[doc = "Rounding Add returning High Narrow (high half)."]
42058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
42059#[inline]
42060#[target_feature(enable = "neon")]
42061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42063#[cfg_attr(
42064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42065    assert_instr(raddhn2)
42066)]
42067#[cfg_attr(
42068    not(target_arch = "arm"),
42069    stable(feature = "neon_intrinsics", since = "1.59.0")
42070)]
42071#[cfg_attr(
42072    target_arch = "arm",
42073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42074)]
42075pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
42076    let x = vraddhn_s64(b, c);
42077    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
42078}
42079#[doc = "Rounding Add returning High Narrow (high half)."]
42080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
42081#[inline]
42082#[target_feature(enable = "neon")]
42083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42085#[cfg_attr(
42086    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42087    assert_instr(raddhn2)
42088)]
42089#[cfg_attr(
42090    not(target_arch = "arm"),
42091    stable(feature = "neon_intrinsics", since = "1.59.0")
42092)]
42093#[cfg_attr(
42094    target_arch = "arm",
42095    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42096)]
42097pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
42098    unsafe {
42099        let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
42100        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
42101    }
42102}
42103#[doc = "Rounding Add returning High Narrow (high half)."]
42104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
42105#[inline]
42106#[target_feature(enable = "neon")]
42107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42108#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42109#[cfg_attr(
42110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42111    assert_instr(raddhn2)
42112)]
42113#[cfg_attr(
42114    not(target_arch = "arm"),
42115    stable(feature = "neon_intrinsics", since = "1.59.0")
42116)]
42117#[cfg_attr(
42118    target_arch = "arm",
42119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42120)]
42121pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
42122    unsafe {
42123        let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
42124        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
42125    }
42126}
42127#[doc = "Rounding Add returning High Narrow (high half)."]
42128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
42129#[inline]
42130#[target_feature(enable = "neon")]
42131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42132#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42133#[cfg_attr(
42134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42135    assert_instr(raddhn2)
42136)]
42137#[cfg_attr(
42138    not(target_arch = "arm"),
42139    stable(feature = "neon_intrinsics", since = "1.59.0")
42140)]
42141#[cfg_attr(
42142    target_arch = "arm",
42143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42144)]
42145pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
42146    unsafe {
42147        let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
42148        simd_shuffle!(a, x, [0, 1, 2, 3])
42149    }
42150}
42151#[doc = "Rounding Add returning High Narrow."]
42152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
42153#[inline]
42154#[target_feature(enable = "neon")]
42155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42157#[cfg_attr(
42158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42159    assert_instr(raddhn)
42160)]
42161#[cfg_attr(
42162    not(target_arch = "arm"),
42163    stable(feature = "neon_intrinsics", since = "1.59.0")
42164)]
42165#[cfg_attr(
42166    target_arch = "arm",
42167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42168)]
42169pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
42170    unsafe extern "unadjusted" {
42171        #[cfg_attr(
42172            any(target_arch = "aarch64", target_arch = "arm64ec"),
42173            link_name = "llvm.aarch64.neon.raddhn.v8i8"
42174        )]
42175        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")]
42176        fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
42177    }
42178    unsafe { _vraddhn_s16(a, b) }
42179}
42180#[doc = "Rounding Add returning High Narrow."]
42181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
42182#[inline]
42183#[target_feature(enable = "neon")]
42184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42186#[cfg_attr(
42187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42188    assert_instr(raddhn)
42189)]
42190#[cfg_attr(
42191    not(target_arch = "arm"),
42192    stable(feature = "neon_intrinsics", since = "1.59.0")
42193)]
42194#[cfg_attr(
42195    target_arch = "arm",
42196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42197)]
42198pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
42199    unsafe extern "unadjusted" {
42200        #[cfg_attr(
42201            any(target_arch = "aarch64", target_arch = "arm64ec"),
42202            link_name = "llvm.aarch64.neon.raddhn.v4i16"
42203        )]
42204        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")]
42205        fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
42206    }
42207    unsafe { _vraddhn_s32(a, b) }
42208}
42209#[doc = "Rounding Add returning High Narrow."]
42210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
42211#[inline]
42212#[target_feature(enable = "neon")]
42213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42214#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42215#[cfg_attr(
42216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42217    assert_instr(raddhn)
42218)]
42219#[cfg_attr(
42220    not(target_arch = "arm"),
42221    stable(feature = "neon_intrinsics", since = "1.59.0")
42222)]
42223#[cfg_attr(
42224    target_arch = "arm",
42225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42226)]
42227pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
42228    unsafe extern "unadjusted" {
42229        #[cfg_attr(
42230            any(target_arch = "aarch64", target_arch = "arm64ec"),
42231            link_name = "llvm.aarch64.neon.raddhn.v2i32"
42232        )]
42233        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")]
42234        fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
42235    }
42236    unsafe { _vraddhn_s64(a, b) }
42237}
42238#[doc = "Rounding Add returning High Narrow."]
42239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42240#[inline]
42241#[cfg(target_endian = "little")]
42242#[target_feature(enable = "neon")]
42243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42244#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42245#[cfg_attr(
42246    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42247    assert_instr(raddhn)
42248)]
42249#[cfg_attr(
42250    not(target_arch = "arm"),
42251    stable(feature = "neon_intrinsics", since = "1.59.0")
42252)]
42253#[cfg_attr(
42254    target_arch = "arm",
42255    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42256)]
42257pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42258    unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
42259}
42260#[doc = "Rounding Add returning High Narrow."]
42261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42262#[inline]
42263#[cfg(target_endian = "big")]
42264#[target_feature(enable = "neon")]
42265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42267#[cfg_attr(
42268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42269    assert_instr(raddhn)
42270)]
42271#[cfg_attr(
42272    not(target_arch = "arm"),
42273    stable(feature = "neon_intrinsics", since = "1.59.0")
42274)]
42275#[cfg_attr(
42276    target_arch = "arm",
42277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42278)]
42279pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42280    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42281    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
42282    unsafe {
42283        let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
42284        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42285    }
42286}
42287#[doc = "Rounding Add returning High Narrow."]
42288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42289#[inline]
42290#[cfg(target_endian = "little")]
42291#[target_feature(enable = "neon")]
42292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42294#[cfg_attr(
42295    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42296    assert_instr(raddhn)
42297)]
42298#[cfg_attr(
42299    not(target_arch = "arm"),
42300    stable(feature = "neon_intrinsics", since = "1.59.0")
42301)]
42302#[cfg_attr(
42303    target_arch = "arm",
42304    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42305)]
42306pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42307    unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
42308}
42309#[doc = "Rounding Add returning High Narrow."]
42310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42311#[inline]
42312#[cfg(target_endian = "big")]
42313#[target_feature(enable = "neon")]
42314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42316#[cfg_attr(
42317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42318    assert_instr(raddhn)
42319)]
42320#[cfg_attr(
42321    not(target_arch = "arm"),
42322    stable(feature = "neon_intrinsics", since = "1.59.0")
42323)]
42324#[cfg_attr(
42325    target_arch = "arm",
42326    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42327)]
42328pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42329    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42330    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
42331    unsafe {
42332        let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
42333        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42334    }
42335}
42336#[doc = "Rounding Add returning High Narrow."]
42337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42338#[inline]
42339#[cfg(target_endian = "little")]
42340#[target_feature(enable = "neon")]
42341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42342#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42343#[cfg_attr(
42344    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42345    assert_instr(raddhn)
42346)]
42347#[cfg_attr(
42348    not(target_arch = "arm"),
42349    stable(feature = "neon_intrinsics", since = "1.59.0")
42350)]
42351#[cfg_attr(
42352    target_arch = "arm",
42353    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42354)]
42355pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42356    unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
42357}
42358#[doc = "Rounding Add returning High Narrow."]
42359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42360#[inline]
42361#[cfg(target_endian = "big")]
42362#[target_feature(enable = "neon")]
42363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42364#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42365#[cfg_attr(
42366    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42367    assert_instr(raddhn)
42368)]
42369#[cfg_attr(
42370    not(target_arch = "arm"),
42371    stable(feature = "neon_intrinsics", since = "1.59.0")
42372)]
42373#[cfg_attr(
42374    target_arch = "arm",
42375    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42376)]
42377pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42378    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42379    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
42380    unsafe {
42381        let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
42382        simd_shuffle!(ret_val, ret_val, [1, 0])
42383    }
42384}
42385#[doc = "Reciprocal estimate."]
42386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
42387#[inline]
42388#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42390#[cfg_attr(
42391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42392    assert_instr(frecpe)
42393)]
42394#[target_feature(enable = "neon,fp16")]
42395#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42396pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
42397    unsafe extern "unadjusted" {
42398        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")]
42399        #[cfg_attr(
42400            any(target_arch = "aarch64", target_arch = "arm64ec"),
42401            link_name = "llvm.aarch64.neon.frecpe.v4f16"
42402        )]
42403        fn _vrecpe_f16(a: float16x4_t) -> float16x4_t;
42404    }
42405    unsafe { _vrecpe_f16(a) }
42406}
42407#[doc = "Reciprocal estimate."]
42408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
42409#[inline]
42410#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42412#[cfg_attr(
42413    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42414    assert_instr(frecpe)
42415)]
42416#[target_feature(enable = "neon,fp16")]
42417#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42418pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
42419    unsafe extern "unadjusted" {
42420        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")]
42421        #[cfg_attr(
42422            any(target_arch = "aarch64", target_arch = "arm64ec"),
42423            link_name = "llvm.aarch64.neon.frecpe.v8f16"
42424        )]
42425        fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t;
42426    }
42427    unsafe { _vrecpeq_f16(a) }
42428}
42429#[doc = "Reciprocal estimate."]
42430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
42431#[inline]
42432#[target_feature(enable = "neon")]
42433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42435#[cfg_attr(
42436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42437    assert_instr(frecpe)
42438)]
42439#[cfg_attr(
42440    not(target_arch = "arm"),
42441    stable(feature = "neon_intrinsics", since = "1.59.0")
42442)]
42443#[cfg_attr(
42444    target_arch = "arm",
42445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42446)]
42447pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
42448    unsafe extern "unadjusted" {
42449        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")]
42450        #[cfg_attr(
42451            any(target_arch = "aarch64", target_arch = "arm64ec"),
42452            link_name = "llvm.aarch64.neon.frecpe.v2f32"
42453        )]
42454        fn _vrecpe_f32(a: float32x2_t) -> float32x2_t;
42455    }
42456    unsafe { _vrecpe_f32(a) }
42457}
42458#[doc = "Reciprocal estimate."]
42459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
42460#[inline]
42461#[target_feature(enable = "neon")]
42462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42464#[cfg_attr(
42465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42466    assert_instr(frecpe)
42467)]
42468#[cfg_attr(
42469    not(target_arch = "arm"),
42470    stable(feature = "neon_intrinsics", since = "1.59.0")
42471)]
42472#[cfg_attr(
42473    target_arch = "arm",
42474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42475)]
42476pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
42477    unsafe extern "unadjusted" {
42478        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")]
42479        #[cfg_attr(
42480            any(target_arch = "aarch64", target_arch = "arm64ec"),
42481            link_name = "llvm.aarch64.neon.frecpe.v4f32"
42482        )]
42483        fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t;
42484    }
42485    unsafe { _vrecpeq_f32(a) }
42486}
42487#[doc = "Unsigned reciprocal estimate"]
42488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
42489#[inline]
42490#[target_feature(enable = "neon")]
42491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42493#[cfg_attr(
42494    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42495    assert_instr(urecpe)
42496)]
42497#[cfg_attr(
42498    not(target_arch = "arm"),
42499    stable(feature = "neon_intrinsics", since = "1.59.0")
42500)]
42501#[cfg_attr(
42502    target_arch = "arm",
42503    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42504)]
42505pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
42506    unsafe extern "unadjusted" {
42507        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")]
42508        #[cfg_attr(
42509            any(target_arch = "aarch64", target_arch = "arm64ec"),
42510            link_name = "llvm.aarch64.neon.urecpe.v2i32"
42511        )]
42512        fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t;
42513    }
42514    unsafe { _vrecpe_u32(a) }
42515}
42516#[doc = "Unsigned reciprocal estimate"]
42517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
42518#[inline]
42519#[target_feature(enable = "neon")]
42520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42522#[cfg_attr(
42523    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42524    assert_instr(urecpe)
42525)]
42526#[cfg_attr(
42527    not(target_arch = "arm"),
42528    stable(feature = "neon_intrinsics", since = "1.59.0")
42529)]
42530#[cfg_attr(
42531    target_arch = "arm",
42532    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42533)]
42534pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
42535    unsafe extern "unadjusted" {
42536        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")]
42537        #[cfg_attr(
42538            any(target_arch = "aarch64", target_arch = "arm64ec"),
42539            link_name = "llvm.aarch64.neon.urecpe.v4i32"
42540        )]
42541        fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t;
42542    }
42543    unsafe { _vrecpeq_u32(a) }
42544}
42545#[doc = "Floating-point reciprocal step"]
42546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
42547#[inline]
42548#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42550#[cfg_attr(
42551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42552    assert_instr(frecps)
42553)]
42554#[target_feature(enable = "neon,fp16")]
42555#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42556pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
42557    unsafe extern "unadjusted" {
42558        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")]
42559        #[cfg_attr(
42560            any(target_arch = "aarch64", target_arch = "arm64ec"),
42561            link_name = "llvm.aarch64.neon.frecps.v4f16"
42562        )]
42563        fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
42564    }
42565    unsafe { _vrecps_f16(a, b) }
42566}
42567#[doc = "Floating-point reciprocal step"]
42568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
42569#[inline]
42570#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42572#[cfg_attr(
42573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42574    assert_instr(frecps)
42575)]
42576#[target_feature(enable = "neon,fp16")]
42577#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42578pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
42579    unsafe extern "unadjusted" {
42580        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")]
42581        #[cfg_attr(
42582            any(target_arch = "aarch64", target_arch = "arm64ec"),
42583            link_name = "llvm.aarch64.neon.frecps.v8f16"
42584        )]
42585        fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
42586    }
42587    unsafe { _vrecpsq_f16(a, b) }
42588}
42589#[doc = "Floating-point reciprocal step"]
42590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
42591#[inline]
42592#[target_feature(enable = "neon")]
42593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42594#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42595#[cfg_attr(
42596    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42597    assert_instr(frecps)
42598)]
42599#[cfg_attr(
42600    not(target_arch = "arm"),
42601    stable(feature = "neon_intrinsics", since = "1.59.0")
42602)]
42603#[cfg_attr(
42604    target_arch = "arm",
42605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42606)]
42607pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
42608    unsafe extern "unadjusted" {
42609        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")]
42610        #[cfg_attr(
42611            any(target_arch = "aarch64", target_arch = "arm64ec"),
42612            link_name = "llvm.aarch64.neon.frecps.v2f32"
42613        )]
42614        fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
42615    }
42616    unsafe { _vrecps_f32(a, b) }
42617}
42618#[doc = "Floating-point reciprocal step"]
42619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
42620#[inline]
42621#[target_feature(enable = "neon")]
42622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42624#[cfg_attr(
42625    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42626    assert_instr(frecps)
42627)]
42628#[cfg_attr(
42629    not(target_arch = "arm"),
42630    stable(feature = "neon_intrinsics", since = "1.59.0")
42631)]
42632#[cfg_attr(
42633    target_arch = "arm",
42634    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42635)]
42636pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
42637    unsafe extern "unadjusted" {
42638        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")]
42639        #[cfg_attr(
42640            any(target_arch = "aarch64", target_arch = "arm64ec"),
42641            link_name = "llvm.aarch64.neon.frecps.v4f32"
42642        )]
42643        fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
42644    }
42645    unsafe { _vrecpsq_f32(a, b) }
42646}
42647#[doc = "Vector reinterpret cast operation"]
42648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42649#[inline]
42650#[cfg(target_endian = "little")]
42651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42653#[cfg_attr(
42654    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42655    assert_instr(nop)
42656)]
42657#[target_feature(enable = "neon,fp16")]
42658#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42659pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42660    unsafe { transmute(a) }
42661}
42662#[doc = "Vector reinterpret cast operation"]
42663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42664#[inline]
42665#[cfg(target_endian = "big")]
42666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42668#[cfg_attr(
42669    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42670    assert_instr(nop)
42671)]
42672#[target_feature(enable = "neon,fp16")]
42673#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42674pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42675    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42676    unsafe {
42677        let ret_val: float32x2_t = transmute(a);
42678        simd_shuffle!(ret_val, ret_val, [1, 0])
42679    }
42680}
42681#[doc = "Vector reinterpret cast operation"]
42682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42683#[inline]
42684#[cfg(target_endian = "little")]
42685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42687#[cfg_attr(
42688    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42689    assert_instr(nop)
42690)]
42691#[target_feature(enable = "neon,fp16")]
42692#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42693pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42694    unsafe { transmute(a) }
42695}
42696#[doc = "Vector reinterpret cast operation"]
42697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42698#[inline]
42699#[cfg(target_endian = "big")]
42700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42702#[cfg_attr(
42703    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42704    assert_instr(nop)
42705)]
42706#[target_feature(enable = "neon,fp16")]
42707#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42708pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42709    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42710    unsafe {
42711        let ret_val: int8x8_t = transmute(a);
42712        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42713    }
42714}
42715#[doc = "Vector reinterpret cast operation"]
42716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42717#[inline]
42718#[cfg(target_endian = "little")]
42719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42721#[cfg_attr(
42722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42723    assert_instr(nop)
42724)]
42725#[target_feature(enable = "neon,fp16")]
42726#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42727pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42728    unsafe { transmute(a) }
42729}
42730#[doc = "Vector reinterpret cast operation"]
42731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42732#[inline]
42733#[cfg(target_endian = "big")]
42734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42736#[cfg_attr(
42737    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42738    assert_instr(nop)
42739)]
42740#[target_feature(enable = "neon,fp16")]
42741#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42742pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42743    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42744    unsafe {
42745        let ret_val: int16x4_t = transmute(a);
42746        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42747    }
42748}
42749#[doc = "Vector reinterpret cast operation"]
42750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42751#[inline]
42752#[cfg(target_endian = "little")]
42753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42755#[cfg_attr(
42756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42757    assert_instr(nop)
42758)]
42759#[target_feature(enable = "neon,fp16")]
42760#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42761pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42762    unsafe { transmute(a) }
42763}
42764#[doc = "Vector reinterpret cast operation"]
42765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42766#[inline]
42767#[cfg(target_endian = "big")]
42768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42770#[cfg_attr(
42771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42772    assert_instr(nop)
42773)]
42774#[target_feature(enable = "neon,fp16")]
42775#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42776pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42777    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42778    unsafe {
42779        let ret_val: int32x2_t = transmute(a);
42780        simd_shuffle!(ret_val, ret_val, [1, 0])
42781    }
42782}
42783#[doc = "Vector reinterpret cast operation"]
42784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42785#[inline]
42786#[cfg(target_endian = "little")]
42787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42789#[cfg_attr(
42790    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42791    assert_instr(nop)
42792)]
42793#[target_feature(enable = "neon,fp16")]
42794#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42795pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42796    unsafe { transmute(a) }
42797}
42798#[doc = "Vector reinterpret cast operation"]
42799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42800#[inline]
42801#[cfg(target_endian = "big")]
42802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42804#[cfg_attr(
42805    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42806    assert_instr(nop)
42807)]
42808#[target_feature(enable = "neon,fp16")]
42809#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42810pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42811    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42812    unsafe { transmute(a) }
42813}
42814#[doc = "Vector reinterpret cast operation"]
42815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42816#[inline]
42817#[cfg(target_endian = "little")]
42818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42820#[cfg_attr(
42821    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42822    assert_instr(nop)
42823)]
42824#[target_feature(enable = "neon,fp16")]
42825#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42826pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42827    unsafe { transmute(a) }
42828}
42829#[doc = "Vector reinterpret cast operation"]
42830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42831#[inline]
42832#[cfg(target_endian = "big")]
42833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42835#[cfg_attr(
42836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42837    assert_instr(nop)
42838)]
42839#[target_feature(enable = "neon,fp16")]
42840#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42841pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42842    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42843    unsafe {
42844        let ret_val: uint8x8_t = transmute(a);
42845        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42846    }
42847}
42848#[doc = "Vector reinterpret cast operation"]
42849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42850#[inline]
42851#[cfg(target_endian = "little")]
42852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42854#[cfg_attr(
42855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42856    assert_instr(nop)
42857)]
42858#[target_feature(enable = "neon,fp16")]
42859#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42860pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42861    unsafe { transmute(a) }
42862}
42863#[doc = "Vector reinterpret cast operation"]
42864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42865#[inline]
42866#[cfg(target_endian = "big")]
42867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42869#[cfg_attr(
42870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42871    assert_instr(nop)
42872)]
42873#[target_feature(enable = "neon,fp16")]
42874#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42875pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42876    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42877    unsafe {
42878        let ret_val: uint16x4_t = transmute(a);
42879        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42880    }
42881}
42882#[doc = "Vector reinterpret cast operation"]
42883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42884#[inline]
42885#[cfg(target_endian = "little")]
42886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42888#[cfg_attr(
42889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42890    assert_instr(nop)
42891)]
42892#[target_feature(enable = "neon,fp16")]
42893#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42894pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42895    unsafe { transmute(a) }
42896}
42897#[doc = "Vector reinterpret cast operation"]
42898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42899#[inline]
42900#[cfg(target_endian = "big")]
42901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42903#[cfg_attr(
42904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42905    assert_instr(nop)
42906)]
42907#[target_feature(enable = "neon,fp16")]
42908#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42909pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42910    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42911    unsafe {
42912        let ret_val: uint32x2_t = transmute(a);
42913        simd_shuffle!(ret_val, ret_val, [1, 0])
42914    }
42915}
42916#[doc = "Vector reinterpret cast operation"]
42917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42918#[inline]
42919#[cfg(target_endian = "little")]
42920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42921#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42922#[cfg_attr(
42923    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42924    assert_instr(nop)
42925)]
42926#[target_feature(enable = "neon,fp16")]
42927#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42928pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42929    unsafe { transmute(a) }
42930}
42931#[doc = "Vector reinterpret cast operation"]
42932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42933#[inline]
42934#[cfg(target_endian = "big")]
42935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42937#[cfg_attr(
42938    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42939    assert_instr(nop)
42940)]
42941#[target_feature(enable = "neon,fp16")]
42942#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42943pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42944    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42945    unsafe { transmute(a) }
42946}
42947#[doc = "Vector reinterpret cast operation"]
42948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42949#[inline]
42950#[cfg(target_endian = "little")]
42951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42953#[cfg_attr(
42954    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42955    assert_instr(nop)
42956)]
42957#[target_feature(enable = "neon,fp16")]
42958#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42959pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42960    unsafe { transmute(a) }
42961}
42962#[doc = "Vector reinterpret cast operation"]
42963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42964#[inline]
42965#[cfg(target_endian = "big")]
42966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42968#[cfg_attr(
42969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42970    assert_instr(nop)
42971)]
42972#[target_feature(enable = "neon,fp16")]
42973#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42974pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42975    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42976    unsafe {
42977        let ret_val: poly8x8_t = transmute(a);
42978        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42979    }
42980}
42981#[doc = "Vector reinterpret cast operation"]
42982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42983#[inline]
42984#[cfg(target_endian = "little")]
42985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42987#[cfg_attr(
42988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42989    assert_instr(nop)
42990)]
42991#[target_feature(enable = "neon,fp16")]
42992#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42993pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42994    unsafe { transmute(a) }
42995}
42996#[doc = "Vector reinterpret cast operation"]
42997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42998#[inline]
42999#[cfg(target_endian = "big")]
43000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43002#[cfg_attr(
43003    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43004    assert_instr(nop)
43005)]
43006#[target_feature(enable = "neon,fp16")]
43007#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43008pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
43009    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43010    unsafe {
43011        let ret_val: poly16x4_t = transmute(a);
43012        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43013    }
43014}
43015#[doc = "Vector reinterpret cast operation"]
43016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
43017#[inline]
43018#[cfg(target_endian = "little")]
43019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43021#[cfg_attr(
43022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43023    assert_instr(nop)
43024)]
43025#[target_feature(enable = "neon,fp16")]
43026#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43027pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
43028    unsafe { transmute(a) }
43029}
43030#[doc = "Vector reinterpret cast operation"]
43031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
43032#[inline]
43033#[cfg(target_endian = "big")]
43034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43036#[cfg_attr(
43037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43038    assert_instr(nop)
43039)]
43040#[target_feature(enable = "neon,fp16")]
43041#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43042pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
43043    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43044    unsafe {
43045        let ret_val: float32x4_t = transmute(a);
43046        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43047    }
43048}
43049#[doc = "Vector reinterpret cast operation"]
43050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
43051#[inline]
43052#[cfg(target_endian = "little")]
43053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43055#[cfg_attr(
43056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43057    assert_instr(nop)
43058)]
43059#[target_feature(enable = "neon,fp16")]
43060#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43061pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
43062    unsafe { transmute(a) }
43063}
43064#[doc = "Vector reinterpret cast operation"]
43065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
43066#[inline]
43067#[cfg(target_endian = "big")]
43068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43070#[cfg_attr(
43071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43072    assert_instr(nop)
43073)]
43074#[target_feature(enable = "neon,fp16")]
43075#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43076pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
43077    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43078    unsafe {
43079        let ret_val: int8x16_t = transmute(a);
43080        simd_shuffle!(
43081            ret_val,
43082            ret_val,
43083            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43084        )
43085    }
43086}
43087#[doc = "Vector reinterpret cast operation"]
43088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43089#[inline]
43090#[cfg(target_endian = "little")]
43091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43093#[cfg_attr(
43094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43095    assert_instr(nop)
43096)]
43097#[target_feature(enable = "neon,fp16")]
43098#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43099pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43100    unsafe { transmute(a) }
43101}
43102#[doc = "Vector reinterpret cast operation"]
43103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43104#[inline]
43105#[cfg(target_endian = "big")]
43106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43108#[cfg_attr(
43109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43110    assert_instr(nop)
43111)]
43112#[target_feature(enable = "neon,fp16")]
43113#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43114pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43115    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43116    unsafe {
43117        let ret_val: int16x8_t = transmute(a);
43118        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43119    }
43120}
43121#[doc = "Vector reinterpret cast operation"]
43122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43123#[inline]
43124#[cfg(target_endian = "little")]
43125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43127#[cfg_attr(
43128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43129    assert_instr(nop)
43130)]
43131#[target_feature(enable = "neon,fp16")]
43132#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43133pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43134    unsafe { transmute(a) }
43135}
43136#[doc = "Vector reinterpret cast operation"]
43137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43138#[inline]
43139#[cfg(target_endian = "big")]
43140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43142#[cfg_attr(
43143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43144    assert_instr(nop)
43145)]
43146#[target_feature(enable = "neon,fp16")]
43147#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43148pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43149    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43150    unsafe {
43151        let ret_val: int32x4_t = transmute(a);
43152        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43153    }
43154}
43155#[doc = "Vector reinterpret cast operation"]
43156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43157#[inline]
43158#[cfg(target_endian = "little")]
43159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43161#[cfg_attr(
43162    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43163    assert_instr(nop)
43164)]
43165#[target_feature(enable = "neon,fp16")]
43166#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43167pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43168    unsafe { transmute(a) }
43169}
43170#[doc = "Vector reinterpret cast operation"]
43171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43172#[inline]
43173#[cfg(target_endian = "big")]
43174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43176#[cfg_attr(
43177    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43178    assert_instr(nop)
43179)]
43180#[target_feature(enable = "neon,fp16")]
43181#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43182pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43183    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43184    unsafe {
43185        let ret_val: int64x2_t = transmute(a);
43186        simd_shuffle!(ret_val, ret_val, [1, 0])
43187    }
43188}
43189#[doc = "Vector reinterpret cast operation"]
43190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43191#[inline]
43192#[cfg(target_endian = "little")]
43193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43195#[cfg_attr(
43196    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43197    assert_instr(nop)
43198)]
43199#[target_feature(enable = "neon,fp16")]
43200#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43201pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43202    unsafe { transmute(a) }
43203}
43204#[doc = "Vector reinterpret cast operation"]
43205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43206#[inline]
43207#[cfg(target_endian = "big")]
43208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43210#[cfg_attr(
43211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43212    assert_instr(nop)
43213)]
43214#[target_feature(enable = "neon,fp16")]
43215#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43216pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43217    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43218    unsafe {
43219        let ret_val: uint8x16_t = transmute(a);
43220        simd_shuffle!(
43221            ret_val,
43222            ret_val,
43223            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43224        )
43225    }
43226}
43227#[doc = "Vector reinterpret cast operation"]
43228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43229#[inline]
43230#[cfg(target_endian = "little")]
43231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43233#[cfg_attr(
43234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43235    assert_instr(nop)
43236)]
43237#[target_feature(enable = "neon,fp16")]
43238#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43239pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43240    unsafe { transmute(a) }
43241}
43242#[doc = "Vector reinterpret cast operation"]
43243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43244#[inline]
43245#[cfg(target_endian = "big")]
43246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43248#[cfg_attr(
43249    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43250    assert_instr(nop)
43251)]
43252#[target_feature(enable = "neon,fp16")]
43253#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43254pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43255    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43256    unsafe {
43257        let ret_val: uint16x8_t = transmute(a);
43258        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43259    }
43260}
43261#[doc = "Vector reinterpret cast operation"]
43262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43263#[inline]
43264#[cfg(target_endian = "little")]
43265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43267#[cfg_attr(
43268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43269    assert_instr(nop)
43270)]
43271#[target_feature(enable = "neon,fp16")]
43272#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43273pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43274    unsafe { transmute(a) }
43275}
43276#[doc = "Vector reinterpret cast operation"]
43277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43278#[inline]
43279#[cfg(target_endian = "big")]
43280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43282#[cfg_attr(
43283    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43284    assert_instr(nop)
43285)]
43286#[target_feature(enable = "neon,fp16")]
43287#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43288pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43289    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43290    unsafe {
43291        let ret_val: uint32x4_t = transmute(a);
43292        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43293    }
43294}
43295#[doc = "Vector reinterpret cast operation"]
43296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43297#[inline]
43298#[cfg(target_endian = "little")]
43299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43301#[cfg_attr(
43302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43303    assert_instr(nop)
43304)]
43305#[target_feature(enable = "neon,fp16")]
43306#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43307pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43308    unsafe { transmute(a) }
43309}
43310#[doc = "Vector reinterpret cast operation"]
43311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43312#[inline]
43313#[cfg(target_endian = "big")]
43314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43316#[cfg_attr(
43317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43318    assert_instr(nop)
43319)]
43320#[target_feature(enable = "neon,fp16")]
43321#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43322pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43323    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43324    unsafe {
43325        let ret_val: uint64x2_t = transmute(a);
43326        simd_shuffle!(ret_val, ret_val, [1, 0])
43327    }
43328}
43329#[doc = "Vector reinterpret cast operation"]
43330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43331#[inline]
43332#[cfg(target_endian = "little")]
43333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43335#[cfg_attr(
43336    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43337    assert_instr(nop)
43338)]
43339#[target_feature(enable = "neon,fp16")]
43340#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43341pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43342    unsafe { transmute(a) }
43343}
43344#[doc = "Vector reinterpret cast operation"]
43345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43346#[inline]
43347#[cfg(target_endian = "big")]
43348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43350#[cfg_attr(
43351    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43352    assert_instr(nop)
43353)]
43354#[target_feature(enable = "neon,fp16")]
43355#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43356pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43357    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43358    unsafe {
43359        let ret_val: poly8x16_t = transmute(a);
43360        simd_shuffle!(
43361            ret_val,
43362            ret_val,
43363            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43364        )
43365    }
43366}
43367#[doc = "Vector reinterpret cast operation"]
43368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43369#[inline]
43370#[cfg(target_endian = "little")]
43371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43373#[cfg_attr(
43374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43375    assert_instr(nop)
43376)]
43377#[target_feature(enable = "neon,fp16")]
43378#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43379pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43380    unsafe { transmute(a) }
43381}
43382#[doc = "Vector reinterpret cast operation"]
43383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43384#[inline]
43385#[cfg(target_endian = "big")]
43386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43388#[cfg_attr(
43389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43390    assert_instr(nop)
43391)]
43392#[target_feature(enable = "neon,fp16")]
43393#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43394pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43395    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43396    unsafe {
43397        let ret_val: poly16x8_t = transmute(a);
43398        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43399    }
43400}
43401#[doc = "Vector reinterpret cast operation"]
43402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43403#[inline]
43404#[cfg(target_endian = "little")]
43405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43407#[cfg_attr(
43408    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43409    assert_instr(nop)
43410)]
43411#[target_feature(enable = "neon,fp16")]
43412#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43413pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43414    unsafe { transmute(a) }
43415}
43416#[doc = "Vector reinterpret cast operation"]
43417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43418#[inline]
43419#[cfg(target_endian = "big")]
43420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43422#[cfg_attr(
43423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43424    assert_instr(nop)
43425)]
43426#[target_feature(enable = "neon,fp16")]
43427#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43428pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43429    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43430    unsafe {
43431        let ret_val: float16x4_t = transmute(a);
43432        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43433    }
43434}
43435#[doc = "Vector reinterpret cast operation"]
43436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43437#[inline]
43438#[cfg(target_endian = "little")]
43439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43441#[cfg_attr(
43442    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43443    assert_instr(nop)
43444)]
43445#[target_feature(enable = "neon,fp16")]
43446#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43447pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43448    unsafe { transmute(a) }
43449}
43450#[doc = "Vector reinterpret cast operation"]
43451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43452#[inline]
43453#[cfg(target_endian = "big")]
43454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43456#[cfg_attr(
43457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43458    assert_instr(nop)
43459)]
43460#[target_feature(enable = "neon,fp16")]
43461#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43462pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43463    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43464    unsafe {
43465        let ret_val: float16x8_t = transmute(a);
43466        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43467    }
43468}
43469#[doc = "Vector reinterpret cast operation"]
43470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43471#[inline]
43472#[cfg(target_endian = "little")]
43473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43475#[cfg_attr(
43476    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43477    assert_instr(nop)
43478)]
43479#[target_feature(enable = "neon,fp16")]
43480#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43481pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43482    unsafe { transmute(a) }
43483}
43484#[doc = "Vector reinterpret cast operation"]
43485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43486#[inline]
43487#[cfg(target_endian = "big")]
43488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43490#[cfg_attr(
43491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43492    assert_instr(nop)
43493)]
43494#[target_feature(enable = "neon,fp16")]
43495#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43496pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43497    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43498    unsafe {
43499        let ret_val: float16x4_t = transmute(a);
43500        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43501    }
43502}
43503#[doc = "Vector reinterpret cast operation"]
43504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43505#[inline]
43506#[cfg(target_endian = "little")]
43507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43509#[cfg_attr(
43510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43511    assert_instr(nop)
43512)]
43513#[target_feature(enable = "neon,fp16")]
43514#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43515pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43516    unsafe { transmute(a) }
43517}
43518#[doc = "Vector reinterpret cast operation"]
43519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43520#[inline]
43521#[cfg(target_endian = "big")]
43522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43524#[cfg_attr(
43525    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43526    assert_instr(nop)
43527)]
43528#[target_feature(enable = "neon,fp16")]
43529#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43530pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43531    let a: int8x16_t =
43532        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43533    unsafe {
43534        let ret_val: float16x8_t = transmute(a);
43535        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43536    }
43537}
43538#[doc = "Vector reinterpret cast operation"]
43539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43540#[inline]
43541#[cfg(target_endian = "little")]
43542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43544#[cfg_attr(
43545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43546    assert_instr(nop)
43547)]
43548#[target_feature(enable = "neon,fp16")]
43549#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43550pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43551    unsafe { transmute(a) }
43552}
43553#[doc = "Vector reinterpret cast operation"]
43554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43555#[inline]
43556#[cfg(target_endian = "big")]
43557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43559#[cfg_attr(
43560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43561    assert_instr(nop)
43562)]
43563#[target_feature(enable = "neon,fp16")]
43564#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43565pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43566    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43567    unsafe {
43568        let ret_val: float16x4_t = transmute(a);
43569        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43570    }
43571}
43572#[doc = "Vector reinterpret cast operation"]
43573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43574#[inline]
43575#[cfg(target_endian = "little")]
43576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43578#[cfg_attr(
43579    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43580    assert_instr(nop)
43581)]
43582#[target_feature(enable = "neon,fp16")]
43583#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43584pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43585    unsafe { transmute(a) }
43586}
43587#[doc = "Vector reinterpret cast operation"]
43588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43589#[inline]
43590#[cfg(target_endian = "big")]
43591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43593#[cfg_attr(
43594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43595    assert_instr(nop)
43596)]
43597#[target_feature(enable = "neon,fp16")]
43598#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43599pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43600    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43601    unsafe {
43602        let ret_val: float16x8_t = transmute(a);
43603        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43604    }
43605}
43606#[doc = "Vector reinterpret cast operation"]
43607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43608#[inline]
43609#[cfg(target_endian = "little")]
43610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43612#[cfg_attr(
43613    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43614    assert_instr(nop)
43615)]
43616#[target_feature(enable = "neon,fp16")]
43617#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43618pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43619    unsafe { transmute(a) }
43620}
43621#[doc = "Vector reinterpret cast operation"]
43622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43623#[inline]
43624#[cfg(target_endian = "big")]
43625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43627#[cfg_attr(
43628    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43629    assert_instr(nop)
43630)]
43631#[target_feature(enable = "neon,fp16")]
43632#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43633pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43634    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43635    unsafe {
43636        let ret_val: float16x4_t = transmute(a);
43637        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43638    }
43639}
43640#[doc = "Vector reinterpret cast operation"]
43641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43642#[inline]
43643#[cfg(target_endian = "little")]
43644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43646#[cfg_attr(
43647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43648    assert_instr(nop)
43649)]
43650#[target_feature(enable = "neon,fp16")]
43651#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43652pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43653    unsafe { transmute(a) }
43654}
43655#[doc = "Vector reinterpret cast operation"]
43656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43657#[inline]
43658#[cfg(target_endian = "big")]
43659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43661#[cfg_attr(
43662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43663    assert_instr(nop)
43664)]
43665#[target_feature(enable = "neon,fp16")]
43666#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43667pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43668    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43669    unsafe {
43670        let ret_val: float16x8_t = transmute(a);
43671        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43672    }
43673}
43674#[doc = "Vector reinterpret cast operation"]
43675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43676#[inline]
43677#[cfg(target_endian = "little")]
43678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43680#[cfg_attr(
43681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43682    assert_instr(nop)
43683)]
43684#[target_feature(enable = "neon,fp16")]
43685#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43686pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43687    unsafe { transmute(a) }
43688}
43689#[doc = "Vector reinterpret cast operation"]
43690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43691#[inline]
43692#[cfg(target_endian = "big")]
43693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43695#[cfg_attr(
43696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43697    assert_instr(nop)
43698)]
43699#[target_feature(enable = "neon,fp16")]
43700#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43701pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43702    unsafe {
43703        let ret_val: float16x4_t = transmute(a);
43704        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43705    }
43706}
43707#[doc = "Vector reinterpret cast operation"]
43708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43709#[inline]
43710#[cfg(target_endian = "little")]
43711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43713#[cfg_attr(
43714    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43715    assert_instr(nop)
43716)]
43717#[target_feature(enable = "neon,fp16")]
43718#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43719pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43720    unsafe { transmute(a) }
43721}
43722#[doc = "Vector reinterpret cast operation"]
43723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43724#[inline]
43725#[cfg(target_endian = "big")]
43726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43728#[cfg_attr(
43729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43730    assert_instr(nop)
43731)]
43732#[target_feature(enable = "neon,fp16")]
43733#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43734pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43735    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43736    unsafe {
43737        let ret_val: float16x8_t = transmute(a);
43738        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43739    }
43740}
43741#[doc = "Vector reinterpret cast operation"]
43742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43743#[inline]
43744#[cfg(target_endian = "little")]
43745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43747#[cfg_attr(
43748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43749    assert_instr(nop)
43750)]
43751#[target_feature(enable = "neon,fp16")]
43752#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43753pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43754    unsafe { transmute(a) }
43755}
43756#[doc = "Vector reinterpret cast operation"]
43757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43758#[inline]
43759#[cfg(target_endian = "big")]
43760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43762#[cfg_attr(
43763    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43764    assert_instr(nop)
43765)]
43766#[target_feature(enable = "neon,fp16")]
43767#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43768pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43769    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43770    unsafe {
43771        let ret_val: float16x4_t = transmute(a);
43772        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43773    }
43774}
43775#[doc = "Vector reinterpret cast operation"]
43776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43777#[inline]
43778#[cfg(target_endian = "little")]
43779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43781#[cfg_attr(
43782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43783    assert_instr(nop)
43784)]
43785#[target_feature(enable = "neon,fp16")]
43786#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43787pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43788    unsafe { transmute(a) }
43789}
43790#[doc = "Vector reinterpret cast operation"]
43791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43792#[inline]
43793#[cfg(target_endian = "big")]
43794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43796#[cfg_attr(
43797    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43798    assert_instr(nop)
43799)]
43800#[target_feature(enable = "neon,fp16")]
43801#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43802pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43803    let a: uint8x16_t =
43804        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43805    unsafe {
43806        let ret_val: float16x8_t = transmute(a);
43807        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43808    }
43809}
43810#[doc = "Vector reinterpret cast operation"]
43811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43812#[inline]
43813#[cfg(target_endian = "little")]
43814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43816#[cfg_attr(
43817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43818    assert_instr(nop)
43819)]
43820#[target_feature(enable = "neon,fp16")]
43821#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43822pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43823    unsafe { transmute(a) }
43824}
43825#[doc = "Vector reinterpret cast operation"]
43826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43827#[inline]
43828#[cfg(target_endian = "big")]
43829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43831#[cfg_attr(
43832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43833    assert_instr(nop)
43834)]
43835#[target_feature(enable = "neon,fp16")]
43836#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43837pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43838    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43839    unsafe {
43840        let ret_val: float16x4_t = transmute(a);
43841        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43842    }
43843}
43844#[doc = "Vector reinterpret cast operation"]
43845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43846#[inline]
43847#[cfg(target_endian = "little")]
43848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43850#[cfg_attr(
43851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43852    assert_instr(nop)
43853)]
43854#[target_feature(enable = "neon,fp16")]
43855#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43856pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43857    unsafe { transmute(a) }
43858}
43859#[doc = "Vector reinterpret cast operation"]
43860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43861#[inline]
43862#[cfg(target_endian = "big")]
43863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43865#[cfg_attr(
43866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43867    assert_instr(nop)
43868)]
43869#[target_feature(enable = "neon,fp16")]
43870#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43871pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43872    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43873    unsafe {
43874        let ret_val: float16x8_t = transmute(a);
43875        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43876    }
43877}
43878#[doc = "Vector reinterpret cast operation"]
43879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43880#[inline]
43881#[cfg(target_endian = "little")]
43882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43883#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43884#[cfg_attr(
43885    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43886    assert_instr(nop)
43887)]
43888#[target_feature(enable = "neon,fp16")]
43889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43890pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43891    unsafe { transmute(a) }
43892}
43893#[doc = "Vector reinterpret cast operation"]
43894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43895#[inline]
43896#[cfg(target_endian = "big")]
43897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43899#[cfg_attr(
43900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43901    assert_instr(nop)
43902)]
43903#[target_feature(enable = "neon,fp16")]
43904#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43905pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43906    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43907    unsafe {
43908        let ret_val: float16x4_t = transmute(a);
43909        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43910    }
43911}
43912#[doc = "Vector reinterpret cast operation"]
43913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43914#[inline]
43915#[cfg(target_endian = "little")]
43916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43918#[cfg_attr(
43919    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43920    assert_instr(nop)
43921)]
43922#[target_feature(enable = "neon,fp16")]
43923#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43924pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43925    unsafe { transmute(a) }
43926}
43927#[doc = "Vector reinterpret cast operation"]
43928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43929#[inline]
43930#[cfg(target_endian = "big")]
43931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43933#[cfg_attr(
43934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43935    assert_instr(nop)
43936)]
43937#[target_feature(enable = "neon,fp16")]
43938#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43939pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43940    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43941    unsafe {
43942        let ret_val: float16x8_t = transmute(a);
43943        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43944    }
43945}
43946#[doc = "Vector reinterpret cast operation"]
43947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43948#[inline]
43949#[cfg(target_endian = "little")]
43950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43952#[cfg_attr(
43953    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43954    assert_instr(nop)
43955)]
43956#[target_feature(enable = "neon,fp16")]
43957#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43958pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43959    unsafe { transmute(a) }
43960}
43961#[doc = "Vector reinterpret cast operation"]
43962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43963#[inline]
43964#[cfg(target_endian = "big")]
43965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43967#[cfg_attr(
43968    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43969    assert_instr(nop)
43970)]
43971#[target_feature(enable = "neon,fp16")]
43972#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43973pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43974    unsafe {
43975        let ret_val: float16x4_t = transmute(a);
43976        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43977    }
43978}
43979#[doc = "Vector reinterpret cast operation"]
43980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43981#[inline]
43982#[cfg(target_endian = "little")]
43983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43985#[cfg_attr(
43986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43987    assert_instr(nop)
43988)]
43989#[target_feature(enable = "neon,fp16")]
43990#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43991pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43992    unsafe { transmute(a) }
43993}
43994#[doc = "Vector reinterpret cast operation"]
43995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43996#[inline]
43997#[cfg(target_endian = "big")]
43998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44000#[cfg_attr(
44001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44002    assert_instr(nop)
44003)]
44004#[target_feature(enable = "neon,fp16")]
44005#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44006pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
44007    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44008    unsafe {
44009        let ret_val: float16x8_t = transmute(a);
44010        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44011    }
44012}
44013#[doc = "Vector reinterpret cast operation"]
44014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
44015#[inline]
44016#[cfg(target_endian = "little")]
44017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44019#[cfg_attr(
44020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44021    assert_instr(nop)
44022)]
44023#[target_feature(enable = "neon,fp16")]
44024#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44025pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
44026    unsafe { transmute(a) }
44027}
44028#[doc = "Vector reinterpret cast operation"]
44029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
44030#[inline]
44031#[cfg(target_endian = "big")]
44032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44034#[cfg_attr(
44035    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44036    assert_instr(nop)
44037)]
44038#[target_feature(enable = "neon,fp16")]
44039#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44040pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
44041    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44042    unsafe {
44043        let ret_val: float16x4_t = transmute(a);
44044        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44045    }
44046}
44047#[doc = "Vector reinterpret cast operation"]
44048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
44049#[inline]
44050#[cfg(target_endian = "little")]
44051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44053#[cfg_attr(
44054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44055    assert_instr(nop)
44056)]
44057#[target_feature(enable = "neon,fp16")]
44058#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44059pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
44060    unsafe { transmute(a) }
44061}
44062#[doc = "Vector reinterpret cast operation"]
44063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
44064#[inline]
44065#[cfg(target_endian = "big")]
44066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44068#[cfg_attr(
44069    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44070    assert_instr(nop)
44071)]
44072#[target_feature(enable = "neon,fp16")]
44073#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44074pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
44075    let a: poly8x16_t =
44076        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
44077    unsafe {
44078        let ret_val: float16x8_t = transmute(a);
44079        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44080    }
44081}
44082#[doc = "Vector reinterpret cast operation"]
44083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
44084#[inline]
44085#[cfg(target_endian = "little")]
44086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44088#[cfg_attr(
44089    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44090    assert_instr(nop)
44091)]
44092#[target_feature(enable = "neon,fp16")]
44093#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44094pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44095    unsafe { transmute(a) }
44096}
44097#[doc = "Vector reinterpret cast operation"]
44098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
44099#[inline]
44100#[cfg(target_endian = "big")]
44101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44103#[cfg_attr(
44104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44105    assert_instr(nop)
44106)]
44107#[target_feature(enable = "neon,fp16")]
44108#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44109pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44110    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44111    unsafe {
44112        let ret_val: float16x4_t = transmute(a);
44113        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44114    }
44115}
44116#[doc = "Vector reinterpret cast operation"]
44117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44118#[inline]
44119#[cfg(target_endian = "little")]
44120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44122#[cfg_attr(
44123    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44124    assert_instr(nop)
44125)]
44126#[target_feature(enable = "neon,fp16")]
44127#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44128pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44129    unsafe { transmute(a) }
44130}
44131#[doc = "Vector reinterpret cast operation"]
44132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44133#[inline]
44134#[cfg(target_endian = "big")]
44135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44137#[cfg_attr(
44138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44139    assert_instr(nop)
44140)]
44141#[target_feature(enable = "neon,fp16")]
44142#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44143pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44144    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44145    unsafe {
44146        let ret_val: float16x8_t = transmute(a);
44147        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44148    }
44149}
44150#[doc = "Vector reinterpret cast operation"]
44151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44152#[inline]
44153#[cfg(target_endian = "little")]
44154#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44156#[cfg_attr(
44157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44158    assert_instr(nop)
44159)]
44160#[target_feature(enable = "neon,fp16")]
44161#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44162pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44163    unsafe { transmute(a) }
44164}
44165#[doc = "Vector reinterpret cast operation"]
44166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44167#[inline]
44168#[cfg(target_endian = "big")]
44169#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44171#[cfg_attr(
44172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44173    assert_instr(nop)
44174)]
44175#[target_feature(enable = "neon,fp16")]
44176#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44177pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44178    unsafe {
44179        let ret_val: float16x8_t = transmute(a);
44180        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44181    }
44182}
44183#[doc = "Vector reinterpret cast operation"]
44184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44185#[inline]
44186#[cfg(target_endian = "little")]
44187#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44189#[cfg_attr(
44190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44191    assert_instr(nop)
44192)]
44193#[target_feature(enable = "neon,fp16")]
44194#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44195pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44196    unsafe { transmute(a) }
44197}
44198#[doc = "Vector reinterpret cast operation"]
44199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44200#[inline]
44201#[cfg(target_endian = "big")]
44202#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44204#[cfg_attr(
44205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44206    assert_instr(nop)
44207)]
44208#[target_feature(enable = "neon,fp16")]
44209#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44210pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44211    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44212    unsafe { transmute(a) }
44213}
44214#[doc = "Vector reinterpret cast operation"]
44215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44216#[inline]
44217#[cfg(target_endian = "little")]
44218#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44220#[cfg_attr(
44221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44222    assert_instr(nop)
44223)]
44224#[target_feature(enable = "neon,fp16")]
44225#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44226pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44227    unsafe { transmute(a) }
44228}
44229#[doc = "Vector reinterpret cast operation"]
44230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44231#[inline]
44232#[cfg(target_endian = "big")]
44233#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44235#[cfg_attr(
44236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44237    assert_instr(nop)
44238)]
44239#[target_feature(enable = "neon,fp16")]
44240#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44241pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44242    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44243    unsafe { transmute(a) }
44244}
44245#[doc = "Vector reinterpret cast operation"]
44246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44247#[inline]
44248#[cfg(target_endian = "little")]
44249#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44251#[cfg_attr(
44252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44253    assert_instr(nop)
44254)]
44255#[target_feature(enable = "neon,fp16")]
44256#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44257pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44258    unsafe { transmute(a) }
44259}
44260#[doc = "Vector reinterpret cast operation"]
44261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44262#[inline]
44263#[cfg(target_endian = "big")]
44264#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44266#[cfg_attr(
44267    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44268    assert_instr(nop)
44269)]
44270#[target_feature(enable = "neon,fp16")]
44271#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44272pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44273    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44274    unsafe {
44275        let ret_val: poly64x2_t = transmute(a);
44276        simd_shuffle!(ret_val, ret_val, [1, 0])
44277    }
44278}
44279#[doc = "Vector reinterpret cast operation"]
44280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44281#[inline]
44282#[cfg(target_endian = "little")]
44283#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44285#[cfg_attr(
44286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44287    assert_instr(nop)
44288)]
44289#[target_feature(enable = "neon,fp16")]
44290#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44291pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44292    unsafe { transmute(a) }
44293}
44294#[doc = "Vector reinterpret cast operation"]
44295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44296#[inline]
44297#[cfg(target_endian = "big")]
44298#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44300#[cfg_attr(
44301    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44302    assert_instr(nop)
44303)]
44304#[target_feature(enable = "neon,fp16")]
44305#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44306pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44307    unsafe {
44308        let ret_val: float16x4_t = transmute(a);
44309        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44310    }
44311}
44312#[doc = "Vector reinterpret cast operation"]
44313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44314#[inline]
44315#[cfg(target_endian = "little")]
44316#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44318#[cfg_attr(
44319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44320    assert_instr(nop)
44321)]
44322#[target_feature(enable = "neon,fp16")]
44323#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44324pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44325    unsafe { transmute(a) }
44326}
44327#[doc = "Vector reinterpret cast operation"]
44328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44329#[inline]
44330#[cfg(target_endian = "big")]
44331#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44333#[cfg_attr(
44334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44335    assert_instr(nop)
44336)]
44337#[target_feature(enable = "neon,fp16")]
44338#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44339pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44340    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44341    unsafe {
44342        let ret_val: float16x8_t = transmute(a);
44343        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44344    }
44345}
44346#[doc = "Vector reinterpret cast operation"]
44347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44348#[inline]
44349#[cfg(target_endian = "little")]
44350#[target_feature(enable = "neon")]
44351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44353#[cfg_attr(
44354    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44355    assert_instr(nop)
44356)]
44357#[cfg_attr(
44358    not(target_arch = "arm"),
44359    stable(feature = "neon_intrinsics", since = "1.59.0")
44360)]
44361#[cfg_attr(
44362    target_arch = "arm",
44363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44364)]
44365pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44366    unsafe { transmute(a) }
44367}
44368#[doc = "Vector reinterpret cast operation"]
44369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44370#[inline]
44371#[cfg(target_endian = "big")]
44372#[target_feature(enable = "neon")]
44373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44375#[cfg_attr(
44376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44377    assert_instr(nop)
44378)]
44379#[cfg_attr(
44380    not(target_arch = "arm"),
44381    stable(feature = "neon_intrinsics", since = "1.59.0")
44382)]
44383#[cfg_attr(
44384    target_arch = "arm",
44385    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44386)]
44387pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44388    unsafe {
44389        let ret_val: float32x4_t = transmute(a);
44390        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44391    }
44392}
44393#[doc = "Vector reinterpret cast operation"]
44394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44395#[inline]
44396#[cfg(target_endian = "little")]
44397#[target_feature(enable = "neon")]
44398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44399#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44400#[cfg_attr(
44401    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44402    assert_instr(nop)
44403)]
44404#[cfg_attr(
44405    not(target_arch = "arm"),
44406    stable(feature = "neon_intrinsics", since = "1.59.0")
44407)]
44408#[cfg_attr(
44409    target_arch = "arm",
44410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44411)]
44412pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44413    unsafe { transmute(a) }
44414}
44415#[doc = "Vector reinterpret cast operation"]
44416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44417#[inline]
44418#[cfg(target_endian = "big")]
44419#[target_feature(enable = "neon")]
44420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44422#[cfg_attr(
44423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44424    assert_instr(nop)
44425)]
44426#[cfg_attr(
44427    not(target_arch = "arm"),
44428    stable(feature = "neon_intrinsics", since = "1.59.0")
44429)]
44430#[cfg_attr(
44431    target_arch = "arm",
44432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44433)]
44434pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44435    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44436    unsafe {
44437        let ret_val: int8x8_t = transmute(a);
44438        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44439    }
44440}
44441#[doc = "Vector reinterpret cast operation"]
44442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44443#[inline]
44444#[cfg(target_endian = "little")]
44445#[target_feature(enable = "neon")]
44446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44448#[cfg_attr(
44449    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44450    assert_instr(nop)
44451)]
44452#[cfg_attr(
44453    not(target_arch = "arm"),
44454    stable(feature = "neon_intrinsics", since = "1.59.0")
44455)]
44456#[cfg_attr(
44457    target_arch = "arm",
44458    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44459)]
44460pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44461    unsafe { transmute(a) }
44462}
44463#[doc = "Vector reinterpret cast operation"]
44464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44465#[inline]
44466#[cfg(target_endian = "big")]
44467#[target_feature(enable = "neon")]
44468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44470#[cfg_attr(
44471    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44472    assert_instr(nop)
44473)]
44474#[cfg_attr(
44475    not(target_arch = "arm"),
44476    stable(feature = "neon_intrinsics", since = "1.59.0")
44477)]
44478#[cfg_attr(
44479    target_arch = "arm",
44480    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44481)]
44482pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44483    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44484    unsafe {
44485        let ret_val: int16x4_t = transmute(a);
44486        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44487    }
44488}
44489#[doc = "Vector reinterpret cast operation"]
44490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44491#[inline]
44492#[cfg(target_endian = "little")]
44493#[target_feature(enable = "neon")]
44494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44496#[cfg_attr(
44497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44498    assert_instr(nop)
44499)]
44500#[cfg_attr(
44501    not(target_arch = "arm"),
44502    stable(feature = "neon_intrinsics", since = "1.59.0")
44503)]
44504#[cfg_attr(
44505    target_arch = "arm",
44506    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44507)]
44508pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44509    unsafe { transmute(a) }
44510}
44511#[doc = "Vector reinterpret cast operation"]
44512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44513#[inline]
44514#[cfg(target_endian = "big")]
44515#[target_feature(enable = "neon")]
44516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44518#[cfg_attr(
44519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44520    assert_instr(nop)
44521)]
44522#[cfg_attr(
44523    not(target_arch = "arm"),
44524    stable(feature = "neon_intrinsics", since = "1.59.0")
44525)]
44526#[cfg_attr(
44527    target_arch = "arm",
44528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44529)]
44530pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44531    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44532    unsafe {
44533        let ret_val: int32x2_t = transmute(a);
44534        simd_shuffle!(ret_val, ret_val, [1, 0])
44535    }
44536}
44537#[doc = "Vector reinterpret cast operation"]
44538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44539#[inline]
44540#[cfg(target_endian = "little")]
44541#[target_feature(enable = "neon")]
44542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44544#[cfg_attr(
44545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44546    assert_instr(nop)
44547)]
44548#[cfg_attr(
44549    not(target_arch = "arm"),
44550    stable(feature = "neon_intrinsics", since = "1.59.0")
44551)]
44552#[cfg_attr(
44553    target_arch = "arm",
44554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44555)]
44556pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44557    unsafe { transmute(a) }
44558}
44559#[doc = "Vector reinterpret cast operation"]
44560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44561#[inline]
44562#[cfg(target_endian = "big")]
44563#[target_feature(enable = "neon")]
44564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44566#[cfg_attr(
44567    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44568    assert_instr(nop)
44569)]
44570#[cfg_attr(
44571    not(target_arch = "arm"),
44572    stable(feature = "neon_intrinsics", since = "1.59.0")
44573)]
44574#[cfg_attr(
44575    target_arch = "arm",
44576    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44577)]
44578pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44579    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44580    unsafe { transmute(a) }
44581}
44582#[doc = "Vector reinterpret cast operation"]
44583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44584#[inline]
44585#[cfg(target_endian = "little")]
44586#[target_feature(enable = "neon")]
44587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44589#[cfg_attr(
44590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44591    assert_instr(nop)
44592)]
44593#[cfg_attr(
44594    not(target_arch = "arm"),
44595    stable(feature = "neon_intrinsics", since = "1.59.0")
44596)]
44597#[cfg_attr(
44598    target_arch = "arm",
44599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44600)]
44601pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44602    unsafe { transmute(a) }
44603}
44604#[doc = "Vector reinterpret cast operation"]
44605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44606#[inline]
44607#[cfg(target_endian = "big")]
44608#[target_feature(enable = "neon")]
44609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44611#[cfg_attr(
44612    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44613    assert_instr(nop)
44614)]
44615#[cfg_attr(
44616    not(target_arch = "arm"),
44617    stable(feature = "neon_intrinsics", since = "1.59.0")
44618)]
44619#[cfg_attr(
44620    target_arch = "arm",
44621    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44622)]
44623pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44624    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44625    unsafe {
44626        let ret_val: uint8x8_t = transmute(a);
44627        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44628    }
44629}
44630#[doc = "Vector reinterpret cast operation"]
44631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44632#[inline]
44633#[cfg(target_endian = "little")]
44634#[target_feature(enable = "neon")]
44635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44637#[cfg_attr(
44638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44639    assert_instr(nop)
44640)]
44641#[cfg_attr(
44642    not(target_arch = "arm"),
44643    stable(feature = "neon_intrinsics", since = "1.59.0")
44644)]
44645#[cfg_attr(
44646    target_arch = "arm",
44647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44648)]
44649pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44650    unsafe { transmute(a) }
44651}
44652#[doc = "Vector reinterpret cast operation"]
44653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44654#[inline]
44655#[cfg(target_endian = "big")]
44656#[target_feature(enable = "neon")]
44657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44659#[cfg_attr(
44660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44661    assert_instr(nop)
44662)]
44663#[cfg_attr(
44664    not(target_arch = "arm"),
44665    stable(feature = "neon_intrinsics", since = "1.59.0")
44666)]
44667#[cfg_attr(
44668    target_arch = "arm",
44669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44670)]
44671pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44672    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44673    unsafe {
44674        let ret_val: uint16x4_t = transmute(a);
44675        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44676    }
44677}
44678#[doc = "Vector reinterpret cast operation"]
44679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44680#[inline]
44681#[cfg(target_endian = "little")]
44682#[target_feature(enable = "neon")]
44683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44685#[cfg_attr(
44686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44687    assert_instr(nop)
44688)]
44689#[cfg_attr(
44690    not(target_arch = "arm"),
44691    stable(feature = "neon_intrinsics", since = "1.59.0")
44692)]
44693#[cfg_attr(
44694    target_arch = "arm",
44695    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44696)]
44697pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44698    unsafe { transmute(a) }
44699}
44700#[doc = "Vector reinterpret cast operation"]
44701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44702#[inline]
44703#[cfg(target_endian = "big")]
44704#[target_feature(enable = "neon")]
44705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44707#[cfg_attr(
44708    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44709    assert_instr(nop)
44710)]
44711#[cfg_attr(
44712    not(target_arch = "arm"),
44713    stable(feature = "neon_intrinsics", since = "1.59.0")
44714)]
44715#[cfg_attr(
44716    target_arch = "arm",
44717    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44718)]
44719pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44720    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44721    unsafe {
44722        let ret_val: uint32x2_t = transmute(a);
44723        simd_shuffle!(ret_val, ret_val, [1, 0])
44724    }
44725}
44726#[doc = "Vector reinterpret cast operation"]
44727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44728#[inline]
44729#[cfg(target_endian = "little")]
44730#[target_feature(enable = "neon")]
44731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44733#[cfg_attr(
44734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44735    assert_instr(nop)
44736)]
44737#[cfg_attr(
44738    not(target_arch = "arm"),
44739    stable(feature = "neon_intrinsics", since = "1.59.0")
44740)]
44741#[cfg_attr(
44742    target_arch = "arm",
44743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44744)]
44745pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44746    unsafe { transmute(a) }
44747}
44748#[doc = "Vector reinterpret cast operation"]
44749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44750#[inline]
44751#[cfg(target_endian = "big")]
44752#[target_feature(enable = "neon")]
44753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44755#[cfg_attr(
44756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44757    assert_instr(nop)
44758)]
44759#[cfg_attr(
44760    not(target_arch = "arm"),
44761    stable(feature = "neon_intrinsics", since = "1.59.0")
44762)]
44763#[cfg_attr(
44764    target_arch = "arm",
44765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44766)]
44767pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44768    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44769    unsafe { transmute(a) }
44770}
44771#[doc = "Vector reinterpret cast operation"]
44772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44773#[inline]
44774#[cfg(target_endian = "little")]
44775#[target_feature(enable = "neon")]
44776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44778#[cfg_attr(
44779    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44780    assert_instr(nop)
44781)]
44782#[cfg_attr(
44783    not(target_arch = "arm"),
44784    stable(feature = "neon_intrinsics", since = "1.59.0")
44785)]
44786#[cfg_attr(
44787    target_arch = "arm",
44788    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44789)]
44790pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44791    unsafe { transmute(a) }
44792}
44793#[doc = "Vector reinterpret cast operation"]
44794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44795#[inline]
44796#[cfg(target_endian = "big")]
44797#[target_feature(enable = "neon")]
44798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44800#[cfg_attr(
44801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44802    assert_instr(nop)
44803)]
44804#[cfg_attr(
44805    not(target_arch = "arm"),
44806    stable(feature = "neon_intrinsics", since = "1.59.0")
44807)]
44808#[cfg_attr(
44809    target_arch = "arm",
44810    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44811)]
44812pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44813    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44814    unsafe {
44815        let ret_val: poly8x8_t = transmute(a);
44816        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44817    }
44818}
44819#[doc = "Vector reinterpret cast operation"]
44820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44821#[inline]
44822#[cfg(target_endian = "little")]
44823#[target_feature(enable = "neon")]
44824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44826#[cfg_attr(
44827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44828    assert_instr(nop)
44829)]
44830#[cfg_attr(
44831    not(target_arch = "arm"),
44832    stable(feature = "neon_intrinsics", since = "1.59.0")
44833)]
44834#[cfg_attr(
44835    target_arch = "arm",
44836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44837)]
44838pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44839    unsafe { transmute(a) }
44840}
44841#[doc = "Vector reinterpret cast operation"]
44842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44843#[inline]
44844#[cfg(target_endian = "big")]
44845#[target_feature(enable = "neon")]
44846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44848#[cfg_attr(
44849    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44850    assert_instr(nop)
44851)]
44852#[cfg_attr(
44853    not(target_arch = "arm"),
44854    stable(feature = "neon_intrinsics", since = "1.59.0")
44855)]
44856#[cfg_attr(
44857    target_arch = "arm",
44858    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44859)]
44860pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44861    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44862    unsafe {
44863        let ret_val: poly16x4_t = transmute(a);
44864        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44865    }
44866}
44867#[doc = "Vector reinterpret cast operation"]
44868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44869#[inline]
44870#[cfg(target_endian = "little")]
44871#[target_feature(enable = "neon")]
44872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44874#[cfg_attr(
44875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44876    assert_instr(nop)
44877)]
44878#[cfg_attr(
44879    not(target_arch = "arm"),
44880    stable(feature = "neon_intrinsics", since = "1.59.0")
44881)]
44882#[cfg_attr(
44883    target_arch = "arm",
44884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44885)]
44886pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44887    unsafe { transmute(a) }
44888}
44889#[doc = "Vector reinterpret cast operation"]
44890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44891#[inline]
44892#[cfg(target_endian = "big")]
44893#[target_feature(enable = "neon")]
44894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44896#[cfg_attr(
44897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44898    assert_instr(nop)
44899)]
44900#[cfg_attr(
44901    not(target_arch = "arm"),
44902    stable(feature = "neon_intrinsics", since = "1.59.0")
44903)]
44904#[cfg_attr(
44905    target_arch = "arm",
44906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44907)]
44908pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44909    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44910    unsafe { transmute(a) }
44911}
44912#[doc = "Vector reinterpret cast operation"]
44913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44914#[inline]
44915#[cfg(target_endian = "little")]
44916#[target_feature(enable = "neon")]
44917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44919#[cfg_attr(
44920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44921    assert_instr(nop)
44922)]
44923#[cfg_attr(
44924    not(target_arch = "arm"),
44925    stable(feature = "neon_intrinsics", since = "1.59.0")
44926)]
44927#[cfg_attr(
44928    target_arch = "arm",
44929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44930)]
44931pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44932    unsafe { transmute(a) }
44933}
44934#[doc = "Vector reinterpret cast operation"]
44935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44936#[inline]
44937#[cfg(target_endian = "big")]
44938#[target_feature(enable = "neon")]
44939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44941#[cfg_attr(
44942    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44943    assert_instr(nop)
44944)]
44945#[cfg_attr(
44946    not(target_arch = "arm"),
44947    stable(feature = "neon_intrinsics", since = "1.59.0")
44948)]
44949#[cfg_attr(
44950    target_arch = "arm",
44951    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44952)]
44953pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44954    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44955    unsafe {
44956        let ret_val: int8x16_t = transmute(a);
44957        simd_shuffle!(
44958            ret_val,
44959            ret_val,
44960            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44961        )
44962    }
44963}
44964#[doc = "Vector reinterpret cast operation"]
44965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44966#[inline]
44967#[cfg(target_endian = "little")]
44968#[target_feature(enable = "neon")]
44969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44971#[cfg_attr(
44972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44973    assert_instr(nop)
44974)]
44975#[cfg_attr(
44976    not(target_arch = "arm"),
44977    stable(feature = "neon_intrinsics", since = "1.59.0")
44978)]
44979#[cfg_attr(
44980    target_arch = "arm",
44981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44982)]
44983pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44984    unsafe { transmute(a) }
44985}
44986#[doc = "Vector reinterpret cast operation"]
44987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44988#[inline]
44989#[cfg(target_endian = "big")]
44990#[target_feature(enable = "neon")]
44991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44993#[cfg_attr(
44994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44995    assert_instr(nop)
44996)]
44997#[cfg_attr(
44998    not(target_arch = "arm"),
44999    stable(feature = "neon_intrinsics", since = "1.59.0")
45000)]
45001#[cfg_attr(
45002    target_arch = "arm",
45003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45004)]
45005pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
45006    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45007    unsafe {
45008        let ret_val: int16x8_t = transmute(a);
45009        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45010    }
45011}
45012#[doc = "Vector reinterpret cast operation"]
45013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
45014#[inline]
45015#[cfg(target_endian = "little")]
45016#[target_feature(enable = "neon")]
45017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45019#[cfg_attr(
45020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45021    assert_instr(nop)
45022)]
45023#[cfg_attr(
45024    not(target_arch = "arm"),
45025    stable(feature = "neon_intrinsics", since = "1.59.0")
45026)]
45027#[cfg_attr(
45028    target_arch = "arm",
45029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45030)]
45031pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
45032    unsafe { transmute(a) }
45033}
45034#[doc = "Vector reinterpret cast operation"]
45035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
45036#[inline]
45037#[cfg(target_endian = "big")]
45038#[target_feature(enable = "neon")]
45039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45041#[cfg_attr(
45042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45043    assert_instr(nop)
45044)]
45045#[cfg_attr(
45046    not(target_arch = "arm"),
45047    stable(feature = "neon_intrinsics", since = "1.59.0")
45048)]
45049#[cfg_attr(
45050    target_arch = "arm",
45051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45052)]
45053pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
45054    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45055    unsafe {
45056        let ret_val: int32x4_t = transmute(a);
45057        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45058    }
45059}
45060#[doc = "Vector reinterpret cast operation"]
45061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
45062#[inline]
45063#[cfg(target_endian = "little")]
45064#[target_feature(enable = "neon")]
45065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45067#[cfg_attr(
45068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45069    assert_instr(nop)
45070)]
45071#[cfg_attr(
45072    not(target_arch = "arm"),
45073    stable(feature = "neon_intrinsics", since = "1.59.0")
45074)]
45075#[cfg_attr(
45076    target_arch = "arm",
45077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45078)]
45079pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
45080    unsafe { transmute(a) }
45081}
45082#[doc = "Vector reinterpret cast operation"]
45083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
45084#[inline]
45085#[cfg(target_endian = "big")]
45086#[target_feature(enable = "neon")]
45087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45089#[cfg_attr(
45090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45091    assert_instr(nop)
45092)]
45093#[cfg_attr(
45094    not(target_arch = "arm"),
45095    stable(feature = "neon_intrinsics", since = "1.59.0")
45096)]
45097#[cfg_attr(
45098    target_arch = "arm",
45099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45100)]
45101pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
45102    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45103    unsafe {
45104        let ret_val: int64x2_t = transmute(a);
45105        simd_shuffle!(ret_val, ret_val, [1, 0])
45106    }
45107}
45108#[doc = "Vector reinterpret cast operation"]
45109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45110#[inline]
45111#[cfg(target_endian = "little")]
45112#[target_feature(enable = "neon")]
45113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45115#[cfg_attr(
45116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45117    assert_instr(nop)
45118)]
45119#[cfg_attr(
45120    not(target_arch = "arm"),
45121    stable(feature = "neon_intrinsics", since = "1.59.0")
45122)]
45123#[cfg_attr(
45124    target_arch = "arm",
45125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45126)]
45127pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45128    unsafe { transmute(a) }
45129}
45130#[doc = "Vector reinterpret cast operation"]
45131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45132#[inline]
45133#[cfg(target_endian = "big")]
45134#[target_feature(enable = "neon")]
45135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45137#[cfg_attr(
45138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45139    assert_instr(nop)
45140)]
45141#[cfg_attr(
45142    not(target_arch = "arm"),
45143    stable(feature = "neon_intrinsics", since = "1.59.0")
45144)]
45145#[cfg_attr(
45146    target_arch = "arm",
45147    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45148)]
45149pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45150    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45151    unsafe {
45152        let ret_val: uint8x16_t = transmute(a);
45153        simd_shuffle!(
45154            ret_val,
45155            ret_val,
45156            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45157        )
45158    }
45159}
45160#[doc = "Vector reinterpret cast operation"]
45161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45162#[inline]
45163#[cfg(target_endian = "little")]
45164#[target_feature(enable = "neon")]
45165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45167#[cfg_attr(
45168    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45169    assert_instr(nop)
45170)]
45171#[cfg_attr(
45172    not(target_arch = "arm"),
45173    stable(feature = "neon_intrinsics", since = "1.59.0")
45174)]
45175#[cfg_attr(
45176    target_arch = "arm",
45177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45178)]
45179pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45180    unsafe { transmute(a) }
45181}
45182#[doc = "Vector reinterpret cast operation"]
45183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45184#[inline]
45185#[cfg(target_endian = "big")]
45186#[target_feature(enable = "neon")]
45187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45189#[cfg_attr(
45190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45191    assert_instr(nop)
45192)]
45193#[cfg_attr(
45194    not(target_arch = "arm"),
45195    stable(feature = "neon_intrinsics", since = "1.59.0")
45196)]
45197#[cfg_attr(
45198    target_arch = "arm",
45199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45200)]
45201pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45202    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45203    unsafe {
45204        let ret_val: uint16x8_t = transmute(a);
45205        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45206    }
45207}
45208#[doc = "Vector reinterpret cast operation"]
45209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45210#[inline]
45211#[cfg(target_endian = "little")]
45212#[target_feature(enable = "neon")]
45213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45215#[cfg_attr(
45216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45217    assert_instr(nop)
45218)]
45219#[cfg_attr(
45220    not(target_arch = "arm"),
45221    stable(feature = "neon_intrinsics", since = "1.59.0")
45222)]
45223#[cfg_attr(
45224    target_arch = "arm",
45225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45226)]
45227pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45228    unsafe { transmute(a) }
45229}
45230#[doc = "Vector reinterpret cast operation"]
45231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45232#[inline]
45233#[cfg(target_endian = "big")]
45234#[target_feature(enable = "neon")]
45235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45237#[cfg_attr(
45238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45239    assert_instr(nop)
45240)]
45241#[cfg_attr(
45242    not(target_arch = "arm"),
45243    stable(feature = "neon_intrinsics", since = "1.59.0")
45244)]
45245#[cfg_attr(
45246    target_arch = "arm",
45247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45248)]
45249pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45250    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45251    unsafe {
45252        let ret_val: uint32x4_t = transmute(a);
45253        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45254    }
45255}
45256#[doc = "Vector reinterpret cast operation"]
45257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45258#[inline]
45259#[cfg(target_endian = "little")]
45260#[target_feature(enable = "neon")]
45261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45263#[cfg_attr(
45264    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45265    assert_instr(nop)
45266)]
45267#[cfg_attr(
45268    not(target_arch = "arm"),
45269    stable(feature = "neon_intrinsics", since = "1.59.0")
45270)]
45271#[cfg_attr(
45272    target_arch = "arm",
45273    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45274)]
45275pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45276    unsafe { transmute(a) }
45277}
45278#[doc = "Vector reinterpret cast operation"]
45279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45280#[inline]
45281#[cfg(target_endian = "big")]
45282#[target_feature(enable = "neon")]
45283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45285#[cfg_attr(
45286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45287    assert_instr(nop)
45288)]
45289#[cfg_attr(
45290    not(target_arch = "arm"),
45291    stable(feature = "neon_intrinsics", since = "1.59.0")
45292)]
45293#[cfg_attr(
45294    target_arch = "arm",
45295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45296)]
45297pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45298    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45299    unsafe {
45300        let ret_val: uint64x2_t = transmute(a);
45301        simd_shuffle!(ret_val, ret_val, [1, 0])
45302    }
45303}
45304#[doc = "Vector reinterpret cast operation"]
45305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45306#[inline]
45307#[cfg(target_endian = "little")]
45308#[target_feature(enable = "neon")]
45309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45311#[cfg_attr(
45312    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45313    assert_instr(nop)
45314)]
45315#[cfg_attr(
45316    not(target_arch = "arm"),
45317    stable(feature = "neon_intrinsics", since = "1.59.0")
45318)]
45319#[cfg_attr(
45320    target_arch = "arm",
45321    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45322)]
45323pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45324    unsafe { transmute(a) }
45325}
45326#[doc = "Vector reinterpret cast operation"]
45327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45328#[inline]
45329#[cfg(target_endian = "big")]
45330#[target_feature(enable = "neon")]
45331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45333#[cfg_attr(
45334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45335    assert_instr(nop)
45336)]
45337#[cfg_attr(
45338    not(target_arch = "arm"),
45339    stable(feature = "neon_intrinsics", since = "1.59.0")
45340)]
45341#[cfg_attr(
45342    target_arch = "arm",
45343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45344)]
45345pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45346    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45347    unsafe {
45348        let ret_val: poly8x16_t = transmute(a);
45349        simd_shuffle!(
45350            ret_val,
45351            ret_val,
45352            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45353        )
45354    }
45355}
45356#[doc = "Vector reinterpret cast operation"]
45357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45358#[inline]
45359#[cfg(target_endian = "little")]
45360#[target_feature(enable = "neon")]
45361#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45363#[cfg_attr(
45364    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45365    assert_instr(nop)
45366)]
45367#[cfg_attr(
45368    not(target_arch = "arm"),
45369    stable(feature = "neon_intrinsics", since = "1.59.0")
45370)]
45371#[cfg_attr(
45372    target_arch = "arm",
45373    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45374)]
45375pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45376    unsafe { transmute(a) }
45377}
45378#[doc = "Vector reinterpret cast operation"]
45379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45380#[inline]
45381#[cfg(target_endian = "big")]
45382#[target_feature(enable = "neon")]
45383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45385#[cfg_attr(
45386    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45387    assert_instr(nop)
45388)]
45389#[cfg_attr(
45390    not(target_arch = "arm"),
45391    stable(feature = "neon_intrinsics", since = "1.59.0")
45392)]
45393#[cfg_attr(
45394    target_arch = "arm",
45395    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45396)]
45397pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45398    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45399    unsafe {
45400        let ret_val: poly16x8_t = transmute(a);
45401        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45402    }
45403}
45404#[doc = "Vector reinterpret cast operation"]
45405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45406#[inline]
45407#[cfg(target_endian = "little")]
45408#[target_feature(enable = "neon")]
45409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45411#[cfg_attr(
45412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45413    assert_instr(nop)
45414)]
45415#[cfg_attr(
45416    not(target_arch = "arm"),
45417    stable(feature = "neon_intrinsics", since = "1.59.0")
45418)]
45419#[cfg_attr(
45420    target_arch = "arm",
45421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45422)]
45423pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45424    unsafe { transmute(a) }
45425}
45426#[doc = "Vector reinterpret cast operation"]
45427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45428#[inline]
45429#[cfg(target_endian = "big")]
45430#[target_feature(enable = "neon")]
45431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45433#[cfg_attr(
45434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45435    assert_instr(nop)
45436)]
45437#[cfg_attr(
45438    not(target_arch = "arm"),
45439    stable(feature = "neon_intrinsics", since = "1.59.0")
45440)]
45441#[cfg_attr(
45442    target_arch = "arm",
45443    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45444)]
45445pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45446    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45447    unsafe {
45448        let ret_val: float32x2_t = transmute(a);
45449        simd_shuffle!(ret_val, ret_val, [1, 0])
45450    }
45451}
45452#[doc = "Vector reinterpret cast operation"]
45453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45454#[inline]
45455#[cfg(target_endian = "little")]
45456#[target_feature(enable = "neon")]
45457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45459#[cfg_attr(
45460    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45461    assert_instr(nop)
45462)]
45463#[cfg_attr(
45464    not(target_arch = "arm"),
45465    stable(feature = "neon_intrinsics", since = "1.59.0")
45466)]
45467#[cfg_attr(
45468    target_arch = "arm",
45469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45470)]
45471pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45472    unsafe { transmute(a) }
45473}
45474#[doc = "Vector reinterpret cast operation"]
45475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45476#[inline]
45477#[cfg(target_endian = "big")]
45478#[target_feature(enable = "neon")]
45479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45481#[cfg_attr(
45482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45483    assert_instr(nop)
45484)]
45485#[cfg_attr(
45486    not(target_arch = "arm"),
45487    stable(feature = "neon_intrinsics", since = "1.59.0")
45488)]
45489#[cfg_attr(
45490    target_arch = "arm",
45491    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45492)]
45493pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45494    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45495    unsafe {
45496        let ret_val: int16x4_t = transmute(a);
45497        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45498    }
45499}
45500#[doc = "Vector reinterpret cast operation"]
45501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45502#[inline]
45503#[cfg(target_endian = "little")]
45504#[target_feature(enable = "neon")]
45505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45507#[cfg_attr(
45508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45509    assert_instr(nop)
45510)]
45511#[cfg_attr(
45512    not(target_arch = "arm"),
45513    stable(feature = "neon_intrinsics", since = "1.59.0")
45514)]
45515#[cfg_attr(
45516    target_arch = "arm",
45517    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45518)]
45519pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45520    unsafe { transmute(a) }
45521}
45522#[doc = "Vector reinterpret cast operation"]
45523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45524#[inline]
45525#[cfg(target_endian = "big")]
45526#[target_feature(enable = "neon")]
45527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45529#[cfg_attr(
45530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45531    assert_instr(nop)
45532)]
45533#[cfg_attr(
45534    not(target_arch = "arm"),
45535    stable(feature = "neon_intrinsics", since = "1.59.0")
45536)]
45537#[cfg_attr(
45538    target_arch = "arm",
45539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45540)]
45541pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45542    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45543    unsafe {
45544        let ret_val: int32x2_t = transmute(a);
45545        simd_shuffle!(ret_val, ret_val, [1, 0])
45546    }
45547}
45548#[doc = "Vector reinterpret cast operation"]
45549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45550#[inline]
45551#[cfg(target_endian = "little")]
45552#[target_feature(enable = "neon")]
45553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45555#[cfg_attr(
45556    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45557    assert_instr(nop)
45558)]
45559#[cfg_attr(
45560    not(target_arch = "arm"),
45561    stable(feature = "neon_intrinsics", since = "1.59.0")
45562)]
45563#[cfg_attr(
45564    target_arch = "arm",
45565    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45566)]
45567pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45568    unsafe { transmute(a) }
45569}
45570#[doc = "Vector reinterpret cast operation"]
45571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45572#[inline]
45573#[cfg(target_endian = "big")]
45574#[target_feature(enable = "neon")]
45575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45577#[cfg_attr(
45578    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45579    assert_instr(nop)
45580)]
45581#[cfg_attr(
45582    not(target_arch = "arm"),
45583    stable(feature = "neon_intrinsics", since = "1.59.0")
45584)]
45585#[cfg_attr(
45586    target_arch = "arm",
45587    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45588)]
45589pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45590    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45591    unsafe { transmute(a) }
45592}
45593#[doc = "Vector reinterpret cast operation"]
45594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45595#[inline]
45596#[cfg(target_endian = "little")]
45597#[target_feature(enable = "neon")]
45598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45600#[cfg_attr(
45601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45602    assert_instr(nop)
45603)]
45604#[cfg_attr(
45605    not(target_arch = "arm"),
45606    stable(feature = "neon_intrinsics", since = "1.59.0")
45607)]
45608#[cfg_attr(
45609    target_arch = "arm",
45610    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45611)]
45612pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45613    unsafe { transmute(a) }
45614}
45615#[doc = "Vector reinterpret cast operation"]
45616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45617#[inline]
45618#[cfg(target_endian = "big")]
45619#[target_feature(enable = "neon")]
45620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45622#[cfg_attr(
45623    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45624    assert_instr(nop)
45625)]
45626#[cfg_attr(
45627    not(target_arch = "arm"),
45628    stable(feature = "neon_intrinsics", since = "1.59.0")
45629)]
45630#[cfg_attr(
45631    target_arch = "arm",
45632    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45633)]
45634pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45635    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45636    unsafe {
45637        let ret_val: uint8x8_t = transmute(a);
45638        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45639    }
45640}
45641#[doc = "Vector reinterpret cast operation"]
45642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45643#[inline]
45644#[cfg(target_endian = "little")]
45645#[target_feature(enable = "neon")]
45646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45648#[cfg_attr(
45649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45650    assert_instr(nop)
45651)]
45652#[cfg_attr(
45653    not(target_arch = "arm"),
45654    stable(feature = "neon_intrinsics", since = "1.59.0")
45655)]
45656#[cfg_attr(
45657    target_arch = "arm",
45658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45659)]
45660pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45661    unsafe { transmute(a) }
45662}
45663#[doc = "Vector reinterpret cast operation"]
45664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45665#[inline]
45666#[cfg(target_endian = "big")]
45667#[target_feature(enable = "neon")]
45668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45670#[cfg_attr(
45671    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45672    assert_instr(nop)
45673)]
45674#[cfg_attr(
45675    not(target_arch = "arm"),
45676    stable(feature = "neon_intrinsics", since = "1.59.0")
45677)]
45678#[cfg_attr(
45679    target_arch = "arm",
45680    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45681)]
45682pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45683    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45684    unsafe {
45685        let ret_val: uint16x4_t = transmute(a);
45686        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45687    }
45688}
45689#[doc = "Vector reinterpret cast operation"]
45690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45691#[inline]
45692#[cfg(target_endian = "little")]
45693#[target_feature(enable = "neon")]
45694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45696#[cfg_attr(
45697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45698    assert_instr(nop)
45699)]
45700#[cfg_attr(
45701    not(target_arch = "arm"),
45702    stable(feature = "neon_intrinsics", since = "1.59.0")
45703)]
45704#[cfg_attr(
45705    target_arch = "arm",
45706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45707)]
45708pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45709    unsafe { transmute(a) }
45710}
45711#[doc = "Vector reinterpret cast operation"]
45712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45713#[inline]
45714#[cfg(target_endian = "big")]
45715#[target_feature(enable = "neon")]
45716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45718#[cfg_attr(
45719    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45720    assert_instr(nop)
45721)]
45722#[cfg_attr(
45723    not(target_arch = "arm"),
45724    stable(feature = "neon_intrinsics", since = "1.59.0")
45725)]
45726#[cfg_attr(
45727    target_arch = "arm",
45728    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45729)]
45730pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45731    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45732    unsafe {
45733        let ret_val: uint32x2_t = transmute(a);
45734        simd_shuffle!(ret_val, ret_val, [1, 0])
45735    }
45736}
45737#[doc = "Vector reinterpret cast operation"]
45738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45739#[inline]
45740#[cfg(target_endian = "little")]
45741#[target_feature(enable = "neon")]
45742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45744#[cfg_attr(
45745    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45746    assert_instr(nop)
45747)]
45748#[cfg_attr(
45749    not(target_arch = "arm"),
45750    stable(feature = "neon_intrinsics", since = "1.59.0")
45751)]
45752#[cfg_attr(
45753    target_arch = "arm",
45754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45755)]
45756pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45757    unsafe { transmute(a) }
45758}
45759#[doc = "Vector reinterpret cast operation"]
45760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45761#[inline]
45762#[cfg(target_endian = "big")]
45763#[target_feature(enable = "neon")]
45764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45766#[cfg_attr(
45767    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45768    assert_instr(nop)
45769)]
45770#[cfg_attr(
45771    not(target_arch = "arm"),
45772    stable(feature = "neon_intrinsics", since = "1.59.0")
45773)]
45774#[cfg_attr(
45775    target_arch = "arm",
45776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45777)]
45778pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45779    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45780    unsafe { transmute(a) }
45781}
45782#[doc = "Vector reinterpret cast operation"]
45783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45784#[inline]
45785#[cfg(target_endian = "little")]
45786#[target_feature(enable = "neon")]
45787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45789#[cfg_attr(
45790    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45791    assert_instr(nop)
45792)]
45793#[cfg_attr(
45794    not(target_arch = "arm"),
45795    stable(feature = "neon_intrinsics", since = "1.59.0")
45796)]
45797#[cfg_attr(
45798    target_arch = "arm",
45799    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45800)]
45801pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45802    unsafe { transmute(a) }
45803}
45804#[doc = "Vector reinterpret cast operation"]
45805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45806#[inline]
45807#[cfg(target_endian = "big")]
45808#[target_feature(enable = "neon")]
45809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45811#[cfg_attr(
45812    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45813    assert_instr(nop)
45814)]
45815#[cfg_attr(
45816    not(target_arch = "arm"),
45817    stable(feature = "neon_intrinsics", since = "1.59.0")
45818)]
45819#[cfg_attr(
45820    target_arch = "arm",
45821    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45822)]
45823pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45824    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45825    unsafe {
45826        let ret_val: poly8x8_t = transmute(a);
45827        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45828    }
45829}
45830#[doc = "Vector reinterpret cast operation"]
45831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45832#[inline]
45833#[cfg(target_endian = "little")]
45834#[target_feature(enable = "neon")]
45835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45837#[cfg_attr(
45838    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45839    assert_instr(nop)
45840)]
45841#[cfg_attr(
45842    not(target_arch = "arm"),
45843    stable(feature = "neon_intrinsics", since = "1.59.0")
45844)]
45845#[cfg_attr(
45846    target_arch = "arm",
45847    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45848)]
45849pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45850    unsafe { transmute(a) }
45851}
45852#[doc = "Vector reinterpret cast operation"]
45853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45854#[inline]
45855#[cfg(target_endian = "big")]
45856#[target_feature(enable = "neon")]
45857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45859#[cfg_attr(
45860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45861    assert_instr(nop)
45862)]
45863#[cfg_attr(
45864    not(target_arch = "arm"),
45865    stable(feature = "neon_intrinsics", since = "1.59.0")
45866)]
45867#[cfg_attr(
45868    target_arch = "arm",
45869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45870)]
45871pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45872    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45873    unsafe {
45874        let ret_val: poly16x4_t = transmute(a);
45875        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45876    }
45877}
45878#[doc = "Vector reinterpret cast operation"]
45879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45880#[inline]
45881#[cfg(target_endian = "little")]
45882#[target_feature(enable = "neon")]
45883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45885#[cfg_attr(
45886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45887    assert_instr(nop)
45888)]
45889#[cfg_attr(
45890    not(target_arch = "arm"),
45891    stable(feature = "neon_intrinsics", since = "1.59.0")
45892)]
45893#[cfg_attr(
45894    target_arch = "arm",
45895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45896)]
45897pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45898    unsafe { transmute(a) }
45899}
45900#[doc = "Vector reinterpret cast operation"]
45901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45902#[inline]
45903#[cfg(target_endian = "big")]
45904#[target_feature(enable = "neon")]
45905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45907#[cfg_attr(
45908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45909    assert_instr(nop)
45910)]
45911#[cfg_attr(
45912    not(target_arch = "arm"),
45913    stable(feature = "neon_intrinsics", since = "1.59.0")
45914)]
45915#[cfg_attr(
45916    target_arch = "arm",
45917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45918)]
45919pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45920    let a: int8x16_t =
45921        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45922    unsafe {
45923        let ret_val: float32x4_t = transmute(a);
45924        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45925    }
45926}
45927#[doc = "Vector reinterpret cast operation"]
45928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45929#[inline]
45930#[cfg(target_endian = "little")]
45931#[target_feature(enable = "neon")]
45932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45934#[cfg_attr(
45935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45936    assert_instr(nop)
45937)]
45938#[cfg_attr(
45939    not(target_arch = "arm"),
45940    stable(feature = "neon_intrinsics", since = "1.59.0")
45941)]
45942#[cfg_attr(
45943    target_arch = "arm",
45944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45945)]
45946pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45947    unsafe { transmute(a) }
45948}
45949#[doc = "Vector reinterpret cast operation"]
45950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45951#[inline]
45952#[cfg(target_endian = "big")]
45953#[target_feature(enable = "neon")]
45954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45956#[cfg_attr(
45957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45958    assert_instr(nop)
45959)]
45960#[cfg_attr(
45961    not(target_arch = "arm"),
45962    stable(feature = "neon_intrinsics", since = "1.59.0")
45963)]
45964#[cfg_attr(
45965    target_arch = "arm",
45966    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45967)]
45968pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45969    let a: int8x16_t =
45970        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45971    unsafe {
45972        let ret_val: int16x8_t = transmute(a);
45973        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45974    }
45975}
45976#[doc = "Vector reinterpret cast operation"]
45977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45978#[inline]
45979#[cfg(target_endian = "little")]
45980#[target_feature(enable = "neon")]
45981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45983#[cfg_attr(
45984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45985    assert_instr(nop)
45986)]
45987#[cfg_attr(
45988    not(target_arch = "arm"),
45989    stable(feature = "neon_intrinsics", since = "1.59.0")
45990)]
45991#[cfg_attr(
45992    target_arch = "arm",
45993    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45994)]
45995pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45996    unsafe { transmute(a) }
45997}
45998#[doc = "Vector reinterpret cast operation"]
45999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
46000#[inline]
46001#[cfg(target_endian = "big")]
46002#[target_feature(enable = "neon")]
46003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46005#[cfg_attr(
46006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46007    assert_instr(nop)
46008)]
46009#[cfg_attr(
46010    not(target_arch = "arm"),
46011    stable(feature = "neon_intrinsics", since = "1.59.0")
46012)]
46013#[cfg_attr(
46014    target_arch = "arm",
46015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46016)]
46017pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
46018    let a: int8x16_t =
46019        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46020    unsafe {
46021        let ret_val: int32x4_t = transmute(a);
46022        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46023    }
46024}
46025#[doc = "Vector reinterpret cast operation"]
46026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
46027#[inline]
46028#[cfg(target_endian = "little")]
46029#[target_feature(enable = "neon")]
46030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46031#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46032#[cfg_attr(
46033    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46034    assert_instr(nop)
46035)]
46036#[cfg_attr(
46037    not(target_arch = "arm"),
46038    stable(feature = "neon_intrinsics", since = "1.59.0")
46039)]
46040#[cfg_attr(
46041    target_arch = "arm",
46042    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46043)]
46044pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
46045    unsafe { transmute(a) }
46046}
46047#[doc = "Vector reinterpret cast operation"]
46048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
46049#[inline]
46050#[cfg(target_endian = "big")]
46051#[target_feature(enable = "neon")]
46052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46054#[cfg_attr(
46055    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46056    assert_instr(nop)
46057)]
46058#[cfg_attr(
46059    not(target_arch = "arm"),
46060    stable(feature = "neon_intrinsics", since = "1.59.0")
46061)]
46062#[cfg_attr(
46063    target_arch = "arm",
46064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46065)]
46066pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
46067    let a: int8x16_t =
46068        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46069    unsafe {
46070        let ret_val: int64x2_t = transmute(a);
46071        simd_shuffle!(ret_val, ret_val, [1, 0])
46072    }
46073}
46074#[doc = "Vector reinterpret cast operation"]
46075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
46076#[inline]
46077#[cfg(target_endian = "little")]
46078#[target_feature(enable = "neon")]
46079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46081#[cfg_attr(
46082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46083    assert_instr(nop)
46084)]
46085#[cfg_attr(
46086    not(target_arch = "arm"),
46087    stable(feature = "neon_intrinsics", since = "1.59.0")
46088)]
46089#[cfg_attr(
46090    target_arch = "arm",
46091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46092)]
46093pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46094    unsafe { transmute(a) }
46095}
46096#[doc = "Vector reinterpret cast operation"]
46097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
46098#[inline]
46099#[cfg(target_endian = "big")]
46100#[target_feature(enable = "neon")]
46101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46103#[cfg_attr(
46104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46105    assert_instr(nop)
46106)]
46107#[cfg_attr(
46108    not(target_arch = "arm"),
46109    stable(feature = "neon_intrinsics", since = "1.59.0")
46110)]
46111#[cfg_attr(
46112    target_arch = "arm",
46113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46114)]
46115pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46116    let a: int8x16_t =
46117        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46118    unsafe {
46119        let ret_val: uint8x16_t = transmute(a);
46120        simd_shuffle!(
46121            ret_val,
46122            ret_val,
46123            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46124        )
46125    }
46126}
46127#[doc = "Vector reinterpret cast operation"]
46128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46129#[inline]
46130#[cfg(target_endian = "little")]
46131#[target_feature(enable = "neon")]
46132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46134#[cfg_attr(
46135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46136    assert_instr(nop)
46137)]
46138#[cfg_attr(
46139    not(target_arch = "arm"),
46140    stable(feature = "neon_intrinsics", since = "1.59.0")
46141)]
46142#[cfg_attr(
46143    target_arch = "arm",
46144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46145)]
46146pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46147    unsafe { transmute(a) }
46148}
46149#[doc = "Vector reinterpret cast operation"]
46150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46151#[inline]
46152#[cfg(target_endian = "big")]
46153#[target_feature(enable = "neon")]
46154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46156#[cfg_attr(
46157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46158    assert_instr(nop)
46159)]
46160#[cfg_attr(
46161    not(target_arch = "arm"),
46162    stable(feature = "neon_intrinsics", since = "1.59.0")
46163)]
46164#[cfg_attr(
46165    target_arch = "arm",
46166    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46167)]
46168pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46169    let a: int8x16_t =
46170        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46171    unsafe {
46172        let ret_val: uint16x8_t = transmute(a);
46173        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46174    }
46175}
46176#[doc = "Vector reinterpret cast operation"]
46177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46178#[inline]
46179#[cfg(target_endian = "little")]
46180#[target_feature(enable = "neon")]
46181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46183#[cfg_attr(
46184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46185    assert_instr(nop)
46186)]
46187#[cfg_attr(
46188    not(target_arch = "arm"),
46189    stable(feature = "neon_intrinsics", since = "1.59.0")
46190)]
46191#[cfg_attr(
46192    target_arch = "arm",
46193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46194)]
46195pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46196    unsafe { transmute(a) }
46197}
46198#[doc = "Vector reinterpret cast operation"]
46199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46200#[inline]
46201#[cfg(target_endian = "big")]
46202#[target_feature(enable = "neon")]
46203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46205#[cfg_attr(
46206    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46207    assert_instr(nop)
46208)]
46209#[cfg_attr(
46210    not(target_arch = "arm"),
46211    stable(feature = "neon_intrinsics", since = "1.59.0")
46212)]
46213#[cfg_attr(
46214    target_arch = "arm",
46215    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46216)]
46217pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46218    let a: int8x16_t =
46219        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46220    unsafe {
46221        let ret_val: uint32x4_t = transmute(a);
46222        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46223    }
46224}
46225#[doc = "Vector reinterpret cast operation"]
46226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46227#[inline]
46228#[cfg(target_endian = "little")]
46229#[target_feature(enable = "neon")]
46230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46232#[cfg_attr(
46233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46234    assert_instr(nop)
46235)]
46236#[cfg_attr(
46237    not(target_arch = "arm"),
46238    stable(feature = "neon_intrinsics", since = "1.59.0")
46239)]
46240#[cfg_attr(
46241    target_arch = "arm",
46242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46243)]
46244pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46245    unsafe { transmute(a) }
46246}
46247#[doc = "Vector reinterpret cast operation"]
46248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46249#[inline]
46250#[cfg(target_endian = "big")]
46251#[target_feature(enable = "neon")]
46252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46254#[cfg_attr(
46255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46256    assert_instr(nop)
46257)]
46258#[cfg_attr(
46259    not(target_arch = "arm"),
46260    stable(feature = "neon_intrinsics", since = "1.59.0")
46261)]
46262#[cfg_attr(
46263    target_arch = "arm",
46264    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46265)]
46266pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46267    let a: int8x16_t =
46268        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46269    unsafe {
46270        let ret_val: uint64x2_t = transmute(a);
46271        simd_shuffle!(ret_val, ret_val, [1, 0])
46272    }
46273}
46274#[doc = "Vector reinterpret cast operation"]
46275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46276#[inline]
46277#[cfg(target_endian = "little")]
46278#[target_feature(enable = "neon")]
46279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46281#[cfg_attr(
46282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46283    assert_instr(nop)
46284)]
46285#[cfg_attr(
46286    not(target_arch = "arm"),
46287    stable(feature = "neon_intrinsics", since = "1.59.0")
46288)]
46289#[cfg_attr(
46290    target_arch = "arm",
46291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46292)]
46293pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46294    unsafe { transmute(a) }
46295}
46296#[doc = "Vector reinterpret cast operation"]
46297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46298#[inline]
46299#[cfg(target_endian = "big")]
46300#[target_feature(enable = "neon")]
46301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46303#[cfg_attr(
46304    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46305    assert_instr(nop)
46306)]
46307#[cfg_attr(
46308    not(target_arch = "arm"),
46309    stable(feature = "neon_intrinsics", since = "1.59.0")
46310)]
46311#[cfg_attr(
46312    target_arch = "arm",
46313    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46314)]
46315pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46316    let a: int8x16_t =
46317        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46318    unsafe {
46319        let ret_val: poly8x16_t = transmute(a);
46320        simd_shuffle!(
46321            ret_val,
46322            ret_val,
46323            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46324        )
46325    }
46326}
46327#[doc = "Vector reinterpret cast operation"]
46328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46329#[inline]
46330#[cfg(target_endian = "little")]
46331#[target_feature(enable = "neon")]
46332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46334#[cfg_attr(
46335    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46336    assert_instr(nop)
46337)]
46338#[cfg_attr(
46339    not(target_arch = "arm"),
46340    stable(feature = "neon_intrinsics", since = "1.59.0")
46341)]
46342#[cfg_attr(
46343    target_arch = "arm",
46344    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46345)]
46346pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46347    unsafe { transmute(a) }
46348}
46349#[doc = "Vector reinterpret cast operation"]
46350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46351#[inline]
46352#[cfg(target_endian = "big")]
46353#[target_feature(enable = "neon")]
46354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46356#[cfg_attr(
46357    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46358    assert_instr(nop)
46359)]
46360#[cfg_attr(
46361    not(target_arch = "arm"),
46362    stable(feature = "neon_intrinsics", since = "1.59.0")
46363)]
46364#[cfg_attr(
46365    target_arch = "arm",
46366    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46367)]
46368pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46369    let a: int8x16_t =
46370        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46371    unsafe {
46372        let ret_val: poly16x8_t = transmute(a);
46373        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46374    }
46375}
46376#[doc = "Vector reinterpret cast operation"]
46377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46378#[inline]
46379#[cfg(target_endian = "little")]
46380#[target_feature(enable = "neon")]
46381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46383#[cfg_attr(
46384    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46385    assert_instr(nop)
46386)]
46387#[cfg_attr(
46388    not(target_arch = "arm"),
46389    stable(feature = "neon_intrinsics", since = "1.59.0")
46390)]
46391#[cfg_attr(
46392    target_arch = "arm",
46393    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46394)]
46395pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46396    unsafe { transmute(a) }
46397}
46398#[doc = "Vector reinterpret cast operation"]
46399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46400#[inline]
46401#[cfg(target_endian = "big")]
46402#[target_feature(enable = "neon")]
46403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46405#[cfg_attr(
46406    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46407    assert_instr(nop)
46408)]
46409#[cfg_attr(
46410    not(target_arch = "arm"),
46411    stable(feature = "neon_intrinsics", since = "1.59.0")
46412)]
46413#[cfg_attr(
46414    target_arch = "arm",
46415    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46416)]
46417pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46418    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46419    unsafe {
46420        let ret_val: float32x2_t = transmute(a);
46421        simd_shuffle!(ret_val, ret_val, [1, 0])
46422    }
46423}
46424#[doc = "Vector reinterpret cast operation"]
46425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46426#[inline]
46427#[cfg(target_endian = "little")]
46428#[target_feature(enable = "neon")]
46429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46431#[cfg_attr(
46432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46433    assert_instr(nop)
46434)]
46435#[cfg_attr(
46436    not(target_arch = "arm"),
46437    stable(feature = "neon_intrinsics", since = "1.59.0")
46438)]
46439#[cfg_attr(
46440    target_arch = "arm",
46441    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46442)]
46443pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46444    unsafe { transmute(a) }
46445}
46446#[doc = "Vector reinterpret cast operation"]
46447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46448#[inline]
46449#[cfg(target_endian = "big")]
46450#[target_feature(enable = "neon")]
46451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46453#[cfg_attr(
46454    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46455    assert_instr(nop)
46456)]
46457#[cfg_attr(
46458    not(target_arch = "arm"),
46459    stable(feature = "neon_intrinsics", since = "1.59.0")
46460)]
46461#[cfg_attr(
46462    target_arch = "arm",
46463    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46464)]
46465pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46466    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46467    unsafe {
46468        let ret_val: int8x8_t = transmute(a);
46469        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46470    }
46471}
46472#[doc = "Vector reinterpret cast operation"]
46473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46474#[inline]
46475#[cfg(target_endian = "little")]
46476#[target_feature(enable = "neon")]
46477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46479#[cfg_attr(
46480    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46481    assert_instr(nop)
46482)]
46483#[cfg_attr(
46484    not(target_arch = "arm"),
46485    stable(feature = "neon_intrinsics", since = "1.59.0")
46486)]
46487#[cfg_attr(
46488    target_arch = "arm",
46489    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46490)]
46491pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46492    unsafe { transmute(a) }
46493}
46494#[doc = "Vector reinterpret cast operation"]
46495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46496#[inline]
46497#[cfg(target_endian = "big")]
46498#[target_feature(enable = "neon")]
46499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46501#[cfg_attr(
46502    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46503    assert_instr(nop)
46504)]
46505#[cfg_attr(
46506    not(target_arch = "arm"),
46507    stable(feature = "neon_intrinsics", since = "1.59.0")
46508)]
46509#[cfg_attr(
46510    target_arch = "arm",
46511    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46512)]
46513pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46514    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46515    unsafe {
46516        let ret_val: int32x2_t = transmute(a);
46517        simd_shuffle!(ret_val, ret_val, [1, 0])
46518    }
46519}
46520#[doc = "Vector reinterpret cast operation"]
46521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46522#[inline]
46523#[cfg(target_endian = "little")]
46524#[target_feature(enable = "neon")]
46525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46527#[cfg_attr(
46528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46529    assert_instr(nop)
46530)]
46531#[cfg_attr(
46532    not(target_arch = "arm"),
46533    stable(feature = "neon_intrinsics", since = "1.59.0")
46534)]
46535#[cfg_attr(
46536    target_arch = "arm",
46537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46538)]
46539pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46540    unsafe { transmute(a) }
46541}
46542#[doc = "Vector reinterpret cast operation"]
46543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46544#[inline]
46545#[cfg(target_endian = "big")]
46546#[target_feature(enable = "neon")]
46547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46549#[cfg_attr(
46550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46551    assert_instr(nop)
46552)]
46553#[cfg_attr(
46554    not(target_arch = "arm"),
46555    stable(feature = "neon_intrinsics", since = "1.59.0")
46556)]
46557#[cfg_attr(
46558    target_arch = "arm",
46559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46560)]
46561pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46562    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46563    unsafe { transmute(a) }
46564}
46565#[doc = "Vector reinterpret cast operation"]
46566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46567#[inline]
46568#[cfg(target_endian = "little")]
46569#[target_feature(enable = "neon")]
46570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46572#[cfg_attr(
46573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46574    assert_instr(nop)
46575)]
46576#[cfg_attr(
46577    not(target_arch = "arm"),
46578    stable(feature = "neon_intrinsics", since = "1.59.0")
46579)]
46580#[cfg_attr(
46581    target_arch = "arm",
46582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46583)]
46584pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46585    unsafe { transmute(a) }
46586}
46587#[doc = "Vector reinterpret cast operation"]
46588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46589#[inline]
46590#[cfg(target_endian = "big")]
46591#[target_feature(enable = "neon")]
46592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46594#[cfg_attr(
46595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46596    assert_instr(nop)
46597)]
46598#[cfg_attr(
46599    not(target_arch = "arm"),
46600    stable(feature = "neon_intrinsics", since = "1.59.0")
46601)]
46602#[cfg_attr(
46603    target_arch = "arm",
46604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46605)]
46606pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46607    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46608    unsafe {
46609        let ret_val: uint8x8_t = transmute(a);
46610        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46611    }
46612}
46613#[doc = "Vector reinterpret cast operation"]
46614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46615#[inline]
46616#[cfg(target_endian = "little")]
46617#[target_feature(enable = "neon")]
46618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46620#[cfg_attr(
46621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46622    assert_instr(nop)
46623)]
46624#[cfg_attr(
46625    not(target_arch = "arm"),
46626    stable(feature = "neon_intrinsics", since = "1.59.0")
46627)]
46628#[cfg_attr(
46629    target_arch = "arm",
46630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46631)]
46632pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46633    unsafe { transmute(a) }
46634}
46635#[doc = "Vector reinterpret cast operation"]
46636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46637#[inline]
46638#[cfg(target_endian = "big")]
46639#[target_feature(enable = "neon")]
46640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46642#[cfg_attr(
46643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46644    assert_instr(nop)
46645)]
46646#[cfg_attr(
46647    not(target_arch = "arm"),
46648    stable(feature = "neon_intrinsics", since = "1.59.0")
46649)]
46650#[cfg_attr(
46651    target_arch = "arm",
46652    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46653)]
46654pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46655    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46656    unsafe {
46657        let ret_val: uint16x4_t = transmute(a);
46658        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46659    }
46660}
46661#[doc = "Vector reinterpret cast operation"]
46662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46663#[inline]
46664#[cfg(target_endian = "little")]
46665#[target_feature(enable = "neon")]
46666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46668#[cfg_attr(
46669    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46670    assert_instr(nop)
46671)]
46672#[cfg_attr(
46673    not(target_arch = "arm"),
46674    stable(feature = "neon_intrinsics", since = "1.59.0")
46675)]
46676#[cfg_attr(
46677    target_arch = "arm",
46678    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46679)]
46680pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46681    unsafe { transmute(a) }
46682}
46683#[doc = "Vector reinterpret cast operation"]
46684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46685#[inline]
46686#[cfg(target_endian = "big")]
46687#[target_feature(enable = "neon")]
46688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46690#[cfg_attr(
46691    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46692    assert_instr(nop)
46693)]
46694#[cfg_attr(
46695    not(target_arch = "arm"),
46696    stable(feature = "neon_intrinsics", since = "1.59.0")
46697)]
46698#[cfg_attr(
46699    target_arch = "arm",
46700    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46701)]
46702pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46703    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46704    unsafe {
46705        let ret_val: uint32x2_t = transmute(a);
46706        simd_shuffle!(ret_val, ret_val, [1, 0])
46707    }
46708}
46709#[doc = "Vector reinterpret cast operation"]
46710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46711#[inline]
46712#[cfg(target_endian = "little")]
46713#[target_feature(enable = "neon")]
46714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46716#[cfg_attr(
46717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46718    assert_instr(nop)
46719)]
46720#[cfg_attr(
46721    not(target_arch = "arm"),
46722    stable(feature = "neon_intrinsics", since = "1.59.0")
46723)]
46724#[cfg_attr(
46725    target_arch = "arm",
46726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46727)]
46728pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46729    unsafe { transmute(a) }
46730}
46731#[doc = "Vector reinterpret cast operation"]
46732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46733#[inline]
46734#[cfg(target_endian = "big")]
46735#[target_feature(enable = "neon")]
46736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46738#[cfg_attr(
46739    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46740    assert_instr(nop)
46741)]
46742#[cfg_attr(
46743    not(target_arch = "arm"),
46744    stable(feature = "neon_intrinsics", since = "1.59.0")
46745)]
46746#[cfg_attr(
46747    target_arch = "arm",
46748    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46749)]
46750pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46751    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46752    unsafe { transmute(a) }
46753}
46754#[doc = "Vector reinterpret cast operation"]
46755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46756#[inline]
46757#[cfg(target_endian = "little")]
46758#[target_feature(enable = "neon")]
46759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46761#[cfg_attr(
46762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46763    assert_instr(nop)
46764)]
46765#[cfg_attr(
46766    not(target_arch = "arm"),
46767    stable(feature = "neon_intrinsics", since = "1.59.0")
46768)]
46769#[cfg_attr(
46770    target_arch = "arm",
46771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46772)]
46773pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46774    unsafe { transmute(a) }
46775}
46776#[doc = "Vector reinterpret cast operation"]
46777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46778#[inline]
46779#[cfg(target_endian = "big")]
46780#[target_feature(enable = "neon")]
46781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46783#[cfg_attr(
46784    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46785    assert_instr(nop)
46786)]
46787#[cfg_attr(
46788    not(target_arch = "arm"),
46789    stable(feature = "neon_intrinsics", since = "1.59.0")
46790)]
46791#[cfg_attr(
46792    target_arch = "arm",
46793    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46794)]
46795pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46796    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46797    unsafe {
46798        let ret_val: poly8x8_t = transmute(a);
46799        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46800    }
46801}
46802#[doc = "Vector reinterpret cast operation"]
46803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46804#[inline]
46805#[cfg(target_endian = "little")]
46806#[target_feature(enable = "neon")]
46807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46809#[cfg_attr(
46810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46811    assert_instr(nop)
46812)]
46813#[cfg_attr(
46814    not(target_arch = "arm"),
46815    stable(feature = "neon_intrinsics", since = "1.59.0")
46816)]
46817#[cfg_attr(
46818    target_arch = "arm",
46819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46820)]
46821pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46822    unsafe { transmute(a) }
46823}
46824#[doc = "Vector reinterpret cast operation"]
46825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46826#[inline]
46827#[cfg(target_endian = "big")]
46828#[target_feature(enable = "neon")]
46829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46831#[cfg_attr(
46832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46833    assert_instr(nop)
46834)]
46835#[cfg_attr(
46836    not(target_arch = "arm"),
46837    stable(feature = "neon_intrinsics", since = "1.59.0")
46838)]
46839#[cfg_attr(
46840    target_arch = "arm",
46841    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46842)]
46843pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46844    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46845    unsafe {
46846        let ret_val: poly16x4_t = transmute(a);
46847        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46848    }
46849}
46850#[doc = "Vector reinterpret cast operation"]
46851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46852#[inline]
46853#[cfg(target_endian = "little")]
46854#[target_feature(enable = "neon")]
46855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46857#[cfg_attr(
46858    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46859    assert_instr(nop)
46860)]
46861#[cfg_attr(
46862    not(target_arch = "arm"),
46863    stable(feature = "neon_intrinsics", since = "1.59.0")
46864)]
46865#[cfg_attr(
46866    target_arch = "arm",
46867    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46868)]
46869pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46870    unsafe { transmute(a) }
46871}
46872#[doc = "Vector reinterpret cast operation"]
46873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46874#[inline]
46875#[cfg(target_endian = "big")]
46876#[target_feature(enable = "neon")]
46877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46879#[cfg_attr(
46880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46881    assert_instr(nop)
46882)]
46883#[cfg_attr(
46884    not(target_arch = "arm"),
46885    stable(feature = "neon_intrinsics", since = "1.59.0")
46886)]
46887#[cfg_attr(
46888    target_arch = "arm",
46889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46890)]
46891pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46892    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46893    unsafe {
46894        let ret_val: float32x4_t = transmute(a);
46895        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46896    }
46897}
46898#[doc = "Vector reinterpret cast operation"]
46899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46900#[inline]
46901#[cfg(target_endian = "little")]
46902#[target_feature(enable = "neon")]
46903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46905#[cfg_attr(
46906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46907    assert_instr(nop)
46908)]
46909#[cfg_attr(
46910    not(target_arch = "arm"),
46911    stable(feature = "neon_intrinsics", since = "1.59.0")
46912)]
46913#[cfg_attr(
46914    target_arch = "arm",
46915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46916)]
46917pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46918    unsafe { transmute(a) }
46919}
46920#[doc = "Vector reinterpret cast operation"]
46921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46922#[inline]
46923#[cfg(target_endian = "big")]
46924#[target_feature(enable = "neon")]
46925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46927#[cfg_attr(
46928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46929    assert_instr(nop)
46930)]
46931#[cfg_attr(
46932    not(target_arch = "arm"),
46933    stable(feature = "neon_intrinsics", since = "1.59.0")
46934)]
46935#[cfg_attr(
46936    target_arch = "arm",
46937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46938)]
46939pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46940    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46941    unsafe {
46942        let ret_val: int8x16_t = transmute(a);
46943        simd_shuffle!(
46944            ret_val,
46945            ret_val,
46946            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46947        )
46948    }
46949}
46950#[doc = "Vector reinterpret cast operation"]
46951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46952#[inline]
46953#[cfg(target_endian = "little")]
46954#[target_feature(enable = "neon")]
46955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46957#[cfg_attr(
46958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46959    assert_instr(nop)
46960)]
46961#[cfg_attr(
46962    not(target_arch = "arm"),
46963    stable(feature = "neon_intrinsics", since = "1.59.0")
46964)]
46965#[cfg_attr(
46966    target_arch = "arm",
46967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46968)]
46969pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46970    unsafe { transmute(a) }
46971}
46972#[doc = "Vector reinterpret cast operation"]
46973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46974#[inline]
46975#[cfg(target_endian = "big")]
46976#[target_feature(enable = "neon")]
46977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46979#[cfg_attr(
46980    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46981    assert_instr(nop)
46982)]
46983#[cfg_attr(
46984    not(target_arch = "arm"),
46985    stable(feature = "neon_intrinsics", since = "1.59.0")
46986)]
46987#[cfg_attr(
46988    target_arch = "arm",
46989    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46990)]
46991pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46992    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46993    unsafe {
46994        let ret_val: int32x4_t = transmute(a);
46995        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46996    }
46997}
46998#[doc = "Vector reinterpret cast operation"]
46999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
47000#[inline]
47001#[cfg(target_endian = "little")]
47002#[target_feature(enable = "neon")]
47003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47005#[cfg_attr(
47006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47007    assert_instr(nop)
47008)]
47009#[cfg_attr(
47010    not(target_arch = "arm"),
47011    stable(feature = "neon_intrinsics", since = "1.59.0")
47012)]
47013#[cfg_attr(
47014    target_arch = "arm",
47015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47016)]
47017pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
47018    unsafe { transmute(a) }
47019}
47020#[doc = "Vector reinterpret cast operation"]
47021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
47022#[inline]
47023#[cfg(target_endian = "big")]
47024#[target_feature(enable = "neon")]
47025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47027#[cfg_attr(
47028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47029    assert_instr(nop)
47030)]
47031#[cfg_attr(
47032    not(target_arch = "arm"),
47033    stable(feature = "neon_intrinsics", since = "1.59.0")
47034)]
47035#[cfg_attr(
47036    target_arch = "arm",
47037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47038)]
47039pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
47040    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47041    unsafe {
47042        let ret_val: int64x2_t = transmute(a);
47043        simd_shuffle!(ret_val, ret_val, [1, 0])
47044    }
47045}
47046#[doc = "Vector reinterpret cast operation"]
47047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
47048#[inline]
47049#[cfg(target_endian = "little")]
47050#[target_feature(enable = "neon")]
47051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47053#[cfg_attr(
47054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47055    assert_instr(nop)
47056)]
47057#[cfg_attr(
47058    not(target_arch = "arm"),
47059    stable(feature = "neon_intrinsics", since = "1.59.0")
47060)]
47061#[cfg_attr(
47062    target_arch = "arm",
47063    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47064)]
47065pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
47066    unsafe { transmute(a) }
47067}
47068#[doc = "Vector reinterpret cast operation"]
47069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
47070#[inline]
47071#[cfg(target_endian = "big")]
47072#[target_feature(enable = "neon")]
47073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47075#[cfg_attr(
47076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47077    assert_instr(nop)
47078)]
47079#[cfg_attr(
47080    not(target_arch = "arm"),
47081    stable(feature = "neon_intrinsics", since = "1.59.0")
47082)]
47083#[cfg_attr(
47084    target_arch = "arm",
47085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47086)]
47087pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
47088    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47089    unsafe {
47090        let ret_val: uint8x16_t = transmute(a);
47091        simd_shuffle!(
47092            ret_val,
47093            ret_val,
47094            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47095        )
47096    }
47097}
47098#[doc = "Vector reinterpret cast operation"]
47099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47100#[inline]
47101#[cfg(target_endian = "little")]
47102#[target_feature(enable = "neon")]
47103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47105#[cfg_attr(
47106    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47107    assert_instr(nop)
47108)]
47109#[cfg_attr(
47110    not(target_arch = "arm"),
47111    stable(feature = "neon_intrinsics", since = "1.59.0")
47112)]
47113#[cfg_attr(
47114    target_arch = "arm",
47115    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47116)]
47117pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47118    unsafe { transmute(a) }
47119}
47120#[doc = "Vector reinterpret cast operation"]
47121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47122#[inline]
47123#[cfg(target_endian = "big")]
47124#[target_feature(enable = "neon")]
47125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47127#[cfg_attr(
47128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47129    assert_instr(nop)
47130)]
47131#[cfg_attr(
47132    not(target_arch = "arm"),
47133    stable(feature = "neon_intrinsics", since = "1.59.0")
47134)]
47135#[cfg_attr(
47136    target_arch = "arm",
47137    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47138)]
47139pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47140    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47141    unsafe {
47142        let ret_val: uint16x8_t = transmute(a);
47143        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47144    }
47145}
47146#[doc = "Vector reinterpret cast operation"]
47147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47148#[inline]
47149#[cfg(target_endian = "little")]
47150#[target_feature(enable = "neon")]
47151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47153#[cfg_attr(
47154    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47155    assert_instr(nop)
47156)]
47157#[cfg_attr(
47158    not(target_arch = "arm"),
47159    stable(feature = "neon_intrinsics", since = "1.59.0")
47160)]
47161#[cfg_attr(
47162    target_arch = "arm",
47163    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47164)]
47165pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47166    unsafe { transmute(a) }
47167}
47168#[doc = "Vector reinterpret cast operation"]
47169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47170#[inline]
47171#[cfg(target_endian = "big")]
47172#[target_feature(enable = "neon")]
47173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47175#[cfg_attr(
47176    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47177    assert_instr(nop)
47178)]
47179#[cfg_attr(
47180    not(target_arch = "arm"),
47181    stable(feature = "neon_intrinsics", since = "1.59.0")
47182)]
47183#[cfg_attr(
47184    target_arch = "arm",
47185    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47186)]
47187pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47188    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47189    unsafe {
47190        let ret_val: uint32x4_t = transmute(a);
47191        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47192    }
47193}
47194#[doc = "Vector reinterpret cast operation"]
47195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47196#[inline]
47197#[cfg(target_endian = "little")]
47198#[target_feature(enable = "neon")]
47199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47201#[cfg_attr(
47202    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47203    assert_instr(nop)
47204)]
47205#[cfg_attr(
47206    not(target_arch = "arm"),
47207    stable(feature = "neon_intrinsics", since = "1.59.0")
47208)]
47209#[cfg_attr(
47210    target_arch = "arm",
47211    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47212)]
47213pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47214    unsafe { transmute(a) }
47215}
47216#[doc = "Vector reinterpret cast operation"]
47217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47218#[inline]
47219#[cfg(target_endian = "big")]
47220#[target_feature(enable = "neon")]
47221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47223#[cfg_attr(
47224    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47225    assert_instr(nop)
47226)]
47227#[cfg_attr(
47228    not(target_arch = "arm"),
47229    stable(feature = "neon_intrinsics", since = "1.59.0")
47230)]
47231#[cfg_attr(
47232    target_arch = "arm",
47233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47234)]
47235pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47236    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47237    unsafe {
47238        let ret_val: uint64x2_t = transmute(a);
47239        simd_shuffle!(ret_val, ret_val, [1, 0])
47240    }
47241}
47242#[doc = "Vector reinterpret cast operation"]
47243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47244#[inline]
47245#[cfg(target_endian = "little")]
47246#[target_feature(enable = "neon")]
47247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47249#[cfg_attr(
47250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47251    assert_instr(nop)
47252)]
47253#[cfg_attr(
47254    not(target_arch = "arm"),
47255    stable(feature = "neon_intrinsics", since = "1.59.0")
47256)]
47257#[cfg_attr(
47258    target_arch = "arm",
47259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47260)]
47261pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47262    unsafe { transmute(a) }
47263}
47264#[doc = "Vector reinterpret cast operation"]
47265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47266#[inline]
47267#[cfg(target_endian = "big")]
47268#[target_feature(enable = "neon")]
47269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47271#[cfg_attr(
47272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47273    assert_instr(nop)
47274)]
47275#[cfg_attr(
47276    not(target_arch = "arm"),
47277    stable(feature = "neon_intrinsics", since = "1.59.0")
47278)]
47279#[cfg_attr(
47280    target_arch = "arm",
47281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47282)]
47283pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47284    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47285    unsafe {
47286        let ret_val: poly8x16_t = transmute(a);
47287        simd_shuffle!(
47288            ret_val,
47289            ret_val,
47290            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47291        )
47292    }
47293}
47294#[doc = "Vector reinterpret cast operation"]
47295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47296#[inline]
47297#[cfg(target_endian = "little")]
47298#[target_feature(enable = "neon")]
47299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47301#[cfg_attr(
47302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47303    assert_instr(nop)
47304)]
47305#[cfg_attr(
47306    not(target_arch = "arm"),
47307    stable(feature = "neon_intrinsics", since = "1.59.0")
47308)]
47309#[cfg_attr(
47310    target_arch = "arm",
47311    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47312)]
47313pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47314    unsafe { transmute(a) }
47315}
47316#[doc = "Vector reinterpret cast operation"]
47317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47318#[inline]
47319#[cfg(target_endian = "big")]
47320#[target_feature(enable = "neon")]
47321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47323#[cfg_attr(
47324    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47325    assert_instr(nop)
47326)]
47327#[cfg_attr(
47328    not(target_arch = "arm"),
47329    stable(feature = "neon_intrinsics", since = "1.59.0")
47330)]
47331#[cfg_attr(
47332    target_arch = "arm",
47333    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47334)]
47335pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47336    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47337    unsafe {
47338        let ret_val: poly16x8_t = transmute(a);
47339        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47340    }
47341}
47342#[doc = "Vector reinterpret cast operation"]
47343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47344#[inline]
47345#[cfg(target_endian = "little")]
47346#[target_feature(enable = "neon")]
47347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47349#[cfg_attr(
47350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47351    assert_instr(nop)
47352)]
47353#[cfg_attr(
47354    not(target_arch = "arm"),
47355    stable(feature = "neon_intrinsics", since = "1.59.0")
47356)]
47357#[cfg_attr(
47358    target_arch = "arm",
47359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47360)]
47361pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47362    unsafe { transmute(a) }
47363}
47364#[doc = "Vector reinterpret cast operation"]
47365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47366#[inline]
47367#[cfg(target_endian = "big")]
47368#[target_feature(enable = "neon")]
47369#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47370#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47371#[cfg_attr(
47372    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47373    assert_instr(nop)
47374)]
47375#[cfg_attr(
47376    not(target_arch = "arm"),
47377    stable(feature = "neon_intrinsics", since = "1.59.0")
47378)]
47379#[cfg_attr(
47380    target_arch = "arm",
47381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47382)]
47383pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47384    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47385    unsafe {
47386        let ret_val: float32x2_t = transmute(a);
47387        simd_shuffle!(ret_val, ret_val, [1, 0])
47388    }
47389}
47390#[doc = "Vector reinterpret cast operation"]
47391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47392#[inline]
47393#[cfg(target_endian = "little")]
47394#[target_feature(enable = "neon")]
47395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47397#[cfg_attr(
47398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47399    assert_instr(nop)
47400)]
47401#[cfg_attr(
47402    not(target_arch = "arm"),
47403    stable(feature = "neon_intrinsics", since = "1.59.0")
47404)]
47405#[cfg_attr(
47406    target_arch = "arm",
47407    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47408)]
47409pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47410    unsafe { transmute(a) }
47411}
47412#[doc = "Vector reinterpret cast operation"]
47413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47414#[inline]
47415#[cfg(target_endian = "big")]
47416#[target_feature(enable = "neon")]
47417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47419#[cfg_attr(
47420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47421    assert_instr(nop)
47422)]
47423#[cfg_attr(
47424    not(target_arch = "arm"),
47425    stable(feature = "neon_intrinsics", since = "1.59.0")
47426)]
47427#[cfg_attr(
47428    target_arch = "arm",
47429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47430)]
47431pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47432    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47433    unsafe {
47434        let ret_val: int8x8_t = transmute(a);
47435        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47436    }
47437}
47438#[doc = "Vector reinterpret cast operation"]
47439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47440#[inline]
47441#[cfg(target_endian = "little")]
47442#[target_feature(enable = "neon")]
47443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47445#[cfg_attr(
47446    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47447    assert_instr(nop)
47448)]
47449#[cfg_attr(
47450    not(target_arch = "arm"),
47451    stable(feature = "neon_intrinsics", since = "1.59.0")
47452)]
47453#[cfg_attr(
47454    target_arch = "arm",
47455    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47456)]
47457pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47458    unsafe { transmute(a) }
47459}
47460#[doc = "Vector reinterpret cast operation"]
47461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47462#[inline]
47463#[cfg(target_endian = "big")]
47464#[target_feature(enable = "neon")]
47465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47467#[cfg_attr(
47468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47469    assert_instr(nop)
47470)]
47471#[cfg_attr(
47472    not(target_arch = "arm"),
47473    stable(feature = "neon_intrinsics", since = "1.59.0")
47474)]
47475#[cfg_attr(
47476    target_arch = "arm",
47477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47478)]
47479pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47480    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47481    unsafe {
47482        let ret_val: int16x4_t = transmute(a);
47483        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47484    }
47485}
47486#[doc = "Vector reinterpret cast operation"]
47487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47488#[inline]
47489#[cfg(target_endian = "little")]
47490#[target_feature(enable = "neon")]
47491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47493#[cfg_attr(
47494    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47495    assert_instr(nop)
47496)]
47497#[cfg_attr(
47498    not(target_arch = "arm"),
47499    stable(feature = "neon_intrinsics", since = "1.59.0")
47500)]
47501#[cfg_attr(
47502    target_arch = "arm",
47503    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47504)]
47505pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47506    unsafe { transmute(a) }
47507}
47508#[doc = "Vector reinterpret cast operation"]
47509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47510#[inline]
47511#[cfg(target_endian = "big")]
47512#[target_feature(enable = "neon")]
47513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47515#[cfg_attr(
47516    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47517    assert_instr(nop)
47518)]
47519#[cfg_attr(
47520    not(target_arch = "arm"),
47521    stable(feature = "neon_intrinsics", since = "1.59.0")
47522)]
47523#[cfg_attr(
47524    target_arch = "arm",
47525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47526)]
47527pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47528    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47529    unsafe { transmute(a) }
47530}
47531#[doc = "Vector reinterpret cast operation"]
47532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47533#[inline]
47534#[cfg(target_endian = "little")]
47535#[target_feature(enable = "neon")]
47536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47538#[cfg_attr(
47539    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47540    assert_instr(nop)
47541)]
47542#[cfg_attr(
47543    not(target_arch = "arm"),
47544    stable(feature = "neon_intrinsics", since = "1.59.0")
47545)]
47546#[cfg_attr(
47547    target_arch = "arm",
47548    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47549)]
47550pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47551    unsafe { transmute(a) }
47552}
47553#[doc = "Vector reinterpret cast operation"]
47554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47555#[inline]
47556#[cfg(target_endian = "big")]
47557#[target_feature(enable = "neon")]
47558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47560#[cfg_attr(
47561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47562    assert_instr(nop)
47563)]
47564#[cfg_attr(
47565    not(target_arch = "arm"),
47566    stable(feature = "neon_intrinsics", since = "1.59.0")
47567)]
47568#[cfg_attr(
47569    target_arch = "arm",
47570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47571)]
47572pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47573    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47574    unsafe {
47575        let ret_val: uint8x8_t = transmute(a);
47576        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47577    }
47578}
47579#[doc = "Vector reinterpret cast operation"]
47580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47581#[inline]
47582#[cfg(target_endian = "little")]
47583#[target_feature(enable = "neon")]
47584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47586#[cfg_attr(
47587    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47588    assert_instr(nop)
47589)]
47590#[cfg_attr(
47591    not(target_arch = "arm"),
47592    stable(feature = "neon_intrinsics", since = "1.59.0")
47593)]
47594#[cfg_attr(
47595    target_arch = "arm",
47596    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47597)]
47598pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47599    unsafe { transmute(a) }
47600}
47601#[doc = "Vector reinterpret cast operation"]
47602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47603#[inline]
47604#[cfg(target_endian = "big")]
47605#[target_feature(enable = "neon")]
47606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47608#[cfg_attr(
47609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47610    assert_instr(nop)
47611)]
47612#[cfg_attr(
47613    not(target_arch = "arm"),
47614    stable(feature = "neon_intrinsics", since = "1.59.0")
47615)]
47616#[cfg_attr(
47617    target_arch = "arm",
47618    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47619)]
47620pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47621    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47622    unsafe {
47623        let ret_val: uint16x4_t = transmute(a);
47624        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47625    }
47626}
47627#[doc = "Vector reinterpret cast operation"]
47628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47629#[inline]
47630#[cfg(target_endian = "little")]
47631#[target_feature(enable = "neon")]
47632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47634#[cfg_attr(
47635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47636    assert_instr(nop)
47637)]
47638#[cfg_attr(
47639    not(target_arch = "arm"),
47640    stable(feature = "neon_intrinsics", since = "1.59.0")
47641)]
47642#[cfg_attr(
47643    target_arch = "arm",
47644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47645)]
47646pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47647    unsafe { transmute(a) }
47648}
47649#[doc = "Vector reinterpret cast operation"]
47650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47651#[inline]
47652#[cfg(target_endian = "big")]
47653#[target_feature(enable = "neon")]
47654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47656#[cfg_attr(
47657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47658    assert_instr(nop)
47659)]
47660#[cfg_attr(
47661    not(target_arch = "arm"),
47662    stable(feature = "neon_intrinsics", since = "1.59.0")
47663)]
47664#[cfg_attr(
47665    target_arch = "arm",
47666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47667)]
47668pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47669    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47670    unsafe {
47671        let ret_val: uint32x2_t = transmute(a);
47672        simd_shuffle!(ret_val, ret_val, [1, 0])
47673    }
47674}
47675#[doc = "Vector reinterpret cast operation"]
47676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47677#[inline]
47678#[cfg(target_endian = "little")]
47679#[target_feature(enable = "neon")]
47680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47682#[cfg_attr(
47683    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47684    assert_instr(nop)
47685)]
47686#[cfg_attr(
47687    not(target_arch = "arm"),
47688    stable(feature = "neon_intrinsics", since = "1.59.0")
47689)]
47690#[cfg_attr(
47691    target_arch = "arm",
47692    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47693)]
47694pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47695    unsafe { transmute(a) }
47696}
47697#[doc = "Vector reinterpret cast operation"]
47698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47699#[inline]
47700#[cfg(target_endian = "big")]
47701#[target_feature(enable = "neon")]
47702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47704#[cfg_attr(
47705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47706    assert_instr(nop)
47707)]
47708#[cfg_attr(
47709    not(target_arch = "arm"),
47710    stable(feature = "neon_intrinsics", since = "1.59.0")
47711)]
47712#[cfg_attr(
47713    target_arch = "arm",
47714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47715)]
47716pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47717    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47718    unsafe { transmute(a) }
47719}
47720#[doc = "Vector reinterpret cast operation"]
47721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47722#[inline]
47723#[cfg(target_endian = "little")]
47724#[target_feature(enable = "neon")]
47725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47727#[cfg_attr(
47728    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47729    assert_instr(nop)
47730)]
47731#[cfg_attr(
47732    not(target_arch = "arm"),
47733    stable(feature = "neon_intrinsics", since = "1.59.0")
47734)]
47735#[cfg_attr(
47736    target_arch = "arm",
47737    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47738)]
47739pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47740    unsafe { transmute(a) }
47741}
47742#[doc = "Vector reinterpret cast operation"]
47743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47744#[inline]
47745#[cfg(target_endian = "big")]
47746#[target_feature(enable = "neon")]
47747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47749#[cfg_attr(
47750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47751    assert_instr(nop)
47752)]
47753#[cfg_attr(
47754    not(target_arch = "arm"),
47755    stable(feature = "neon_intrinsics", since = "1.59.0")
47756)]
47757#[cfg_attr(
47758    target_arch = "arm",
47759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47760)]
47761pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47762    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47763    unsafe {
47764        let ret_val: poly8x8_t = transmute(a);
47765        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47766    }
47767}
47768#[doc = "Vector reinterpret cast operation"]
47769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47770#[inline]
47771#[cfg(target_endian = "little")]
47772#[target_feature(enable = "neon")]
47773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47775#[cfg_attr(
47776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47777    assert_instr(nop)
47778)]
47779#[cfg_attr(
47780    not(target_arch = "arm"),
47781    stable(feature = "neon_intrinsics", since = "1.59.0")
47782)]
47783#[cfg_attr(
47784    target_arch = "arm",
47785    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47786)]
47787pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47788    unsafe { transmute(a) }
47789}
47790#[doc = "Vector reinterpret cast operation"]
47791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47792#[inline]
47793#[cfg(target_endian = "big")]
47794#[target_feature(enable = "neon")]
47795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47797#[cfg_attr(
47798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47799    assert_instr(nop)
47800)]
47801#[cfg_attr(
47802    not(target_arch = "arm"),
47803    stable(feature = "neon_intrinsics", since = "1.59.0")
47804)]
47805#[cfg_attr(
47806    target_arch = "arm",
47807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47808)]
47809pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47810    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47811    unsafe {
47812        let ret_val: poly16x4_t = transmute(a);
47813        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47814    }
47815}
47816#[doc = "Vector reinterpret cast operation"]
47817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47818#[inline]
47819#[cfg(target_endian = "little")]
47820#[target_feature(enable = "neon")]
47821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47822#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47823#[cfg_attr(
47824    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47825    assert_instr(nop)
47826)]
47827#[cfg_attr(
47828    not(target_arch = "arm"),
47829    stable(feature = "neon_intrinsics", since = "1.59.0")
47830)]
47831#[cfg_attr(
47832    target_arch = "arm",
47833    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47834)]
47835pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47836    unsafe { transmute(a) }
47837}
47838#[doc = "Vector reinterpret cast operation"]
47839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47840#[inline]
47841#[cfg(target_endian = "big")]
47842#[target_feature(enable = "neon")]
47843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47845#[cfg_attr(
47846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47847    assert_instr(nop)
47848)]
47849#[cfg_attr(
47850    not(target_arch = "arm"),
47851    stable(feature = "neon_intrinsics", since = "1.59.0")
47852)]
47853#[cfg_attr(
47854    target_arch = "arm",
47855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47856)]
47857pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47858    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47859    unsafe {
47860        let ret_val: float32x4_t = transmute(a);
47861        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47862    }
47863}
47864#[doc = "Vector reinterpret cast operation"]
47865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47866#[inline]
47867#[cfg(target_endian = "little")]
47868#[target_feature(enable = "neon")]
47869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47871#[cfg_attr(
47872    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47873    assert_instr(nop)
47874)]
47875#[cfg_attr(
47876    not(target_arch = "arm"),
47877    stable(feature = "neon_intrinsics", since = "1.59.0")
47878)]
47879#[cfg_attr(
47880    target_arch = "arm",
47881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47882)]
47883pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47884    unsafe { transmute(a) }
47885}
47886#[doc = "Vector reinterpret cast operation"]
47887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47888#[inline]
47889#[cfg(target_endian = "big")]
47890#[target_feature(enable = "neon")]
47891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47893#[cfg_attr(
47894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47895    assert_instr(nop)
47896)]
47897#[cfg_attr(
47898    not(target_arch = "arm"),
47899    stable(feature = "neon_intrinsics", since = "1.59.0")
47900)]
47901#[cfg_attr(
47902    target_arch = "arm",
47903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47904)]
47905pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47906    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47907    unsafe {
47908        let ret_val: int8x16_t = transmute(a);
47909        simd_shuffle!(
47910            ret_val,
47911            ret_val,
47912            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47913        )
47914    }
47915}
47916#[doc = "Vector reinterpret cast operation"]
47917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47918#[inline]
47919#[cfg(target_endian = "little")]
47920#[target_feature(enable = "neon")]
47921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47923#[cfg_attr(
47924    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47925    assert_instr(nop)
47926)]
47927#[cfg_attr(
47928    not(target_arch = "arm"),
47929    stable(feature = "neon_intrinsics", since = "1.59.0")
47930)]
47931#[cfg_attr(
47932    target_arch = "arm",
47933    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47934)]
47935pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47936    unsafe { transmute(a) }
47937}
47938#[doc = "Vector reinterpret cast operation"]
47939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47940#[inline]
47941#[cfg(target_endian = "big")]
47942#[target_feature(enable = "neon")]
47943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47945#[cfg_attr(
47946    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47947    assert_instr(nop)
47948)]
47949#[cfg_attr(
47950    not(target_arch = "arm"),
47951    stable(feature = "neon_intrinsics", since = "1.59.0")
47952)]
47953#[cfg_attr(
47954    target_arch = "arm",
47955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47956)]
47957pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47958    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47959    unsafe {
47960        let ret_val: int16x8_t = transmute(a);
47961        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47962    }
47963}
47964#[doc = "Vector reinterpret cast operation"]
47965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47966#[inline]
47967#[cfg(target_endian = "little")]
47968#[target_feature(enable = "neon")]
47969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47971#[cfg_attr(
47972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47973    assert_instr(nop)
47974)]
47975#[cfg_attr(
47976    not(target_arch = "arm"),
47977    stable(feature = "neon_intrinsics", since = "1.59.0")
47978)]
47979#[cfg_attr(
47980    target_arch = "arm",
47981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47982)]
47983pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47984    unsafe { transmute(a) }
47985}
47986#[doc = "Vector reinterpret cast operation"]
47987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47988#[inline]
47989#[cfg(target_endian = "big")]
47990#[target_feature(enable = "neon")]
47991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47993#[cfg_attr(
47994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47995    assert_instr(nop)
47996)]
47997#[cfg_attr(
47998    not(target_arch = "arm"),
47999    stable(feature = "neon_intrinsics", since = "1.59.0")
48000)]
48001#[cfg_attr(
48002    target_arch = "arm",
48003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48004)]
48005pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
48006    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48007    unsafe {
48008        let ret_val: int64x2_t = transmute(a);
48009        simd_shuffle!(ret_val, ret_val, [1, 0])
48010    }
48011}
48012#[doc = "Vector reinterpret cast operation"]
48013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
48014#[inline]
48015#[cfg(target_endian = "little")]
48016#[target_feature(enable = "neon")]
48017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48019#[cfg_attr(
48020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48021    assert_instr(nop)
48022)]
48023#[cfg_attr(
48024    not(target_arch = "arm"),
48025    stable(feature = "neon_intrinsics", since = "1.59.0")
48026)]
48027#[cfg_attr(
48028    target_arch = "arm",
48029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48030)]
48031pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
48032    unsafe { transmute(a) }
48033}
48034#[doc = "Vector reinterpret cast operation"]
48035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
48036#[inline]
48037#[cfg(target_endian = "big")]
48038#[target_feature(enable = "neon")]
48039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48041#[cfg_attr(
48042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48043    assert_instr(nop)
48044)]
48045#[cfg_attr(
48046    not(target_arch = "arm"),
48047    stable(feature = "neon_intrinsics", since = "1.59.0")
48048)]
48049#[cfg_attr(
48050    target_arch = "arm",
48051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48052)]
48053pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
48054    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48055    unsafe {
48056        let ret_val: uint8x16_t = transmute(a);
48057        simd_shuffle!(
48058            ret_val,
48059            ret_val,
48060            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48061        )
48062    }
48063}
48064#[doc = "Vector reinterpret cast operation"]
48065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
48066#[inline]
48067#[cfg(target_endian = "little")]
48068#[target_feature(enable = "neon")]
48069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48071#[cfg_attr(
48072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48073    assert_instr(nop)
48074)]
48075#[cfg_attr(
48076    not(target_arch = "arm"),
48077    stable(feature = "neon_intrinsics", since = "1.59.0")
48078)]
48079#[cfg_attr(
48080    target_arch = "arm",
48081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48082)]
48083pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
48084    unsafe { transmute(a) }
48085}
48086#[doc = "Vector reinterpret cast operation"]
48087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
48088#[inline]
48089#[cfg(target_endian = "big")]
48090#[target_feature(enable = "neon")]
48091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48093#[cfg_attr(
48094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48095    assert_instr(nop)
48096)]
48097#[cfg_attr(
48098    not(target_arch = "arm"),
48099    stable(feature = "neon_intrinsics", since = "1.59.0")
48100)]
48101#[cfg_attr(
48102    target_arch = "arm",
48103    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48104)]
48105pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
48106    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48107    unsafe {
48108        let ret_val: uint16x8_t = transmute(a);
48109        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48110    }
48111}
48112#[doc = "Vector reinterpret cast operation"]
48113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48114#[inline]
48115#[cfg(target_endian = "little")]
48116#[target_feature(enable = "neon")]
48117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48119#[cfg_attr(
48120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48121    assert_instr(nop)
48122)]
48123#[cfg_attr(
48124    not(target_arch = "arm"),
48125    stable(feature = "neon_intrinsics", since = "1.59.0")
48126)]
48127#[cfg_attr(
48128    target_arch = "arm",
48129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48130)]
48131pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48132    unsafe { transmute(a) }
48133}
48134#[doc = "Vector reinterpret cast operation"]
48135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48136#[inline]
48137#[cfg(target_endian = "big")]
48138#[target_feature(enable = "neon")]
48139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48141#[cfg_attr(
48142    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48143    assert_instr(nop)
48144)]
48145#[cfg_attr(
48146    not(target_arch = "arm"),
48147    stable(feature = "neon_intrinsics", since = "1.59.0")
48148)]
48149#[cfg_attr(
48150    target_arch = "arm",
48151    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48152)]
48153pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48154    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48155    unsafe {
48156        let ret_val: uint32x4_t = transmute(a);
48157        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48158    }
48159}
48160#[doc = "Vector reinterpret cast operation"]
48161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48162#[inline]
48163#[cfg(target_endian = "little")]
48164#[target_feature(enable = "neon")]
48165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48167#[cfg_attr(
48168    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48169    assert_instr(nop)
48170)]
48171#[cfg_attr(
48172    not(target_arch = "arm"),
48173    stable(feature = "neon_intrinsics", since = "1.59.0")
48174)]
48175#[cfg_attr(
48176    target_arch = "arm",
48177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48178)]
48179pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48180    unsafe { transmute(a) }
48181}
48182#[doc = "Vector reinterpret cast operation"]
48183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48184#[inline]
48185#[cfg(target_endian = "big")]
48186#[target_feature(enable = "neon")]
48187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48189#[cfg_attr(
48190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48191    assert_instr(nop)
48192)]
48193#[cfg_attr(
48194    not(target_arch = "arm"),
48195    stable(feature = "neon_intrinsics", since = "1.59.0")
48196)]
48197#[cfg_attr(
48198    target_arch = "arm",
48199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48200)]
48201pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48202    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48203    unsafe {
48204        let ret_val: uint64x2_t = transmute(a);
48205        simd_shuffle!(ret_val, ret_val, [1, 0])
48206    }
48207}
48208#[doc = "Vector reinterpret cast operation"]
48209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48210#[inline]
48211#[cfg(target_endian = "little")]
48212#[target_feature(enable = "neon")]
48213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48215#[cfg_attr(
48216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48217    assert_instr(nop)
48218)]
48219#[cfg_attr(
48220    not(target_arch = "arm"),
48221    stable(feature = "neon_intrinsics", since = "1.59.0")
48222)]
48223#[cfg_attr(
48224    target_arch = "arm",
48225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48226)]
48227pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48228    unsafe { transmute(a) }
48229}
48230#[doc = "Vector reinterpret cast operation"]
48231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48232#[inline]
48233#[cfg(target_endian = "big")]
48234#[target_feature(enable = "neon")]
48235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48237#[cfg_attr(
48238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48239    assert_instr(nop)
48240)]
48241#[cfg_attr(
48242    not(target_arch = "arm"),
48243    stable(feature = "neon_intrinsics", since = "1.59.0")
48244)]
48245#[cfg_attr(
48246    target_arch = "arm",
48247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48248)]
48249pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48250    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48251    unsafe {
48252        let ret_val: poly8x16_t = transmute(a);
48253        simd_shuffle!(
48254            ret_val,
48255            ret_val,
48256            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48257        )
48258    }
48259}
48260#[doc = "Vector reinterpret cast operation"]
48261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48262#[inline]
48263#[cfg(target_endian = "little")]
48264#[target_feature(enable = "neon")]
48265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48267#[cfg_attr(
48268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48269    assert_instr(nop)
48270)]
48271#[cfg_attr(
48272    not(target_arch = "arm"),
48273    stable(feature = "neon_intrinsics", since = "1.59.0")
48274)]
48275#[cfg_attr(
48276    target_arch = "arm",
48277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48278)]
48279pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48280    unsafe { transmute(a) }
48281}
48282#[doc = "Vector reinterpret cast operation"]
48283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48284#[inline]
48285#[cfg(target_endian = "big")]
48286#[target_feature(enable = "neon")]
48287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48289#[cfg_attr(
48290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48291    assert_instr(nop)
48292)]
48293#[cfg_attr(
48294    not(target_arch = "arm"),
48295    stable(feature = "neon_intrinsics", since = "1.59.0")
48296)]
48297#[cfg_attr(
48298    target_arch = "arm",
48299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48300)]
48301pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48302    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48303    unsafe {
48304        let ret_val: poly16x8_t = transmute(a);
48305        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48306    }
48307}
48308#[doc = "Vector reinterpret cast operation"]
48309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48310#[inline]
48311#[cfg(target_endian = "little")]
48312#[target_feature(enable = "neon")]
48313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48315#[cfg_attr(
48316    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48317    assert_instr(nop)
48318)]
48319#[cfg_attr(
48320    not(target_arch = "arm"),
48321    stable(feature = "neon_intrinsics", since = "1.59.0")
48322)]
48323#[cfg_attr(
48324    target_arch = "arm",
48325    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48326)]
48327pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48328    unsafe { transmute(a) }
48329}
48330#[doc = "Vector reinterpret cast operation"]
48331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48332#[inline]
48333#[cfg(target_endian = "big")]
48334#[target_feature(enable = "neon")]
48335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48337#[cfg_attr(
48338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48339    assert_instr(nop)
48340)]
48341#[cfg_attr(
48342    not(target_arch = "arm"),
48343    stable(feature = "neon_intrinsics", since = "1.59.0")
48344)]
48345#[cfg_attr(
48346    target_arch = "arm",
48347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48348)]
48349pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48350    unsafe {
48351        let ret_val: float32x2_t = transmute(a);
48352        simd_shuffle!(ret_val, ret_val, [1, 0])
48353    }
48354}
48355#[doc = "Vector reinterpret cast operation"]
48356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48357#[inline]
48358#[cfg(target_endian = "little")]
48359#[target_feature(enable = "neon")]
48360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48362#[cfg_attr(
48363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48364    assert_instr(nop)
48365)]
48366#[cfg_attr(
48367    not(target_arch = "arm"),
48368    stable(feature = "neon_intrinsics", since = "1.59.0")
48369)]
48370#[cfg_attr(
48371    target_arch = "arm",
48372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48373)]
48374pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48375    unsafe { transmute(a) }
48376}
48377#[doc = "Vector reinterpret cast operation"]
48378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48379#[inline]
48380#[cfg(target_endian = "big")]
48381#[target_feature(enable = "neon")]
48382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48384#[cfg_attr(
48385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48386    assert_instr(nop)
48387)]
48388#[cfg_attr(
48389    not(target_arch = "arm"),
48390    stable(feature = "neon_intrinsics", since = "1.59.0")
48391)]
48392#[cfg_attr(
48393    target_arch = "arm",
48394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48395)]
48396pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48397    unsafe {
48398        let ret_val: int8x8_t = transmute(a);
48399        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48400    }
48401}
48402#[doc = "Vector reinterpret cast operation"]
48403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48404#[inline]
48405#[cfg(target_endian = "little")]
48406#[target_feature(enable = "neon")]
48407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48409#[cfg_attr(
48410    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48411    assert_instr(nop)
48412)]
48413#[cfg_attr(
48414    not(target_arch = "arm"),
48415    stable(feature = "neon_intrinsics", since = "1.59.0")
48416)]
48417#[cfg_attr(
48418    target_arch = "arm",
48419    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48420)]
48421pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48422    unsafe { transmute(a) }
48423}
48424#[doc = "Vector reinterpret cast operation"]
48425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48426#[inline]
48427#[cfg(target_endian = "big")]
48428#[target_feature(enable = "neon")]
48429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48431#[cfg_attr(
48432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48433    assert_instr(nop)
48434)]
48435#[cfg_attr(
48436    not(target_arch = "arm"),
48437    stable(feature = "neon_intrinsics", since = "1.59.0")
48438)]
48439#[cfg_attr(
48440    target_arch = "arm",
48441    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48442)]
48443pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48444    unsafe {
48445        let ret_val: int16x4_t = transmute(a);
48446        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48447    }
48448}
48449#[doc = "Vector reinterpret cast operation"]
48450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48451#[inline]
48452#[cfg(target_endian = "little")]
48453#[target_feature(enable = "neon")]
48454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48456#[cfg_attr(
48457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48458    assert_instr(nop)
48459)]
48460#[cfg_attr(
48461    not(target_arch = "arm"),
48462    stable(feature = "neon_intrinsics", since = "1.59.0")
48463)]
48464#[cfg_attr(
48465    target_arch = "arm",
48466    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48467)]
48468pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48469    unsafe { transmute(a) }
48470}
48471#[doc = "Vector reinterpret cast operation"]
48472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48473#[inline]
48474#[cfg(target_endian = "big")]
48475#[target_feature(enable = "neon")]
48476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48478#[cfg_attr(
48479    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48480    assert_instr(nop)
48481)]
48482#[cfg_attr(
48483    not(target_arch = "arm"),
48484    stable(feature = "neon_intrinsics", since = "1.59.0")
48485)]
48486#[cfg_attr(
48487    target_arch = "arm",
48488    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48489)]
48490pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48491    unsafe {
48492        let ret_val: int32x2_t = transmute(a);
48493        simd_shuffle!(ret_val, ret_val, [1, 0])
48494    }
48495}
48496#[doc = "Vector reinterpret cast operation"]
48497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48498#[inline]
48499#[cfg(target_endian = "little")]
48500#[target_feature(enable = "neon")]
48501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48503#[cfg_attr(
48504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48505    assert_instr(nop)
48506)]
48507#[cfg_attr(
48508    not(target_arch = "arm"),
48509    stable(feature = "neon_intrinsics", since = "1.59.0")
48510)]
48511#[cfg_attr(
48512    target_arch = "arm",
48513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48514)]
48515pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48516    unsafe { transmute(a) }
48517}
48518#[doc = "Vector reinterpret cast operation"]
48519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48520#[inline]
48521#[cfg(target_endian = "big")]
48522#[target_feature(enable = "neon")]
48523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48525#[cfg_attr(
48526    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48527    assert_instr(nop)
48528)]
48529#[cfg_attr(
48530    not(target_arch = "arm"),
48531    stable(feature = "neon_intrinsics", since = "1.59.0")
48532)]
48533#[cfg_attr(
48534    target_arch = "arm",
48535    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48536)]
48537pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48538    unsafe {
48539        let ret_val: uint8x8_t = transmute(a);
48540        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48541    }
48542}
48543#[doc = "Vector reinterpret cast operation"]
48544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48545#[inline]
48546#[cfg(target_endian = "little")]
48547#[target_feature(enable = "neon")]
48548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48550#[cfg_attr(
48551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48552    assert_instr(nop)
48553)]
48554#[cfg_attr(
48555    not(target_arch = "arm"),
48556    stable(feature = "neon_intrinsics", since = "1.59.0")
48557)]
48558#[cfg_attr(
48559    target_arch = "arm",
48560    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48561)]
48562pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48563    unsafe { transmute(a) }
48564}
48565#[doc = "Vector reinterpret cast operation"]
48566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48567#[inline]
48568#[cfg(target_endian = "big")]
48569#[target_feature(enable = "neon")]
48570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48572#[cfg_attr(
48573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48574    assert_instr(nop)
48575)]
48576#[cfg_attr(
48577    not(target_arch = "arm"),
48578    stable(feature = "neon_intrinsics", since = "1.59.0")
48579)]
48580#[cfg_attr(
48581    target_arch = "arm",
48582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48583)]
48584pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48585    unsafe {
48586        let ret_val: uint16x4_t = transmute(a);
48587        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48588    }
48589}
48590#[doc = "Vector reinterpret cast operation"]
48591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48592#[inline]
48593#[cfg(target_endian = "little")]
48594#[target_feature(enable = "neon")]
48595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48597#[cfg_attr(
48598    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48599    assert_instr(nop)
48600)]
48601#[cfg_attr(
48602    not(target_arch = "arm"),
48603    stable(feature = "neon_intrinsics", since = "1.59.0")
48604)]
48605#[cfg_attr(
48606    target_arch = "arm",
48607    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48608)]
48609pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48610    unsafe { transmute(a) }
48611}
48612#[doc = "Vector reinterpret cast operation"]
48613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48614#[inline]
48615#[cfg(target_endian = "big")]
48616#[target_feature(enable = "neon")]
48617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48619#[cfg_attr(
48620    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48621    assert_instr(nop)
48622)]
48623#[cfg_attr(
48624    not(target_arch = "arm"),
48625    stable(feature = "neon_intrinsics", since = "1.59.0")
48626)]
48627#[cfg_attr(
48628    target_arch = "arm",
48629    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48630)]
48631pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48632    unsafe {
48633        let ret_val: uint32x2_t = transmute(a);
48634        simd_shuffle!(ret_val, ret_val, [1, 0])
48635    }
48636}
48637#[doc = "Vector reinterpret cast operation"]
48638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
48639#[inline]
48640#[target_feature(enable = "neon")]
48641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48643#[cfg_attr(
48644    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48645    assert_instr(nop)
48646)]
48647#[cfg_attr(
48648    not(target_arch = "arm"),
48649    stable(feature = "neon_intrinsics", since = "1.59.0")
48650)]
48651#[cfg_attr(
48652    target_arch = "arm",
48653    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48654)]
48655pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
48656    unsafe { transmute(a) }
48657}
48658#[doc = "Vector reinterpret cast operation"]
48659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48660#[inline]
48661#[cfg(target_endian = "little")]
48662#[target_feature(enable = "neon")]
48663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48665#[cfg_attr(
48666    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48667    assert_instr(nop)
48668)]
48669#[cfg_attr(
48670    not(target_arch = "arm"),
48671    stable(feature = "neon_intrinsics", since = "1.59.0")
48672)]
48673#[cfg_attr(
48674    target_arch = "arm",
48675    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48676)]
48677pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48678    unsafe { transmute(a) }
48679}
48680#[doc = "Vector reinterpret cast operation"]
48681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48682#[inline]
48683#[cfg(target_endian = "big")]
48684#[target_feature(enable = "neon")]
48685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48687#[cfg_attr(
48688    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48689    assert_instr(nop)
48690)]
48691#[cfg_attr(
48692    not(target_arch = "arm"),
48693    stable(feature = "neon_intrinsics", since = "1.59.0")
48694)]
48695#[cfg_attr(
48696    target_arch = "arm",
48697    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48698)]
48699pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48700    unsafe {
48701        let ret_val: poly8x8_t = transmute(a);
48702        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48703    }
48704}
48705#[doc = "Vector reinterpret cast operation"]
48706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48707#[inline]
48708#[cfg(target_endian = "little")]
48709#[target_feature(enable = "neon")]
48710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48712#[cfg_attr(
48713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48714    assert_instr(nop)
48715)]
48716#[cfg_attr(
48717    not(target_arch = "arm"),
48718    stable(feature = "neon_intrinsics", since = "1.59.0")
48719)]
48720#[cfg_attr(
48721    target_arch = "arm",
48722    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48723)]
48724pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48725    unsafe { transmute(a) }
48726}
48727#[doc = "Vector reinterpret cast operation"]
48728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48729#[inline]
48730#[cfg(target_endian = "big")]
48731#[target_feature(enable = "neon")]
48732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48734#[cfg_attr(
48735    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48736    assert_instr(nop)
48737)]
48738#[cfg_attr(
48739    not(target_arch = "arm"),
48740    stable(feature = "neon_intrinsics", since = "1.59.0")
48741)]
48742#[cfg_attr(
48743    target_arch = "arm",
48744    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48745)]
48746pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48747    unsafe {
48748        let ret_val: poly16x4_t = transmute(a);
48749        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48750    }
48751}
48752#[doc = "Vector reinterpret cast operation"]
48753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48754#[inline]
48755#[cfg(target_endian = "little")]
48756#[target_feature(enable = "neon")]
48757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48759#[cfg_attr(
48760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48761    assert_instr(nop)
48762)]
48763#[cfg_attr(
48764    not(target_arch = "arm"),
48765    stable(feature = "neon_intrinsics", since = "1.59.0")
48766)]
48767#[cfg_attr(
48768    target_arch = "arm",
48769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48770)]
48771pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48772    unsafe { transmute(a) }
48773}
48774#[doc = "Vector reinterpret cast operation"]
48775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48776#[inline]
48777#[cfg(target_endian = "big")]
48778#[target_feature(enable = "neon")]
48779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48781#[cfg_attr(
48782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48783    assert_instr(nop)
48784)]
48785#[cfg_attr(
48786    not(target_arch = "arm"),
48787    stable(feature = "neon_intrinsics", since = "1.59.0")
48788)]
48789#[cfg_attr(
48790    target_arch = "arm",
48791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48792)]
48793pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48794    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48795    unsafe {
48796        let ret_val: float32x4_t = transmute(a);
48797        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48798    }
48799}
48800#[doc = "Vector reinterpret cast operation"]
48801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48802#[inline]
48803#[cfg(target_endian = "little")]
48804#[target_feature(enable = "neon")]
48805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48807#[cfg_attr(
48808    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48809    assert_instr(nop)
48810)]
48811#[cfg_attr(
48812    not(target_arch = "arm"),
48813    stable(feature = "neon_intrinsics", since = "1.59.0")
48814)]
48815#[cfg_attr(
48816    target_arch = "arm",
48817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48818)]
48819pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48820    unsafe { transmute(a) }
48821}
48822#[doc = "Vector reinterpret cast operation"]
48823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48824#[inline]
48825#[cfg(target_endian = "big")]
48826#[target_feature(enable = "neon")]
48827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48829#[cfg_attr(
48830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48831    assert_instr(nop)
48832)]
48833#[cfg_attr(
48834    not(target_arch = "arm"),
48835    stable(feature = "neon_intrinsics", since = "1.59.0")
48836)]
48837#[cfg_attr(
48838    target_arch = "arm",
48839    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48840)]
48841pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48842    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48843    unsafe {
48844        let ret_val: int8x16_t = transmute(a);
48845        simd_shuffle!(
48846            ret_val,
48847            ret_val,
48848            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48849        )
48850    }
48851}
48852#[doc = "Vector reinterpret cast operation"]
48853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48854#[inline]
48855#[cfg(target_endian = "little")]
48856#[target_feature(enable = "neon")]
48857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48859#[cfg_attr(
48860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48861    assert_instr(nop)
48862)]
48863#[cfg_attr(
48864    not(target_arch = "arm"),
48865    stable(feature = "neon_intrinsics", since = "1.59.0")
48866)]
48867#[cfg_attr(
48868    target_arch = "arm",
48869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48870)]
48871pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48872    unsafe { transmute(a) }
48873}
48874#[doc = "Vector reinterpret cast operation"]
48875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48876#[inline]
48877#[cfg(target_endian = "big")]
48878#[target_feature(enable = "neon")]
48879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48881#[cfg_attr(
48882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48883    assert_instr(nop)
48884)]
48885#[cfg_attr(
48886    not(target_arch = "arm"),
48887    stable(feature = "neon_intrinsics", since = "1.59.0")
48888)]
48889#[cfg_attr(
48890    target_arch = "arm",
48891    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48892)]
48893pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48894    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48895    unsafe {
48896        let ret_val: int16x8_t = transmute(a);
48897        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48898    }
48899}
48900#[doc = "Vector reinterpret cast operation"]
48901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48902#[inline]
48903#[cfg(target_endian = "little")]
48904#[target_feature(enable = "neon")]
48905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48907#[cfg_attr(
48908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48909    assert_instr(nop)
48910)]
48911#[cfg_attr(
48912    not(target_arch = "arm"),
48913    stable(feature = "neon_intrinsics", since = "1.59.0")
48914)]
48915#[cfg_attr(
48916    target_arch = "arm",
48917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48918)]
48919pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48920    unsafe { transmute(a) }
48921}
48922#[doc = "Vector reinterpret cast operation"]
48923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48924#[inline]
48925#[cfg(target_endian = "big")]
48926#[target_feature(enable = "neon")]
48927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48929#[cfg_attr(
48930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48931    assert_instr(nop)
48932)]
48933#[cfg_attr(
48934    not(target_arch = "arm"),
48935    stable(feature = "neon_intrinsics", since = "1.59.0")
48936)]
48937#[cfg_attr(
48938    target_arch = "arm",
48939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48940)]
48941pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48942    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48943    unsafe {
48944        let ret_val: int32x4_t = transmute(a);
48945        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48946    }
48947}
48948#[doc = "Vector reinterpret cast operation"]
48949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48950#[inline]
48951#[cfg(target_endian = "little")]
48952#[target_feature(enable = "neon")]
48953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48955#[cfg_attr(
48956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48957    assert_instr(nop)
48958)]
48959#[cfg_attr(
48960    not(target_arch = "arm"),
48961    stable(feature = "neon_intrinsics", since = "1.59.0")
48962)]
48963#[cfg_attr(
48964    target_arch = "arm",
48965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48966)]
48967pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48968    unsafe { transmute(a) }
48969}
48970#[doc = "Vector reinterpret cast operation"]
48971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48972#[inline]
48973#[cfg(target_endian = "big")]
48974#[target_feature(enable = "neon")]
48975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48977#[cfg_attr(
48978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48979    assert_instr(nop)
48980)]
48981#[cfg_attr(
48982    not(target_arch = "arm"),
48983    stable(feature = "neon_intrinsics", since = "1.59.0")
48984)]
48985#[cfg_attr(
48986    target_arch = "arm",
48987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48988)]
48989pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48990    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48991    unsafe {
48992        let ret_val: uint8x16_t = transmute(a);
48993        simd_shuffle!(
48994            ret_val,
48995            ret_val,
48996            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48997        )
48998    }
48999}
49000#[doc = "Vector reinterpret cast operation"]
49001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
49002#[inline]
49003#[cfg(target_endian = "little")]
49004#[target_feature(enable = "neon")]
49005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49007#[cfg_attr(
49008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49009    assert_instr(nop)
49010)]
49011#[cfg_attr(
49012    not(target_arch = "arm"),
49013    stable(feature = "neon_intrinsics", since = "1.59.0")
49014)]
49015#[cfg_attr(
49016    target_arch = "arm",
49017    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49018)]
49019pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
49020    unsafe { transmute(a) }
49021}
49022#[doc = "Vector reinterpret cast operation"]
49023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
49024#[inline]
49025#[cfg(target_endian = "big")]
49026#[target_feature(enable = "neon")]
49027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49029#[cfg_attr(
49030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49031    assert_instr(nop)
49032)]
49033#[cfg_attr(
49034    not(target_arch = "arm"),
49035    stable(feature = "neon_intrinsics", since = "1.59.0")
49036)]
49037#[cfg_attr(
49038    target_arch = "arm",
49039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49040)]
49041pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
49042    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49043    unsafe {
49044        let ret_val: uint16x8_t = transmute(a);
49045        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49046    }
49047}
49048#[doc = "Vector reinterpret cast operation"]
49049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
49050#[inline]
49051#[cfg(target_endian = "little")]
49052#[target_feature(enable = "neon")]
49053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49055#[cfg_attr(
49056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49057    assert_instr(nop)
49058)]
49059#[cfg_attr(
49060    not(target_arch = "arm"),
49061    stable(feature = "neon_intrinsics", since = "1.59.0")
49062)]
49063#[cfg_attr(
49064    target_arch = "arm",
49065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49066)]
49067pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
49068    unsafe { transmute(a) }
49069}
49070#[doc = "Vector reinterpret cast operation"]
49071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
49072#[inline]
49073#[cfg(target_endian = "big")]
49074#[target_feature(enable = "neon")]
49075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49077#[cfg_attr(
49078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49079    assert_instr(nop)
49080)]
49081#[cfg_attr(
49082    not(target_arch = "arm"),
49083    stable(feature = "neon_intrinsics", since = "1.59.0")
49084)]
49085#[cfg_attr(
49086    target_arch = "arm",
49087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49088)]
49089pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
49090    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49091    unsafe {
49092        let ret_val: uint32x4_t = transmute(a);
49093        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49094    }
49095}
49096#[doc = "Vector reinterpret cast operation"]
49097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49098#[inline]
49099#[cfg(target_endian = "little")]
49100#[target_feature(enable = "neon")]
49101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49103#[cfg_attr(
49104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49105    assert_instr(nop)
49106)]
49107#[cfg_attr(
49108    not(target_arch = "arm"),
49109    stable(feature = "neon_intrinsics", since = "1.59.0")
49110)]
49111#[cfg_attr(
49112    target_arch = "arm",
49113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49114)]
49115pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49116    unsafe { transmute(a) }
49117}
49118#[doc = "Vector reinterpret cast operation"]
49119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49120#[inline]
49121#[cfg(target_endian = "big")]
49122#[target_feature(enable = "neon")]
49123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49125#[cfg_attr(
49126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49127    assert_instr(nop)
49128)]
49129#[cfg_attr(
49130    not(target_arch = "arm"),
49131    stable(feature = "neon_intrinsics", since = "1.59.0")
49132)]
49133#[cfg_attr(
49134    target_arch = "arm",
49135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49136)]
49137pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49138    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49139    unsafe {
49140        let ret_val: uint64x2_t = transmute(a);
49141        simd_shuffle!(ret_val, ret_val, [1, 0])
49142    }
49143}
49144#[doc = "Vector reinterpret cast operation"]
49145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49146#[inline]
49147#[cfg(target_endian = "little")]
49148#[target_feature(enable = "neon")]
49149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49151#[cfg_attr(
49152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49153    assert_instr(nop)
49154)]
49155#[cfg_attr(
49156    not(target_arch = "arm"),
49157    stable(feature = "neon_intrinsics", since = "1.59.0")
49158)]
49159#[cfg_attr(
49160    target_arch = "arm",
49161    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49162)]
49163pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49164    unsafe { transmute(a) }
49165}
49166#[doc = "Vector reinterpret cast operation"]
49167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49168#[inline]
49169#[cfg(target_endian = "big")]
49170#[target_feature(enable = "neon")]
49171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49173#[cfg_attr(
49174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49175    assert_instr(nop)
49176)]
49177#[cfg_attr(
49178    not(target_arch = "arm"),
49179    stable(feature = "neon_intrinsics", since = "1.59.0")
49180)]
49181#[cfg_attr(
49182    target_arch = "arm",
49183    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49184)]
49185pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49186    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49187    unsafe {
49188        let ret_val: poly8x16_t = transmute(a);
49189        simd_shuffle!(
49190            ret_val,
49191            ret_val,
49192            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49193        )
49194    }
49195}
49196#[doc = "Vector reinterpret cast operation"]
49197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49198#[inline]
49199#[cfg(target_endian = "little")]
49200#[target_feature(enable = "neon")]
49201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49203#[cfg_attr(
49204    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49205    assert_instr(nop)
49206)]
49207#[cfg_attr(
49208    not(target_arch = "arm"),
49209    stable(feature = "neon_intrinsics", since = "1.59.0")
49210)]
49211#[cfg_attr(
49212    target_arch = "arm",
49213    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49214)]
49215pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49216    unsafe { transmute(a) }
49217}
49218#[doc = "Vector reinterpret cast operation"]
49219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49220#[inline]
49221#[cfg(target_endian = "big")]
49222#[target_feature(enable = "neon")]
49223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49225#[cfg_attr(
49226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49227    assert_instr(nop)
49228)]
49229#[cfg_attr(
49230    not(target_arch = "arm"),
49231    stable(feature = "neon_intrinsics", since = "1.59.0")
49232)]
49233#[cfg_attr(
49234    target_arch = "arm",
49235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49236)]
49237pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49238    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49239    unsafe {
49240        let ret_val: poly16x8_t = transmute(a);
49241        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49242    }
49243}
49244#[doc = "Vector reinterpret cast operation"]
49245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49246#[inline]
49247#[cfg(target_endian = "little")]
49248#[target_feature(enable = "neon")]
49249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49251#[cfg_attr(
49252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49253    assert_instr(nop)
49254)]
49255#[cfg_attr(
49256    not(target_arch = "arm"),
49257    stable(feature = "neon_intrinsics", since = "1.59.0")
49258)]
49259#[cfg_attr(
49260    target_arch = "arm",
49261    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49262)]
49263pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49264    unsafe { transmute(a) }
49265}
49266#[doc = "Vector reinterpret cast operation"]
49267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49268#[inline]
49269#[cfg(target_endian = "big")]
49270#[target_feature(enable = "neon")]
49271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49273#[cfg_attr(
49274    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49275    assert_instr(nop)
49276)]
49277#[cfg_attr(
49278    not(target_arch = "arm"),
49279    stable(feature = "neon_intrinsics", since = "1.59.0")
49280)]
49281#[cfg_attr(
49282    target_arch = "arm",
49283    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49284)]
49285pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49286    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49287    unsafe {
49288        let ret_val: float32x2_t = transmute(a);
49289        simd_shuffle!(ret_val, ret_val, [1, 0])
49290    }
49291}
49292#[doc = "Vector reinterpret cast operation"]
49293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49294#[inline]
49295#[cfg(target_endian = "little")]
49296#[target_feature(enable = "neon")]
49297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49299#[cfg_attr(
49300    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49301    assert_instr(nop)
49302)]
49303#[cfg_attr(
49304    not(target_arch = "arm"),
49305    stable(feature = "neon_intrinsics", since = "1.59.0")
49306)]
49307#[cfg_attr(
49308    target_arch = "arm",
49309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49310)]
49311pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49312    unsafe { transmute(a) }
49313}
49314#[doc = "Vector reinterpret cast operation"]
49315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49316#[inline]
49317#[cfg(target_endian = "big")]
49318#[target_feature(enable = "neon")]
49319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49321#[cfg_attr(
49322    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49323    assert_instr(nop)
49324)]
49325#[cfg_attr(
49326    not(target_arch = "arm"),
49327    stable(feature = "neon_intrinsics", since = "1.59.0")
49328)]
49329#[cfg_attr(
49330    target_arch = "arm",
49331    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49332)]
49333pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49334    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49335    unsafe {
49336        let ret_val: int8x8_t = transmute(a);
49337        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49338    }
49339}
49340#[doc = "Vector reinterpret cast operation"]
49341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49342#[inline]
49343#[cfg(target_endian = "little")]
49344#[target_feature(enable = "neon")]
49345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49347#[cfg_attr(
49348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49349    assert_instr(nop)
49350)]
49351#[cfg_attr(
49352    not(target_arch = "arm"),
49353    stable(feature = "neon_intrinsics", since = "1.59.0")
49354)]
49355#[cfg_attr(
49356    target_arch = "arm",
49357    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49358)]
49359pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49360    unsafe { transmute(a) }
49361}
49362#[doc = "Vector reinterpret cast operation"]
49363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49364#[inline]
49365#[cfg(target_endian = "big")]
49366#[target_feature(enable = "neon")]
49367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49369#[cfg_attr(
49370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49371    assert_instr(nop)
49372)]
49373#[cfg_attr(
49374    not(target_arch = "arm"),
49375    stable(feature = "neon_intrinsics", since = "1.59.0")
49376)]
49377#[cfg_attr(
49378    target_arch = "arm",
49379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49380)]
49381pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49382    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49383    unsafe {
49384        let ret_val: int16x4_t = transmute(a);
49385        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49386    }
49387}
49388#[doc = "Vector reinterpret cast operation"]
49389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49390#[inline]
49391#[cfg(target_endian = "little")]
49392#[target_feature(enable = "neon")]
49393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49395#[cfg_attr(
49396    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49397    assert_instr(nop)
49398)]
49399#[cfg_attr(
49400    not(target_arch = "arm"),
49401    stable(feature = "neon_intrinsics", since = "1.59.0")
49402)]
49403#[cfg_attr(
49404    target_arch = "arm",
49405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49406)]
49407pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49408    unsafe { transmute(a) }
49409}
49410#[doc = "Vector reinterpret cast operation"]
49411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49412#[inline]
49413#[cfg(target_endian = "big")]
49414#[target_feature(enable = "neon")]
49415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49417#[cfg_attr(
49418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49419    assert_instr(nop)
49420)]
49421#[cfg_attr(
49422    not(target_arch = "arm"),
49423    stable(feature = "neon_intrinsics", since = "1.59.0")
49424)]
49425#[cfg_attr(
49426    target_arch = "arm",
49427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49428)]
49429pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49430    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49431    unsafe {
49432        let ret_val: int32x2_t = transmute(a);
49433        simd_shuffle!(ret_val, ret_val, [1, 0])
49434    }
49435}
49436#[doc = "Vector reinterpret cast operation"]
49437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49438#[inline]
49439#[cfg(target_endian = "little")]
49440#[target_feature(enable = "neon")]
49441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49443#[cfg_attr(
49444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49445    assert_instr(nop)
49446)]
49447#[cfg_attr(
49448    not(target_arch = "arm"),
49449    stable(feature = "neon_intrinsics", since = "1.59.0")
49450)]
49451#[cfg_attr(
49452    target_arch = "arm",
49453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49454)]
49455pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49456    unsafe { transmute(a) }
49457}
49458#[doc = "Vector reinterpret cast operation"]
49459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49460#[inline]
49461#[cfg(target_endian = "big")]
49462#[target_feature(enable = "neon")]
49463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49465#[cfg_attr(
49466    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49467    assert_instr(nop)
49468)]
49469#[cfg_attr(
49470    not(target_arch = "arm"),
49471    stable(feature = "neon_intrinsics", since = "1.59.0")
49472)]
49473#[cfg_attr(
49474    target_arch = "arm",
49475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49476)]
49477pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49478    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49479    unsafe { transmute(a) }
49480}
49481#[doc = "Vector reinterpret cast operation"]
49482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49483#[inline]
49484#[cfg(target_endian = "little")]
49485#[target_feature(enable = "neon")]
49486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49488#[cfg_attr(
49489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49490    assert_instr(nop)
49491)]
49492#[cfg_attr(
49493    not(target_arch = "arm"),
49494    stable(feature = "neon_intrinsics", since = "1.59.0")
49495)]
49496#[cfg_attr(
49497    target_arch = "arm",
49498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49499)]
49500pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49501    unsafe { transmute(a) }
49502}
49503#[doc = "Vector reinterpret cast operation"]
49504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49505#[inline]
49506#[cfg(target_endian = "big")]
49507#[target_feature(enable = "neon")]
49508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49510#[cfg_attr(
49511    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49512    assert_instr(nop)
49513)]
49514#[cfg_attr(
49515    not(target_arch = "arm"),
49516    stable(feature = "neon_intrinsics", since = "1.59.0")
49517)]
49518#[cfg_attr(
49519    target_arch = "arm",
49520    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49521)]
49522pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49523    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49524    unsafe {
49525        let ret_val: uint16x4_t = transmute(a);
49526        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49527    }
49528}
49529#[doc = "Vector reinterpret cast operation"]
49530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49531#[inline]
49532#[cfg(target_endian = "little")]
49533#[target_feature(enable = "neon")]
49534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49536#[cfg_attr(
49537    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49538    assert_instr(nop)
49539)]
49540#[cfg_attr(
49541    not(target_arch = "arm"),
49542    stable(feature = "neon_intrinsics", since = "1.59.0")
49543)]
49544#[cfg_attr(
49545    target_arch = "arm",
49546    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49547)]
49548pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49549    unsafe { transmute(a) }
49550}
49551#[doc = "Vector reinterpret cast operation"]
49552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49553#[inline]
49554#[cfg(target_endian = "big")]
49555#[target_feature(enable = "neon")]
49556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49558#[cfg_attr(
49559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49560    assert_instr(nop)
49561)]
49562#[cfg_attr(
49563    not(target_arch = "arm"),
49564    stable(feature = "neon_intrinsics", since = "1.59.0")
49565)]
49566#[cfg_attr(
49567    target_arch = "arm",
49568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49569)]
49570pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49571    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49572    unsafe {
49573        let ret_val: uint32x2_t = transmute(a);
49574        simd_shuffle!(ret_val, ret_val, [1, 0])
49575    }
49576}
49577#[doc = "Vector reinterpret cast operation"]
49578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49579#[inline]
49580#[cfg(target_endian = "little")]
49581#[target_feature(enable = "neon")]
49582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49584#[cfg_attr(
49585    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49586    assert_instr(nop)
49587)]
49588#[cfg_attr(
49589    not(target_arch = "arm"),
49590    stable(feature = "neon_intrinsics", since = "1.59.0")
49591)]
49592#[cfg_attr(
49593    target_arch = "arm",
49594    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49595)]
49596pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49597    unsafe { transmute(a) }
49598}
49599#[doc = "Vector reinterpret cast operation"]
49600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49601#[inline]
49602#[cfg(target_endian = "big")]
49603#[target_feature(enable = "neon")]
49604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49606#[cfg_attr(
49607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49608    assert_instr(nop)
49609)]
49610#[cfg_attr(
49611    not(target_arch = "arm"),
49612    stable(feature = "neon_intrinsics", since = "1.59.0")
49613)]
49614#[cfg_attr(
49615    target_arch = "arm",
49616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49617)]
49618pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49619    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49620    unsafe { transmute(a) }
49621}
49622#[doc = "Vector reinterpret cast operation"]
49623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49624#[inline]
49625#[cfg(target_endian = "little")]
49626#[target_feature(enable = "neon")]
49627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49629#[cfg_attr(
49630    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49631    assert_instr(nop)
49632)]
49633#[cfg_attr(
49634    not(target_arch = "arm"),
49635    stable(feature = "neon_intrinsics", since = "1.59.0")
49636)]
49637#[cfg_attr(
49638    target_arch = "arm",
49639    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49640)]
49641pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49642    unsafe { transmute(a) }
49643}
49644#[doc = "Vector reinterpret cast operation"]
49645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49646#[inline]
49647#[cfg(target_endian = "big")]
49648#[target_feature(enable = "neon")]
49649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49651#[cfg_attr(
49652    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49653    assert_instr(nop)
49654)]
49655#[cfg_attr(
49656    not(target_arch = "arm"),
49657    stable(feature = "neon_intrinsics", since = "1.59.0")
49658)]
49659#[cfg_attr(
49660    target_arch = "arm",
49661    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49662)]
49663pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49664    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49665    unsafe {
49666        let ret_val: poly8x8_t = transmute(a);
49667        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49668    }
49669}
49670#[doc = "Vector reinterpret cast operation"]
49671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49672#[inline]
49673#[cfg(target_endian = "little")]
49674#[target_feature(enable = "neon")]
49675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49677#[cfg_attr(
49678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49679    assert_instr(nop)
49680)]
49681#[cfg_attr(
49682    not(target_arch = "arm"),
49683    stable(feature = "neon_intrinsics", since = "1.59.0")
49684)]
49685#[cfg_attr(
49686    target_arch = "arm",
49687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49688)]
49689pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49690    unsafe { transmute(a) }
49691}
49692#[doc = "Vector reinterpret cast operation"]
49693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49694#[inline]
49695#[cfg(target_endian = "big")]
49696#[target_feature(enable = "neon")]
49697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49699#[cfg_attr(
49700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49701    assert_instr(nop)
49702)]
49703#[cfg_attr(
49704    not(target_arch = "arm"),
49705    stable(feature = "neon_intrinsics", since = "1.59.0")
49706)]
49707#[cfg_attr(
49708    target_arch = "arm",
49709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49710)]
49711pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49712    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49713    unsafe {
49714        let ret_val: poly16x4_t = transmute(a);
49715        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49716    }
49717}
49718#[doc = "Vector reinterpret cast operation"]
49719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49720#[inline]
49721#[cfg(target_endian = "little")]
49722#[target_feature(enable = "neon")]
49723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49725#[cfg_attr(
49726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49727    assert_instr(nop)
49728)]
49729#[cfg_attr(
49730    not(target_arch = "arm"),
49731    stable(feature = "neon_intrinsics", since = "1.59.0")
49732)]
49733#[cfg_attr(
49734    target_arch = "arm",
49735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49736)]
49737pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49738    unsafe { transmute(a) }
49739}
49740#[doc = "Vector reinterpret cast operation"]
49741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49742#[inline]
49743#[cfg(target_endian = "big")]
49744#[target_feature(enable = "neon")]
49745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49747#[cfg_attr(
49748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49749    assert_instr(nop)
49750)]
49751#[cfg_attr(
49752    not(target_arch = "arm"),
49753    stable(feature = "neon_intrinsics", since = "1.59.0")
49754)]
49755#[cfg_attr(
49756    target_arch = "arm",
49757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49758)]
49759pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49760    let a: uint8x16_t =
49761        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49762    unsafe {
49763        let ret_val: float32x4_t = transmute(a);
49764        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49765    }
49766}
49767#[doc = "Vector reinterpret cast operation"]
49768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49769#[inline]
49770#[cfg(target_endian = "little")]
49771#[target_feature(enable = "neon")]
49772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49774#[cfg_attr(
49775    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49776    assert_instr(nop)
49777)]
49778#[cfg_attr(
49779    not(target_arch = "arm"),
49780    stable(feature = "neon_intrinsics", since = "1.59.0")
49781)]
49782#[cfg_attr(
49783    target_arch = "arm",
49784    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49785)]
49786pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49787    unsafe { transmute(a) }
49788}
49789#[doc = "Vector reinterpret cast operation"]
49790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49791#[inline]
49792#[cfg(target_endian = "big")]
49793#[target_feature(enable = "neon")]
49794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49796#[cfg_attr(
49797    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49798    assert_instr(nop)
49799)]
49800#[cfg_attr(
49801    not(target_arch = "arm"),
49802    stable(feature = "neon_intrinsics", since = "1.59.0")
49803)]
49804#[cfg_attr(
49805    target_arch = "arm",
49806    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49807)]
49808pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49809    let a: uint8x16_t =
49810        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49811    unsafe {
49812        let ret_val: int8x16_t = transmute(a);
49813        simd_shuffle!(
49814            ret_val,
49815            ret_val,
49816            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49817        )
49818    }
49819}
49820#[doc = "Vector reinterpret cast operation"]
49821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49822#[inline]
49823#[cfg(target_endian = "little")]
49824#[target_feature(enable = "neon")]
49825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49827#[cfg_attr(
49828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49829    assert_instr(nop)
49830)]
49831#[cfg_attr(
49832    not(target_arch = "arm"),
49833    stable(feature = "neon_intrinsics", since = "1.59.0")
49834)]
49835#[cfg_attr(
49836    target_arch = "arm",
49837    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49838)]
49839pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49840    unsafe { transmute(a) }
49841}
49842#[doc = "Vector reinterpret cast operation"]
49843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49844#[inline]
49845#[cfg(target_endian = "big")]
49846#[target_feature(enable = "neon")]
49847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49849#[cfg_attr(
49850    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49851    assert_instr(nop)
49852)]
49853#[cfg_attr(
49854    not(target_arch = "arm"),
49855    stable(feature = "neon_intrinsics", since = "1.59.0")
49856)]
49857#[cfg_attr(
49858    target_arch = "arm",
49859    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49860)]
49861pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49862    let a: uint8x16_t =
49863        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49864    unsafe {
49865        let ret_val: int16x8_t = transmute(a);
49866        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49867    }
49868}
49869#[doc = "Vector reinterpret cast operation"]
49870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49871#[inline]
49872#[cfg(target_endian = "little")]
49873#[target_feature(enable = "neon")]
49874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49875#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49876#[cfg_attr(
49877    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49878    assert_instr(nop)
49879)]
49880#[cfg_attr(
49881    not(target_arch = "arm"),
49882    stable(feature = "neon_intrinsics", since = "1.59.0")
49883)]
49884#[cfg_attr(
49885    target_arch = "arm",
49886    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49887)]
49888pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49889    unsafe { transmute(a) }
49890}
49891#[doc = "Vector reinterpret cast operation"]
49892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49893#[inline]
49894#[cfg(target_endian = "big")]
49895#[target_feature(enable = "neon")]
49896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49898#[cfg_attr(
49899    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49900    assert_instr(nop)
49901)]
49902#[cfg_attr(
49903    not(target_arch = "arm"),
49904    stable(feature = "neon_intrinsics", since = "1.59.0")
49905)]
49906#[cfg_attr(
49907    target_arch = "arm",
49908    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49909)]
49910pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49911    let a: uint8x16_t =
49912        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49913    unsafe {
49914        let ret_val: int32x4_t = transmute(a);
49915        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49916    }
49917}
49918#[doc = "Vector reinterpret cast operation"]
49919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49920#[inline]
49921#[cfg(target_endian = "little")]
49922#[target_feature(enable = "neon")]
49923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49925#[cfg_attr(
49926    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49927    assert_instr(nop)
49928)]
49929#[cfg_attr(
49930    not(target_arch = "arm"),
49931    stable(feature = "neon_intrinsics", since = "1.59.0")
49932)]
49933#[cfg_attr(
49934    target_arch = "arm",
49935    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49936)]
49937pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49938    unsafe { transmute(a) }
49939}
49940#[doc = "Vector reinterpret cast operation"]
49941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49942#[inline]
49943#[cfg(target_endian = "big")]
49944#[target_feature(enable = "neon")]
49945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49947#[cfg_attr(
49948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49949    assert_instr(nop)
49950)]
49951#[cfg_attr(
49952    not(target_arch = "arm"),
49953    stable(feature = "neon_intrinsics", since = "1.59.0")
49954)]
49955#[cfg_attr(
49956    target_arch = "arm",
49957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49958)]
49959pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49960    let a: uint8x16_t =
49961        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49962    unsafe {
49963        let ret_val: int64x2_t = transmute(a);
49964        simd_shuffle!(ret_val, ret_val, [1, 0])
49965    }
49966}
49967#[doc = "Vector reinterpret cast operation"]
49968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49969#[inline]
49970#[cfg(target_endian = "little")]
49971#[target_feature(enable = "neon")]
49972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49974#[cfg_attr(
49975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49976    assert_instr(nop)
49977)]
49978#[cfg_attr(
49979    not(target_arch = "arm"),
49980    stable(feature = "neon_intrinsics", since = "1.59.0")
49981)]
49982#[cfg_attr(
49983    target_arch = "arm",
49984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49985)]
49986pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49987    unsafe { transmute(a) }
49988}
49989#[doc = "Vector reinterpret cast operation"]
49990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49991#[inline]
49992#[cfg(target_endian = "big")]
49993#[target_feature(enable = "neon")]
49994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49996#[cfg_attr(
49997    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49998    assert_instr(nop)
49999)]
50000#[cfg_attr(
50001    not(target_arch = "arm"),
50002    stable(feature = "neon_intrinsics", since = "1.59.0")
50003)]
50004#[cfg_attr(
50005    target_arch = "arm",
50006    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50007)]
50008pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
50009    let a: uint8x16_t =
50010        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50011    unsafe {
50012        let ret_val: uint16x8_t = transmute(a);
50013        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50014    }
50015}
50016#[doc = "Vector reinterpret cast operation"]
50017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
50018#[inline]
50019#[cfg(target_endian = "little")]
50020#[target_feature(enable = "neon")]
50021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50023#[cfg_attr(
50024    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50025    assert_instr(nop)
50026)]
50027#[cfg_attr(
50028    not(target_arch = "arm"),
50029    stable(feature = "neon_intrinsics", since = "1.59.0")
50030)]
50031#[cfg_attr(
50032    target_arch = "arm",
50033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50034)]
50035pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
50036    unsafe { transmute(a) }
50037}
50038#[doc = "Vector reinterpret cast operation"]
50039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
50040#[inline]
50041#[cfg(target_endian = "big")]
50042#[target_feature(enable = "neon")]
50043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50045#[cfg_attr(
50046    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50047    assert_instr(nop)
50048)]
50049#[cfg_attr(
50050    not(target_arch = "arm"),
50051    stable(feature = "neon_intrinsics", since = "1.59.0")
50052)]
50053#[cfg_attr(
50054    target_arch = "arm",
50055    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50056)]
50057pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
50058    let a: uint8x16_t =
50059        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50060    unsafe {
50061        let ret_val: uint32x4_t = transmute(a);
50062        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50063    }
50064}
50065#[doc = "Vector reinterpret cast operation"]
50066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
50067#[inline]
50068#[cfg(target_endian = "little")]
50069#[target_feature(enable = "neon")]
50070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50072#[cfg_attr(
50073    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50074    assert_instr(nop)
50075)]
50076#[cfg_attr(
50077    not(target_arch = "arm"),
50078    stable(feature = "neon_intrinsics", since = "1.59.0")
50079)]
50080#[cfg_attr(
50081    target_arch = "arm",
50082    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50083)]
50084pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
50085    unsafe { transmute(a) }
50086}
50087#[doc = "Vector reinterpret cast operation"]
50088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
50089#[inline]
50090#[cfg(target_endian = "big")]
50091#[target_feature(enable = "neon")]
50092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50094#[cfg_attr(
50095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50096    assert_instr(nop)
50097)]
50098#[cfg_attr(
50099    not(target_arch = "arm"),
50100    stable(feature = "neon_intrinsics", since = "1.59.0")
50101)]
50102#[cfg_attr(
50103    target_arch = "arm",
50104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50105)]
50106pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
50107    let a: uint8x16_t =
50108        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50109    unsafe {
50110        let ret_val: uint64x2_t = transmute(a);
50111        simd_shuffle!(ret_val, ret_val, [1, 0])
50112    }
50113}
50114#[doc = "Vector reinterpret cast operation"]
50115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50116#[inline]
50117#[cfg(target_endian = "little")]
50118#[target_feature(enable = "neon")]
50119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50121#[cfg_attr(
50122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50123    assert_instr(nop)
50124)]
50125#[cfg_attr(
50126    not(target_arch = "arm"),
50127    stable(feature = "neon_intrinsics", since = "1.59.0")
50128)]
50129#[cfg_attr(
50130    target_arch = "arm",
50131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50132)]
50133pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50134    unsafe { transmute(a) }
50135}
50136#[doc = "Vector reinterpret cast operation"]
50137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50138#[inline]
50139#[cfg(target_endian = "big")]
50140#[target_feature(enable = "neon")]
50141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50143#[cfg_attr(
50144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50145    assert_instr(nop)
50146)]
50147#[cfg_attr(
50148    not(target_arch = "arm"),
50149    stable(feature = "neon_intrinsics", since = "1.59.0")
50150)]
50151#[cfg_attr(
50152    target_arch = "arm",
50153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50154)]
50155pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50156    let a: uint8x16_t =
50157        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50158    unsafe {
50159        let ret_val: poly8x16_t = transmute(a);
50160        simd_shuffle!(
50161            ret_val,
50162            ret_val,
50163            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50164        )
50165    }
50166}
50167#[doc = "Vector reinterpret cast operation"]
50168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50169#[inline]
50170#[cfg(target_endian = "little")]
50171#[target_feature(enable = "neon")]
50172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50174#[cfg_attr(
50175    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50176    assert_instr(nop)
50177)]
50178#[cfg_attr(
50179    not(target_arch = "arm"),
50180    stable(feature = "neon_intrinsics", since = "1.59.0")
50181)]
50182#[cfg_attr(
50183    target_arch = "arm",
50184    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50185)]
50186pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50187    unsafe { transmute(a) }
50188}
50189#[doc = "Vector reinterpret cast operation"]
50190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50191#[inline]
50192#[cfg(target_endian = "big")]
50193#[target_feature(enable = "neon")]
50194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50196#[cfg_attr(
50197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50198    assert_instr(nop)
50199)]
50200#[cfg_attr(
50201    not(target_arch = "arm"),
50202    stable(feature = "neon_intrinsics", since = "1.59.0")
50203)]
50204#[cfg_attr(
50205    target_arch = "arm",
50206    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50207)]
50208pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50209    let a: uint8x16_t =
50210        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50211    unsafe {
50212        let ret_val: poly16x8_t = transmute(a);
50213        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50214    }
50215}
50216#[doc = "Vector reinterpret cast operation"]
50217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50218#[inline]
50219#[cfg(target_endian = "little")]
50220#[target_feature(enable = "neon")]
50221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50223#[cfg_attr(
50224    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50225    assert_instr(nop)
50226)]
50227#[cfg_attr(
50228    not(target_arch = "arm"),
50229    stable(feature = "neon_intrinsics", since = "1.59.0")
50230)]
50231#[cfg_attr(
50232    target_arch = "arm",
50233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50234)]
50235pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50236    unsafe { transmute(a) }
50237}
50238#[doc = "Vector reinterpret cast operation"]
50239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50240#[inline]
50241#[cfg(target_endian = "big")]
50242#[target_feature(enable = "neon")]
50243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50244#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50245#[cfg_attr(
50246    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50247    assert_instr(nop)
50248)]
50249#[cfg_attr(
50250    not(target_arch = "arm"),
50251    stable(feature = "neon_intrinsics", since = "1.59.0")
50252)]
50253#[cfg_attr(
50254    target_arch = "arm",
50255    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50256)]
50257pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50258    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50259    unsafe {
50260        let ret_val: float32x2_t = transmute(a);
50261        simd_shuffle!(ret_val, ret_val, [1, 0])
50262    }
50263}
50264#[doc = "Vector reinterpret cast operation"]
50265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50266#[inline]
50267#[cfg(target_endian = "little")]
50268#[target_feature(enable = "neon")]
50269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50271#[cfg_attr(
50272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50273    assert_instr(nop)
50274)]
50275#[cfg_attr(
50276    not(target_arch = "arm"),
50277    stable(feature = "neon_intrinsics", since = "1.59.0")
50278)]
50279#[cfg_attr(
50280    target_arch = "arm",
50281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50282)]
50283pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50284    unsafe { transmute(a) }
50285}
50286#[doc = "Vector reinterpret cast operation"]
50287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50288#[inline]
50289#[cfg(target_endian = "big")]
50290#[target_feature(enable = "neon")]
50291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50293#[cfg_attr(
50294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50295    assert_instr(nop)
50296)]
50297#[cfg_attr(
50298    not(target_arch = "arm"),
50299    stable(feature = "neon_intrinsics", since = "1.59.0")
50300)]
50301#[cfg_attr(
50302    target_arch = "arm",
50303    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50304)]
50305pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50306    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50307    unsafe {
50308        let ret_val: int8x8_t = transmute(a);
50309        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50310    }
50311}
50312#[doc = "Vector reinterpret cast operation"]
50313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50314#[inline]
50315#[cfg(target_endian = "little")]
50316#[target_feature(enable = "neon")]
50317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50319#[cfg_attr(
50320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50321    assert_instr(nop)
50322)]
50323#[cfg_attr(
50324    not(target_arch = "arm"),
50325    stable(feature = "neon_intrinsics", since = "1.59.0")
50326)]
50327#[cfg_attr(
50328    target_arch = "arm",
50329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50330)]
50331pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50332    unsafe { transmute(a) }
50333}
50334#[doc = "Vector reinterpret cast operation"]
50335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50336#[inline]
50337#[cfg(target_endian = "big")]
50338#[target_feature(enable = "neon")]
50339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50341#[cfg_attr(
50342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50343    assert_instr(nop)
50344)]
50345#[cfg_attr(
50346    not(target_arch = "arm"),
50347    stable(feature = "neon_intrinsics", since = "1.59.0")
50348)]
50349#[cfg_attr(
50350    target_arch = "arm",
50351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50352)]
50353pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50354    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50355    unsafe {
50356        let ret_val: int16x4_t = transmute(a);
50357        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50358    }
50359}
50360#[doc = "Vector reinterpret cast operation"]
50361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50362#[inline]
50363#[cfg(target_endian = "little")]
50364#[target_feature(enable = "neon")]
50365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50367#[cfg_attr(
50368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50369    assert_instr(nop)
50370)]
50371#[cfg_attr(
50372    not(target_arch = "arm"),
50373    stable(feature = "neon_intrinsics", since = "1.59.0")
50374)]
50375#[cfg_attr(
50376    target_arch = "arm",
50377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50378)]
50379pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50380    unsafe { transmute(a) }
50381}
50382#[doc = "Vector reinterpret cast operation"]
50383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50384#[inline]
50385#[cfg(target_endian = "big")]
50386#[target_feature(enable = "neon")]
50387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50389#[cfg_attr(
50390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50391    assert_instr(nop)
50392)]
50393#[cfg_attr(
50394    not(target_arch = "arm"),
50395    stable(feature = "neon_intrinsics", since = "1.59.0")
50396)]
50397#[cfg_attr(
50398    target_arch = "arm",
50399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50400)]
50401pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50402    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50403    unsafe {
50404        let ret_val: int32x2_t = transmute(a);
50405        simd_shuffle!(ret_val, ret_val, [1, 0])
50406    }
50407}
50408#[doc = "Vector reinterpret cast operation"]
50409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50410#[inline]
50411#[cfg(target_endian = "little")]
50412#[target_feature(enable = "neon")]
50413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50415#[cfg_attr(
50416    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50417    assert_instr(nop)
50418)]
50419#[cfg_attr(
50420    not(target_arch = "arm"),
50421    stable(feature = "neon_intrinsics", since = "1.59.0")
50422)]
50423#[cfg_attr(
50424    target_arch = "arm",
50425    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50426)]
50427pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50428    unsafe { transmute(a) }
50429}
50430#[doc = "Vector reinterpret cast operation"]
50431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50432#[inline]
50433#[cfg(target_endian = "big")]
50434#[target_feature(enable = "neon")]
50435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50437#[cfg_attr(
50438    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50439    assert_instr(nop)
50440)]
50441#[cfg_attr(
50442    not(target_arch = "arm"),
50443    stable(feature = "neon_intrinsics", since = "1.59.0")
50444)]
50445#[cfg_attr(
50446    target_arch = "arm",
50447    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50448)]
50449pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50450    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50451    unsafe { transmute(a) }
50452}
50453#[doc = "Vector reinterpret cast operation"]
50454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50455#[inline]
50456#[cfg(target_endian = "little")]
50457#[target_feature(enable = "neon")]
50458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50460#[cfg_attr(
50461    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50462    assert_instr(nop)
50463)]
50464#[cfg_attr(
50465    not(target_arch = "arm"),
50466    stable(feature = "neon_intrinsics", since = "1.59.0")
50467)]
50468#[cfg_attr(
50469    target_arch = "arm",
50470    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50471)]
50472pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50473    unsafe { transmute(a) }
50474}
50475#[doc = "Vector reinterpret cast operation"]
50476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50477#[inline]
50478#[cfg(target_endian = "big")]
50479#[target_feature(enable = "neon")]
50480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50482#[cfg_attr(
50483    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50484    assert_instr(nop)
50485)]
50486#[cfg_attr(
50487    not(target_arch = "arm"),
50488    stable(feature = "neon_intrinsics", since = "1.59.0")
50489)]
50490#[cfg_attr(
50491    target_arch = "arm",
50492    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50493)]
50494pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50495    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50496    unsafe {
50497        let ret_val: uint8x8_t = transmute(a);
50498        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50499    }
50500}
50501#[doc = "Vector reinterpret cast operation"]
50502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50503#[inline]
50504#[cfg(target_endian = "little")]
50505#[target_feature(enable = "neon")]
50506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50508#[cfg_attr(
50509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50510    assert_instr(nop)
50511)]
50512#[cfg_attr(
50513    not(target_arch = "arm"),
50514    stable(feature = "neon_intrinsics", since = "1.59.0")
50515)]
50516#[cfg_attr(
50517    target_arch = "arm",
50518    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50519)]
50520pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50521    unsafe { transmute(a) }
50522}
50523#[doc = "Vector reinterpret cast operation"]
50524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50525#[inline]
50526#[cfg(target_endian = "big")]
50527#[target_feature(enable = "neon")]
50528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50530#[cfg_attr(
50531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50532    assert_instr(nop)
50533)]
50534#[cfg_attr(
50535    not(target_arch = "arm"),
50536    stable(feature = "neon_intrinsics", since = "1.59.0")
50537)]
50538#[cfg_attr(
50539    target_arch = "arm",
50540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50541)]
50542pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50543    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50544    unsafe {
50545        let ret_val: uint32x2_t = transmute(a);
50546        simd_shuffle!(ret_val, ret_val, [1, 0])
50547    }
50548}
50549#[doc = "Vector reinterpret cast operation"]
50550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50551#[inline]
50552#[cfg(target_endian = "little")]
50553#[target_feature(enable = "neon")]
50554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50556#[cfg_attr(
50557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50558    assert_instr(nop)
50559)]
50560#[cfg_attr(
50561    not(target_arch = "arm"),
50562    stable(feature = "neon_intrinsics", since = "1.59.0")
50563)]
50564#[cfg_attr(
50565    target_arch = "arm",
50566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50567)]
50568pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50569    unsafe { transmute(a) }
50570}
50571#[doc = "Vector reinterpret cast operation"]
50572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50573#[inline]
50574#[cfg(target_endian = "big")]
50575#[target_feature(enable = "neon")]
50576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50578#[cfg_attr(
50579    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50580    assert_instr(nop)
50581)]
50582#[cfg_attr(
50583    not(target_arch = "arm"),
50584    stable(feature = "neon_intrinsics", since = "1.59.0")
50585)]
50586#[cfg_attr(
50587    target_arch = "arm",
50588    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50589)]
50590pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50591    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50592    unsafe { transmute(a) }
50593}
50594#[doc = "Vector reinterpret cast operation"]
50595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50596#[inline]
50597#[cfg(target_endian = "little")]
50598#[target_feature(enable = "neon")]
50599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50601#[cfg_attr(
50602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50603    assert_instr(nop)
50604)]
50605#[cfg_attr(
50606    not(target_arch = "arm"),
50607    stable(feature = "neon_intrinsics", since = "1.59.0")
50608)]
50609#[cfg_attr(
50610    target_arch = "arm",
50611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50612)]
50613pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50614    unsafe { transmute(a) }
50615}
50616#[doc = "Vector reinterpret cast operation"]
50617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50618#[inline]
50619#[cfg(target_endian = "big")]
50620#[target_feature(enable = "neon")]
50621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50623#[cfg_attr(
50624    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50625    assert_instr(nop)
50626)]
50627#[cfg_attr(
50628    not(target_arch = "arm"),
50629    stable(feature = "neon_intrinsics", since = "1.59.0")
50630)]
50631#[cfg_attr(
50632    target_arch = "arm",
50633    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50634)]
50635pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50636    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50637    unsafe {
50638        let ret_val: poly8x8_t = transmute(a);
50639        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50640    }
50641}
50642#[doc = "Vector reinterpret cast operation"]
50643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50644#[inline]
50645#[cfg(target_endian = "little")]
50646#[target_feature(enable = "neon")]
50647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50649#[cfg_attr(
50650    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50651    assert_instr(nop)
50652)]
50653#[cfg_attr(
50654    not(target_arch = "arm"),
50655    stable(feature = "neon_intrinsics", since = "1.59.0")
50656)]
50657#[cfg_attr(
50658    target_arch = "arm",
50659    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50660)]
50661pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50662    unsafe { transmute(a) }
50663}
50664#[doc = "Vector reinterpret cast operation"]
50665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50666#[inline]
50667#[cfg(target_endian = "big")]
50668#[target_feature(enable = "neon")]
50669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50671#[cfg_attr(
50672    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50673    assert_instr(nop)
50674)]
50675#[cfg_attr(
50676    not(target_arch = "arm"),
50677    stable(feature = "neon_intrinsics", since = "1.59.0")
50678)]
50679#[cfg_attr(
50680    target_arch = "arm",
50681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50682)]
50683pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50684    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50685    unsafe {
50686        let ret_val: poly16x4_t = transmute(a);
50687        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50688    }
50689}
50690#[doc = "Vector reinterpret cast operation"]
50691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50692#[inline]
50693#[cfg(target_endian = "little")]
50694#[target_feature(enable = "neon")]
50695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50697#[cfg_attr(
50698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50699    assert_instr(nop)
50700)]
50701#[cfg_attr(
50702    not(target_arch = "arm"),
50703    stable(feature = "neon_intrinsics", since = "1.59.0")
50704)]
50705#[cfg_attr(
50706    target_arch = "arm",
50707    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50708)]
50709pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50710    unsafe { transmute(a) }
50711}
50712#[doc = "Vector reinterpret cast operation"]
50713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50714#[inline]
50715#[cfg(target_endian = "big")]
50716#[target_feature(enable = "neon")]
50717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50719#[cfg_attr(
50720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50721    assert_instr(nop)
50722)]
50723#[cfg_attr(
50724    not(target_arch = "arm"),
50725    stable(feature = "neon_intrinsics", since = "1.59.0")
50726)]
50727#[cfg_attr(
50728    target_arch = "arm",
50729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50730)]
50731pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50732    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50733    unsafe {
50734        let ret_val: float32x4_t = transmute(a);
50735        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50736    }
50737}
50738#[doc = "Vector reinterpret cast operation"]
50739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50740#[inline]
50741#[cfg(target_endian = "little")]
50742#[target_feature(enable = "neon")]
50743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50745#[cfg_attr(
50746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50747    assert_instr(nop)
50748)]
50749#[cfg_attr(
50750    not(target_arch = "arm"),
50751    stable(feature = "neon_intrinsics", since = "1.59.0")
50752)]
50753#[cfg_attr(
50754    target_arch = "arm",
50755    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50756)]
50757pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50758    unsafe { transmute(a) }
50759}
50760#[doc = "Vector reinterpret cast operation"]
50761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50762#[inline]
50763#[cfg(target_endian = "big")]
50764#[target_feature(enable = "neon")]
50765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50767#[cfg_attr(
50768    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50769    assert_instr(nop)
50770)]
50771#[cfg_attr(
50772    not(target_arch = "arm"),
50773    stable(feature = "neon_intrinsics", since = "1.59.0")
50774)]
50775#[cfg_attr(
50776    target_arch = "arm",
50777    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50778)]
50779pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50780    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50781    unsafe {
50782        let ret_val: int8x16_t = transmute(a);
50783        simd_shuffle!(
50784            ret_val,
50785            ret_val,
50786            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50787        )
50788    }
50789}
50790#[doc = "Vector reinterpret cast operation"]
50791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50792#[inline]
50793#[cfg(target_endian = "little")]
50794#[target_feature(enable = "neon")]
50795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50797#[cfg_attr(
50798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50799    assert_instr(nop)
50800)]
50801#[cfg_attr(
50802    not(target_arch = "arm"),
50803    stable(feature = "neon_intrinsics", since = "1.59.0")
50804)]
50805#[cfg_attr(
50806    target_arch = "arm",
50807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50808)]
50809pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50810    unsafe { transmute(a) }
50811}
50812#[doc = "Vector reinterpret cast operation"]
50813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50814#[inline]
50815#[cfg(target_endian = "big")]
50816#[target_feature(enable = "neon")]
50817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50819#[cfg_attr(
50820    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50821    assert_instr(nop)
50822)]
50823#[cfg_attr(
50824    not(target_arch = "arm"),
50825    stable(feature = "neon_intrinsics", since = "1.59.0")
50826)]
50827#[cfg_attr(
50828    target_arch = "arm",
50829    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50830)]
50831pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50832    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50833    unsafe {
50834        let ret_val: int16x8_t = transmute(a);
50835        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50836    }
50837}
50838#[doc = "Vector reinterpret cast operation"]
50839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50840#[inline]
50841#[cfg(target_endian = "little")]
50842#[target_feature(enable = "neon")]
50843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50845#[cfg_attr(
50846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50847    assert_instr(nop)
50848)]
50849#[cfg_attr(
50850    not(target_arch = "arm"),
50851    stable(feature = "neon_intrinsics", since = "1.59.0")
50852)]
50853#[cfg_attr(
50854    target_arch = "arm",
50855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50856)]
50857pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50858    unsafe { transmute(a) }
50859}
50860#[doc = "Vector reinterpret cast operation"]
50861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50862#[inline]
50863#[cfg(target_endian = "big")]
50864#[target_feature(enable = "neon")]
50865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50867#[cfg_attr(
50868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50869    assert_instr(nop)
50870)]
50871#[cfg_attr(
50872    not(target_arch = "arm"),
50873    stable(feature = "neon_intrinsics", since = "1.59.0")
50874)]
50875#[cfg_attr(
50876    target_arch = "arm",
50877    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50878)]
50879pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50880    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50881    unsafe {
50882        let ret_val: int32x4_t = transmute(a);
50883        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50884    }
50885}
50886#[doc = "Vector reinterpret cast operation"]
50887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50888#[inline]
50889#[cfg(target_endian = "little")]
50890#[target_feature(enable = "neon")]
50891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50893#[cfg_attr(
50894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50895    assert_instr(nop)
50896)]
50897#[cfg_attr(
50898    not(target_arch = "arm"),
50899    stable(feature = "neon_intrinsics", since = "1.59.0")
50900)]
50901#[cfg_attr(
50902    target_arch = "arm",
50903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50904)]
50905pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50906    unsafe { transmute(a) }
50907}
50908#[doc = "Vector reinterpret cast operation"]
50909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50910#[inline]
50911#[cfg(target_endian = "big")]
50912#[target_feature(enable = "neon")]
50913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50915#[cfg_attr(
50916    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50917    assert_instr(nop)
50918)]
50919#[cfg_attr(
50920    not(target_arch = "arm"),
50921    stable(feature = "neon_intrinsics", since = "1.59.0")
50922)]
50923#[cfg_attr(
50924    target_arch = "arm",
50925    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50926)]
50927pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50928    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50929    unsafe {
50930        let ret_val: int64x2_t = transmute(a);
50931        simd_shuffle!(ret_val, ret_val, [1, 0])
50932    }
50933}
50934#[doc = "Vector reinterpret cast operation"]
50935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50936#[inline]
50937#[cfg(target_endian = "little")]
50938#[target_feature(enable = "neon")]
50939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50941#[cfg_attr(
50942    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50943    assert_instr(nop)
50944)]
50945#[cfg_attr(
50946    not(target_arch = "arm"),
50947    stable(feature = "neon_intrinsics", since = "1.59.0")
50948)]
50949#[cfg_attr(
50950    target_arch = "arm",
50951    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50952)]
50953pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50954    unsafe { transmute(a) }
50955}
50956#[doc = "Vector reinterpret cast operation"]
50957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50958#[inline]
50959#[cfg(target_endian = "big")]
50960#[target_feature(enable = "neon")]
50961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50963#[cfg_attr(
50964    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50965    assert_instr(nop)
50966)]
50967#[cfg_attr(
50968    not(target_arch = "arm"),
50969    stable(feature = "neon_intrinsics", since = "1.59.0")
50970)]
50971#[cfg_attr(
50972    target_arch = "arm",
50973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50974)]
50975pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50976    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50977    unsafe {
50978        let ret_val: uint8x16_t = transmute(a);
50979        simd_shuffle!(
50980            ret_val,
50981            ret_val,
50982            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50983        )
50984    }
50985}
50986#[doc = "Vector reinterpret cast operation"]
50987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50988#[inline]
50989#[cfg(target_endian = "little")]
50990#[target_feature(enable = "neon")]
50991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50993#[cfg_attr(
50994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50995    assert_instr(nop)
50996)]
50997#[cfg_attr(
50998    not(target_arch = "arm"),
50999    stable(feature = "neon_intrinsics", since = "1.59.0")
51000)]
51001#[cfg_attr(
51002    target_arch = "arm",
51003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51004)]
51005pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
51006    unsafe { transmute(a) }
51007}
51008#[doc = "Vector reinterpret cast operation"]
51009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
51010#[inline]
51011#[cfg(target_endian = "big")]
51012#[target_feature(enable = "neon")]
51013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51015#[cfg_attr(
51016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51017    assert_instr(nop)
51018)]
51019#[cfg_attr(
51020    not(target_arch = "arm"),
51021    stable(feature = "neon_intrinsics", since = "1.59.0")
51022)]
51023#[cfg_attr(
51024    target_arch = "arm",
51025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51026)]
51027pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
51028    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51029    unsafe {
51030        let ret_val: uint32x4_t = transmute(a);
51031        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51032    }
51033}
51034#[doc = "Vector reinterpret cast operation"]
51035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
51036#[inline]
51037#[cfg(target_endian = "little")]
51038#[target_feature(enable = "neon")]
51039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51041#[cfg_attr(
51042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51043    assert_instr(nop)
51044)]
51045#[cfg_attr(
51046    not(target_arch = "arm"),
51047    stable(feature = "neon_intrinsics", since = "1.59.0")
51048)]
51049#[cfg_attr(
51050    target_arch = "arm",
51051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51052)]
51053pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
51054    unsafe { transmute(a) }
51055}
51056#[doc = "Vector reinterpret cast operation"]
51057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
51058#[inline]
51059#[cfg(target_endian = "big")]
51060#[target_feature(enable = "neon")]
51061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51063#[cfg_attr(
51064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51065    assert_instr(nop)
51066)]
51067#[cfg_attr(
51068    not(target_arch = "arm"),
51069    stable(feature = "neon_intrinsics", since = "1.59.0")
51070)]
51071#[cfg_attr(
51072    target_arch = "arm",
51073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51074)]
51075pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
51076    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51077    unsafe {
51078        let ret_val: uint64x2_t = transmute(a);
51079        simd_shuffle!(ret_val, ret_val, [1, 0])
51080    }
51081}
51082#[doc = "Vector reinterpret cast operation"]
51083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
51084#[inline]
51085#[cfg(target_endian = "little")]
51086#[target_feature(enable = "neon")]
51087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51089#[cfg_attr(
51090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51091    assert_instr(nop)
51092)]
51093#[cfg_attr(
51094    not(target_arch = "arm"),
51095    stable(feature = "neon_intrinsics", since = "1.59.0")
51096)]
51097#[cfg_attr(
51098    target_arch = "arm",
51099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51100)]
51101pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51102    unsafe { transmute(a) }
51103}
51104#[doc = "Vector reinterpret cast operation"]
51105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
51106#[inline]
51107#[cfg(target_endian = "big")]
51108#[target_feature(enable = "neon")]
51109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51111#[cfg_attr(
51112    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51113    assert_instr(nop)
51114)]
51115#[cfg_attr(
51116    not(target_arch = "arm"),
51117    stable(feature = "neon_intrinsics", since = "1.59.0")
51118)]
51119#[cfg_attr(
51120    target_arch = "arm",
51121    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51122)]
51123pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51124    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51125    unsafe {
51126        let ret_val: poly8x16_t = transmute(a);
51127        simd_shuffle!(
51128            ret_val,
51129            ret_val,
51130            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51131        )
51132    }
51133}
51134#[doc = "Vector reinterpret cast operation"]
51135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51136#[inline]
51137#[cfg(target_endian = "little")]
51138#[target_feature(enable = "neon")]
51139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51141#[cfg_attr(
51142    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51143    assert_instr(nop)
51144)]
51145#[cfg_attr(
51146    not(target_arch = "arm"),
51147    stable(feature = "neon_intrinsics", since = "1.59.0")
51148)]
51149#[cfg_attr(
51150    target_arch = "arm",
51151    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51152)]
51153pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51154    unsafe { transmute(a) }
51155}
51156#[doc = "Vector reinterpret cast operation"]
51157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51158#[inline]
51159#[cfg(target_endian = "big")]
51160#[target_feature(enable = "neon")]
51161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51163#[cfg_attr(
51164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51165    assert_instr(nop)
51166)]
51167#[cfg_attr(
51168    not(target_arch = "arm"),
51169    stable(feature = "neon_intrinsics", since = "1.59.0")
51170)]
51171#[cfg_attr(
51172    target_arch = "arm",
51173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51174)]
51175pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51176    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51177    unsafe {
51178        let ret_val: poly16x8_t = transmute(a);
51179        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51180    }
51181}
51182#[doc = "Vector reinterpret cast operation"]
51183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51184#[inline]
51185#[cfg(target_endian = "little")]
51186#[target_feature(enable = "neon")]
51187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51189#[cfg_attr(
51190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51191    assert_instr(nop)
51192)]
51193#[cfg_attr(
51194    not(target_arch = "arm"),
51195    stable(feature = "neon_intrinsics", since = "1.59.0")
51196)]
51197#[cfg_attr(
51198    target_arch = "arm",
51199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51200)]
51201pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51202    unsafe { transmute(a) }
51203}
51204#[doc = "Vector reinterpret cast operation"]
51205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51206#[inline]
51207#[cfg(target_endian = "big")]
51208#[target_feature(enable = "neon")]
51209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51211#[cfg_attr(
51212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51213    assert_instr(nop)
51214)]
51215#[cfg_attr(
51216    not(target_arch = "arm"),
51217    stable(feature = "neon_intrinsics", since = "1.59.0")
51218)]
51219#[cfg_attr(
51220    target_arch = "arm",
51221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51222)]
51223pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51224    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51225    unsafe {
51226        let ret_val: float32x2_t = transmute(a);
51227        simd_shuffle!(ret_val, ret_val, [1, 0])
51228    }
51229}
51230#[doc = "Vector reinterpret cast operation"]
51231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51232#[inline]
51233#[cfg(target_endian = "little")]
51234#[target_feature(enable = "neon")]
51235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51237#[cfg_attr(
51238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51239    assert_instr(nop)
51240)]
51241#[cfg_attr(
51242    not(target_arch = "arm"),
51243    stable(feature = "neon_intrinsics", since = "1.59.0")
51244)]
51245#[cfg_attr(
51246    target_arch = "arm",
51247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51248)]
51249pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51250    unsafe { transmute(a) }
51251}
51252#[doc = "Vector reinterpret cast operation"]
51253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51254#[inline]
51255#[cfg(target_endian = "big")]
51256#[target_feature(enable = "neon")]
51257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51258#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51259#[cfg_attr(
51260    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51261    assert_instr(nop)
51262)]
51263#[cfg_attr(
51264    not(target_arch = "arm"),
51265    stable(feature = "neon_intrinsics", since = "1.59.0")
51266)]
51267#[cfg_attr(
51268    target_arch = "arm",
51269    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51270)]
51271pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51272    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51273    unsafe {
51274        let ret_val: int8x8_t = transmute(a);
51275        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51276    }
51277}
51278#[doc = "Vector reinterpret cast operation"]
51279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51280#[inline]
51281#[cfg(target_endian = "little")]
51282#[target_feature(enable = "neon")]
51283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51285#[cfg_attr(
51286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51287    assert_instr(nop)
51288)]
51289#[cfg_attr(
51290    not(target_arch = "arm"),
51291    stable(feature = "neon_intrinsics", since = "1.59.0")
51292)]
51293#[cfg_attr(
51294    target_arch = "arm",
51295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51296)]
51297pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51298    unsafe { transmute(a) }
51299}
51300#[doc = "Vector reinterpret cast operation"]
51301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51302#[inline]
51303#[cfg(target_endian = "big")]
51304#[target_feature(enable = "neon")]
51305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51307#[cfg_attr(
51308    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51309    assert_instr(nop)
51310)]
51311#[cfg_attr(
51312    not(target_arch = "arm"),
51313    stable(feature = "neon_intrinsics", since = "1.59.0")
51314)]
51315#[cfg_attr(
51316    target_arch = "arm",
51317    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51318)]
51319pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51320    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51321    unsafe {
51322        let ret_val: int16x4_t = transmute(a);
51323        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51324    }
51325}
51326#[doc = "Vector reinterpret cast operation"]
51327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51328#[inline]
51329#[cfg(target_endian = "little")]
51330#[target_feature(enable = "neon")]
51331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51333#[cfg_attr(
51334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51335    assert_instr(nop)
51336)]
51337#[cfg_attr(
51338    not(target_arch = "arm"),
51339    stable(feature = "neon_intrinsics", since = "1.59.0")
51340)]
51341#[cfg_attr(
51342    target_arch = "arm",
51343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51344)]
51345pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51346    unsafe { transmute(a) }
51347}
51348#[doc = "Vector reinterpret cast operation"]
51349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51350#[inline]
51351#[cfg(target_endian = "big")]
51352#[target_feature(enable = "neon")]
51353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51355#[cfg_attr(
51356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51357    assert_instr(nop)
51358)]
51359#[cfg_attr(
51360    not(target_arch = "arm"),
51361    stable(feature = "neon_intrinsics", since = "1.59.0")
51362)]
51363#[cfg_attr(
51364    target_arch = "arm",
51365    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51366)]
51367pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51368    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51369    unsafe {
51370        let ret_val: int32x2_t = transmute(a);
51371        simd_shuffle!(ret_val, ret_val, [1, 0])
51372    }
51373}
51374#[doc = "Vector reinterpret cast operation"]
51375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51376#[inline]
51377#[cfg(target_endian = "little")]
51378#[target_feature(enable = "neon")]
51379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51381#[cfg_attr(
51382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51383    assert_instr(nop)
51384)]
51385#[cfg_attr(
51386    not(target_arch = "arm"),
51387    stable(feature = "neon_intrinsics", since = "1.59.0")
51388)]
51389#[cfg_attr(
51390    target_arch = "arm",
51391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51392)]
51393pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51394    unsafe { transmute(a) }
51395}
51396#[doc = "Vector reinterpret cast operation"]
51397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51398#[inline]
51399#[cfg(target_endian = "big")]
51400#[target_feature(enable = "neon")]
51401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51403#[cfg_attr(
51404    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51405    assert_instr(nop)
51406)]
51407#[cfg_attr(
51408    not(target_arch = "arm"),
51409    stable(feature = "neon_intrinsics", since = "1.59.0")
51410)]
51411#[cfg_attr(
51412    target_arch = "arm",
51413    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51414)]
51415pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51416    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51417    unsafe { transmute(a) }
51418}
51419#[doc = "Vector reinterpret cast operation"]
51420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51421#[inline]
51422#[cfg(target_endian = "little")]
51423#[target_feature(enable = "neon")]
51424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51426#[cfg_attr(
51427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51428    assert_instr(nop)
51429)]
51430#[cfg_attr(
51431    not(target_arch = "arm"),
51432    stable(feature = "neon_intrinsics", since = "1.59.0")
51433)]
51434#[cfg_attr(
51435    target_arch = "arm",
51436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51437)]
51438pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51439    unsafe { transmute(a) }
51440}
51441#[doc = "Vector reinterpret cast operation"]
51442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51443#[inline]
51444#[cfg(target_endian = "big")]
51445#[target_feature(enable = "neon")]
51446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51448#[cfg_attr(
51449    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51450    assert_instr(nop)
51451)]
51452#[cfg_attr(
51453    not(target_arch = "arm"),
51454    stable(feature = "neon_intrinsics", since = "1.59.0")
51455)]
51456#[cfg_attr(
51457    target_arch = "arm",
51458    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51459)]
51460pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51461    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51462    unsafe {
51463        let ret_val: uint8x8_t = transmute(a);
51464        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51465    }
51466}
51467#[doc = "Vector reinterpret cast operation"]
51468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51469#[inline]
51470#[cfg(target_endian = "little")]
51471#[target_feature(enable = "neon")]
51472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51474#[cfg_attr(
51475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51476    assert_instr(nop)
51477)]
51478#[cfg_attr(
51479    not(target_arch = "arm"),
51480    stable(feature = "neon_intrinsics", since = "1.59.0")
51481)]
51482#[cfg_attr(
51483    target_arch = "arm",
51484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51485)]
51486pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51487    unsafe { transmute(a) }
51488}
51489#[doc = "Vector reinterpret cast operation"]
51490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51491#[inline]
51492#[cfg(target_endian = "big")]
51493#[target_feature(enable = "neon")]
51494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51496#[cfg_attr(
51497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51498    assert_instr(nop)
51499)]
51500#[cfg_attr(
51501    not(target_arch = "arm"),
51502    stable(feature = "neon_intrinsics", since = "1.59.0")
51503)]
51504#[cfg_attr(
51505    target_arch = "arm",
51506    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51507)]
51508pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51509    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51510    unsafe {
51511        let ret_val: uint16x4_t = transmute(a);
51512        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51513    }
51514}
51515#[doc = "Vector reinterpret cast operation"]
51516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51517#[inline]
51518#[cfg(target_endian = "little")]
51519#[target_feature(enable = "neon")]
51520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51522#[cfg_attr(
51523    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51524    assert_instr(nop)
51525)]
51526#[cfg_attr(
51527    not(target_arch = "arm"),
51528    stable(feature = "neon_intrinsics", since = "1.59.0")
51529)]
51530#[cfg_attr(
51531    target_arch = "arm",
51532    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51533)]
51534pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51535    unsafe { transmute(a) }
51536}
51537#[doc = "Vector reinterpret cast operation"]
51538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51539#[inline]
51540#[cfg(target_endian = "big")]
51541#[target_feature(enable = "neon")]
51542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51544#[cfg_attr(
51545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51546    assert_instr(nop)
51547)]
51548#[cfg_attr(
51549    not(target_arch = "arm"),
51550    stable(feature = "neon_intrinsics", since = "1.59.0")
51551)]
51552#[cfg_attr(
51553    target_arch = "arm",
51554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51555)]
51556pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51557    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51558    unsafe { transmute(a) }
51559}
51560#[doc = "Vector reinterpret cast operation"]
51561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51562#[inline]
51563#[cfg(target_endian = "little")]
51564#[target_feature(enable = "neon")]
51565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51567#[cfg_attr(
51568    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51569    assert_instr(nop)
51570)]
51571#[cfg_attr(
51572    not(target_arch = "arm"),
51573    stable(feature = "neon_intrinsics", since = "1.59.0")
51574)]
51575#[cfg_attr(
51576    target_arch = "arm",
51577    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51578)]
51579pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51580    unsafe { transmute(a) }
51581}
51582#[doc = "Vector reinterpret cast operation"]
51583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51584#[inline]
51585#[cfg(target_endian = "big")]
51586#[target_feature(enable = "neon")]
51587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51589#[cfg_attr(
51590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51591    assert_instr(nop)
51592)]
51593#[cfg_attr(
51594    not(target_arch = "arm"),
51595    stable(feature = "neon_intrinsics", since = "1.59.0")
51596)]
51597#[cfg_attr(
51598    target_arch = "arm",
51599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51600)]
51601pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51602    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51603    unsafe {
51604        let ret_val: poly8x8_t = transmute(a);
51605        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51606    }
51607}
51608#[doc = "Vector reinterpret cast operation"]
51609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51610#[inline]
51611#[cfg(target_endian = "little")]
51612#[target_feature(enable = "neon")]
51613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51615#[cfg_attr(
51616    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51617    assert_instr(nop)
51618)]
51619#[cfg_attr(
51620    not(target_arch = "arm"),
51621    stable(feature = "neon_intrinsics", since = "1.59.0")
51622)]
51623#[cfg_attr(
51624    target_arch = "arm",
51625    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51626)]
51627pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51628    unsafe { transmute(a) }
51629}
51630#[doc = "Vector reinterpret cast operation"]
51631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51632#[inline]
51633#[cfg(target_endian = "big")]
51634#[target_feature(enable = "neon")]
51635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51637#[cfg_attr(
51638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51639    assert_instr(nop)
51640)]
51641#[cfg_attr(
51642    not(target_arch = "arm"),
51643    stable(feature = "neon_intrinsics", since = "1.59.0")
51644)]
51645#[cfg_attr(
51646    target_arch = "arm",
51647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51648)]
51649pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51650    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51651    unsafe {
51652        let ret_val: poly16x4_t = transmute(a);
51653        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51654    }
51655}
51656#[doc = "Vector reinterpret cast operation"]
51657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51658#[inline]
51659#[cfg(target_endian = "little")]
51660#[target_feature(enable = "neon")]
51661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51663#[cfg_attr(
51664    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51665    assert_instr(nop)
51666)]
51667#[cfg_attr(
51668    not(target_arch = "arm"),
51669    stable(feature = "neon_intrinsics", since = "1.59.0")
51670)]
51671#[cfg_attr(
51672    target_arch = "arm",
51673    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51674)]
51675pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51676    unsafe { transmute(a) }
51677}
51678#[doc = "Vector reinterpret cast operation"]
51679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51680#[inline]
51681#[cfg(target_endian = "big")]
51682#[target_feature(enable = "neon")]
51683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51685#[cfg_attr(
51686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51687    assert_instr(nop)
51688)]
51689#[cfg_attr(
51690    not(target_arch = "arm"),
51691    stable(feature = "neon_intrinsics", since = "1.59.0")
51692)]
51693#[cfg_attr(
51694    target_arch = "arm",
51695    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51696)]
51697pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51698    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51699    unsafe {
51700        let ret_val: float32x4_t = transmute(a);
51701        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51702    }
51703}
51704#[doc = "Vector reinterpret cast operation"]
51705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51706#[inline]
51707#[cfg(target_endian = "little")]
51708#[target_feature(enable = "neon")]
51709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51711#[cfg_attr(
51712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51713    assert_instr(nop)
51714)]
51715#[cfg_attr(
51716    not(target_arch = "arm"),
51717    stable(feature = "neon_intrinsics", since = "1.59.0")
51718)]
51719#[cfg_attr(
51720    target_arch = "arm",
51721    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51722)]
51723pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51724    unsafe { transmute(a) }
51725}
51726#[doc = "Vector reinterpret cast operation"]
51727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51728#[inline]
51729#[cfg(target_endian = "big")]
51730#[target_feature(enable = "neon")]
51731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51733#[cfg_attr(
51734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51735    assert_instr(nop)
51736)]
51737#[cfg_attr(
51738    not(target_arch = "arm"),
51739    stable(feature = "neon_intrinsics", since = "1.59.0")
51740)]
51741#[cfg_attr(
51742    target_arch = "arm",
51743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51744)]
51745pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51746    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51747    unsafe {
51748        let ret_val: int8x16_t = transmute(a);
51749        simd_shuffle!(
51750            ret_val,
51751            ret_val,
51752            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51753        )
51754    }
51755}
51756#[doc = "Vector reinterpret cast operation"]
51757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51758#[inline]
51759#[cfg(target_endian = "little")]
51760#[target_feature(enable = "neon")]
51761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51762#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51763#[cfg_attr(
51764    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51765    assert_instr(nop)
51766)]
51767#[cfg_attr(
51768    not(target_arch = "arm"),
51769    stable(feature = "neon_intrinsics", since = "1.59.0")
51770)]
51771#[cfg_attr(
51772    target_arch = "arm",
51773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51774)]
51775pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51776    unsafe { transmute(a) }
51777}
51778#[doc = "Vector reinterpret cast operation"]
51779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51780#[inline]
51781#[cfg(target_endian = "big")]
51782#[target_feature(enable = "neon")]
51783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51785#[cfg_attr(
51786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51787    assert_instr(nop)
51788)]
51789#[cfg_attr(
51790    not(target_arch = "arm"),
51791    stable(feature = "neon_intrinsics", since = "1.59.0")
51792)]
51793#[cfg_attr(
51794    target_arch = "arm",
51795    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51796)]
51797pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51798    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51799    unsafe {
51800        let ret_val: int16x8_t = transmute(a);
51801        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51802    }
51803}
51804#[doc = "Vector reinterpret cast operation"]
51805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51806#[inline]
51807#[cfg(target_endian = "little")]
51808#[target_feature(enable = "neon")]
51809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51811#[cfg_attr(
51812    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51813    assert_instr(nop)
51814)]
51815#[cfg_attr(
51816    not(target_arch = "arm"),
51817    stable(feature = "neon_intrinsics", since = "1.59.0")
51818)]
51819#[cfg_attr(
51820    target_arch = "arm",
51821    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51822)]
51823pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51824    unsafe { transmute(a) }
51825}
51826#[doc = "Vector reinterpret cast operation"]
51827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51828#[inline]
51829#[cfg(target_endian = "big")]
51830#[target_feature(enable = "neon")]
51831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51833#[cfg_attr(
51834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51835    assert_instr(nop)
51836)]
51837#[cfg_attr(
51838    not(target_arch = "arm"),
51839    stable(feature = "neon_intrinsics", since = "1.59.0")
51840)]
51841#[cfg_attr(
51842    target_arch = "arm",
51843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51844)]
51845pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51846    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51847    unsafe {
51848        let ret_val: int32x4_t = transmute(a);
51849        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51850    }
51851}
51852#[doc = "Vector reinterpret cast operation"]
51853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51854#[inline]
51855#[cfg(target_endian = "little")]
51856#[target_feature(enable = "neon")]
51857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51859#[cfg_attr(
51860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51861    assert_instr(nop)
51862)]
51863#[cfg_attr(
51864    not(target_arch = "arm"),
51865    stable(feature = "neon_intrinsics", since = "1.59.0")
51866)]
51867#[cfg_attr(
51868    target_arch = "arm",
51869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51870)]
51871pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51872    unsafe { transmute(a) }
51873}
51874#[doc = "Vector reinterpret cast operation"]
51875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51876#[inline]
51877#[cfg(target_endian = "big")]
51878#[target_feature(enable = "neon")]
51879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51881#[cfg_attr(
51882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51883    assert_instr(nop)
51884)]
51885#[cfg_attr(
51886    not(target_arch = "arm"),
51887    stable(feature = "neon_intrinsics", since = "1.59.0")
51888)]
51889#[cfg_attr(
51890    target_arch = "arm",
51891    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51892)]
51893pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51894    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51895    unsafe {
51896        let ret_val: int64x2_t = transmute(a);
51897        simd_shuffle!(ret_val, ret_val, [1, 0])
51898    }
51899}
51900#[doc = "Vector reinterpret cast operation"]
51901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51902#[inline]
51903#[cfg(target_endian = "little")]
51904#[target_feature(enable = "neon")]
51905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51907#[cfg_attr(
51908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51909    assert_instr(nop)
51910)]
51911#[cfg_attr(
51912    not(target_arch = "arm"),
51913    stable(feature = "neon_intrinsics", since = "1.59.0")
51914)]
51915#[cfg_attr(
51916    target_arch = "arm",
51917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51918)]
51919pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51920    unsafe { transmute(a) }
51921}
51922#[doc = "Vector reinterpret cast operation"]
51923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51924#[inline]
51925#[cfg(target_endian = "big")]
51926#[target_feature(enable = "neon")]
51927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51929#[cfg_attr(
51930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51931    assert_instr(nop)
51932)]
51933#[cfg_attr(
51934    not(target_arch = "arm"),
51935    stable(feature = "neon_intrinsics", since = "1.59.0")
51936)]
51937#[cfg_attr(
51938    target_arch = "arm",
51939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51940)]
51941pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51942    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51943    unsafe {
51944        let ret_val: uint8x16_t = transmute(a);
51945        simd_shuffle!(
51946            ret_val,
51947            ret_val,
51948            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51949        )
51950    }
51951}
51952#[doc = "Vector reinterpret cast operation"]
51953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51954#[inline]
51955#[cfg(target_endian = "little")]
51956#[target_feature(enable = "neon")]
51957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51959#[cfg_attr(
51960    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51961    assert_instr(nop)
51962)]
51963#[cfg_attr(
51964    not(target_arch = "arm"),
51965    stable(feature = "neon_intrinsics", since = "1.59.0")
51966)]
51967#[cfg_attr(
51968    target_arch = "arm",
51969    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51970)]
51971pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51972    unsafe { transmute(a) }
51973}
51974#[doc = "Vector reinterpret cast operation"]
51975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51976#[inline]
51977#[cfg(target_endian = "big")]
51978#[target_feature(enable = "neon")]
51979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51981#[cfg_attr(
51982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51983    assert_instr(nop)
51984)]
51985#[cfg_attr(
51986    not(target_arch = "arm"),
51987    stable(feature = "neon_intrinsics", since = "1.59.0")
51988)]
51989#[cfg_attr(
51990    target_arch = "arm",
51991    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51992)]
51993pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51994    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51995    unsafe {
51996        let ret_val: uint16x8_t = transmute(a);
51997        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51998    }
51999}
52000#[doc = "Vector reinterpret cast operation"]
52001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
52002#[inline]
52003#[cfg(target_endian = "little")]
52004#[target_feature(enable = "neon")]
52005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52007#[cfg_attr(
52008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52009    assert_instr(nop)
52010)]
52011#[cfg_attr(
52012    not(target_arch = "arm"),
52013    stable(feature = "neon_intrinsics", since = "1.59.0")
52014)]
52015#[cfg_attr(
52016    target_arch = "arm",
52017    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52018)]
52019pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
52020    unsafe { transmute(a) }
52021}
52022#[doc = "Vector reinterpret cast operation"]
52023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
52024#[inline]
52025#[cfg(target_endian = "big")]
52026#[target_feature(enable = "neon")]
52027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52029#[cfg_attr(
52030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52031    assert_instr(nop)
52032)]
52033#[cfg_attr(
52034    not(target_arch = "arm"),
52035    stable(feature = "neon_intrinsics", since = "1.59.0")
52036)]
52037#[cfg_attr(
52038    target_arch = "arm",
52039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52040)]
52041pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
52042    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52043    unsafe {
52044        let ret_val: uint64x2_t = transmute(a);
52045        simd_shuffle!(ret_val, ret_val, [1, 0])
52046    }
52047}
52048#[doc = "Vector reinterpret cast operation"]
52049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
52050#[inline]
52051#[cfg(target_endian = "little")]
52052#[target_feature(enable = "neon")]
52053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52055#[cfg_attr(
52056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52057    assert_instr(nop)
52058)]
52059#[cfg_attr(
52060    not(target_arch = "arm"),
52061    stable(feature = "neon_intrinsics", since = "1.59.0")
52062)]
52063#[cfg_attr(
52064    target_arch = "arm",
52065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52066)]
52067pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
52068    unsafe { transmute(a) }
52069}
52070#[doc = "Vector reinterpret cast operation"]
52071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
52072#[inline]
52073#[cfg(target_endian = "big")]
52074#[target_feature(enable = "neon")]
52075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52077#[cfg_attr(
52078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52079    assert_instr(nop)
52080)]
52081#[cfg_attr(
52082    not(target_arch = "arm"),
52083    stable(feature = "neon_intrinsics", since = "1.59.0")
52084)]
52085#[cfg_attr(
52086    target_arch = "arm",
52087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52088)]
52089pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
52090    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52091    unsafe {
52092        let ret_val: poly8x16_t = transmute(a);
52093        simd_shuffle!(
52094            ret_val,
52095            ret_val,
52096            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52097        )
52098    }
52099}
52100#[doc = "Vector reinterpret cast operation"]
52101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52102#[inline]
52103#[cfg(target_endian = "little")]
52104#[target_feature(enable = "neon")]
52105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52107#[cfg_attr(
52108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52109    assert_instr(nop)
52110)]
52111#[cfg_attr(
52112    not(target_arch = "arm"),
52113    stable(feature = "neon_intrinsics", since = "1.59.0")
52114)]
52115#[cfg_attr(
52116    target_arch = "arm",
52117    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52118)]
52119pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52120    unsafe { transmute(a) }
52121}
52122#[doc = "Vector reinterpret cast operation"]
52123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52124#[inline]
52125#[cfg(target_endian = "big")]
52126#[target_feature(enable = "neon")]
52127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52129#[cfg_attr(
52130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52131    assert_instr(nop)
52132)]
52133#[cfg_attr(
52134    not(target_arch = "arm"),
52135    stable(feature = "neon_intrinsics", since = "1.59.0")
52136)]
52137#[cfg_attr(
52138    target_arch = "arm",
52139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52140)]
52141pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52142    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52143    unsafe {
52144        let ret_val: poly16x8_t = transmute(a);
52145        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52146    }
52147}
52148#[doc = "Vector reinterpret cast operation"]
52149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52150#[inline]
52151#[cfg(target_endian = "little")]
52152#[target_feature(enable = "neon")]
52153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52155#[cfg_attr(
52156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52157    assert_instr(nop)
52158)]
52159#[cfg_attr(
52160    not(target_arch = "arm"),
52161    stable(feature = "neon_intrinsics", since = "1.59.0")
52162)]
52163#[cfg_attr(
52164    target_arch = "arm",
52165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52166)]
52167pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52168    unsafe { transmute(a) }
52169}
52170#[doc = "Vector reinterpret cast operation"]
52171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52172#[inline]
52173#[cfg(target_endian = "big")]
52174#[target_feature(enable = "neon")]
52175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52177#[cfg_attr(
52178    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52179    assert_instr(nop)
52180)]
52181#[cfg_attr(
52182    not(target_arch = "arm"),
52183    stable(feature = "neon_intrinsics", since = "1.59.0")
52184)]
52185#[cfg_attr(
52186    target_arch = "arm",
52187    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52188)]
52189pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52190    unsafe {
52191        let ret_val: float32x2_t = transmute(a);
52192        simd_shuffle!(ret_val, ret_val, [1, 0])
52193    }
52194}
52195#[doc = "Vector reinterpret cast operation"]
52196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52197#[inline]
52198#[cfg(target_endian = "little")]
52199#[target_feature(enable = "neon")]
52200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52201#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52202#[cfg_attr(
52203    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52204    assert_instr(nop)
52205)]
52206#[cfg_attr(
52207    not(target_arch = "arm"),
52208    stable(feature = "neon_intrinsics", since = "1.59.0")
52209)]
52210#[cfg_attr(
52211    target_arch = "arm",
52212    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52213)]
52214pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52215    unsafe { transmute(a) }
52216}
52217#[doc = "Vector reinterpret cast operation"]
52218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52219#[inline]
52220#[cfg(target_endian = "big")]
52221#[target_feature(enable = "neon")]
52222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52223#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52224#[cfg_attr(
52225    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52226    assert_instr(nop)
52227)]
52228#[cfg_attr(
52229    not(target_arch = "arm"),
52230    stable(feature = "neon_intrinsics", since = "1.59.0")
52231)]
52232#[cfg_attr(
52233    target_arch = "arm",
52234    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52235)]
52236pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52237    unsafe {
52238        let ret_val: int8x8_t = transmute(a);
52239        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52240    }
52241}
52242#[doc = "Vector reinterpret cast operation"]
52243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52244#[inline]
52245#[cfg(target_endian = "little")]
52246#[target_feature(enable = "neon")]
52247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52249#[cfg_attr(
52250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52251    assert_instr(nop)
52252)]
52253#[cfg_attr(
52254    not(target_arch = "arm"),
52255    stable(feature = "neon_intrinsics", since = "1.59.0")
52256)]
52257#[cfg_attr(
52258    target_arch = "arm",
52259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52260)]
52261pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52262    unsafe { transmute(a) }
52263}
52264#[doc = "Vector reinterpret cast operation"]
52265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52266#[inline]
52267#[cfg(target_endian = "big")]
52268#[target_feature(enable = "neon")]
52269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52271#[cfg_attr(
52272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52273    assert_instr(nop)
52274)]
52275#[cfg_attr(
52276    not(target_arch = "arm"),
52277    stable(feature = "neon_intrinsics", since = "1.59.0")
52278)]
52279#[cfg_attr(
52280    target_arch = "arm",
52281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52282)]
52283pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52284    unsafe {
52285        let ret_val: int16x4_t = transmute(a);
52286        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52287    }
52288}
52289#[doc = "Vector reinterpret cast operation"]
52290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52291#[inline]
52292#[cfg(target_endian = "little")]
52293#[target_feature(enable = "neon")]
52294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52296#[cfg_attr(
52297    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52298    assert_instr(nop)
52299)]
52300#[cfg_attr(
52301    not(target_arch = "arm"),
52302    stable(feature = "neon_intrinsics", since = "1.59.0")
52303)]
52304#[cfg_attr(
52305    target_arch = "arm",
52306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52307)]
52308pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52309    unsafe { transmute(a) }
52310}
52311#[doc = "Vector reinterpret cast operation"]
52312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52313#[inline]
52314#[cfg(target_endian = "big")]
52315#[target_feature(enable = "neon")]
52316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52318#[cfg_attr(
52319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52320    assert_instr(nop)
52321)]
52322#[cfg_attr(
52323    not(target_arch = "arm"),
52324    stable(feature = "neon_intrinsics", since = "1.59.0")
52325)]
52326#[cfg_attr(
52327    target_arch = "arm",
52328    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52329)]
52330pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52331    unsafe {
52332        let ret_val: int32x2_t = transmute(a);
52333        simd_shuffle!(ret_val, ret_val, [1, 0])
52334    }
52335}
52336#[doc = "Vector reinterpret cast operation"]
52337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
52338#[inline]
52339#[target_feature(enable = "neon")]
52340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52342#[cfg_attr(
52343    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52344    assert_instr(nop)
52345)]
52346#[cfg_attr(
52347    not(target_arch = "arm"),
52348    stable(feature = "neon_intrinsics", since = "1.59.0")
52349)]
52350#[cfg_attr(
52351    target_arch = "arm",
52352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52353)]
52354pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
52355    unsafe { transmute(a) }
52356}
52357#[doc = "Vector reinterpret cast operation"]
52358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52359#[inline]
52360#[cfg(target_endian = "little")]
52361#[target_feature(enable = "neon")]
52362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52364#[cfg_attr(
52365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52366    assert_instr(nop)
52367)]
52368#[cfg_attr(
52369    not(target_arch = "arm"),
52370    stable(feature = "neon_intrinsics", since = "1.59.0")
52371)]
52372#[cfg_attr(
52373    target_arch = "arm",
52374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52375)]
52376pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52377    unsafe { transmute(a) }
52378}
52379#[doc = "Vector reinterpret cast operation"]
52380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52381#[inline]
52382#[cfg(target_endian = "big")]
52383#[target_feature(enable = "neon")]
52384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52386#[cfg_attr(
52387    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52388    assert_instr(nop)
52389)]
52390#[cfg_attr(
52391    not(target_arch = "arm"),
52392    stable(feature = "neon_intrinsics", since = "1.59.0")
52393)]
52394#[cfg_attr(
52395    target_arch = "arm",
52396    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52397)]
52398pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52399    unsafe {
52400        let ret_val: uint8x8_t = transmute(a);
52401        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52402    }
52403}
52404#[doc = "Vector reinterpret cast operation"]
52405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52406#[inline]
52407#[cfg(target_endian = "little")]
52408#[target_feature(enable = "neon")]
52409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52411#[cfg_attr(
52412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52413    assert_instr(nop)
52414)]
52415#[cfg_attr(
52416    not(target_arch = "arm"),
52417    stable(feature = "neon_intrinsics", since = "1.59.0")
52418)]
52419#[cfg_attr(
52420    target_arch = "arm",
52421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52422)]
52423pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52424    unsafe { transmute(a) }
52425}
52426#[doc = "Vector reinterpret cast operation"]
52427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52428#[inline]
52429#[cfg(target_endian = "big")]
52430#[target_feature(enable = "neon")]
52431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52433#[cfg_attr(
52434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52435    assert_instr(nop)
52436)]
52437#[cfg_attr(
52438    not(target_arch = "arm"),
52439    stable(feature = "neon_intrinsics", since = "1.59.0")
52440)]
52441#[cfg_attr(
52442    target_arch = "arm",
52443    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52444)]
52445pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52446    unsafe {
52447        let ret_val: uint16x4_t = transmute(a);
52448        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52449    }
52450}
52451#[doc = "Vector reinterpret cast operation"]
52452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52453#[inline]
52454#[cfg(target_endian = "little")]
52455#[target_feature(enable = "neon")]
52456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52458#[cfg_attr(
52459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52460    assert_instr(nop)
52461)]
52462#[cfg_attr(
52463    not(target_arch = "arm"),
52464    stable(feature = "neon_intrinsics", since = "1.59.0")
52465)]
52466#[cfg_attr(
52467    target_arch = "arm",
52468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52469)]
52470pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52471    unsafe { transmute(a) }
52472}
52473#[doc = "Vector reinterpret cast operation"]
52474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52475#[inline]
52476#[cfg(target_endian = "big")]
52477#[target_feature(enable = "neon")]
52478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52480#[cfg_attr(
52481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52482    assert_instr(nop)
52483)]
52484#[cfg_attr(
52485    not(target_arch = "arm"),
52486    stable(feature = "neon_intrinsics", since = "1.59.0")
52487)]
52488#[cfg_attr(
52489    target_arch = "arm",
52490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52491)]
52492pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52493    unsafe {
52494        let ret_val: uint32x2_t = transmute(a);
52495        simd_shuffle!(ret_val, ret_val, [1, 0])
52496    }
52497}
52498#[doc = "Vector reinterpret cast operation"]
52499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52500#[inline]
52501#[cfg(target_endian = "little")]
52502#[target_feature(enable = "neon")]
52503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52505#[cfg_attr(
52506    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52507    assert_instr(nop)
52508)]
52509#[cfg_attr(
52510    not(target_arch = "arm"),
52511    stable(feature = "neon_intrinsics", since = "1.59.0")
52512)]
52513#[cfg_attr(
52514    target_arch = "arm",
52515    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52516)]
52517pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52518    unsafe { transmute(a) }
52519}
52520#[doc = "Vector reinterpret cast operation"]
52521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52522#[inline]
52523#[cfg(target_endian = "big")]
52524#[target_feature(enable = "neon")]
52525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52527#[cfg_attr(
52528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52529    assert_instr(nop)
52530)]
52531#[cfg_attr(
52532    not(target_arch = "arm"),
52533    stable(feature = "neon_intrinsics", since = "1.59.0")
52534)]
52535#[cfg_attr(
52536    target_arch = "arm",
52537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52538)]
52539pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52540    unsafe {
52541        let ret_val: poly8x8_t = transmute(a);
52542        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52543    }
52544}
52545#[doc = "Vector reinterpret cast operation"]
52546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52547#[inline]
52548#[cfg(target_endian = "little")]
52549#[target_feature(enable = "neon")]
52550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52552#[cfg_attr(
52553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52554    assert_instr(nop)
52555)]
52556#[cfg_attr(
52557    not(target_arch = "arm"),
52558    stable(feature = "neon_intrinsics", since = "1.59.0")
52559)]
52560#[cfg_attr(
52561    target_arch = "arm",
52562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52563)]
52564pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52565    unsafe { transmute(a) }
52566}
52567#[doc = "Vector reinterpret cast operation"]
52568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52569#[inline]
52570#[cfg(target_endian = "big")]
52571#[target_feature(enable = "neon")]
52572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52574#[cfg_attr(
52575    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52576    assert_instr(nop)
52577)]
52578#[cfg_attr(
52579    not(target_arch = "arm"),
52580    stable(feature = "neon_intrinsics", since = "1.59.0")
52581)]
52582#[cfg_attr(
52583    target_arch = "arm",
52584    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52585)]
52586pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52587    unsafe {
52588        let ret_val: poly16x4_t = transmute(a);
52589        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52590    }
52591}
52592#[doc = "Vector reinterpret cast operation"]
52593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52594#[inline]
52595#[cfg(target_endian = "little")]
52596#[target_feature(enable = "neon")]
52597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52599#[cfg_attr(
52600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52601    assert_instr(nop)
52602)]
52603#[cfg_attr(
52604    not(target_arch = "arm"),
52605    stable(feature = "neon_intrinsics", since = "1.59.0")
52606)]
52607#[cfg_attr(
52608    target_arch = "arm",
52609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52610)]
52611pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52612    unsafe { transmute(a) }
52613}
52614#[doc = "Vector reinterpret cast operation"]
52615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52616#[inline]
52617#[cfg(target_endian = "big")]
52618#[target_feature(enable = "neon")]
52619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52621#[cfg_attr(
52622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52623    assert_instr(nop)
52624)]
52625#[cfg_attr(
52626    not(target_arch = "arm"),
52627    stable(feature = "neon_intrinsics", since = "1.59.0")
52628)]
52629#[cfg_attr(
52630    target_arch = "arm",
52631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52632)]
52633pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52634    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52635    unsafe {
52636        let ret_val: float32x4_t = transmute(a);
52637        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52638    }
52639}
52640#[doc = "Vector reinterpret cast operation"]
52641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52642#[inline]
52643#[cfg(target_endian = "little")]
52644#[target_feature(enable = "neon")]
52645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52647#[cfg_attr(
52648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52649    assert_instr(nop)
52650)]
52651#[cfg_attr(
52652    not(target_arch = "arm"),
52653    stable(feature = "neon_intrinsics", since = "1.59.0")
52654)]
52655#[cfg_attr(
52656    target_arch = "arm",
52657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52658)]
52659pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52660    unsafe { transmute(a) }
52661}
52662#[doc = "Vector reinterpret cast operation"]
52663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52664#[inline]
52665#[cfg(target_endian = "big")]
52666#[target_feature(enable = "neon")]
52667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52669#[cfg_attr(
52670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52671    assert_instr(nop)
52672)]
52673#[cfg_attr(
52674    not(target_arch = "arm"),
52675    stable(feature = "neon_intrinsics", since = "1.59.0")
52676)]
52677#[cfg_attr(
52678    target_arch = "arm",
52679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52680)]
52681pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52682    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52683    unsafe {
52684        let ret_val: int8x16_t = transmute(a);
52685        simd_shuffle!(
52686            ret_val,
52687            ret_val,
52688            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52689        )
52690    }
52691}
52692#[doc = "Vector reinterpret cast operation"]
52693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52694#[inline]
52695#[cfg(target_endian = "little")]
52696#[target_feature(enable = "neon")]
52697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52699#[cfg_attr(
52700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52701    assert_instr(nop)
52702)]
52703#[cfg_attr(
52704    not(target_arch = "arm"),
52705    stable(feature = "neon_intrinsics", since = "1.59.0")
52706)]
52707#[cfg_attr(
52708    target_arch = "arm",
52709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52710)]
52711pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52712    unsafe { transmute(a) }
52713}
52714#[doc = "Vector reinterpret cast operation"]
52715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52716#[inline]
52717#[cfg(target_endian = "big")]
52718#[target_feature(enable = "neon")]
52719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52721#[cfg_attr(
52722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52723    assert_instr(nop)
52724)]
52725#[cfg_attr(
52726    not(target_arch = "arm"),
52727    stable(feature = "neon_intrinsics", since = "1.59.0")
52728)]
52729#[cfg_attr(
52730    target_arch = "arm",
52731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52732)]
52733pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52734    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52735    unsafe {
52736        let ret_val: int16x8_t = transmute(a);
52737        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52738    }
52739}
52740#[doc = "Vector reinterpret cast operation"]
52741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52742#[inline]
52743#[cfg(target_endian = "little")]
52744#[target_feature(enable = "neon")]
52745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52747#[cfg_attr(
52748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52749    assert_instr(nop)
52750)]
52751#[cfg_attr(
52752    not(target_arch = "arm"),
52753    stable(feature = "neon_intrinsics", since = "1.59.0")
52754)]
52755#[cfg_attr(
52756    target_arch = "arm",
52757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52758)]
52759pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52760    unsafe { transmute(a) }
52761}
52762#[doc = "Vector reinterpret cast operation"]
52763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52764#[inline]
52765#[cfg(target_endian = "big")]
52766#[target_feature(enable = "neon")]
52767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52769#[cfg_attr(
52770    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52771    assert_instr(nop)
52772)]
52773#[cfg_attr(
52774    not(target_arch = "arm"),
52775    stable(feature = "neon_intrinsics", since = "1.59.0")
52776)]
52777#[cfg_attr(
52778    target_arch = "arm",
52779    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52780)]
52781pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52782    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52783    unsafe {
52784        let ret_val: int32x4_t = transmute(a);
52785        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52786    }
52787}
52788#[doc = "Vector reinterpret cast operation"]
52789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52790#[inline]
52791#[cfg(target_endian = "little")]
52792#[target_feature(enable = "neon")]
52793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52795#[cfg_attr(
52796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52797    assert_instr(nop)
52798)]
52799#[cfg_attr(
52800    not(target_arch = "arm"),
52801    stable(feature = "neon_intrinsics", since = "1.59.0")
52802)]
52803#[cfg_attr(
52804    target_arch = "arm",
52805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52806)]
52807pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52808    unsafe { transmute(a) }
52809}
52810#[doc = "Vector reinterpret cast operation"]
52811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52812#[inline]
52813#[cfg(target_endian = "big")]
52814#[target_feature(enable = "neon")]
52815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52817#[cfg_attr(
52818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52819    assert_instr(nop)
52820)]
52821#[cfg_attr(
52822    not(target_arch = "arm"),
52823    stable(feature = "neon_intrinsics", since = "1.59.0")
52824)]
52825#[cfg_attr(
52826    target_arch = "arm",
52827    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52828)]
52829pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52830    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52831    unsafe {
52832        let ret_val: int64x2_t = transmute(a);
52833        simd_shuffle!(ret_val, ret_val, [1, 0])
52834    }
52835}
52836#[doc = "Vector reinterpret cast operation"]
52837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52838#[inline]
52839#[cfg(target_endian = "little")]
52840#[target_feature(enable = "neon")]
52841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52843#[cfg_attr(
52844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52845    assert_instr(nop)
52846)]
52847#[cfg_attr(
52848    not(target_arch = "arm"),
52849    stable(feature = "neon_intrinsics", since = "1.59.0")
52850)]
52851#[cfg_attr(
52852    target_arch = "arm",
52853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52854)]
52855pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52856    unsafe { transmute(a) }
52857}
52858#[doc = "Vector reinterpret cast operation"]
52859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52860#[inline]
52861#[cfg(target_endian = "big")]
52862#[target_feature(enable = "neon")]
52863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52865#[cfg_attr(
52866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52867    assert_instr(nop)
52868)]
52869#[cfg_attr(
52870    not(target_arch = "arm"),
52871    stable(feature = "neon_intrinsics", since = "1.59.0")
52872)]
52873#[cfg_attr(
52874    target_arch = "arm",
52875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52876)]
52877pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52878    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52879    unsafe {
52880        let ret_val: uint8x16_t = transmute(a);
52881        simd_shuffle!(
52882            ret_val,
52883            ret_val,
52884            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52885        )
52886    }
52887}
52888#[doc = "Vector reinterpret cast operation"]
52889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52890#[inline]
52891#[cfg(target_endian = "little")]
52892#[target_feature(enable = "neon")]
52893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52895#[cfg_attr(
52896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52897    assert_instr(nop)
52898)]
52899#[cfg_attr(
52900    not(target_arch = "arm"),
52901    stable(feature = "neon_intrinsics", since = "1.59.0")
52902)]
52903#[cfg_attr(
52904    target_arch = "arm",
52905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52906)]
52907pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52908    unsafe { transmute(a) }
52909}
52910#[doc = "Vector reinterpret cast operation"]
52911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52912#[inline]
52913#[cfg(target_endian = "big")]
52914#[target_feature(enable = "neon")]
52915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52917#[cfg_attr(
52918    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52919    assert_instr(nop)
52920)]
52921#[cfg_attr(
52922    not(target_arch = "arm"),
52923    stable(feature = "neon_intrinsics", since = "1.59.0")
52924)]
52925#[cfg_attr(
52926    target_arch = "arm",
52927    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52928)]
52929pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52930    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52931    unsafe {
52932        let ret_val: uint16x8_t = transmute(a);
52933        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52934    }
52935}
52936#[doc = "Vector reinterpret cast operation"]
52937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52938#[inline]
52939#[cfg(target_endian = "little")]
52940#[target_feature(enable = "neon")]
52941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52943#[cfg_attr(
52944    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52945    assert_instr(nop)
52946)]
52947#[cfg_attr(
52948    not(target_arch = "arm"),
52949    stable(feature = "neon_intrinsics", since = "1.59.0")
52950)]
52951#[cfg_attr(
52952    target_arch = "arm",
52953    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52954)]
52955pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52956    unsafe { transmute(a) }
52957}
52958#[doc = "Vector reinterpret cast operation"]
52959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52960#[inline]
52961#[cfg(target_endian = "big")]
52962#[target_feature(enable = "neon")]
52963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52965#[cfg_attr(
52966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52967    assert_instr(nop)
52968)]
52969#[cfg_attr(
52970    not(target_arch = "arm"),
52971    stable(feature = "neon_intrinsics", since = "1.59.0")
52972)]
52973#[cfg_attr(
52974    target_arch = "arm",
52975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52976)]
52977pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52978    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52979    unsafe {
52980        let ret_val: uint32x4_t = transmute(a);
52981        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52982    }
52983}
52984#[doc = "Vector reinterpret cast operation"]
52985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52986#[inline]
52987#[cfg(target_endian = "little")]
52988#[target_feature(enable = "neon")]
52989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52991#[cfg_attr(
52992    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52993    assert_instr(nop)
52994)]
52995#[cfg_attr(
52996    not(target_arch = "arm"),
52997    stable(feature = "neon_intrinsics", since = "1.59.0")
52998)]
52999#[cfg_attr(
53000    target_arch = "arm",
53001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53002)]
53003pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
53004    unsafe { transmute(a) }
53005}
53006#[doc = "Vector reinterpret cast operation"]
53007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
53008#[inline]
53009#[cfg(target_endian = "big")]
53010#[target_feature(enable = "neon")]
53011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53013#[cfg_attr(
53014    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53015    assert_instr(nop)
53016)]
53017#[cfg_attr(
53018    not(target_arch = "arm"),
53019    stable(feature = "neon_intrinsics", since = "1.59.0")
53020)]
53021#[cfg_attr(
53022    target_arch = "arm",
53023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53024)]
53025pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
53026    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
53027    unsafe {
53028        let ret_val: poly8x16_t = transmute(a);
53029        simd_shuffle!(
53030            ret_val,
53031            ret_val,
53032            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53033        )
53034    }
53035}
53036#[doc = "Vector reinterpret cast operation"]
53037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
53038#[inline]
53039#[cfg(target_endian = "little")]
53040#[target_feature(enable = "neon")]
53041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53043#[cfg_attr(
53044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53045    assert_instr(nop)
53046)]
53047#[cfg_attr(
53048    not(target_arch = "arm"),
53049    stable(feature = "neon_intrinsics", since = "1.59.0")
53050)]
53051#[cfg_attr(
53052    target_arch = "arm",
53053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53054)]
53055pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
53056    unsafe { transmute(a) }
53057}
53058#[doc = "Vector reinterpret cast operation"]
53059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
53060#[inline]
53061#[cfg(target_endian = "big")]
53062#[target_feature(enable = "neon")]
53063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53065#[cfg_attr(
53066    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53067    assert_instr(nop)
53068)]
53069#[cfg_attr(
53070    not(target_arch = "arm"),
53071    stable(feature = "neon_intrinsics", since = "1.59.0")
53072)]
53073#[cfg_attr(
53074    target_arch = "arm",
53075    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53076)]
53077pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
53078    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
53079    unsafe {
53080        let ret_val: poly16x8_t = transmute(a);
53081        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53082    }
53083}
53084#[doc = "Vector reinterpret cast operation"]
53085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53086#[inline]
53087#[cfg(target_endian = "little")]
53088#[target_feature(enable = "neon")]
53089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53091#[cfg_attr(
53092    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53093    assert_instr(nop)
53094)]
53095#[cfg_attr(
53096    not(target_arch = "arm"),
53097    stable(feature = "neon_intrinsics", since = "1.59.0")
53098)]
53099#[cfg_attr(
53100    target_arch = "arm",
53101    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53102)]
53103pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53104    unsafe { transmute(a) }
53105}
53106#[doc = "Vector reinterpret cast operation"]
53107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53108#[inline]
53109#[cfg(target_endian = "big")]
53110#[target_feature(enable = "neon")]
53111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53113#[cfg_attr(
53114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53115    assert_instr(nop)
53116)]
53117#[cfg_attr(
53118    not(target_arch = "arm"),
53119    stable(feature = "neon_intrinsics", since = "1.59.0")
53120)]
53121#[cfg_attr(
53122    target_arch = "arm",
53123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53124)]
53125pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53126    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53127    unsafe {
53128        let ret_val: float32x2_t = transmute(a);
53129        simd_shuffle!(ret_val, ret_val, [1, 0])
53130    }
53131}
53132#[doc = "Vector reinterpret cast operation"]
53133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53134#[inline]
53135#[cfg(target_endian = "little")]
53136#[target_feature(enable = "neon")]
53137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53139#[cfg_attr(
53140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53141    assert_instr(nop)
53142)]
53143#[cfg_attr(
53144    not(target_arch = "arm"),
53145    stable(feature = "neon_intrinsics", since = "1.59.0")
53146)]
53147#[cfg_attr(
53148    target_arch = "arm",
53149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53150)]
53151pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53152    unsafe { transmute(a) }
53153}
53154#[doc = "Vector reinterpret cast operation"]
53155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53156#[inline]
53157#[cfg(target_endian = "big")]
53158#[target_feature(enable = "neon")]
53159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53161#[cfg_attr(
53162    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53163    assert_instr(nop)
53164)]
53165#[cfg_attr(
53166    not(target_arch = "arm"),
53167    stable(feature = "neon_intrinsics", since = "1.59.0")
53168)]
53169#[cfg_attr(
53170    target_arch = "arm",
53171    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53172)]
53173pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53174    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53175    unsafe {
53176        let ret_val: int8x8_t = transmute(a);
53177        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53178    }
53179}
53180#[doc = "Vector reinterpret cast operation"]
53181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53182#[inline]
53183#[cfg(target_endian = "little")]
53184#[target_feature(enable = "neon")]
53185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53187#[cfg_attr(
53188    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53189    assert_instr(nop)
53190)]
53191#[cfg_attr(
53192    not(target_arch = "arm"),
53193    stable(feature = "neon_intrinsics", since = "1.59.0")
53194)]
53195#[cfg_attr(
53196    target_arch = "arm",
53197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53198)]
53199pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53200    unsafe { transmute(a) }
53201}
53202#[doc = "Vector reinterpret cast operation"]
53203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53204#[inline]
53205#[cfg(target_endian = "big")]
53206#[target_feature(enable = "neon")]
53207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53209#[cfg_attr(
53210    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53211    assert_instr(nop)
53212)]
53213#[cfg_attr(
53214    not(target_arch = "arm"),
53215    stable(feature = "neon_intrinsics", since = "1.59.0")
53216)]
53217#[cfg_attr(
53218    target_arch = "arm",
53219    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53220)]
53221pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53222    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53223    unsafe {
53224        let ret_val: int16x4_t = transmute(a);
53225        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53226    }
53227}
53228#[doc = "Vector reinterpret cast operation"]
53229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53230#[inline]
53231#[cfg(target_endian = "little")]
53232#[target_feature(enable = "neon")]
53233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53235#[cfg_attr(
53236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53237    assert_instr(nop)
53238)]
53239#[cfg_attr(
53240    not(target_arch = "arm"),
53241    stable(feature = "neon_intrinsics", since = "1.59.0")
53242)]
53243#[cfg_attr(
53244    target_arch = "arm",
53245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53246)]
53247pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53248    unsafe { transmute(a) }
53249}
53250#[doc = "Vector reinterpret cast operation"]
53251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53252#[inline]
53253#[cfg(target_endian = "big")]
53254#[target_feature(enable = "neon")]
53255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53257#[cfg_attr(
53258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53259    assert_instr(nop)
53260)]
53261#[cfg_attr(
53262    not(target_arch = "arm"),
53263    stable(feature = "neon_intrinsics", since = "1.59.0")
53264)]
53265#[cfg_attr(
53266    target_arch = "arm",
53267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53268)]
53269pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53270    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53271    unsafe {
53272        let ret_val: int32x2_t = transmute(a);
53273        simd_shuffle!(ret_val, ret_val, [1, 0])
53274    }
53275}
53276#[doc = "Vector reinterpret cast operation"]
53277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53278#[inline]
53279#[cfg(target_endian = "little")]
53280#[target_feature(enable = "neon")]
53281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53283#[cfg_attr(
53284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53285    assert_instr(nop)
53286)]
53287#[cfg_attr(
53288    not(target_arch = "arm"),
53289    stable(feature = "neon_intrinsics", since = "1.59.0")
53290)]
53291#[cfg_attr(
53292    target_arch = "arm",
53293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53294)]
53295pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53296    unsafe { transmute(a) }
53297}
53298#[doc = "Vector reinterpret cast operation"]
53299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53300#[inline]
53301#[cfg(target_endian = "big")]
53302#[target_feature(enable = "neon")]
53303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53305#[cfg_attr(
53306    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53307    assert_instr(nop)
53308)]
53309#[cfg_attr(
53310    not(target_arch = "arm"),
53311    stable(feature = "neon_intrinsics", since = "1.59.0")
53312)]
53313#[cfg_attr(
53314    target_arch = "arm",
53315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53316)]
53317pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53318    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53319    unsafe { transmute(a) }
53320}
53321#[doc = "Vector reinterpret cast operation"]
53322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53323#[inline]
53324#[cfg(target_endian = "little")]
53325#[target_feature(enable = "neon")]
53326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53328#[cfg_attr(
53329    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53330    assert_instr(nop)
53331)]
53332#[cfg_attr(
53333    not(target_arch = "arm"),
53334    stable(feature = "neon_intrinsics", since = "1.59.0")
53335)]
53336#[cfg_attr(
53337    target_arch = "arm",
53338    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53339)]
53340pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53341    unsafe { transmute(a) }
53342}
53343#[doc = "Vector reinterpret cast operation"]
53344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53345#[inline]
53346#[cfg(target_endian = "big")]
53347#[target_feature(enable = "neon")]
53348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53350#[cfg_attr(
53351    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53352    assert_instr(nop)
53353)]
53354#[cfg_attr(
53355    not(target_arch = "arm"),
53356    stable(feature = "neon_intrinsics", since = "1.59.0")
53357)]
53358#[cfg_attr(
53359    target_arch = "arm",
53360    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53361)]
53362pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53363    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53364    unsafe {
53365        let ret_val: uint8x8_t = transmute(a);
53366        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53367    }
53368}
53369#[doc = "Vector reinterpret cast operation"]
53370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53371#[inline]
53372#[cfg(target_endian = "little")]
53373#[target_feature(enable = "neon")]
53374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53376#[cfg_attr(
53377    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53378    assert_instr(nop)
53379)]
53380#[cfg_attr(
53381    not(target_arch = "arm"),
53382    stable(feature = "neon_intrinsics", since = "1.59.0")
53383)]
53384#[cfg_attr(
53385    target_arch = "arm",
53386    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53387)]
53388pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53389    unsafe { transmute(a) }
53390}
53391#[doc = "Vector reinterpret cast operation"]
53392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53393#[inline]
53394#[cfg(target_endian = "big")]
53395#[target_feature(enable = "neon")]
53396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53398#[cfg_attr(
53399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53400    assert_instr(nop)
53401)]
53402#[cfg_attr(
53403    not(target_arch = "arm"),
53404    stable(feature = "neon_intrinsics", since = "1.59.0")
53405)]
53406#[cfg_attr(
53407    target_arch = "arm",
53408    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53409)]
53410pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53411    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53412    unsafe {
53413        let ret_val: uint16x4_t = transmute(a);
53414        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53415    }
53416}
53417#[doc = "Vector reinterpret cast operation"]
53418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53419#[inline]
53420#[cfg(target_endian = "little")]
53421#[target_feature(enable = "neon")]
53422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53424#[cfg_attr(
53425    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53426    assert_instr(nop)
53427)]
53428#[cfg_attr(
53429    not(target_arch = "arm"),
53430    stable(feature = "neon_intrinsics", since = "1.59.0")
53431)]
53432#[cfg_attr(
53433    target_arch = "arm",
53434    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53435)]
53436pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53437    unsafe { transmute(a) }
53438}
53439#[doc = "Vector reinterpret cast operation"]
53440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53441#[inline]
53442#[cfg(target_endian = "big")]
53443#[target_feature(enable = "neon")]
53444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53446#[cfg_attr(
53447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53448    assert_instr(nop)
53449)]
53450#[cfg_attr(
53451    not(target_arch = "arm"),
53452    stable(feature = "neon_intrinsics", since = "1.59.0")
53453)]
53454#[cfg_attr(
53455    target_arch = "arm",
53456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53457)]
53458pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53459    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53460    unsafe {
53461        let ret_val: uint32x2_t = transmute(a);
53462        simd_shuffle!(ret_val, ret_val, [1, 0])
53463    }
53464}
53465#[doc = "Vector reinterpret cast operation"]
53466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53467#[inline]
53468#[cfg(target_endian = "little")]
53469#[target_feature(enable = "neon")]
53470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53472#[cfg_attr(
53473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53474    assert_instr(nop)
53475)]
53476#[cfg_attr(
53477    not(target_arch = "arm"),
53478    stable(feature = "neon_intrinsics", since = "1.59.0")
53479)]
53480#[cfg_attr(
53481    target_arch = "arm",
53482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53483)]
53484pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53485    unsafe { transmute(a) }
53486}
53487#[doc = "Vector reinterpret cast operation"]
53488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53489#[inline]
53490#[cfg(target_endian = "big")]
53491#[target_feature(enable = "neon")]
53492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53494#[cfg_attr(
53495    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53496    assert_instr(nop)
53497)]
53498#[cfg_attr(
53499    not(target_arch = "arm"),
53500    stable(feature = "neon_intrinsics", since = "1.59.0")
53501)]
53502#[cfg_attr(
53503    target_arch = "arm",
53504    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53505)]
53506pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53507    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53508    unsafe { transmute(a) }
53509}
53510#[doc = "Vector reinterpret cast operation"]
53511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53512#[inline]
53513#[cfg(target_endian = "little")]
53514#[target_feature(enable = "neon")]
53515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53517#[cfg_attr(
53518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53519    assert_instr(nop)
53520)]
53521#[cfg_attr(
53522    not(target_arch = "arm"),
53523    stable(feature = "neon_intrinsics", since = "1.59.0")
53524)]
53525#[cfg_attr(
53526    target_arch = "arm",
53527    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53528)]
53529pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53530    unsafe { transmute(a) }
53531}
53532#[doc = "Vector reinterpret cast operation"]
53533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53534#[inline]
53535#[cfg(target_endian = "big")]
53536#[target_feature(enable = "neon")]
53537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53539#[cfg_attr(
53540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53541    assert_instr(nop)
53542)]
53543#[cfg_attr(
53544    not(target_arch = "arm"),
53545    stable(feature = "neon_intrinsics", since = "1.59.0")
53546)]
53547#[cfg_attr(
53548    target_arch = "arm",
53549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53550)]
53551pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53552    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53553    unsafe {
53554        let ret_val: poly16x4_t = transmute(a);
53555        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53556    }
53557}
53558#[doc = "Vector reinterpret cast operation"]
53559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53560#[inline]
53561#[cfg(target_endian = "little")]
53562#[target_feature(enable = "neon")]
53563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53565#[cfg_attr(
53566    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53567    assert_instr(nop)
53568)]
53569#[cfg_attr(
53570    not(target_arch = "arm"),
53571    stable(feature = "neon_intrinsics", since = "1.59.0")
53572)]
53573#[cfg_attr(
53574    target_arch = "arm",
53575    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53576)]
53577pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53578    unsafe { transmute(a) }
53579}
53580#[doc = "Vector reinterpret cast operation"]
53581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53582#[inline]
53583#[cfg(target_endian = "big")]
53584#[target_feature(enable = "neon")]
53585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53587#[cfg_attr(
53588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53589    assert_instr(nop)
53590)]
53591#[cfg_attr(
53592    not(target_arch = "arm"),
53593    stable(feature = "neon_intrinsics", since = "1.59.0")
53594)]
53595#[cfg_attr(
53596    target_arch = "arm",
53597    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53598)]
53599pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53600    let a: poly8x16_t =
53601        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53602    unsafe {
53603        let ret_val: float32x4_t = transmute(a);
53604        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53605    }
53606}
53607#[doc = "Vector reinterpret cast operation"]
53608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53609#[inline]
53610#[cfg(target_endian = "little")]
53611#[target_feature(enable = "neon")]
53612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53614#[cfg_attr(
53615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53616    assert_instr(nop)
53617)]
53618#[cfg_attr(
53619    not(target_arch = "arm"),
53620    stable(feature = "neon_intrinsics", since = "1.59.0")
53621)]
53622#[cfg_attr(
53623    target_arch = "arm",
53624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53625)]
53626pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53627    unsafe { transmute(a) }
53628}
53629#[doc = "Vector reinterpret cast operation"]
53630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53631#[inline]
53632#[cfg(target_endian = "big")]
53633#[target_feature(enable = "neon")]
53634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53636#[cfg_attr(
53637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53638    assert_instr(nop)
53639)]
53640#[cfg_attr(
53641    not(target_arch = "arm"),
53642    stable(feature = "neon_intrinsics", since = "1.59.0")
53643)]
53644#[cfg_attr(
53645    target_arch = "arm",
53646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53647)]
53648pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53649    let a: poly8x16_t =
53650        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53651    unsafe {
53652        let ret_val: int8x16_t = transmute(a);
53653        simd_shuffle!(
53654            ret_val,
53655            ret_val,
53656            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53657        )
53658    }
53659}
53660#[doc = "Vector reinterpret cast operation"]
53661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53662#[inline]
53663#[cfg(target_endian = "little")]
53664#[target_feature(enable = "neon")]
53665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53667#[cfg_attr(
53668    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53669    assert_instr(nop)
53670)]
53671#[cfg_attr(
53672    not(target_arch = "arm"),
53673    stable(feature = "neon_intrinsics", since = "1.59.0")
53674)]
53675#[cfg_attr(
53676    target_arch = "arm",
53677    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53678)]
53679pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53680    unsafe { transmute(a) }
53681}
53682#[doc = "Vector reinterpret cast operation"]
53683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53684#[inline]
53685#[cfg(target_endian = "big")]
53686#[target_feature(enable = "neon")]
53687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53689#[cfg_attr(
53690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53691    assert_instr(nop)
53692)]
53693#[cfg_attr(
53694    not(target_arch = "arm"),
53695    stable(feature = "neon_intrinsics", since = "1.59.0")
53696)]
53697#[cfg_attr(
53698    target_arch = "arm",
53699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53700)]
53701pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53702    let a: poly8x16_t =
53703        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53704    unsafe {
53705        let ret_val: int16x8_t = transmute(a);
53706        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53707    }
53708}
53709#[doc = "Vector reinterpret cast operation"]
53710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53711#[inline]
53712#[cfg(target_endian = "little")]
53713#[target_feature(enable = "neon")]
53714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53716#[cfg_attr(
53717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53718    assert_instr(nop)
53719)]
53720#[cfg_attr(
53721    not(target_arch = "arm"),
53722    stable(feature = "neon_intrinsics", since = "1.59.0")
53723)]
53724#[cfg_attr(
53725    target_arch = "arm",
53726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53727)]
53728pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53729    unsafe { transmute(a) }
53730}
53731#[doc = "Vector reinterpret cast operation"]
53732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53733#[inline]
53734#[cfg(target_endian = "big")]
53735#[target_feature(enable = "neon")]
53736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53738#[cfg_attr(
53739    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53740    assert_instr(nop)
53741)]
53742#[cfg_attr(
53743    not(target_arch = "arm"),
53744    stable(feature = "neon_intrinsics", since = "1.59.0")
53745)]
53746#[cfg_attr(
53747    target_arch = "arm",
53748    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53749)]
53750pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53751    let a: poly8x16_t =
53752        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53753    unsafe {
53754        let ret_val: int32x4_t = transmute(a);
53755        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53756    }
53757}
53758#[doc = "Vector reinterpret cast operation"]
53759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53760#[inline]
53761#[cfg(target_endian = "little")]
53762#[target_feature(enable = "neon")]
53763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53765#[cfg_attr(
53766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53767    assert_instr(nop)
53768)]
53769#[cfg_attr(
53770    not(target_arch = "arm"),
53771    stable(feature = "neon_intrinsics", since = "1.59.0")
53772)]
53773#[cfg_attr(
53774    target_arch = "arm",
53775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53776)]
53777pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53778    unsafe { transmute(a) }
53779}
53780#[doc = "Vector reinterpret cast operation"]
53781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53782#[inline]
53783#[cfg(target_endian = "big")]
53784#[target_feature(enable = "neon")]
53785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53787#[cfg_attr(
53788    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53789    assert_instr(nop)
53790)]
53791#[cfg_attr(
53792    not(target_arch = "arm"),
53793    stable(feature = "neon_intrinsics", since = "1.59.0")
53794)]
53795#[cfg_attr(
53796    target_arch = "arm",
53797    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53798)]
53799pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53800    let a: poly8x16_t =
53801        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53802    unsafe {
53803        let ret_val: int64x2_t = transmute(a);
53804        simd_shuffle!(ret_val, ret_val, [1, 0])
53805    }
53806}
53807#[doc = "Vector reinterpret cast operation"]
53808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53809#[inline]
53810#[cfg(target_endian = "little")]
53811#[target_feature(enable = "neon")]
53812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53814#[cfg_attr(
53815    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53816    assert_instr(nop)
53817)]
53818#[cfg_attr(
53819    not(target_arch = "arm"),
53820    stable(feature = "neon_intrinsics", since = "1.59.0")
53821)]
53822#[cfg_attr(
53823    target_arch = "arm",
53824    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53825)]
53826pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53827    unsafe { transmute(a) }
53828}
53829#[doc = "Vector reinterpret cast operation"]
53830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53831#[inline]
53832#[cfg(target_endian = "big")]
53833#[target_feature(enable = "neon")]
53834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53836#[cfg_attr(
53837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53838    assert_instr(nop)
53839)]
53840#[cfg_attr(
53841    not(target_arch = "arm"),
53842    stable(feature = "neon_intrinsics", since = "1.59.0")
53843)]
53844#[cfg_attr(
53845    target_arch = "arm",
53846    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53847)]
53848pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53849    let a: poly8x16_t =
53850        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53851    unsafe {
53852        let ret_val: uint8x16_t = transmute(a);
53853        simd_shuffle!(
53854            ret_val,
53855            ret_val,
53856            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53857        )
53858    }
53859}
53860#[doc = "Vector reinterpret cast operation"]
53861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53862#[inline]
53863#[cfg(target_endian = "little")]
53864#[target_feature(enable = "neon")]
53865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53867#[cfg_attr(
53868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53869    assert_instr(nop)
53870)]
53871#[cfg_attr(
53872    not(target_arch = "arm"),
53873    stable(feature = "neon_intrinsics", since = "1.59.0")
53874)]
53875#[cfg_attr(
53876    target_arch = "arm",
53877    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53878)]
53879pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53880    unsafe { transmute(a) }
53881}
53882#[doc = "Vector reinterpret cast operation"]
53883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53884#[inline]
53885#[cfg(target_endian = "big")]
53886#[target_feature(enable = "neon")]
53887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53889#[cfg_attr(
53890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53891    assert_instr(nop)
53892)]
53893#[cfg_attr(
53894    not(target_arch = "arm"),
53895    stable(feature = "neon_intrinsics", since = "1.59.0")
53896)]
53897#[cfg_attr(
53898    target_arch = "arm",
53899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53900)]
53901pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53902    let a: poly8x16_t =
53903        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53904    unsafe {
53905        let ret_val: uint16x8_t = transmute(a);
53906        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53907    }
53908}
53909#[doc = "Vector reinterpret cast operation"]
53910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53911#[inline]
53912#[cfg(target_endian = "little")]
53913#[target_feature(enable = "neon")]
53914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53916#[cfg_attr(
53917    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53918    assert_instr(nop)
53919)]
53920#[cfg_attr(
53921    not(target_arch = "arm"),
53922    stable(feature = "neon_intrinsics", since = "1.59.0")
53923)]
53924#[cfg_attr(
53925    target_arch = "arm",
53926    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53927)]
53928pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53929    unsafe { transmute(a) }
53930}
53931#[doc = "Vector reinterpret cast operation"]
53932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53933#[inline]
53934#[cfg(target_endian = "big")]
53935#[target_feature(enable = "neon")]
53936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53938#[cfg_attr(
53939    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53940    assert_instr(nop)
53941)]
53942#[cfg_attr(
53943    not(target_arch = "arm"),
53944    stable(feature = "neon_intrinsics", since = "1.59.0")
53945)]
53946#[cfg_attr(
53947    target_arch = "arm",
53948    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53949)]
53950pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53951    let a: poly8x16_t =
53952        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53953    unsafe {
53954        let ret_val: uint32x4_t = transmute(a);
53955        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53956    }
53957}
53958#[doc = "Vector reinterpret cast operation"]
53959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53960#[inline]
53961#[cfg(target_endian = "little")]
53962#[target_feature(enable = "neon")]
53963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53965#[cfg_attr(
53966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53967    assert_instr(nop)
53968)]
53969#[cfg_attr(
53970    not(target_arch = "arm"),
53971    stable(feature = "neon_intrinsics", since = "1.59.0")
53972)]
53973#[cfg_attr(
53974    target_arch = "arm",
53975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53976)]
53977pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53978    unsafe { transmute(a) }
53979}
53980#[doc = "Vector reinterpret cast operation"]
53981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53982#[inline]
53983#[cfg(target_endian = "big")]
53984#[target_feature(enable = "neon")]
53985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53987#[cfg_attr(
53988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53989    assert_instr(nop)
53990)]
53991#[cfg_attr(
53992    not(target_arch = "arm"),
53993    stable(feature = "neon_intrinsics", since = "1.59.0")
53994)]
53995#[cfg_attr(
53996    target_arch = "arm",
53997    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53998)]
53999pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
54000    let a: poly8x16_t =
54001        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
54002    unsafe {
54003        let ret_val: uint64x2_t = transmute(a);
54004        simd_shuffle!(ret_val, ret_val, [1, 0])
54005    }
54006}
54007#[doc = "Vector reinterpret cast operation"]
54008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
54009#[inline]
54010#[cfg(target_endian = "little")]
54011#[target_feature(enable = "neon")]
54012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54014#[cfg_attr(
54015    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54016    assert_instr(nop)
54017)]
54018#[cfg_attr(
54019    not(target_arch = "arm"),
54020    stable(feature = "neon_intrinsics", since = "1.59.0")
54021)]
54022#[cfg_attr(
54023    target_arch = "arm",
54024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54025)]
54026pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
54027    unsafe { transmute(a) }
54028}
54029#[doc = "Vector reinterpret cast operation"]
54030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
54031#[inline]
54032#[cfg(target_endian = "big")]
54033#[target_feature(enable = "neon")]
54034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54036#[cfg_attr(
54037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54038    assert_instr(nop)
54039)]
54040#[cfg_attr(
54041    not(target_arch = "arm"),
54042    stable(feature = "neon_intrinsics", since = "1.59.0")
54043)]
54044#[cfg_attr(
54045    target_arch = "arm",
54046    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54047)]
54048pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
54049    let a: poly8x16_t =
54050        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
54051    unsafe {
54052        let ret_val: poly16x8_t = transmute(a);
54053        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54054    }
54055}
54056#[doc = "Vector reinterpret cast operation"]
54057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
54058#[inline]
54059#[cfg(target_endian = "little")]
54060#[target_feature(enable = "neon")]
54061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54063#[cfg_attr(
54064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54065    assert_instr(nop)
54066)]
54067#[cfg_attr(
54068    not(target_arch = "arm"),
54069    stable(feature = "neon_intrinsics", since = "1.59.0")
54070)]
54071#[cfg_attr(
54072    target_arch = "arm",
54073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54074)]
54075pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
54076    unsafe { transmute(a) }
54077}
54078#[doc = "Vector reinterpret cast operation"]
54079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
54080#[inline]
54081#[cfg(target_endian = "big")]
54082#[target_feature(enable = "neon")]
54083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54085#[cfg_attr(
54086    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54087    assert_instr(nop)
54088)]
54089#[cfg_attr(
54090    not(target_arch = "arm"),
54091    stable(feature = "neon_intrinsics", since = "1.59.0")
54092)]
54093#[cfg_attr(
54094    target_arch = "arm",
54095    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54096)]
54097pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
54098    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54099    unsafe {
54100        let ret_val: float32x2_t = transmute(a);
54101        simd_shuffle!(ret_val, ret_val, [1, 0])
54102    }
54103}
54104#[doc = "Vector reinterpret cast operation"]
54105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54106#[inline]
54107#[cfg(target_endian = "little")]
54108#[target_feature(enable = "neon")]
54109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54111#[cfg_attr(
54112    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54113    assert_instr(nop)
54114)]
54115#[cfg_attr(
54116    not(target_arch = "arm"),
54117    stable(feature = "neon_intrinsics", since = "1.59.0")
54118)]
54119#[cfg_attr(
54120    target_arch = "arm",
54121    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54122)]
54123pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54124    unsafe { transmute(a) }
54125}
54126#[doc = "Vector reinterpret cast operation"]
54127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54128#[inline]
54129#[cfg(target_endian = "big")]
54130#[target_feature(enable = "neon")]
54131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54133#[cfg_attr(
54134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54135    assert_instr(nop)
54136)]
54137#[cfg_attr(
54138    not(target_arch = "arm"),
54139    stable(feature = "neon_intrinsics", since = "1.59.0")
54140)]
54141#[cfg_attr(
54142    target_arch = "arm",
54143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54144)]
54145pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54146    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54147    unsafe {
54148        let ret_val: int8x8_t = transmute(a);
54149        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54150    }
54151}
54152#[doc = "Vector reinterpret cast operation"]
54153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54154#[inline]
54155#[cfg(target_endian = "little")]
54156#[target_feature(enable = "neon")]
54157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54159#[cfg_attr(
54160    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54161    assert_instr(nop)
54162)]
54163#[cfg_attr(
54164    not(target_arch = "arm"),
54165    stable(feature = "neon_intrinsics", since = "1.59.0")
54166)]
54167#[cfg_attr(
54168    target_arch = "arm",
54169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54170)]
54171pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54172    unsafe { transmute(a) }
54173}
54174#[doc = "Vector reinterpret cast operation"]
54175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54176#[inline]
54177#[cfg(target_endian = "big")]
54178#[target_feature(enable = "neon")]
54179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54181#[cfg_attr(
54182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54183    assert_instr(nop)
54184)]
54185#[cfg_attr(
54186    not(target_arch = "arm"),
54187    stable(feature = "neon_intrinsics", since = "1.59.0")
54188)]
54189#[cfg_attr(
54190    target_arch = "arm",
54191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54192)]
54193pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54194    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54195    unsafe {
54196        let ret_val: int16x4_t = transmute(a);
54197        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54198    }
54199}
54200#[doc = "Vector reinterpret cast operation"]
54201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54202#[inline]
54203#[cfg(target_endian = "little")]
54204#[target_feature(enable = "neon")]
54205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54207#[cfg_attr(
54208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54209    assert_instr(nop)
54210)]
54211#[cfg_attr(
54212    not(target_arch = "arm"),
54213    stable(feature = "neon_intrinsics", since = "1.59.0")
54214)]
54215#[cfg_attr(
54216    target_arch = "arm",
54217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54218)]
54219pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54220    unsafe { transmute(a) }
54221}
54222#[doc = "Vector reinterpret cast operation"]
54223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54224#[inline]
54225#[cfg(target_endian = "big")]
54226#[target_feature(enable = "neon")]
54227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54229#[cfg_attr(
54230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54231    assert_instr(nop)
54232)]
54233#[cfg_attr(
54234    not(target_arch = "arm"),
54235    stable(feature = "neon_intrinsics", since = "1.59.0")
54236)]
54237#[cfg_attr(
54238    target_arch = "arm",
54239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54240)]
54241pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54242    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54243    unsafe {
54244        let ret_val: int32x2_t = transmute(a);
54245        simd_shuffle!(ret_val, ret_val, [1, 0])
54246    }
54247}
54248#[doc = "Vector reinterpret cast operation"]
54249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54250#[inline]
54251#[cfg(target_endian = "little")]
54252#[target_feature(enable = "neon")]
54253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54255#[cfg_attr(
54256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54257    assert_instr(nop)
54258)]
54259#[cfg_attr(
54260    not(target_arch = "arm"),
54261    stable(feature = "neon_intrinsics", since = "1.59.0")
54262)]
54263#[cfg_attr(
54264    target_arch = "arm",
54265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54266)]
54267pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54268    unsafe { transmute(a) }
54269}
54270#[doc = "Vector reinterpret cast operation"]
54271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54272#[inline]
54273#[cfg(target_endian = "big")]
54274#[target_feature(enable = "neon")]
54275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54277#[cfg_attr(
54278    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54279    assert_instr(nop)
54280)]
54281#[cfg_attr(
54282    not(target_arch = "arm"),
54283    stable(feature = "neon_intrinsics", since = "1.59.0")
54284)]
54285#[cfg_attr(
54286    target_arch = "arm",
54287    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54288)]
54289pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54290    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54291    unsafe { transmute(a) }
54292}
54293#[doc = "Vector reinterpret cast operation"]
54294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54295#[inline]
54296#[cfg(target_endian = "little")]
54297#[target_feature(enable = "neon")]
54298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54300#[cfg_attr(
54301    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54302    assert_instr(nop)
54303)]
54304#[cfg_attr(
54305    not(target_arch = "arm"),
54306    stable(feature = "neon_intrinsics", since = "1.59.0")
54307)]
54308#[cfg_attr(
54309    target_arch = "arm",
54310    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54311)]
54312pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54313    unsafe { transmute(a) }
54314}
54315#[doc = "Vector reinterpret cast operation"]
54316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54317#[inline]
54318#[cfg(target_endian = "big")]
54319#[target_feature(enable = "neon")]
54320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54322#[cfg_attr(
54323    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54324    assert_instr(nop)
54325)]
54326#[cfg_attr(
54327    not(target_arch = "arm"),
54328    stable(feature = "neon_intrinsics", since = "1.59.0")
54329)]
54330#[cfg_attr(
54331    target_arch = "arm",
54332    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54333)]
54334pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54335    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54336    unsafe {
54337        let ret_val: uint8x8_t = transmute(a);
54338        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54339    }
54340}
54341#[doc = "Vector reinterpret cast operation"]
54342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54343#[inline]
54344#[cfg(target_endian = "little")]
54345#[target_feature(enable = "neon")]
54346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54348#[cfg_attr(
54349    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54350    assert_instr(nop)
54351)]
54352#[cfg_attr(
54353    not(target_arch = "arm"),
54354    stable(feature = "neon_intrinsics", since = "1.59.0")
54355)]
54356#[cfg_attr(
54357    target_arch = "arm",
54358    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54359)]
54360pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54361    unsafe { transmute(a) }
54362}
54363#[doc = "Vector reinterpret cast operation"]
54364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54365#[inline]
54366#[cfg(target_endian = "big")]
54367#[target_feature(enable = "neon")]
54368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54370#[cfg_attr(
54371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54372    assert_instr(nop)
54373)]
54374#[cfg_attr(
54375    not(target_arch = "arm"),
54376    stable(feature = "neon_intrinsics", since = "1.59.0")
54377)]
54378#[cfg_attr(
54379    target_arch = "arm",
54380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54381)]
54382pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54383    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54384    unsafe {
54385        let ret_val: uint16x4_t = transmute(a);
54386        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54387    }
54388}
54389#[doc = "Vector reinterpret cast operation"]
54390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54391#[inline]
54392#[cfg(target_endian = "little")]
54393#[target_feature(enable = "neon")]
54394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54396#[cfg_attr(
54397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54398    assert_instr(nop)
54399)]
54400#[cfg_attr(
54401    not(target_arch = "arm"),
54402    stable(feature = "neon_intrinsics", since = "1.59.0")
54403)]
54404#[cfg_attr(
54405    target_arch = "arm",
54406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54407)]
54408pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54409    unsafe { transmute(a) }
54410}
54411#[doc = "Vector reinterpret cast operation"]
54412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54413#[inline]
54414#[cfg(target_endian = "big")]
54415#[target_feature(enable = "neon")]
54416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54418#[cfg_attr(
54419    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54420    assert_instr(nop)
54421)]
54422#[cfg_attr(
54423    not(target_arch = "arm"),
54424    stable(feature = "neon_intrinsics", since = "1.59.0")
54425)]
54426#[cfg_attr(
54427    target_arch = "arm",
54428    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54429)]
54430pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54431    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54432    unsafe {
54433        let ret_val: uint32x2_t = transmute(a);
54434        simd_shuffle!(ret_val, ret_val, [1, 0])
54435    }
54436}
54437#[doc = "Vector reinterpret cast operation"]
54438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54439#[inline]
54440#[cfg(target_endian = "little")]
54441#[target_feature(enable = "neon")]
54442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54444#[cfg_attr(
54445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54446    assert_instr(nop)
54447)]
54448#[cfg_attr(
54449    not(target_arch = "arm"),
54450    stable(feature = "neon_intrinsics", since = "1.59.0")
54451)]
54452#[cfg_attr(
54453    target_arch = "arm",
54454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54455)]
54456pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54457    unsafe { transmute(a) }
54458}
54459#[doc = "Vector reinterpret cast operation"]
54460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54461#[inline]
54462#[cfg(target_endian = "big")]
54463#[target_feature(enable = "neon")]
54464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54466#[cfg_attr(
54467    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54468    assert_instr(nop)
54469)]
54470#[cfg_attr(
54471    not(target_arch = "arm"),
54472    stable(feature = "neon_intrinsics", since = "1.59.0")
54473)]
54474#[cfg_attr(
54475    target_arch = "arm",
54476    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54477)]
54478pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54479    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54480    unsafe { transmute(a) }
54481}
54482#[doc = "Vector reinterpret cast operation"]
54483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54484#[inline]
54485#[cfg(target_endian = "little")]
54486#[target_feature(enable = "neon")]
54487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54489#[cfg_attr(
54490    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54491    assert_instr(nop)
54492)]
54493#[cfg_attr(
54494    not(target_arch = "arm"),
54495    stable(feature = "neon_intrinsics", since = "1.59.0")
54496)]
54497#[cfg_attr(
54498    target_arch = "arm",
54499    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54500)]
54501pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54502    unsafe { transmute(a) }
54503}
54504#[doc = "Vector reinterpret cast operation"]
54505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54506#[inline]
54507#[cfg(target_endian = "big")]
54508#[target_feature(enable = "neon")]
54509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54511#[cfg_attr(
54512    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54513    assert_instr(nop)
54514)]
54515#[cfg_attr(
54516    not(target_arch = "arm"),
54517    stable(feature = "neon_intrinsics", since = "1.59.0")
54518)]
54519#[cfg_attr(
54520    target_arch = "arm",
54521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54522)]
54523pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54524    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54525    unsafe {
54526        let ret_val: poly8x8_t = transmute(a);
54527        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54528    }
54529}
54530#[doc = "Vector reinterpret cast operation"]
54531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54532#[inline]
54533#[cfg(target_endian = "little")]
54534#[target_feature(enable = "neon")]
54535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54537#[cfg_attr(
54538    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54539    assert_instr(nop)
54540)]
54541#[cfg_attr(
54542    not(target_arch = "arm"),
54543    stable(feature = "neon_intrinsics", since = "1.59.0")
54544)]
54545#[cfg_attr(
54546    target_arch = "arm",
54547    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54548)]
54549pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54550    unsafe { transmute(a) }
54551}
54552#[doc = "Vector reinterpret cast operation"]
54553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54554#[inline]
54555#[cfg(target_endian = "big")]
54556#[target_feature(enable = "neon")]
54557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54559#[cfg_attr(
54560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54561    assert_instr(nop)
54562)]
54563#[cfg_attr(
54564    not(target_arch = "arm"),
54565    stable(feature = "neon_intrinsics", since = "1.59.0")
54566)]
54567#[cfg_attr(
54568    target_arch = "arm",
54569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54570)]
54571pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54572    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54573    unsafe {
54574        let ret_val: float32x4_t = transmute(a);
54575        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54576    }
54577}
54578#[doc = "Vector reinterpret cast operation"]
54579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54580#[inline]
54581#[cfg(target_endian = "little")]
54582#[target_feature(enable = "neon")]
54583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54585#[cfg_attr(
54586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54587    assert_instr(nop)
54588)]
54589#[cfg_attr(
54590    not(target_arch = "arm"),
54591    stable(feature = "neon_intrinsics", since = "1.59.0")
54592)]
54593#[cfg_attr(
54594    target_arch = "arm",
54595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54596)]
54597pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54598    unsafe { transmute(a) }
54599}
54600#[doc = "Vector reinterpret cast operation"]
54601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54602#[inline]
54603#[cfg(target_endian = "big")]
54604#[target_feature(enable = "neon")]
54605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54607#[cfg_attr(
54608    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54609    assert_instr(nop)
54610)]
54611#[cfg_attr(
54612    not(target_arch = "arm"),
54613    stable(feature = "neon_intrinsics", since = "1.59.0")
54614)]
54615#[cfg_attr(
54616    target_arch = "arm",
54617    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54618)]
54619pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54620    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54621    unsafe {
54622        let ret_val: int8x16_t = transmute(a);
54623        simd_shuffle!(
54624            ret_val,
54625            ret_val,
54626            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54627        )
54628    }
54629}
54630#[doc = "Vector reinterpret cast operation"]
54631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54632#[inline]
54633#[cfg(target_endian = "little")]
54634#[target_feature(enable = "neon")]
54635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54637#[cfg_attr(
54638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54639    assert_instr(nop)
54640)]
54641#[cfg_attr(
54642    not(target_arch = "arm"),
54643    stable(feature = "neon_intrinsics", since = "1.59.0")
54644)]
54645#[cfg_attr(
54646    target_arch = "arm",
54647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54648)]
54649pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54650    unsafe { transmute(a) }
54651}
54652#[doc = "Vector reinterpret cast operation"]
54653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54654#[inline]
54655#[cfg(target_endian = "big")]
54656#[target_feature(enable = "neon")]
54657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54659#[cfg_attr(
54660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54661    assert_instr(nop)
54662)]
54663#[cfg_attr(
54664    not(target_arch = "arm"),
54665    stable(feature = "neon_intrinsics", since = "1.59.0")
54666)]
54667#[cfg_attr(
54668    target_arch = "arm",
54669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54670)]
54671pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54672    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54673    unsafe {
54674        let ret_val: int16x8_t = transmute(a);
54675        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54676    }
54677}
54678#[doc = "Vector reinterpret cast operation"]
54679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54680#[inline]
54681#[cfg(target_endian = "little")]
54682#[target_feature(enable = "neon")]
54683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54685#[cfg_attr(
54686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54687    assert_instr(nop)
54688)]
54689#[cfg_attr(
54690    not(target_arch = "arm"),
54691    stable(feature = "neon_intrinsics", since = "1.59.0")
54692)]
54693#[cfg_attr(
54694    target_arch = "arm",
54695    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54696)]
54697pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54698    unsafe { transmute(a) }
54699}
54700#[doc = "Vector reinterpret cast operation"]
54701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54702#[inline]
54703#[cfg(target_endian = "big")]
54704#[target_feature(enable = "neon")]
54705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54707#[cfg_attr(
54708    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54709    assert_instr(nop)
54710)]
54711#[cfg_attr(
54712    not(target_arch = "arm"),
54713    stable(feature = "neon_intrinsics", since = "1.59.0")
54714)]
54715#[cfg_attr(
54716    target_arch = "arm",
54717    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54718)]
54719pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54720    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54721    unsafe {
54722        let ret_val: int32x4_t = transmute(a);
54723        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54724    }
54725}
54726#[doc = "Vector reinterpret cast operation"]
54727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54728#[inline]
54729#[cfg(target_endian = "little")]
54730#[target_feature(enable = "neon")]
54731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54733#[cfg_attr(
54734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54735    assert_instr(nop)
54736)]
54737#[cfg_attr(
54738    not(target_arch = "arm"),
54739    stable(feature = "neon_intrinsics", since = "1.59.0")
54740)]
54741#[cfg_attr(
54742    target_arch = "arm",
54743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54744)]
54745pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54746    unsafe { transmute(a) }
54747}
54748#[doc = "Vector reinterpret cast operation"]
54749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54750#[inline]
54751#[cfg(target_endian = "big")]
54752#[target_feature(enable = "neon")]
54753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54755#[cfg_attr(
54756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54757    assert_instr(nop)
54758)]
54759#[cfg_attr(
54760    not(target_arch = "arm"),
54761    stable(feature = "neon_intrinsics", since = "1.59.0")
54762)]
54763#[cfg_attr(
54764    target_arch = "arm",
54765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54766)]
54767pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54768    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54769    unsafe {
54770        let ret_val: int64x2_t = transmute(a);
54771        simd_shuffle!(ret_val, ret_val, [1, 0])
54772    }
54773}
54774#[doc = "Vector reinterpret cast operation"]
54775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54776#[inline]
54777#[cfg(target_endian = "little")]
54778#[target_feature(enable = "neon")]
54779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54781#[cfg_attr(
54782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54783    assert_instr(nop)
54784)]
54785#[cfg_attr(
54786    not(target_arch = "arm"),
54787    stable(feature = "neon_intrinsics", since = "1.59.0")
54788)]
54789#[cfg_attr(
54790    target_arch = "arm",
54791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54792)]
54793pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54794    unsafe { transmute(a) }
54795}
54796#[doc = "Vector reinterpret cast operation"]
54797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54798#[inline]
54799#[cfg(target_endian = "big")]
54800#[target_feature(enable = "neon")]
54801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54803#[cfg_attr(
54804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54805    assert_instr(nop)
54806)]
54807#[cfg_attr(
54808    not(target_arch = "arm"),
54809    stable(feature = "neon_intrinsics", since = "1.59.0")
54810)]
54811#[cfg_attr(
54812    target_arch = "arm",
54813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54814)]
54815pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54816    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54817    unsafe {
54818        let ret_val: uint8x16_t = transmute(a);
54819        simd_shuffle!(
54820            ret_val,
54821            ret_val,
54822            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54823        )
54824    }
54825}
54826#[doc = "Vector reinterpret cast operation"]
54827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54828#[inline]
54829#[cfg(target_endian = "little")]
54830#[target_feature(enable = "neon")]
54831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54833#[cfg_attr(
54834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54835    assert_instr(nop)
54836)]
54837#[cfg_attr(
54838    not(target_arch = "arm"),
54839    stable(feature = "neon_intrinsics", since = "1.59.0")
54840)]
54841#[cfg_attr(
54842    target_arch = "arm",
54843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54844)]
54845pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54846    unsafe { transmute(a) }
54847}
54848#[doc = "Vector reinterpret cast operation"]
54849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54850#[inline]
54851#[cfg(target_endian = "big")]
54852#[target_feature(enable = "neon")]
54853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54855#[cfg_attr(
54856    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54857    assert_instr(nop)
54858)]
54859#[cfg_attr(
54860    not(target_arch = "arm"),
54861    stable(feature = "neon_intrinsics", since = "1.59.0")
54862)]
54863#[cfg_attr(
54864    target_arch = "arm",
54865    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54866)]
54867pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54868    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54869    unsafe {
54870        let ret_val: uint16x8_t = transmute(a);
54871        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54872    }
54873}
54874#[doc = "Vector reinterpret cast operation"]
54875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54876#[inline]
54877#[cfg(target_endian = "little")]
54878#[target_feature(enable = "neon")]
54879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54881#[cfg_attr(
54882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54883    assert_instr(nop)
54884)]
54885#[cfg_attr(
54886    not(target_arch = "arm"),
54887    stable(feature = "neon_intrinsics", since = "1.59.0")
54888)]
54889#[cfg_attr(
54890    target_arch = "arm",
54891    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54892)]
54893pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54894    unsafe { transmute(a) }
54895}
54896#[doc = "Vector reinterpret cast operation"]
54897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54898#[inline]
54899#[cfg(target_endian = "big")]
54900#[target_feature(enable = "neon")]
54901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54903#[cfg_attr(
54904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54905    assert_instr(nop)
54906)]
54907#[cfg_attr(
54908    not(target_arch = "arm"),
54909    stable(feature = "neon_intrinsics", since = "1.59.0")
54910)]
54911#[cfg_attr(
54912    target_arch = "arm",
54913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54914)]
54915pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54916    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54917    unsafe {
54918        let ret_val: uint32x4_t = transmute(a);
54919        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54920    }
54921}
54922#[doc = "Vector reinterpret cast operation"]
54923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54924#[inline]
54925#[cfg(target_endian = "little")]
54926#[target_feature(enable = "neon")]
54927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54929#[cfg_attr(
54930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54931    assert_instr(nop)
54932)]
54933#[cfg_attr(
54934    not(target_arch = "arm"),
54935    stable(feature = "neon_intrinsics", since = "1.59.0")
54936)]
54937#[cfg_attr(
54938    target_arch = "arm",
54939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54940)]
54941pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54942    unsafe { transmute(a) }
54943}
54944#[doc = "Vector reinterpret cast operation"]
54945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54946#[inline]
54947#[cfg(target_endian = "big")]
54948#[target_feature(enable = "neon")]
54949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54951#[cfg_attr(
54952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54953    assert_instr(nop)
54954)]
54955#[cfg_attr(
54956    not(target_arch = "arm"),
54957    stable(feature = "neon_intrinsics", since = "1.59.0")
54958)]
54959#[cfg_attr(
54960    target_arch = "arm",
54961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54962)]
54963pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54964    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54965    unsafe {
54966        let ret_val: uint64x2_t = transmute(a);
54967        simd_shuffle!(ret_val, ret_val, [1, 0])
54968    }
54969}
54970#[doc = "Vector reinterpret cast operation"]
54971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54972#[inline]
54973#[cfg(target_endian = "little")]
54974#[target_feature(enable = "neon")]
54975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54977#[cfg_attr(
54978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54979    assert_instr(nop)
54980)]
54981#[cfg_attr(
54982    not(target_arch = "arm"),
54983    stable(feature = "neon_intrinsics", since = "1.59.0")
54984)]
54985#[cfg_attr(
54986    target_arch = "arm",
54987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54988)]
54989pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54990    unsafe { transmute(a) }
54991}
54992#[doc = "Vector reinterpret cast operation"]
54993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54994#[inline]
54995#[cfg(target_endian = "big")]
54996#[target_feature(enable = "neon")]
54997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54999#[cfg_attr(
55000    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55001    assert_instr(nop)
55002)]
55003#[cfg_attr(
55004    not(target_arch = "arm"),
55005    stable(feature = "neon_intrinsics", since = "1.59.0")
55006)]
55007#[cfg_attr(
55008    target_arch = "arm",
55009    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55010)]
55011pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
55012    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55013    unsafe {
55014        let ret_val: poly8x16_t = transmute(a);
55015        simd_shuffle!(
55016            ret_val,
55017            ret_val,
55018            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55019        )
55020    }
55021}
55022#[doc = "Vector reinterpret cast operation"]
55023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
55024#[inline]
55025#[cfg(target_endian = "little")]
55026#[target_feature(enable = "neon,aes")]
55027#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55029#[cfg_attr(
55030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55031    assert_instr(nop)
55032)]
55033#[cfg_attr(
55034    not(target_arch = "arm"),
55035    stable(feature = "neon_intrinsics", since = "1.59.0")
55036)]
55037#[cfg_attr(
55038    target_arch = "arm",
55039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55040)]
55041pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
55042    unsafe { transmute(a) }
55043}
55044#[doc = "Vector reinterpret cast operation"]
55045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
55046#[inline]
55047#[cfg(target_endian = "big")]
55048#[target_feature(enable = "neon,aes")]
55049#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55051#[cfg_attr(
55052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55053    assert_instr(nop)
55054)]
55055#[cfg_attr(
55056    not(target_arch = "arm"),
55057    stable(feature = "neon_intrinsics", since = "1.59.0")
55058)]
55059#[cfg_attr(
55060    target_arch = "arm",
55061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55062)]
55063pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
55064    unsafe {
55065        let ret_val: int8x16_t = transmute(a);
55066        simd_shuffle!(
55067            ret_val,
55068            ret_val,
55069            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55070        )
55071    }
55072}
55073#[doc = "Vector reinterpret cast operation"]
55074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
55075#[inline]
55076#[cfg(target_endian = "little")]
55077#[target_feature(enable = "neon,aes")]
55078#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55080#[cfg_attr(
55081    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55082    assert_instr(nop)
55083)]
55084#[cfg_attr(
55085    not(target_arch = "arm"),
55086    stable(feature = "neon_intrinsics", since = "1.59.0")
55087)]
55088#[cfg_attr(
55089    target_arch = "arm",
55090    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55091)]
55092pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55093    unsafe { transmute(a) }
55094}
55095#[doc = "Vector reinterpret cast operation"]
55096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
55097#[inline]
55098#[cfg(target_endian = "big")]
55099#[target_feature(enable = "neon,aes")]
55100#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55102#[cfg_attr(
55103    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55104    assert_instr(nop)
55105)]
55106#[cfg_attr(
55107    not(target_arch = "arm"),
55108    stable(feature = "neon_intrinsics", since = "1.59.0")
55109)]
55110#[cfg_attr(
55111    target_arch = "arm",
55112    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55113)]
55114pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55115    unsafe {
55116        let ret_val: int16x8_t = transmute(a);
55117        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55118    }
55119}
55120#[doc = "Vector reinterpret cast operation"]
55121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55122#[inline]
55123#[cfg(target_endian = "little")]
55124#[target_feature(enable = "neon,aes")]
55125#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55127#[cfg_attr(
55128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55129    assert_instr(nop)
55130)]
55131#[cfg_attr(
55132    not(target_arch = "arm"),
55133    stable(feature = "neon_intrinsics", since = "1.59.0")
55134)]
55135#[cfg_attr(
55136    target_arch = "arm",
55137    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55138)]
55139pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55140    unsafe { transmute(a) }
55141}
55142#[doc = "Vector reinterpret cast operation"]
55143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55144#[inline]
55145#[cfg(target_endian = "big")]
55146#[target_feature(enable = "neon,aes")]
55147#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55149#[cfg_attr(
55150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55151    assert_instr(nop)
55152)]
55153#[cfg_attr(
55154    not(target_arch = "arm"),
55155    stable(feature = "neon_intrinsics", since = "1.59.0")
55156)]
55157#[cfg_attr(
55158    target_arch = "arm",
55159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55160)]
55161pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55162    unsafe {
55163        let ret_val: int32x4_t = transmute(a);
55164        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55165    }
55166}
55167#[doc = "Vector reinterpret cast operation"]
55168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55169#[inline]
55170#[cfg(target_endian = "little")]
55171#[target_feature(enable = "neon,aes")]
55172#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55174#[cfg_attr(
55175    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55176    assert_instr(nop)
55177)]
55178#[cfg_attr(
55179    not(target_arch = "arm"),
55180    stable(feature = "neon_intrinsics", since = "1.59.0")
55181)]
55182#[cfg_attr(
55183    target_arch = "arm",
55184    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55185)]
55186pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55187    unsafe { transmute(a) }
55188}
55189#[doc = "Vector reinterpret cast operation"]
55190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55191#[inline]
55192#[cfg(target_endian = "big")]
55193#[target_feature(enable = "neon,aes")]
55194#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55196#[cfg_attr(
55197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55198    assert_instr(nop)
55199)]
55200#[cfg_attr(
55201    not(target_arch = "arm"),
55202    stable(feature = "neon_intrinsics", since = "1.59.0")
55203)]
55204#[cfg_attr(
55205    target_arch = "arm",
55206    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55207)]
55208pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55209    unsafe {
55210        let ret_val: int64x2_t = transmute(a);
55211        simd_shuffle!(ret_val, ret_val, [1, 0])
55212    }
55213}
55214#[doc = "Vector reinterpret cast operation"]
55215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55216#[inline]
55217#[cfg(target_endian = "little")]
55218#[target_feature(enable = "neon,aes")]
55219#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55221#[cfg_attr(
55222    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55223    assert_instr(nop)
55224)]
55225#[cfg_attr(
55226    not(target_arch = "arm"),
55227    stable(feature = "neon_intrinsics", since = "1.59.0")
55228)]
55229#[cfg_attr(
55230    target_arch = "arm",
55231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55232)]
55233pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55234    unsafe { transmute(a) }
55235}
55236#[doc = "Vector reinterpret cast operation"]
55237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55238#[inline]
55239#[cfg(target_endian = "big")]
55240#[target_feature(enable = "neon,aes")]
55241#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55243#[cfg_attr(
55244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55245    assert_instr(nop)
55246)]
55247#[cfg_attr(
55248    not(target_arch = "arm"),
55249    stable(feature = "neon_intrinsics", since = "1.59.0")
55250)]
55251#[cfg_attr(
55252    target_arch = "arm",
55253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55254)]
55255pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55256    unsafe {
55257        let ret_val: uint8x16_t = transmute(a);
55258        simd_shuffle!(
55259            ret_val,
55260            ret_val,
55261            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55262        )
55263    }
55264}
55265#[doc = "Vector reinterpret cast operation"]
55266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55267#[inline]
55268#[cfg(target_endian = "little")]
55269#[target_feature(enable = "neon,aes")]
55270#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55272#[cfg_attr(
55273    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55274    assert_instr(nop)
55275)]
55276#[cfg_attr(
55277    not(target_arch = "arm"),
55278    stable(feature = "neon_intrinsics", since = "1.59.0")
55279)]
55280#[cfg_attr(
55281    target_arch = "arm",
55282    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55283)]
55284pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55285    unsafe { transmute(a) }
55286}
55287#[doc = "Vector reinterpret cast operation"]
55288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55289#[inline]
55290#[cfg(target_endian = "big")]
55291#[target_feature(enable = "neon,aes")]
55292#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55294#[cfg_attr(
55295    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55296    assert_instr(nop)
55297)]
55298#[cfg_attr(
55299    not(target_arch = "arm"),
55300    stable(feature = "neon_intrinsics", since = "1.59.0")
55301)]
55302#[cfg_attr(
55303    target_arch = "arm",
55304    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55305)]
55306pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55307    unsafe {
55308        let ret_val: uint16x8_t = transmute(a);
55309        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55310    }
55311}
55312#[doc = "Vector reinterpret cast operation"]
55313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55314#[inline]
55315#[cfg(target_endian = "little")]
55316#[target_feature(enable = "neon,aes")]
55317#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55319#[cfg_attr(
55320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55321    assert_instr(nop)
55322)]
55323#[cfg_attr(
55324    not(target_arch = "arm"),
55325    stable(feature = "neon_intrinsics", since = "1.59.0")
55326)]
55327#[cfg_attr(
55328    target_arch = "arm",
55329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55330)]
55331pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55332    unsafe { transmute(a) }
55333}
55334#[doc = "Vector reinterpret cast operation"]
55335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55336#[inline]
55337#[cfg(target_endian = "big")]
55338#[target_feature(enable = "neon,aes")]
55339#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55341#[cfg_attr(
55342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55343    assert_instr(nop)
55344)]
55345#[cfg_attr(
55346    not(target_arch = "arm"),
55347    stable(feature = "neon_intrinsics", since = "1.59.0")
55348)]
55349#[cfg_attr(
55350    target_arch = "arm",
55351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55352)]
55353pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55354    unsafe {
55355        let ret_val: uint32x4_t = transmute(a);
55356        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55357    }
55358}
55359#[doc = "Vector reinterpret cast operation"]
55360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55361#[inline]
55362#[cfg(target_endian = "little")]
55363#[target_feature(enable = "neon,aes")]
55364#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55366#[cfg_attr(
55367    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55368    assert_instr(nop)
55369)]
55370#[cfg_attr(
55371    not(target_arch = "arm"),
55372    stable(feature = "neon_intrinsics", since = "1.59.0")
55373)]
55374#[cfg_attr(
55375    target_arch = "arm",
55376    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55377)]
55378pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55379    unsafe { transmute(a) }
55380}
55381#[doc = "Vector reinterpret cast operation"]
55382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55383#[inline]
55384#[cfg(target_endian = "big")]
55385#[target_feature(enable = "neon,aes")]
55386#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55388#[cfg_attr(
55389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55390    assert_instr(nop)
55391)]
55392#[cfg_attr(
55393    not(target_arch = "arm"),
55394    stable(feature = "neon_intrinsics", since = "1.59.0")
55395)]
55396#[cfg_attr(
55397    target_arch = "arm",
55398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55399)]
55400pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55401    unsafe {
55402        let ret_val: uint64x2_t = transmute(a);
55403        simd_shuffle!(ret_val, ret_val, [1, 0])
55404    }
55405}
55406#[doc = "Vector reinterpret cast operation"]
55407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55408#[inline]
55409#[cfg(target_endian = "little")]
55410#[target_feature(enable = "neon,aes")]
55411#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55413#[cfg_attr(
55414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55415    assert_instr(nop)
55416)]
55417#[cfg_attr(
55418    not(target_arch = "arm"),
55419    stable(feature = "neon_intrinsics", since = "1.59.0")
55420)]
55421#[cfg_attr(
55422    target_arch = "arm",
55423    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55424)]
55425pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55426    unsafe { transmute(a) }
55427}
55428#[doc = "Vector reinterpret cast operation"]
55429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55430#[inline]
55431#[cfg(target_endian = "big")]
55432#[target_feature(enable = "neon,aes")]
55433#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55435#[cfg_attr(
55436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55437    assert_instr(nop)
55438)]
55439#[cfg_attr(
55440    not(target_arch = "arm"),
55441    stable(feature = "neon_intrinsics", since = "1.59.0")
55442)]
55443#[cfg_attr(
55444    target_arch = "arm",
55445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55446)]
55447pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55448    unsafe {
55449        let ret_val: poly8x16_t = transmute(a);
55450        simd_shuffle!(
55451            ret_val,
55452            ret_val,
55453            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55454        )
55455    }
55456}
55457#[doc = "Vector reinterpret cast operation"]
55458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55459#[inline]
55460#[cfg(target_endian = "little")]
55461#[target_feature(enable = "neon,aes")]
55462#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55464#[cfg_attr(
55465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55466    assert_instr(nop)
55467)]
55468#[cfg_attr(
55469    not(target_arch = "arm"),
55470    stable(feature = "neon_intrinsics", since = "1.59.0")
55471)]
55472#[cfg_attr(
55473    target_arch = "arm",
55474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55475)]
55476pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55477    unsafe { transmute(a) }
55478}
55479#[doc = "Vector reinterpret cast operation"]
55480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55481#[inline]
55482#[cfg(target_endian = "big")]
55483#[target_feature(enable = "neon,aes")]
55484#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55486#[cfg_attr(
55487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55488    assert_instr(nop)
55489)]
55490#[cfg_attr(
55491    not(target_arch = "arm"),
55492    stable(feature = "neon_intrinsics", since = "1.59.0")
55493)]
55494#[cfg_attr(
55495    target_arch = "arm",
55496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55497)]
55498pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55499    unsafe {
55500        let ret_val: poly16x8_t = transmute(a);
55501        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55502    }
55503}
55504#[doc = "Vector reinterpret cast operation"]
55505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55506#[inline]
55507#[cfg(target_endian = "little")]
55508#[target_feature(enable = "neon,aes")]
55509#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55511#[cfg_attr(
55512    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55513    assert_instr(nop)
55514)]
55515#[cfg_attr(
55516    not(target_arch = "arm"),
55517    stable(feature = "neon_intrinsics", since = "1.59.0")
55518)]
55519#[cfg_attr(
55520    target_arch = "arm",
55521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55522)]
55523pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55524    unsafe { transmute(a) }
55525}
55526#[doc = "Vector reinterpret cast operation"]
55527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55528#[inline]
55529#[cfg(target_endian = "big")]
55530#[target_feature(enable = "neon,aes")]
55531#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55533#[cfg_attr(
55534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55535    assert_instr(nop)
55536)]
55537#[cfg_attr(
55538    not(target_arch = "arm"),
55539    stable(feature = "neon_intrinsics", since = "1.59.0")
55540)]
55541#[cfg_attr(
55542    target_arch = "arm",
55543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55544)]
55545pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55546    unsafe {
55547        let ret_val: poly64x2_t = transmute(a);
55548        simd_shuffle!(ret_val, ret_val, [1, 0])
55549    }
55550}
55551#[doc = "Vector reinterpret cast operation"]
55552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55553#[inline]
55554#[cfg(target_endian = "little")]
55555#[target_feature(enable = "neon,aes")]
55556#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55558#[cfg_attr(
55559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55560    assert_instr(nop)
55561)]
55562#[cfg_attr(
55563    not(target_arch = "arm"),
55564    stable(feature = "neon_intrinsics", since = "1.59.0")
55565)]
55566#[cfg_attr(
55567    target_arch = "arm",
55568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55569)]
55570pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55571    unsafe { transmute(a) }
55572}
55573#[doc = "Vector reinterpret cast operation"]
55574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55575#[inline]
55576#[cfg(target_endian = "big")]
55577#[target_feature(enable = "neon,aes")]
55578#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55580#[cfg_attr(
55581    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55582    assert_instr(nop)
55583)]
55584#[cfg_attr(
55585    not(target_arch = "arm"),
55586    stable(feature = "neon_intrinsics", since = "1.59.0")
55587)]
55588#[cfg_attr(
55589    target_arch = "arm",
55590    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55591)]
55592pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55593    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55594    unsafe { transmute(a) }
55595}
55596#[doc = "Vector reinterpret cast operation"]
55597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55598#[inline]
55599#[cfg(target_endian = "little")]
55600#[target_feature(enable = "neon,aes")]
55601#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55603#[cfg_attr(
55604    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55605    assert_instr(nop)
55606)]
55607#[cfg_attr(
55608    not(target_arch = "arm"),
55609    stable(feature = "neon_intrinsics", since = "1.59.0")
55610)]
55611#[cfg_attr(
55612    target_arch = "arm",
55613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55614)]
55615pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55616    unsafe { transmute(a) }
55617}
55618#[doc = "Vector reinterpret cast operation"]
55619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55620#[inline]
55621#[cfg(target_endian = "big")]
55622#[target_feature(enable = "neon,aes")]
55623#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55625#[cfg_attr(
55626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55627    assert_instr(nop)
55628)]
55629#[cfg_attr(
55630    not(target_arch = "arm"),
55631    stable(feature = "neon_intrinsics", since = "1.59.0")
55632)]
55633#[cfg_attr(
55634    target_arch = "arm",
55635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55636)]
55637pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55638    let a: int8x16_t =
55639        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55640    unsafe { transmute(a) }
55641}
55642#[doc = "Vector reinterpret cast operation"]
55643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55644#[inline]
55645#[cfg(target_endian = "little")]
55646#[target_feature(enable = "neon,aes")]
55647#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55649#[cfg_attr(
55650    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55651    assert_instr(nop)
55652)]
55653#[cfg_attr(
55654    not(target_arch = "arm"),
55655    stable(feature = "neon_intrinsics", since = "1.59.0")
55656)]
55657#[cfg_attr(
55658    target_arch = "arm",
55659    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55660)]
55661pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55662    unsafe { transmute(a) }
55663}
55664#[doc = "Vector reinterpret cast operation"]
55665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55666#[inline]
55667#[cfg(target_endian = "big")]
55668#[target_feature(enable = "neon,aes")]
55669#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55671#[cfg_attr(
55672    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55673    assert_instr(nop)
55674)]
55675#[cfg_attr(
55676    not(target_arch = "arm"),
55677    stable(feature = "neon_intrinsics", since = "1.59.0")
55678)]
55679#[cfg_attr(
55680    target_arch = "arm",
55681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55682)]
55683pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55684    let a: int8x16_t =
55685        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55686    unsafe {
55687        let ret_val: poly64x2_t = transmute(a);
55688        simd_shuffle!(ret_val, ret_val, [1, 0])
55689    }
55690}
55691#[doc = "Vector reinterpret cast operation"]
55692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55693#[inline]
55694#[cfg(target_endian = "little")]
55695#[target_feature(enable = "neon,aes")]
55696#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55698#[cfg_attr(
55699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55700    assert_instr(nop)
55701)]
55702#[cfg_attr(
55703    not(target_arch = "arm"),
55704    stable(feature = "neon_intrinsics", since = "1.59.0")
55705)]
55706#[cfg_attr(
55707    target_arch = "arm",
55708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55709)]
55710pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55711    unsafe { transmute(a) }
55712}
55713#[doc = "Vector reinterpret cast operation"]
55714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55715#[inline]
55716#[cfg(target_endian = "big")]
55717#[target_feature(enable = "neon,aes")]
55718#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55720#[cfg_attr(
55721    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55722    assert_instr(nop)
55723)]
55724#[cfg_attr(
55725    not(target_arch = "arm"),
55726    stable(feature = "neon_intrinsics", since = "1.59.0")
55727)]
55728#[cfg_attr(
55729    target_arch = "arm",
55730    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55731)]
55732pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55733    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55734    unsafe { transmute(a) }
55735}
55736#[doc = "Vector reinterpret cast operation"]
55737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55738#[inline]
55739#[cfg(target_endian = "little")]
55740#[target_feature(enable = "neon,aes")]
55741#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55743#[cfg_attr(
55744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55745    assert_instr(nop)
55746)]
55747#[cfg_attr(
55748    not(target_arch = "arm"),
55749    stable(feature = "neon_intrinsics", since = "1.59.0")
55750)]
55751#[cfg_attr(
55752    target_arch = "arm",
55753    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55754)]
55755pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55756    unsafe { transmute(a) }
55757}
55758#[doc = "Vector reinterpret cast operation"]
55759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55760#[inline]
55761#[cfg(target_endian = "big")]
55762#[target_feature(enable = "neon,aes")]
55763#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55765#[cfg_attr(
55766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55767    assert_instr(nop)
55768)]
55769#[cfg_attr(
55770    not(target_arch = "arm"),
55771    stable(feature = "neon_intrinsics", since = "1.59.0")
55772)]
55773#[cfg_attr(
55774    target_arch = "arm",
55775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55776)]
55777pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55778    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55779    unsafe { transmute(a) }
55780}
55781#[doc = "Vector reinterpret cast operation"]
55782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55783#[inline]
55784#[cfg(target_endian = "little")]
55785#[target_feature(enable = "neon,aes")]
55786#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55788#[cfg_attr(
55789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55790    assert_instr(nop)
55791)]
55792#[cfg_attr(
55793    not(target_arch = "arm"),
55794    stable(feature = "neon_intrinsics", since = "1.59.0")
55795)]
55796#[cfg_attr(
55797    target_arch = "arm",
55798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55799)]
55800pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55801    unsafe { transmute(a) }
55802}
55803#[doc = "Vector reinterpret cast operation"]
55804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55805#[inline]
55806#[cfg(target_endian = "big")]
55807#[target_feature(enable = "neon,aes")]
55808#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55810#[cfg_attr(
55811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55812    assert_instr(nop)
55813)]
55814#[cfg_attr(
55815    not(target_arch = "arm"),
55816    stable(feature = "neon_intrinsics", since = "1.59.0")
55817)]
55818#[cfg_attr(
55819    target_arch = "arm",
55820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55821)]
55822pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55823    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55824    unsafe {
55825        let ret_val: poly64x2_t = transmute(a);
55826        simd_shuffle!(ret_val, ret_val, [1, 0])
55827    }
55828}
55829#[doc = "Vector reinterpret cast operation"]
55830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55831#[inline]
55832#[cfg(target_endian = "little")]
55833#[target_feature(enable = "neon,aes")]
55834#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55836#[cfg_attr(
55837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55838    assert_instr(nop)
55839)]
55840#[cfg_attr(
55841    not(target_arch = "arm"),
55842    stable(feature = "neon_intrinsics", since = "1.59.0")
55843)]
55844#[cfg_attr(
55845    target_arch = "arm",
55846    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55847)]
55848pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55849    unsafe { transmute(a) }
55850}
55851#[doc = "Vector reinterpret cast operation"]
55852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55853#[inline]
55854#[cfg(target_endian = "big")]
55855#[target_feature(enable = "neon,aes")]
55856#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55858#[cfg_attr(
55859    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55860    assert_instr(nop)
55861)]
55862#[cfg_attr(
55863    not(target_arch = "arm"),
55864    stable(feature = "neon_intrinsics", since = "1.59.0")
55865)]
55866#[cfg_attr(
55867    target_arch = "arm",
55868    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55869)]
55870pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55871    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55872    unsafe { transmute(a) }
55873}
55874#[doc = "Vector reinterpret cast operation"]
55875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55876#[inline]
55877#[cfg(target_endian = "little")]
55878#[target_feature(enable = "neon,aes")]
55879#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55881#[cfg_attr(
55882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55883    assert_instr(nop)
55884)]
55885#[cfg_attr(
55886    not(target_arch = "arm"),
55887    stable(feature = "neon_intrinsics", since = "1.59.0")
55888)]
55889#[cfg_attr(
55890    target_arch = "arm",
55891    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55892)]
55893pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55894    unsafe { transmute(a) }
55895}
55896#[doc = "Vector reinterpret cast operation"]
55897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55898#[inline]
55899#[cfg(target_endian = "big")]
55900#[target_feature(enable = "neon,aes")]
55901#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55903#[cfg_attr(
55904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55905    assert_instr(nop)
55906)]
55907#[cfg_attr(
55908    not(target_arch = "arm"),
55909    stable(feature = "neon_intrinsics", since = "1.59.0")
55910)]
55911#[cfg_attr(
55912    target_arch = "arm",
55913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55914)]
55915pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55916    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55917    unsafe { transmute(a) }
55918}
55919#[doc = "Vector reinterpret cast operation"]
55920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55921#[inline]
55922#[cfg(target_endian = "little")]
55923#[target_feature(enable = "neon,aes")]
55924#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55926#[cfg_attr(
55927    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55928    assert_instr(nop)
55929)]
55930#[cfg_attr(
55931    not(target_arch = "arm"),
55932    stable(feature = "neon_intrinsics", since = "1.59.0")
55933)]
55934#[cfg_attr(
55935    target_arch = "arm",
55936    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55937)]
55938pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55939    unsafe { transmute(a) }
55940}
55941#[doc = "Vector reinterpret cast operation"]
55942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55943#[inline]
55944#[cfg(target_endian = "big")]
55945#[target_feature(enable = "neon,aes")]
55946#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55948#[cfg_attr(
55949    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55950    assert_instr(nop)
55951)]
55952#[cfg_attr(
55953    not(target_arch = "arm"),
55954    stable(feature = "neon_intrinsics", since = "1.59.0")
55955)]
55956#[cfg_attr(
55957    target_arch = "arm",
55958    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55959)]
55960pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55961    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55962    unsafe {
55963        let ret_val: poly64x2_t = transmute(a);
55964        simd_shuffle!(ret_val, ret_val, [1, 0])
55965    }
55966}
55967#[doc = "Vector reinterpret cast operation"]
55968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55969#[inline]
55970#[cfg(target_endian = "little")]
55971#[target_feature(enable = "neon,aes")]
55972#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55974#[cfg_attr(
55975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55976    assert_instr(nop)
55977)]
55978#[cfg_attr(
55979    not(target_arch = "arm"),
55980    stable(feature = "neon_intrinsics", since = "1.59.0")
55981)]
55982#[cfg_attr(
55983    target_arch = "arm",
55984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55985)]
55986pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55987    unsafe { transmute(a) }
55988}
55989#[doc = "Vector reinterpret cast operation"]
55990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55991#[inline]
55992#[cfg(target_endian = "big")]
55993#[target_feature(enable = "neon,aes")]
55994#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55996#[cfg_attr(
55997    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55998    assert_instr(nop)
55999)]
56000#[cfg_attr(
56001    not(target_arch = "arm"),
56002    stable(feature = "neon_intrinsics", since = "1.59.0")
56003)]
56004#[cfg_attr(
56005    target_arch = "arm",
56006    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56007)]
56008pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
56009    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56010    unsafe { transmute(a) }
56011}
56012#[doc = "Vector reinterpret cast operation"]
56013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
56014#[inline]
56015#[cfg(target_endian = "little")]
56016#[target_feature(enable = "neon,aes")]
56017#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56019#[cfg_attr(
56020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56021    assert_instr(nop)
56022)]
56023#[cfg_attr(
56024    not(target_arch = "arm"),
56025    stable(feature = "neon_intrinsics", since = "1.59.0")
56026)]
56027#[cfg_attr(
56028    target_arch = "arm",
56029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56030)]
56031pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
56032    unsafe { transmute(a) }
56033}
56034#[doc = "Vector reinterpret cast operation"]
56035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
56036#[inline]
56037#[cfg(target_endian = "big")]
56038#[target_feature(enable = "neon,aes")]
56039#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56041#[cfg_attr(
56042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56043    assert_instr(nop)
56044)]
56045#[cfg_attr(
56046    not(target_arch = "arm"),
56047    stable(feature = "neon_intrinsics", since = "1.59.0")
56048)]
56049#[cfg_attr(
56050    target_arch = "arm",
56051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56052)]
56053pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
56054    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56055    unsafe { transmute(a) }
56056}
56057#[doc = "Vector reinterpret cast operation"]
56058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
56059#[inline]
56060#[cfg(target_endian = "little")]
56061#[target_feature(enable = "neon,aes")]
56062#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56064#[cfg_attr(
56065    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56066    assert_instr(nop)
56067)]
56068#[cfg_attr(
56069    not(target_arch = "arm"),
56070    stable(feature = "neon_intrinsics", since = "1.59.0")
56071)]
56072#[cfg_attr(
56073    target_arch = "arm",
56074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56075)]
56076pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
56077    unsafe { transmute(a) }
56078}
56079#[doc = "Vector reinterpret cast operation"]
56080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
56081#[inline]
56082#[cfg(target_endian = "big")]
56083#[target_feature(enable = "neon,aes")]
56084#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56086#[cfg_attr(
56087    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56088    assert_instr(nop)
56089)]
56090#[cfg_attr(
56091    not(target_arch = "arm"),
56092    stable(feature = "neon_intrinsics", since = "1.59.0")
56093)]
56094#[cfg_attr(
56095    target_arch = "arm",
56096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56097)]
56098pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
56099    let a: uint8x16_t =
56100        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56101    unsafe { transmute(a) }
56102}
56103#[doc = "Vector reinterpret cast operation"]
56104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56105#[inline]
56106#[cfg(target_endian = "little")]
56107#[target_feature(enable = "neon,aes")]
56108#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56110#[cfg_attr(
56111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56112    assert_instr(nop)
56113)]
56114#[cfg_attr(
56115    not(target_arch = "arm"),
56116    stable(feature = "neon_intrinsics", since = "1.59.0")
56117)]
56118#[cfg_attr(
56119    target_arch = "arm",
56120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56121)]
56122pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56123    unsafe { transmute(a) }
56124}
56125#[doc = "Vector reinterpret cast operation"]
56126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56127#[inline]
56128#[cfg(target_endian = "big")]
56129#[target_feature(enable = "neon,aes")]
56130#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56132#[cfg_attr(
56133    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56134    assert_instr(nop)
56135)]
56136#[cfg_attr(
56137    not(target_arch = "arm"),
56138    stable(feature = "neon_intrinsics", since = "1.59.0")
56139)]
56140#[cfg_attr(
56141    target_arch = "arm",
56142    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56143)]
56144pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56145    let a: uint8x16_t =
56146        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56147    unsafe {
56148        let ret_val: poly64x2_t = transmute(a);
56149        simd_shuffle!(ret_val, ret_val, [1, 0])
56150    }
56151}
56152#[doc = "Vector reinterpret cast operation"]
56153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56154#[inline]
56155#[cfg(target_endian = "little")]
56156#[target_feature(enable = "neon,aes")]
56157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56159#[cfg_attr(
56160    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56161    assert_instr(nop)
56162)]
56163#[cfg_attr(
56164    not(target_arch = "arm"),
56165    stable(feature = "neon_intrinsics", since = "1.59.0")
56166)]
56167#[cfg_attr(
56168    target_arch = "arm",
56169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56170)]
56171pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56172    unsafe { transmute(a) }
56173}
56174#[doc = "Vector reinterpret cast operation"]
56175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56176#[inline]
56177#[cfg(target_endian = "big")]
56178#[target_feature(enable = "neon,aes")]
56179#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56181#[cfg_attr(
56182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56183    assert_instr(nop)
56184)]
56185#[cfg_attr(
56186    not(target_arch = "arm"),
56187    stable(feature = "neon_intrinsics", since = "1.59.0")
56188)]
56189#[cfg_attr(
56190    target_arch = "arm",
56191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56192)]
56193pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56194    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56195    unsafe { transmute(a) }
56196}
56197#[doc = "Vector reinterpret cast operation"]
56198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56199#[inline]
56200#[cfg(target_endian = "little")]
56201#[target_feature(enable = "neon,aes")]
56202#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56204#[cfg_attr(
56205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56206    assert_instr(nop)
56207)]
56208#[cfg_attr(
56209    not(target_arch = "arm"),
56210    stable(feature = "neon_intrinsics", since = "1.59.0")
56211)]
56212#[cfg_attr(
56213    target_arch = "arm",
56214    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56215)]
56216pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56217    unsafe { transmute(a) }
56218}
56219#[doc = "Vector reinterpret cast operation"]
56220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56221#[inline]
56222#[cfg(target_endian = "big")]
56223#[target_feature(enable = "neon,aes")]
56224#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56226#[cfg_attr(
56227    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56228    assert_instr(nop)
56229)]
56230#[cfg_attr(
56231    not(target_arch = "arm"),
56232    stable(feature = "neon_intrinsics", since = "1.59.0")
56233)]
56234#[cfg_attr(
56235    target_arch = "arm",
56236    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56237)]
56238pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56239    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56240    unsafe { transmute(a) }
56241}
56242#[doc = "Vector reinterpret cast operation"]
56243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56244#[inline]
56245#[cfg(target_endian = "little")]
56246#[target_feature(enable = "neon,aes")]
56247#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56249#[cfg_attr(
56250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56251    assert_instr(nop)
56252)]
56253#[cfg_attr(
56254    not(target_arch = "arm"),
56255    stable(feature = "neon_intrinsics", since = "1.59.0")
56256)]
56257#[cfg_attr(
56258    target_arch = "arm",
56259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56260)]
56261pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56262    unsafe { transmute(a) }
56263}
56264#[doc = "Vector reinterpret cast operation"]
56265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56266#[inline]
56267#[cfg(target_endian = "big")]
56268#[target_feature(enable = "neon,aes")]
56269#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56271#[cfg_attr(
56272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56273    assert_instr(nop)
56274)]
56275#[cfg_attr(
56276    not(target_arch = "arm"),
56277    stable(feature = "neon_intrinsics", since = "1.59.0")
56278)]
56279#[cfg_attr(
56280    target_arch = "arm",
56281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56282)]
56283pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56284    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56285    unsafe {
56286        let ret_val: poly64x2_t = transmute(a);
56287        simd_shuffle!(ret_val, ret_val, [1, 0])
56288    }
56289}
56290#[doc = "Vector reinterpret cast operation"]
56291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56292#[inline]
56293#[cfg(target_endian = "little")]
56294#[target_feature(enable = "neon,aes")]
56295#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56297#[cfg_attr(
56298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56299    assert_instr(nop)
56300)]
56301#[cfg_attr(
56302    not(target_arch = "arm"),
56303    stable(feature = "neon_intrinsics", since = "1.59.0")
56304)]
56305#[cfg_attr(
56306    target_arch = "arm",
56307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56308)]
56309pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56310    unsafe { transmute(a) }
56311}
56312#[doc = "Vector reinterpret cast operation"]
56313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56314#[inline]
56315#[cfg(target_endian = "big")]
56316#[target_feature(enable = "neon,aes")]
56317#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56319#[cfg_attr(
56320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56321    assert_instr(nop)
56322)]
56323#[cfg_attr(
56324    not(target_arch = "arm"),
56325    stable(feature = "neon_intrinsics", since = "1.59.0")
56326)]
56327#[cfg_attr(
56328    target_arch = "arm",
56329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56330)]
56331pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56332    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56333    unsafe { transmute(a) }
56334}
56335#[doc = "Vector reinterpret cast operation"]
56336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56337#[inline]
56338#[cfg(target_endian = "little")]
56339#[target_feature(enable = "neon,aes")]
56340#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56342#[cfg_attr(
56343    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56344    assert_instr(nop)
56345)]
56346#[cfg_attr(
56347    not(target_arch = "arm"),
56348    stable(feature = "neon_intrinsics", since = "1.59.0")
56349)]
56350#[cfg_attr(
56351    target_arch = "arm",
56352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56353)]
56354pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56355    unsafe { transmute(a) }
56356}
56357#[doc = "Vector reinterpret cast operation"]
56358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56359#[inline]
56360#[cfg(target_endian = "big")]
56361#[target_feature(enable = "neon,aes")]
56362#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56364#[cfg_attr(
56365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56366    assert_instr(nop)
56367)]
56368#[cfg_attr(
56369    not(target_arch = "arm"),
56370    stable(feature = "neon_intrinsics", since = "1.59.0")
56371)]
56372#[cfg_attr(
56373    target_arch = "arm",
56374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56375)]
56376pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56377    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56378    unsafe { transmute(a) }
56379}
56380#[doc = "Vector reinterpret cast operation"]
56381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56382#[inline]
56383#[cfg(target_endian = "little")]
56384#[target_feature(enable = "neon,aes")]
56385#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56387#[cfg_attr(
56388    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56389    assert_instr(nop)
56390)]
56391#[cfg_attr(
56392    not(target_arch = "arm"),
56393    stable(feature = "neon_intrinsics", since = "1.59.0")
56394)]
56395#[cfg_attr(
56396    target_arch = "arm",
56397    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56398)]
56399pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56400    unsafe { transmute(a) }
56401}
56402#[doc = "Vector reinterpret cast operation"]
56403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56404#[inline]
56405#[cfg(target_endian = "big")]
56406#[target_feature(enable = "neon,aes")]
56407#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56409#[cfg_attr(
56410    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56411    assert_instr(nop)
56412)]
56413#[cfg_attr(
56414    not(target_arch = "arm"),
56415    stable(feature = "neon_intrinsics", since = "1.59.0")
56416)]
56417#[cfg_attr(
56418    target_arch = "arm",
56419    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56420)]
56421pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56422    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56423    unsafe {
56424        let ret_val: poly64x2_t = transmute(a);
56425        simd_shuffle!(ret_val, ret_val, [1, 0])
56426    }
56427}
56428#[doc = "Vector reinterpret cast operation"]
56429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56430#[inline]
56431#[cfg(target_endian = "little")]
56432#[target_feature(enable = "neon,aes")]
56433#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56435#[cfg_attr(
56436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56437    assert_instr(nop)
56438)]
56439#[cfg_attr(
56440    not(target_arch = "arm"),
56441    stable(feature = "neon_intrinsics", since = "1.59.0")
56442)]
56443#[cfg_attr(
56444    target_arch = "arm",
56445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56446)]
56447pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56448    unsafe { transmute(a) }
56449}
56450#[doc = "Vector reinterpret cast operation"]
56451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56452#[inline]
56453#[cfg(target_endian = "big")]
56454#[target_feature(enable = "neon,aes")]
56455#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56457#[cfg_attr(
56458    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56459    assert_instr(nop)
56460)]
56461#[cfg_attr(
56462    not(target_arch = "arm"),
56463    stable(feature = "neon_intrinsics", since = "1.59.0")
56464)]
56465#[cfg_attr(
56466    target_arch = "arm",
56467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56468)]
56469pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56470    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56471    unsafe { transmute(a) }
56472}
56473#[doc = "Vector reinterpret cast operation"]
56474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56475#[inline]
56476#[cfg(target_endian = "little")]
56477#[target_feature(enable = "neon,aes")]
56478#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56480#[cfg_attr(
56481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56482    assert_instr(nop)
56483)]
56484#[cfg_attr(
56485    not(target_arch = "arm"),
56486    stable(feature = "neon_intrinsics", since = "1.59.0")
56487)]
56488#[cfg_attr(
56489    target_arch = "arm",
56490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56491)]
56492pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56493    unsafe { transmute(a) }
56494}
56495#[doc = "Vector reinterpret cast operation"]
56496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56497#[inline]
56498#[cfg(target_endian = "big")]
56499#[target_feature(enable = "neon,aes")]
56500#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56502#[cfg_attr(
56503    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56504    assert_instr(nop)
56505)]
56506#[cfg_attr(
56507    not(target_arch = "arm"),
56508    stable(feature = "neon_intrinsics", since = "1.59.0")
56509)]
56510#[cfg_attr(
56511    target_arch = "arm",
56512    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56513)]
56514pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56515    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56516    unsafe { transmute(a) }
56517}
56518#[doc = "Vector reinterpret cast operation"]
56519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56520#[inline]
56521#[cfg(target_endian = "little")]
56522#[target_feature(enable = "neon,aes")]
56523#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56525#[cfg_attr(
56526    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56527    assert_instr(nop)
56528)]
56529#[cfg_attr(
56530    not(target_arch = "arm"),
56531    stable(feature = "neon_intrinsics", since = "1.59.0")
56532)]
56533#[cfg_attr(
56534    target_arch = "arm",
56535    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56536)]
56537pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56538    unsafe { transmute(a) }
56539}
56540#[doc = "Vector reinterpret cast operation"]
56541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56542#[inline]
56543#[cfg(target_endian = "big")]
56544#[target_feature(enable = "neon,aes")]
56545#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56547#[cfg_attr(
56548    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56549    assert_instr(nop)
56550)]
56551#[cfg_attr(
56552    not(target_arch = "arm"),
56553    stable(feature = "neon_intrinsics", since = "1.59.0")
56554)]
56555#[cfg_attr(
56556    target_arch = "arm",
56557    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56558)]
56559pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56560    let a: poly8x16_t =
56561        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56562    unsafe { transmute(a) }
56563}
56564#[doc = "Vector reinterpret cast operation"]
56565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56566#[inline]
56567#[cfg(target_endian = "little")]
56568#[target_feature(enable = "neon,aes")]
56569#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56571#[cfg_attr(
56572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56573    assert_instr(nop)
56574)]
56575#[cfg_attr(
56576    not(target_arch = "arm"),
56577    stable(feature = "neon_intrinsics", since = "1.59.0")
56578)]
56579#[cfg_attr(
56580    target_arch = "arm",
56581    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56582)]
56583pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56584    unsafe { transmute(a) }
56585}
56586#[doc = "Vector reinterpret cast operation"]
56587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56588#[inline]
56589#[cfg(target_endian = "big")]
56590#[target_feature(enable = "neon,aes")]
56591#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56593#[cfg_attr(
56594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56595    assert_instr(nop)
56596)]
56597#[cfg_attr(
56598    not(target_arch = "arm"),
56599    stable(feature = "neon_intrinsics", since = "1.59.0")
56600)]
56601#[cfg_attr(
56602    target_arch = "arm",
56603    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56604)]
56605pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56606    let a: poly8x16_t =
56607        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56608    unsafe {
56609        let ret_val: poly64x2_t = transmute(a);
56610        simd_shuffle!(ret_val, ret_val, [1, 0])
56611    }
56612}
56613#[doc = "Vector reinterpret cast operation"]
56614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56615#[inline]
56616#[cfg(target_endian = "little")]
56617#[target_feature(enable = "neon,aes")]
56618#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56620#[cfg_attr(
56621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56622    assert_instr(nop)
56623)]
56624#[cfg_attr(
56625    not(target_arch = "arm"),
56626    stable(feature = "neon_intrinsics", since = "1.59.0")
56627)]
56628#[cfg_attr(
56629    target_arch = "arm",
56630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56631)]
56632pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56633    unsafe { transmute(a) }
56634}
56635#[doc = "Vector reinterpret cast operation"]
56636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56637#[inline]
56638#[cfg(target_endian = "big")]
56639#[target_feature(enable = "neon,aes")]
56640#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56642#[cfg_attr(
56643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56644    assert_instr(nop)
56645)]
56646#[cfg_attr(
56647    not(target_arch = "arm"),
56648    stable(feature = "neon_intrinsics", since = "1.59.0")
56649)]
56650#[cfg_attr(
56651    target_arch = "arm",
56652    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56653)]
56654pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56655    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56656    unsafe { transmute(a) }
56657}
56658#[doc = "Vector reinterpret cast operation"]
56659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56660#[inline]
56661#[cfg(target_endian = "little")]
56662#[target_feature(enable = "neon,aes")]
56663#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56665#[cfg_attr(
56666    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56667    assert_instr(nop)
56668)]
56669#[cfg_attr(
56670    not(target_arch = "arm"),
56671    stable(feature = "neon_intrinsics", since = "1.59.0")
56672)]
56673#[cfg_attr(
56674    target_arch = "arm",
56675    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56676)]
56677pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56678    unsafe { transmute(a) }
56679}
56680#[doc = "Vector reinterpret cast operation"]
56681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56682#[inline]
56683#[cfg(target_endian = "big")]
56684#[target_feature(enable = "neon,aes")]
56685#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56687#[cfg_attr(
56688    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56689    assert_instr(nop)
56690)]
56691#[cfg_attr(
56692    not(target_arch = "arm"),
56693    stable(feature = "neon_intrinsics", since = "1.59.0")
56694)]
56695#[cfg_attr(
56696    target_arch = "arm",
56697    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56698)]
56699pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56700    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56701    unsafe { transmute(a) }
56702}
56703#[doc = "Vector reinterpret cast operation"]
56704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56705#[inline]
56706#[cfg(target_endian = "little")]
56707#[target_feature(enable = "neon,aes")]
56708#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56710#[cfg_attr(
56711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56712    assert_instr(nop)
56713)]
56714#[cfg_attr(
56715    not(target_arch = "arm"),
56716    stable(feature = "neon_intrinsics", since = "1.59.0")
56717)]
56718#[cfg_attr(
56719    target_arch = "arm",
56720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56721)]
56722pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56723    unsafe { transmute(a) }
56724}
56725#[doc = "Vector reinterpret cast operation"]
56726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56727#[inline]
56728#[cfg(target_endian = "big")]
56729#[target_feature(enable = "neon,aes")]
56730#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56732#[cfg_attr(
56733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56734    assert_instr(nop)
56735)]
56736#[cfg_attr(
56737    not(target_arch = "arm"),
56738    stable(feature = "neon_intrinsics", since = "1.59.0")
56739)]
56740#[cfg_attr(
56741    target_arch = "arm",
56742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56743)]
56744pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56745    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56746    unsafe {
56747        let ret_val: poly64x2_t = transmute(a);
56748        simd_shuffle!(ret_val, ret_val, [1, 0])
56749    }
56750}
56751#[doc = "Vector reinterpret cast operation"]
56752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56753#[inline]
56754#[cfg(target_endian = "little")]
56755#[target_feature(enable = "neon,aes")]
56756#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56758#[cfg_attr(
56759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56760    assert_instr(nop)
56761)]
56762#[cfg_attr(
56763    not(target_arch = "arm"),
56764    stable(feature = "neon_intrinsics", since = "1.59.0")
56765)]
56766#[cfg_attr(
56767    target_arch = "arm",
56768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56769)]
56770pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56771    unsafe { transmute(a) }
56772}
56773#[doc = "Vector reinterpret cast operation"]
56774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56775#[inline]
56776#[cfg(target_endian = "big")]
56777#[target_feature(enable = "neon,aes")]
56778#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56780#[cfg_attr(
56781    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56782    assert_instr(nop)
56783)]
56784#[cfg_attr(
56785    not(target_arch = "arm"),
56786    stable(feature = "neon_intrinsics", since = "1.59.0")
56787)]
56788#[cfg_attr(
56789    target_arch = "arm",
56790    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56791)]
56792pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56793    unsafe {
56794        let ret_val: int8x8_t = transmute(a);
56795        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56796    }
56797}
56798#[doc = "Vector reinterpret cast operation"]
56799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56800#[inline]
56801#[cfg(target_endian = "little")]
56802#[target_feature(enable = "neon,aes")]
56803#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56805#[cfg_attr(
56806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56807    assert_instr(nop)
56808)]
56809#[cfg_attr(
56810    not(target_arch = "arm"),
56811    stable(feature = "neon_intrinsics", since = "1.59.0")
56812)]
56813#[cfg_attr(
56814    target_arch = "arm",
56815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56816)]
56817pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56818    unsafe { transmute(a) }
56819}
56820#[doc = "Vector reinterpret cast operation"]
56821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56822#[inline]
56823#[cfg(target_endian = "big")]
56824#[target_feature(enable = "neon,aes")]
56825#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56827#[cfg_attr(
56828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56829    assert_instr(nop)
56830)]
56831#[cfg_attr(
56832    not(target_arch = "arm"),
56833    stable(feature = "neon_intrinsics", since = "1.59.0")
56834)]
56835#[cfg_attr(
56836    target_arch = "arm",
56837    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56838)]
56839pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56840    unsafe {
56841        let ret_val: int16x4_t = transmute(a);
56842        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56843    }
56844}
56845#[doc = "Vector reinterpret cast operation"]
56846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56847#[inline]
56848#[cfg(target_endian = "little")]
56849#[target_feature(enable = "neon,aes")]
56850#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56852#[cfg_attr(
56853    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56854    assert_instr(nop)
56855)]
56856#[cfg_attr(
56857    not(target_arch = "arm"),
56858    stable(feature = "neon_intrinsics", since = "1.59.0")
56859)]
56860#[cfg_attr(
56861    target_arch = "arm",
56862    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56863)]
56864pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56865    unsafe { transmute(a) }
56866}
56867#[doc = "Vector reinterpret cast operation"]
56868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56869#[inline]
56870#[cfg(target_endian = "big")]
56871#[target_feature(enable = "neon,aes")]
56872#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56874#[cfg_attr(
56875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56876    assert_instr(nop)
56877)]
56878#[cfg_attr(
56879    not(target_arch = "arm"),
56880    stable(feature = "neon_intrinsics", since = "1.59.0")
56881)]
56882#[cfg_attr(
56883    target_arch = "arm",
56884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56885)]
56886pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56887    unsafe {
56888        let ret_val: int32x2_t = transmute(a);
56889        simd_shuffle!(ret_val, ret_val, [1, 0])
56890    }
56891}
56892#[doc = "Vector reinterpret cast operation"]
56893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56894#[inline]
56895#[cfg(target_endian = "little")]
56896#[target_feature(enable = "neon,aes")]
56897#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56899#[cfg_attr(
56900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56901    assert_instr(nop)
56902)]
56903#[cfg_attr(
56904    not(target_arch = "arm"),
56905    stable(feature = "neon_intrinsics", since = "1.59.0")
56906)]
56907#[cfg_attr(
56908    target_arch = "arm",
56909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56910)]
56911pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56912    unsafe { transmute(a) }
56913}
56914#[doc = "Vector reinterpret cast operation"]
56915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56916#[inline]
56917#[cfg(target_endian = "big")]
56918#[target_feature(enable = "neon,aes")]
56919#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56921#[cfg_attr(
56922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56923    assert_instr(nop)
56924)]
56925#[cfg_attr(
56926    not(target_arch = "arm"),
56927    stable(feature = "neon_intrinsics", since = "1.59.0")
56928)]
56929#[cfg_attr(
56930    target_arch = "arm",
56931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56932)]
56933pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56934    unsafe {
56935        let ret_val: uint8x8_t = transmute(a);
56936        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56937    }
56938}
56939#[doc = "Vector reinterpret cast operation"]
56940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56941#[inline]
56942#[cfg(target_endian = "little")]
56943#[target_feature(enable = "neon,aes")]
56944#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56946#[cfg_attr(
56947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56948    assert_instr(nop)
56949)]
56950#[cfg_attr(
56951    not(target_arch = "arm"),
56952    stable(feature = "neon_intrinsics", since = "1.59.0")
56953)]
56954#[cfg_attr(
56955    target_arch = "arm",
56956    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56957)]
56958pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56959    unsafe { transmute(a) }
56960}
56961#[doc = "Vector reinterpret cast operation"]
56962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56963#[inline]
56964#[cfg(target_endian = "big")]
56965#[target_feature(enable = "neon,aes")]
56966#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56968#[cfg_attr(
56969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56970    assert_instr(nop)
56971)]
56972#[cfg_attr(
56973    not(target_arch = "arm"),
56974    stable(feature = "neon_intrinsics", since = "1.59.0")
56975)]
56976#[cfg_attr(
56977    target_arch = "arm",
56978    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56979)]
56980pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56981    unsafe {
56982        let ret_val: uint16x4_t = transmute(a);
56983        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56984    }
56985}
56986#[doc = "Vector reinterpret cast operation"]
56987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56988#[inline]
56989#[cfg(target_endian = "little")]
56990#[target_feature(enable = "neon,aes")]
56991#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56993#[cfg_attr(
56994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56995    assert_instr(nop)
56996)]
56997#[cfg_attr(
56998    not(target_arch = "arm"),
56999    stable(feature = "neon_intrinsics", since = "1.59.0")
57000)]
57001#[cfg_attr(
57002    target_arch = "arm",
57003    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57004)]
57005pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
57006    unsafe { transmute(a) }
57007}
57008#[doc = "Vector reinterpret cast operation"]
57009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
57010#[inline]
57011#[cfg(target_endian = "big")]
57012#[target_feature(enable = "neon,aes")]
57013#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57015#[cfg_attr(
57016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57017    assert_instr(nop)
57018)]
57019#[cfg_attr(
57020    not(target_arch = "arm"),
57021    stable(feature = "neon_intrinsics", since = "1.59.0")
57022)]
57023#[cfg_attr(
57024    target_arch = "arm",
57025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57026)]
57027pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
57028    unsafe {
57029        let ret_val: uint32x2_t = transmute(a);
57030        simd_shuffle!(ret_val, ret_val, [1, 0])
57031    }
57032}
57033#[doc = "Vector reinterpret cast operation"]
57034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
57035#[inline]
57036#[cfg(target_endian = "little")]
57037#[target_feature(enable = "neon,aes")]
57038#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57040#[cfg_attr(
57041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57042    assert_instr(nop)
57043)]
57044#[cfg_attr(
57045    not(target_arch = "arm"),
57046    stable(feature = "neon_intrinsics", since = "1.59.0")
57047)]
57048#[cfg_attr(
57049    target_arch = "arm",
57050    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57051)]
57052pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
57053    unsafe { transmute(a) }
57054}
57055#[doc = "Vector reinterpret cast operation"]
57056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
57057#[inline]
57058#[cfg(target_endian = "big")]
57059#[target_feature(enable = "neon,aes")]
57060#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57062#[cfg_attr(
57063    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57064    assert_instr(nop)
57065)]
57066#[cfg_attr(
57067    not(target_arch = "arm"),
57068    stable(feature = "neon_intrinsics", since = "1.59.0")
57069)]
57070#[cfg_attr(
57071    target_arch = "arm",
57072    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57073)]
57074pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
57075    unsafe {
57076        let ret_val: poly8x8_t = transmute(a);
57077        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57078    }
57079}
57080#[doc = "Vector reinterpret cast operation"]
57081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
57082#[inline]
57083#[cfg(target_endian = "little")]
57084#[target_feature(enable = "neon,aes")]
57085#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57087#[cfg_attr(
57088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57089    assert_instr(nop)
57090)]
57091#[cfg_attr(
57092    not(target_arch = "arm"),
57093    stable(feature = "neon_intrinsics", since = "1.59.0")
57094)]
57095#[cfg_attr(
57096    target_arch = "arm",
57097    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57098)]
57099pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57100    unsafe { transmute(a) }
57101}
57102#[doc = "Vector reinterpret cast operation"]
57103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
57104#[inline]
57105#[cfg(target_endian = "big")]
57106#[target_feature(enable = "neon,aes")]
57107#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57109#[cfg_attr(
57110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57111    assert_instr(nop)
57112)]
57113#[cfg_attr(
57114    not(target_arch = "arm"),
57115    stable(feature = "neon_intrinsics", since = "1.59.0")
57116)]
57117#[cfg_attr(
57118    target_arch = "arm",
57119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57120)]
57121pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57122    unsafe {
57123        let ret_val: poly16x4_t = transmute(a);
57124        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57125    }
57126}
57127#[doc = "Vector reinterpret cast operation"]
57128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57129#[inline]
57130#[cfg(target_endian = "little")]
57131#[target_feature(enable = "neon,aes")]
57132#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57134#[cfg_attr(
57135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57136    assert_instr(nop)
57137)]
57138#[cfg_attr(
57139    not(target_arch = "arm"),
57140    stable(feature = "neon_intrinsics", since = "1.59.0")
57141)]
57142#[cfg_attr(
57143    target_arch = "arm",
57144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57145)]
57146pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57147    unsafe { transmute(a) }
57148}
57149#[doc = "Vector reinterpret cast operation"]
57150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57151#[inline]
57152#[cfg(target_endian = "big")]
57153#[target_feature(enable = "neon,aes")]
57154#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57156#[cfg_attr(
57157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57158    assert_instr(nop)
57159)]
57160#[cfg_attr(
57161    not(target_arch = "arm"),
57162    stable(feature = "neon_intrinsics", since = "1.59.0")
57163)]
57164#[cfg_attr(
57165    target_arch = "arm",
57166    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57167)]
57168pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57169    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57170    unsafe { transmute(a) }
57171}
57172#[doc = "Vector reinterpret cast operation"]
57173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57174#[inline]
57175#[cfg(target_endian = "little")]
57176#[target_feature(enable = "neon,aes")]
57177#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57179#[cfg_attr(
57180    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57181    assert_instr(nop)
57182)]
57183#[cfg_attr(
57184    not(target_arch = "arm"),
57185    stable(feature = "neon_intrinsics", since = "1.59.0")
57186)]
57187#[cfg_attr(
57188    target_arch = "arm",
57189    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57190)]
57191pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57192    unsafe { transmute(a) }
57193}
57194#[doc = "Vector reinterpret cast operation"]
57195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57196#[inline]
57197#[cfg(target_endian = "big")]
57198#[target_feature(enable = "neon,aes")]
57199#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57201#[cfg_attr(
57202    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57203    assert_instr(nop)
57204)]
57205#[cfg_attr(
57206    not(target_arch = "arm"),
57207    stable(feature = "neon_intrinsics", since = "1.59.0")
57208)]
57209#[cfg_attr(
57210    target_arch = "arm",
57211    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57212)]
57213pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57214    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57215    unsafe {
57216        let ret_val: int8x16_t = transmute(a);
57217        simd_shuffle!(
57218            ret_val,
57219            ret_val,
57220            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57221        )
57222    }
57223}
57224#[doc = "Vector reinterpret cast operation"]
57225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57226#[inline]
57227#[cfg(target_endian = "little")]
57228#[target_feature(enable = "neon,aes")]
57229#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57231#[cfg_attr(
57232    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57233    assert_instr(nop)
57234)]
57235#[cfg_attr(
57236    not(target_arch = "arm"),
57237    stable(feature = "neon_intrinsics", since = "1.59.0")
57238)]
57239#[cfg_attr(
57240    target_arch = "arm",
57241    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57242)]
57243pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57244    unsafe { transmute(a) }
57245}
57246#[doc = "Vector reinterpret cast operation"]
57247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57248#[inline]
57249#[cfg(target_endian = "big")]
57250#[target_feature(enable = "neon,aes")]
57251#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57253#[cfg_attr(
57254    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57255    assert_instr(nop)
57256)]
57257#[cfg_attr(
57258    not(target_arch = "arm"),
57259    stable(feature = "neon_intrinsics", since = "1.59.0")
57260)]
57261#[cfg_attr(
57262    target_arch = "arm",
57263    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57264)]
57265pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57266    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57267    unsafe {
57268        let ret_val: int16x8_t = transmute(a);
57269        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57270    }
57271}
57272#[doc = "Vector reinterpret cast operation"]
57273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57274#[inline]
57275#[cfg(target_endian = "little")]
57276#[target_feature(enable = "neon,aes")]
57277#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57279#[cfg_attr(
57280    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57281    assert_instr(nop)
57282)]
57283#[cfg_attr(
57284    not(target_arch = "arm"),
57285    stable(feature = "neon_intrinsics", since = "1.59.0")
57286)]
57287#[cfg_attr(
57288    target_arch = "arm",
57289    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57290)]
57291pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57292    unsafe { transmute(a) }
57293}
57294#[doc = "Vector reinterpret cast operation"]
57295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57296#[inline]
57297#[cfg(target_endian = "big")]
57298#[target_feature(enable = "neon,aes")]
57299#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57301#[cfg_attr(
57302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57303    assert_instr(nop)
57304)]
57305#[cfg_attr(
57306    not(target_arch = "arm"),
57307    stable(feature = "neon_intrinsics", since = "1.59.0")
57308)]
57309#[cfg_attr(
57310    target_arch = "arm",
57311    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57312)]
57313pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57314    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57315    unsafe {
57316        let ret_val: int32x4_t = transmute(a);
57317        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57318    }
57319}
57320#[doc = "Vector reinterpret cast operation"]
57321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57322#[inline]
57323#[cfg(target_endian = "little")]
57324#[target_feature(enable = "neon,aes")]
57325#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57327#[cfg_attr(
57328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57329    assert_instr(nop)
57330)]
57331#[cfg_attr(
57332    not(target_arch = "arm"),
57333    stable(feature = "neon_intrinsics", since = "1.59.0")
57334)]
57335#[cfg_attr(
57336    target_arch = "arm",
57337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57338)]
57339pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57340    unsafe { transmute(a) }
57341}
57342#[doc = "Vector reinterpret cast operation"]
57343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57344#[inline]
57345#[cfg(target_endian = "big")]
57346#[target_feature(enable = "neon,aes")]
57347#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57349#[cfg_attr(
57350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57351    assert_instr(nop)
57352)]
57353#[cfg_attr(
57354    not(target_arch = "arm"),
57355    stable(feature = "neon_intrinsics", since = "1.59.0")
57356)]
57357#[cfg_attr(
57358    target_arch = "arm",
57359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57360)]
57361pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57362    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57363    unsafe {
57364        let ret_val: uint8x16_t = transmute(a);
57365        simd_shuffle!(
57366            ret_val,
57367            ret_val,
57368            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57369        )
57370    }
57371}
57372#[doc = "Vector reinterpret cast operation"]
57373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57374#[inline]
57375#[cfg(target_endian = "little")]
57376#[target_feature(enable = "neon,aes")]
57377#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57379#[cfg_attr(
57380    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57381    assert_instr(nop)
57382)]
57383#[cfg_attr(
57384    not(target_arch = "arm"),
57385    stable(feature = "neon_intrinsics", since = "1.59.0")
57386)]
57387#[cfg_attr(
57388    target_arch = "arm",
57389    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57390)]
57391pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57392    unsafe { transmute(a) }
57393}
57394#[doc = "Vector reinterpret cast operation"]
57395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57396#[inline]
57397#[cfg(target_endian = "big")]
57398#[target_feature(enable = "neon,aes")]
57399#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57401#[cfg_attr(
57402    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57403    assert_instr(nop)
57404)]
57405#[cfg_attr(
57406    not(target_arch = "arm"),
57407    stable(feature = "neon_intrinsics", since = "1.59.0")
57408)]
57409#[cfg_attr(
57410    target_arch = "arm",
57411    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57412)]
57413pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57414    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57415    unsafe {
57416        let ret_val: uint16x8_t = transmute(a);
57417        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57418    }
57419}
57420#[doc = "Vector reinterpret cast operation"]
57421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57422#[inline]
57423#[cfg(target_endian = "little")]
57424#[target_feature(enable = "neon,aes")]
57425#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57426#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57427#[cfg_attr(
57428    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57429    assert_instr(nop)
57430)]
57431#[cfg_attr(
57432    not(target_arch = "arm"),
57433    stable(feature = "neon_intrinsics", since = "1.59.0")
57434)]
57435#[cfg_attr(
57436    target_arch = "arm",
57437    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57438)]
57439pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57440    unsafe { transmute(a) }
57441}
57442#[doc = "Vector reinterpret cast operation"]
57443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57444#[inline]
57445#[cfg(target_endian = "big")]
57446#[target_feature(enable = "neon,aes")]
57447#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57449#[cfg_attr(
57450    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57451    assert_instr(nop)
57452)]
57453#[cfg_attr(
57454    not(target_arch = "arm"),
57455    stable(feature = "neon_intrinsics", since = "1.59.0")
57456)]
57457#[cfg_attr(
57458    target_arch = "arm",
57459    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57460)]
57461pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57462    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57463    unsafe {
57464        let ret_val: uint32x4_t = transmute(a);
57465        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57466    }
57467}
57468#[doc = "Vector reinterpret cast operation"]
57469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57470#[inline]
57471#[cfg(target_endian = "little")]
57472#[target_feature(enable = "neon,aes")]
57473#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57475#[cfg_attr(
57476    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57477    assert_instr(nop)
57478)]
57479#[cfg_attr(
57480    not(target_arch = "arm"),
57481    stable(feature = "neon_intrinsics", since = "1.59.0")
57482)]
57483#[cfg_attr(
57484    target_arch = "arm",
57485    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57486)]
57487pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57488    unsafe { transmute(a) }
57489}
57490#[doc = "Vector reinterpret cast operation"]
57491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57492#[inline]
57493#[cfg(target_endian = "big")]
57494#[target_feature(enable = "neon,aes")]
57495#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57496#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57497#[cfg_attr(
57498    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57499    assert_instr(nop)
57500)]
57501#[cfg_attr(
57502    not(target_arch = "arm"),
57503    stable(feature = "neon_intrinsics", since = "1.59.0")
57504)]
57505#[cfg_attr(
57506    target_arch = "arm",
57507    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57508)]
57509pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57510    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57511    unsafe {
57512        let ret_val: poly8x16_t = transmute(a);
57513        simd_shuffle!(
57514            ret_val,
57515            ret_val,
57516            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57517        )
57518    }
57519}
57520#[doc = "Vector reinterpret cast operation"]
57521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57522#[inline]
57523#[cfg(target_endian = "little")]
57524#[target_feature(enable = "neon,aes")]
57525#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57527#[cfg_attr(
57528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57529    assert_instr(nop)
57530)]
57531#[cfg_attr(
57532    not(target_arch = "arm"),
57533    stable(feature = "neon_intrinsics", since = "1.59.0")
57534)]
57535#[cfg_attr(
57536    target_arch = "arm",
57537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57538)]
57539pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57540    unsafe { transmute(a) }
57541}
57542#[doc = "Vector reinterpret cast operation"]
57543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57544#[inline]
57545#[cfg(target_endian = "big")]
57546#[target_feature(enable = "neon,aes")]
57547#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57549#[cfg_attr(
57550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57551    assert_instr(nop)
57552)]
57553#[cfg_attr(
57554    not(target_arch = "arm"),
57555    stable(feature = "neon_intrinsics", since = "1.59.0")
57556)]
57557#[cfg_attr(
57558    target_arch = "arm",
57559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57560)]
57561pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57562    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57563    unsafe {
57564        let ret_val: poly16x8_t = transmute(a);
57565        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57566    }
57567}
57568#[doc = "Reversing vector elements (swap endianness)"]
57569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
57570#[inline]
57571#[target_feature(enable = "neon")]
57572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57574#[cfg_attr(
57575    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57576    assert_instr(rev16)
57577)]
57578#[cfg_attr(
57579    not(target_arch = "arm"),
57580    stable(feature = "neon_intrinsics", since = "1.59.0")
57581)]
57582#[cfg_attr(
57583    target_arch = "arm",
57584    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57585)]
57586pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
57587    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57588}
57589#[doc = "Reversing vector elements (swap endianness)"]
57590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
57591#[inline]
57592#[target_feature(enable = "neon")]
57593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57595#[cfg_attr(
57596    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57597    assert_instr(rev16)
57598)]
57599#[cfg_attr(
57600    not(target_arch = "arm"),
57601    stable(feature = "neon_intrinsics", since = "1.59.0")
57602)]
57603#[cfg_attr(
57604    target_arch = "arm",
57605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57606)]
57607pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
57608    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57609}
57610#[doc = "Reversing vector elements (swap endianness)"]
57611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
57612#[inline]
57613#[target_feature(enable = "neon")]
57614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57615#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57616#[cfg_attr(
57617    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57618    assert_instr(rev16)
57619)]
57620#[cfg_attr(
57621    not(target_arch = "arm"),
57622    stable(feature = "neon_intrinsics", since = "1.59.0")
57623)]
57624#[cfg_attr(
57625    target_arch = "arm",
57626    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57627)]
57628pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
57629    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57630}
57631#[doc = "Reversing vector elements (swap endianness)"]
57632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
57633#[inline]
57634#[target_feature(enable = "neon")]
57635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57636#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57637#[cfg_attr(
57638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57639    assert_instr(rev16)
57640)]
57641#[cfg_attr(
57642    not(target_arch = "arm"),
57643    stable(feature = "neon_intrinsics", since = "1.59.0")
57644)]
57645#[cfg_attr(
57646    target_arch = "arm",
57647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57648)]
57649pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
57650    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57651}
57652#[doc = "Reversing vector elements (swap endianness)"]
57653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
57654#[inline]
57655#[target_feature(enable = "neon")]
57656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57658#[cfg_attr(
57659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57660    assert_instr(rev16)
57661)]
57662#[cfg_attr(
57663    not(target_arch = "arm"),
57664    stable(feature = "neon_intrinsics", since = "1.59.0")
57665)]
57666#[cfg_attr(
57667    target_arch = "arm",
57668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57669)]
57670pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
57671    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57672}
57673#[doc = "Reversing vector elements (swap endianness)"]
57674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
57675#[inline]
57676#[target_feature(enable = "neon")]
57677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57679#[cfg_attr(
57680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57681    assert_instr(rev16)
57682)]
57683#[cfg_attr(
57684    not(target_arch = "arm"),
57685    stable(feature = "neon_intrinsics", since = "1.59.0")
57686)]
57687#[cfg_attr(
57688    target_arch = "arm",
57689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57690)]
57691pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
57692    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57693}
57694#[doc = "Reversing vector elements (swap endianness)"]
57695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
57696#[inline]
57697#[target_feature(enable = "neon")]
57698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57700#[cfg_attr(
57701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57702    assert_instr(rev32)
57703)]
57704#[cfg_attr(
57705    not(target_arch = "arm"),
57706    stable(feature = "neon_intrinsics", since = "1.59.0")
57707)]
57708#[cfg_attr(
57709    target_arch = "arm",
57710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57711)]
57712pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
57713    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57714}
57715#[doc = "Reversing vector elements (swap endianness)"]
57716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
57717#[inline]
57718#[target_feature(enable = "neon")]
57719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57721#[cfg_attr(
57722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57723    assert_instr(rev32)
57724)]
57725#[cfg_attr(
57726    not(target_arch = "arm"),
57727    stable(feature = "neon_intrinsics", since = "1.59.0")
57728)]
57729#[cfg_attr(
57730    target_arch = "arm",
57731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57732)]
57733pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
57734    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57735}
57736#[doc = "Reversing vector elements (swap endianness)"]
57737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
57738#[inline]
57739#[target_feature(enable = "neon")]
57740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57742#[cfg_attr(
57743    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57744    assert_instr(rev32)
57745)]
57746#[cfg_attr(
57747    not(target_arch = "arm"),
57748    stable(feature = "neon_intrinsics", since = "1.59.0")
57749)]
57750#[cfg_attr(
57751    target_arch = "arm",
57752    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57753)]
57754pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
57755    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57756}
57757#[doc = "Reversing vector elements (swap endianness)"]
57758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
57759#[inline]
57760#[target_feature(enable = "neon")]
57761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57762#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57763#[cfg_attr(
57764    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57765    assert_instr(rev32)
57766)]
57767#[cfg_attr(
57768    not(target_arch = "arm"),
57769    stable(feature = "neon_intrinsics", since = "1.59.0")
57770)]
57771#[cfg_attr(
57772    target_arch = "arm",
57773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57774)]
57775pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
57776    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57777}
57778#[doc = "Reversing vector elements (swap endianness)"]
57779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
57780#[inline]
57781#[target_feature(enable = "neon")]
57782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57783#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57784#[cfg_attr(
57785    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57786    assert_instr(rev32)
57787)]
57788#[cfg_attr(
57789    not(target_arch = "arm"),
57790    stable(feature = "neon_intrinsics", since = "1.59.0")
57791)]
57792#[cfg_attr(
57793    target_arch = "arm",
57794    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57795)]
57796pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
57797    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57798}
57799#[doc = "Reversing vector elements (swap endianness)"]
57800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
57801#[inline]
57802#[target_feature(enable = "neon")]
57803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57805#[cfg_attr(
57806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57807    assert_instr(rev32)
57808)]
57809#[cfg_attr(
57810    not(target_arch = "arm"),
57811    stable(feature = "neon_intrinsics", since = "1.59.0")
57812)]
57813#[cfg_attr(
57814    target_arch = "arm",
57815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57816)]
57817pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
57818    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57819}
57820#[doc = "Reversing vector elements (swap endianness)"]
57821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
57822#[inline]
57823#[target_feature(enable = "neon")]
57824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57826#[cfg_attr(
57827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57828    assert_instr(rev32)
57829)]
57830#[cfg_attr(
57831    not(target_arch = "arm"),
57832    stable(feature = "neon_intrinsics", since = "1.59.0")
57833)]
57834#[cfg_attr(
57835    target_arch = "arm",
57836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57837)]
57838pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
57839    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57840}
57841#[doc = "Reversing vector elements (swap endianness)"]
57842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
57843#[inline]
57844#[target_feature(enable = "neon")]
57845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57847#[cfg_attr(
57848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57849    assert_instr(rev32)
57850)]
57851#[cfg_attr(
57852    not(target_arch = "arm"),
57853    stable(feature = "neon_intrinsics", since = "1.59.0")
57854)]
57855#[cfg_attr(
57856    target_arch = "arm",
57857    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57858)]
57859pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
57860    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57861}
57862#[doc = "Reversing vector elements (swap endianness)"]
57863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
57864#[inline]
57865#[target_feature(enable = "neon")]
57866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57867#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57868#[cfg_attr(
57869    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57870    assert_instr(rev32)
57871)]
57872#[cfg_attr(
57873    not(target_arch = "arm"),
57874    stable(feature = "neon_intrinsics", since = "1.59.0")
57875)]
57876#[cfg_attr(
57877    target_arch = "arm",
57878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57879)]
57880pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
57881    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57882}
57883#[doc = "Reversing vector elements (swap endianness)"]
57884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
57885#[inline]
57886#[target_feature(enable = "neon")]
57887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57888#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57889#[cfg_attr(
57890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57891    assert_instr(rev32)
57892)]
57893#[cfg_attr(
57894    not(target_arch = "arm"),
57895    stable(feature = "neon_intrinsics", since = "1.59.0")
57896)]
57897#[cfg_attr(
57898    target_arch = "arm",
57899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57900)]
57901pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
57902    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57903}
57904#[doc = "Reversing vector elements (swap endianness)"]
57905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
57906#[inline]
57907#[target_feature(enable = "neon")]
57908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57909#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57910#[cfg_attr(
57911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57912    assert_instr(rev32)
57913)]
57914#[cfg_attr(
57915    not(target_arch = "arm"),
57916    stable(feature = "neon_intrinsics", since = "1.59.0")
57917)]
57918#[cfg_attr(
57919    target_arch = "arm",
57920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57921)]
57922pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
57923    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57924}
57925#[doc = "Reversing vector elements (swap endianness)"]
57926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
57927#[inline]
57928#[target_feature(enable = "neon")]
57929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57930#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57931#[cfg_attr(
57932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57933    assert_instr(rev32)
57934)]
57935#[cfg_attr(
57936    not(target_arch = "arm"),
57937    stable(feature = "neon_intrinsics", since = "1.59.0")
57938)]
57939#[cfg_attr(
57940    target_arch = "arm",
57941    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57942)]
57943pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
57944    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57945}
57946#[doc = "Reversing vector elements (swap endianness)"]
57947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
57948#[inline]
57949#[target_feature(enable = "neon")]
57950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57951#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57952#[cfg_attr(
57953    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57954    assert_instr(rev64)
57955)]
57956#[cfg_attr(
57957    not(target_arch = "arm"),
57958    stable(feature = "neon_intrinsics", since = "1.59.0")
57959)]
57960#[cfg_attr(
57961    target_arch = "arm",
57962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57963)]
57964pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
57965    unsafe { simd_shuffle!(a, a, [1, 0]) }
57966}
57967#[doc = "Reversing vector elements (swap endianness)"]
57968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
57969#[inline]
57970#[target_feature(enable = "neon")]
57971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57972#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57973#[cfg_attr(
57974    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57975    assert_instr(rev64)
57976)]
57977#[cfg_attr(
57978    not(target_arch = "arm"),
57979    stable(feature = "neon_intrinsics", since = "1.59.0")
57980)]
57981#[cfg_attr(
57982    target_arch = "arm",
57983    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57984)]
57985pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
57986    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57987}
57988#[doc = "Reversing vector elements (swap endianness)"]
57989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
57990#[inline]
57991#[target_feature(enable = "neon")]
57992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57994#[cfg_attr(
57995    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57996    assert_instr(rev64)
57997)]
57998#[cfg_attr(
57999    not(target_arch = "arm"),
58000    stable(feature = "neon_intrinsics", since = "1.59.0")
58001)]
58002#[cfg_attr(
58003    target_arch = "arm",
58004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58005)]
58006pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
58007    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58008}
58009#[doc = "Reversing vector elements (swap endianness)"]
58010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
58011#[inline]
58012#[target_feature(enable = "neon")]
58013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58014#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58015#[cfg_attr(
58016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58017    assert_instr(rev64)
58018)]
58019#[cfg_attr(
58020    not(target_arch = "arm"),
58021    stable(feature = "neon_intrinsics", since = "1.59.0")
58022)]
58023#[cfg_attr(
58024    target_arch = "arm",
58025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58026)]
58027pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
58028    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58029}
58030#[doc = "Reversing vector elements (swap endianness)"]
58031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
58032#[inline]
58033#[target_feature(enable = "neon")]
58034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58035#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58036#[cfg_attr(
58037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58038    assert_instr(rev64)
58039)]
58040#[cfg_attr(
58041    not(target_arch = "arm"),
58042    stable(feature = "neon_intrinsics", since = "1.59.0")
58043)]
58044#[cfg_attr(
58045    target_arch = "arm",
58046    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58047)]
58048pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
58049    unsafe { simd_shuffle!(a, a, [1, 0]) }
58050}
58051#[doc = "Reversing vector elements (swap endianness)"]
58052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
58053#[inline]
58054#[target_feature(enable = "neon")]
58055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58056#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58057#[cfg_attr(
58058    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58059    assert_instr(rev64)
58060)]
58061#[cfg_attr(
58062    not(target_arch = "arm"),
58063    stable(feature = "neon_intrinsics", since = "1.59.0")
58064)]
58065#[cfg_attr(
58066    target_arch = "arm",
58067    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58068)]
58069pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
58070    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58071}
58072#[doc = "Reversing vector elements (swap endianness)"]
58073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
58074#[inline]
58075#[target_feature(enable = "neon")]
58076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58077#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58078#[cfg_attr(
58079    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58080    assert_instr(rev64)
58081)]
58082#[cfg_attr(
58083    not(target_arch = "arm"),
58084    stable(feature = "neon_intrinsics", since = "1.59.0")
58085)]
58086#[cfg_attr(
58087    target_arch = "arm",
58088    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58089)]
58090pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
58091    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58092}
58093#[doc = "Reversing vector elements (swap endianness)"]
58094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
58095#[inline]
58096#[target_feature(enable = "neon")]
58097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58099#[cfg_attr(
58100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58101    assert_instr(rev64)
58102)]
58103#[cfg_attr(
58104    not(target_arch = "arm"),
58105    stable(feature = "neon_intrinsics", since = "1.59.0")
58106)]
58107#[cfg_attr(
58108    target_arch = "arm",
58109    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58110)]
58111pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
58112    unsafe { simd_shuffle!(a, a, [1, 0]) }
58113}
58114#[doc = "Reversing vector elements (swap endianness)"]
58115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
58116#[inline]
58117#[target_feature(enable = "neon")]
58118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58119#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58120#[cfg_attr(
58121    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58122    assert_instr(rev64)
58123)]
58124#[cfg_attr(
58125    not(target_arch = "arm"),
58126    stable(feature = "neon_intrinsics", since = "1.59.0")
58127)]
58128#[cfg_attr(
58129    target_arch = "arm",
58130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58131)]
58132pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
58133    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58134}
58135#[doc = "Reversing vector elements (swap endianness)"]
58136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
58137#[inline]
58138#[target_feature(enable = "neon")]
58139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58141#[cfg_attr(
58142    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58143    assert_instr(rev64)
58144)]
58145#[cfg_attr(
58146    not(target_arch = "arm"),
58147    stable(feature = "neon_intrinsics", since = "1.59.0")
58148)]
58149#[cfg_attr(
58150    target_arch = "arm",
58151    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58152)]
58153pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
58154    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58155}
58156#[doc = "Reversing vector elements (swap endianness)"]
58157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
58158#[inline]
58159#[target_feature(enable = "neon")]
58160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58161#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58162#[cfg_attr(
58163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58164    assert_instr(rev64)
58165)]
58166#[cfg_attr(
58167    not(target_arch = "arm"),
58168    stable(feature = "neon_intrinsics", since = "1.59.0")
58169)]
58170#[cfg_attr(
58171    target_arch = "arm",
58172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58173)]
58174pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
58175    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58176}
58177#[doc = "Reversing vector elements (swap endianness)"]
58178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
58179#[inline]
58180#[target_feature(enable = "neon")]
58181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58182#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58183#[cfg_attr(
58184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58185    assert_instr(rev64)
58186)]
58187#[cfg_attr(
58188    not(target_arch = "arm"),
58189    stable(feature = "neon_intrinsics", since = "1.59.0")
58190)]
58191#[cfg_attr(
58192    target_arch = "arm",
58193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58194)]
58195pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
58196    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58197}
58198#[doc = "Reversing vector elements (swap endianness)"]
58199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
58200#[inline]
58201#[target_feature(enable = "neon")]
58202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58203#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58204#[cfg_attr(
58205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58206    assert_instr(rev64)
58207)]
58208#[cfg_attr(
58209    not(target_arch = "arm"),
58210    stable(feature = "neon_intrinsics", since = "1.59.0")
58211)]
58212#[cfg_attr(
58213    target_arch = "arm",
58214    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58215)]
58216pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
58217    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58218}
58219#[doc = "Reversing vector elements (swap endianness)"]
58220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
58221#[inline]
58222#[target_feature(enable = "neon")]
58223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58225#[cfg_attr(
58226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58227    assert_instr(rev64)
58228)]
58229#[cfg_attr(
58230    not(target_arch = "arm"),
58231    stable(feature = "neon_intrinsics", since = "1.59.0")
58232)]
58233#[cfg_attr(
58234    target_arch = "arm",
58235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58236)]
58237pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
58238    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58239}
58240#[doc = "Reversing vector elements (swap endianness)"]
58241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
58242#[inline]
58243#[target_feature(enable = "neon")]
58244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58246#[cfg_attr(
58247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58248    assert_instr(rev64)
58249)]
58250#[cfg_attr(
58251    not(target_arch = "arm"),
58252    stable(feature = "neon_intrinsics", since = "1.59.0")
58253)]
58254#[cfg_attr(
58255    target_arch = "arm",
58256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58257)]
58258pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
58259    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58260}
58261#[doc = "Reversing vector elements (swap endianness)"]
58262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
58263#[inline]
58264#[target_feature(enable = "neon")]
58265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58267#[cfg_attr(
58268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58269    assert_instr(rev64)
58270)]
58271#[cfg_attr(
58272    not(target_arch = "arm"),
58273    stable(feature = "neon_intrinsics", since = "1.59.0")
58274)]
58275#[cfg_attr(
58276    target_arch = "arm",
58277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58278)]
58279pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
58280    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58281}
58282#[doc = "Reversing vector elements (swap endianness)"]
58283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
58284#[inline]
58285#[target_feature(enable = "neon")]
58286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58287#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58288#[cfg_attr(
58289    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58290    assert_instr(rev64)
58291)]
58292#[cfg_attr(
58293    not(target_arch = "arm"),
58294    stable(feature = "neon_intrinsics", since = "1.59.0")
58295)]
58296#[cfg_attr(
58297    target_arch = "arm",
58298    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58299)]
58300pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
58301    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58302}
58303#[doc = "Reversing vector elements (swap endianness)"]
58304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
58305#[inline]
58306#[target_feature(enable = "neon")]
58307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58308#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58309#[cfg_attr(
58310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58311    assert_instr(rev64)
58312)]
58313#[cfg_attr(
58314    not(target_arch = "arm"),
58315    stable(feature = "neon_intrinsics", since = "1.59.0")
58316)]
58317#[cfg_attr(
58318    target_arch = "arm",
58319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58320)]
58321pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
58322    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58323}
58324#[doc = "Reverse elements in 64-bit doublewords"]
58325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
58326#[inline]
58327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58329#[cfg_attr(
58330    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58331    assert_instr(rev64)
58332)]
58333#[target_feature(enable = "neon,fp16")]
58334#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58335pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
58336    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58337}
58338#[doc = "Reverse elements in 64-bit doublewords"]
58339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
58340#[inline]
58341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58343#[cfg_attr(
58344    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58345    assert_instr(rev64)
58346)]
58347#[target_feature(enable = "neon,fp16")]
58348#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58349pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
58350    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58351}
58352#[doc = "Rounding halving add"]
58353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
58354#[inline]
58355#[target_feature(enable = "neon")]
58356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58357#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58358#[cfg_attr(
58359    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58360    assert_instr(srhadd)
58361)]
58362#[cfg_attr(
58363    not(target_arch = "arm"),
58364    stable(feature = "neon_intrinsics", since = "1.59.0")
58365)]
58366#[cfg_attr(
58367    target_arch = "arm",
58368    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58369)]
58370pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58371    unsafe extern "unadjusted" {
58372        #[cfg_attr(
58373            any(target_arch = "aarch64", target_arch = "arm64ec"),
58374            link_name = "llvm.aarch64.neon.srhadd.v8i8"
58375        )]
58376        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
58377        fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58378    }
58379    unsafe { _vrhadd_s8(a, b) }
58380}
58381#[doc = "Rounding halving add"]
58382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
58383#[inline]
58384#[target_feature(enable = "neon")]
58385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58386#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58387#[cfg_attr(
58388    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58389    assert_instr(srhadd)
58390)]
58391#[cfg_attr(
58392    not(target_arch = "arm"),
58393    stable(feature = "neon_intrinsics", since = "1.59.0")
58394)]
58395#[cfg_attr(
58396    target_arch = "arm",
58397    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58398)]
58399pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58400    unsafe extern "unadjusted" {
58401        #[cfg_attr(
58402            any(target_arch = "aarch64", target_arch = "arm64ec"),
58403            link_name = "llvm.aarch64.neon.srhadd.v16i8"
58404        )]
58405        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
58406        fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58407    }
58408    unsafe { _vrhaddq_s8(a, b) }
58409}
58410#[doc = "Rounding halving add"]
58411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
58412#[inline]
58413#[target_feature(enable = "neon")]
58414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58415#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58416#[cfg_attr(
58417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58418    assert_instr(srhadd)
58419)]
58420#[cfg_attr(
58421    not(target_arch = "arm"),
58422    stable(feature = "neon_intrinsics", since = "1.59.0")
58423)]
58424#[cfg_attr(
58425    target_arch = "arm",
58426    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58427)]
58428pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58429    unsafe extern "unadjusted" {
58430        #[cfg_attr(
58431            any(target_arch = "aarch64", target_arch = "arm64ec"),
58432            link_name = "llvm.aarch64.neon.srhadd.v4i16"
58433        )]
58434        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
58435        fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58436    }
58437    unsafe { _vrhadd_s16(a, b) }
58438}
58439#[doc = "Rounding halving add"]
58440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
58441#[inline]
58442#[target_feature(enable = "neon")]
58443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58444#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58445#[cfg_attr(
58446    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58447    assert_instr(srhadd)
58448)]
58449#[cfg_attr(
58450    not(target_arch = "arm"),
58451    stable(feature = "neon_intrinsics", since = "1.59.0")
58452)]
58453#[cfg_attr(
58454    target_arch = "arm",
58455    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58456)]
58457pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58458    unsafe extern "unadjusted" {
58459        #[cfg_attr(
58460            any(target_arch = "aarch64", target_arch = "arm64ec"),
58461            link_name = "llvm.aarch64.neon.srhadd.v8i16"
58462        )]
58463        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
58464        fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58465    }
58466    unsafe { _vrhaddq_s16(a, b) }
58467}
58468#[doc = "Rounding halving add"]
58469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
58470#[inline]
58471#[target_feature(enable = "neon")]
58472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58473#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58474#[cfg_attr(
58475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58476    assert_instr(srhadd)
58477)]
58478#[cfg_attr(
58479    not(target_arch = "arm"),
58480    stable(feature = "neon_intrinsics", since = "1.59.0")
58481)]
58482#[cfg_attr(
58483    target_arch = "arm",
58484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58485)]
58486pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58487    unsafe extern "unadjusted" {
58488        #[cfg_attr(
58489            any(target_arch = "aarch64", target_arch = "arm64ec"),
58490            link_name = "llvm.aarch64.neon.srhadd.v2i32"
58491        )]
58492        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
58493        fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58494    }
58495    unsafe { _vrhadd_s32(a, b) }
58496}
58497#[doc = "Rounding halving add"]
58498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
58499#[inline]
58500#[target_feature(enable = "neon")]
58501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58502#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58503#[cfg_attr(
58504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58505    assert_instr(srhadd)
58506)]
58507#[cfg_attr(
58508    not(target_arch = "arm"),
58509    stable(feature = "neon_intrinsics", since = "1.59.0")
58510)]
58511#[cfg_attr(
58512    target_arch = "arm",
58513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58514)]
58515pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58516    unsafe extern "unadjusted" {
58517        #[cfg_attr(
58518            any(target_arch = "aarch64", target_arch = "arm64ec"),
58519            link_name = "llvm.aarch64.neon.srhadd.v4i32"
58520        )]
58521        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
58522        fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58523    }
58524    unsafe { _vrhaddq_s32(a, b) }
58525}
58526#[doc = "Rounding halving add"]
58527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
58528#[inline]
58529#[target_feature(enable = "neon")]
58530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58531#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58532#[cfg_attr(
58533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58534    assert_instr(urhadd)
58535)]
58536#[cfg_attr(
58537    not(target_arch = "arm"),
58538    stable(feature = "neon_intrinsics", since = "1.59.0")
58539)]
58540#[cfg_attr(
58541    target_arch = "arm",
58542    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58543)]
58544pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
58545    unsafe extern "unadjusted" {
58546        #[cfg_attr(
58547            any(target_arch = "aarch64", target_arch = "arm64ec"),
58548            link_name = "llvm.aarch64.neon.urhadd.v8i8"
58549        )]
58550        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
58551        fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
58552    }
58553    unsafe { _vrhadd_u8(a, b) }
58554}
58555#[doc = "Rounding halving add"]
58556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
58557#[inline]
58558#[target_feature(enable = "neon")]
58559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58561#[cfg_attr(
58562    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58563    assert_instr(urhadd)
58564)]
58565#[cfg_attr(
58566    not(target_arch = "arm"),
58567    stable(feature = "neon_intrinsics", since = "1.59.0")
58568)]
58569#[cfg_attr(
58570    target_arch = "arm",
58571    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58572)]
58573pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
58574    unsafe extern "unadjusted" {
58575        #[cfg_attr(
58576            any(target_arch = "aarch64", target_arch = "arm64ec"),
58577            link_name = "llvm.aarch64.neon.urhadd.v16i8"
58578        )]
58579        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
58580        fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
58581    }
58582    unsafe { _vrhaddq_u8(a, b) }
58583}
58584#[doc = "Rounding halving add"]
58585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
58586#[inline]
58587#[target_feature(enable = "neon")]
58588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58589#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58590#[cfg_attr(
58591    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58592    assert_instr(urhadd)
58593)]
58594#[cfg_attr(
58595    not(target_arch = "arm"),
58596    stable(feature = "neon_intrinsics", since = "1.59.0")
58597)]
58598#[cfg_attr(
58599    target_arch = "arm",
58600    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58601)]
58602pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
58603    unsafe extern "unadjusted" {
58604        #[cfg_attr(
58605            any(target_arch = "aarch64", target_arch = "arm64ec"),
58606            link_name = "llvm.aarch64.neon.urhadd.v4i16"
58607        )]
58608        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
58609        fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
58610    }
58611    unsafe { _vrhadd_u16(a, b) }
58612}
58613#[doc = "Rounding halving add"]
58614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
58615#[inline]
58616#[target_feature(enable = "neon")]
58617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58618#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58619#[cfg_attr(
58620    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58621    assert_instr(urhadd)
58622)]
58623#[cfg_attr(
58624    not(target_arch = "arm"),
58625    stable(feature = "neon_intrinsics", since = "1.59.0")
58626)]
58627#[cfg_attr(
58628    target_arch = "arm",
58629    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58630)]
58631pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
58632    unsafe extern "unadjusted" {
58633        #[cfg_attr(
58634            any(target_arch = "aarch64", target_arch = "arm64ec"),
58635            link_name = "llvm.aarch64.neon.urhadd.v8i16"
58636        )]
58637        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
58638        fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
58639    }
58640    unsafe { _vrhaddq_u16(a, b) }
58641}
58642#[doc = "Rounding halving add"]
58643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
58644#[inline]
58645#[target_feature(enable = "neon")]
58646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58648#[cfg_attr(
58649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58650    assert_instr(urhadd)
58651)]
58652#[cfg_attr(
58653    not(target_arch = "arm"),
58654    stable(feature = "neon_intrinsics", since = "1.59.0")
58655)]
58656#[cfg_attr(
58657    target_arch = "arm",
58658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58659)]
58660pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
58661    unsafe extern "unadjusted" {
58662        #[cfg_attr(
58663            any(target_arch = "aarch64", target_arch = "arm64ec"),
58664            link_name = "llvm.aarch64.neon.urhadd.v2i32"
58665        )]
58666        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
58667        fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
58668    }
58669    unsafe { _vrhadd_u32(a, b) }
58670}
58671#[doc = "Rounding halving add"]
58672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
58673#[inline]
58674#[target_feature(enable = "neon")]
58675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58677#[cfg_attr(
58678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58679    assert_instr(urhadd)
58680)]
58681#[cfg_attr(
58682    not(target_arch = "arm"),
58683    stable(feature = "neon_intrinsics", since = "1.59.0")
58684)]
58685#[cfg_attr(
58686    target_arch = "arm",
58687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58688)]
58689pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
58690    unsafe extern "unadjusted" {
58691        #[cfg_attr(
58692            any(target_arch = "aarch64", target_arch = "arm64ec"),
58693            link_name = "llvm.aarch64.neon.urhadd.v4i32"
58694        )]
58695        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
58696        fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
58697    }
58698    unsafe { _vrhaddq_u32(a, b) }
58699}
58700#[doc = "Floating-point round to integral, to nearest with ties to even"]
58701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
58702#[inline]
58703#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58705#[cfg_attr(
58706    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58707    assert_instr(frintn)
58708)]
58709#[target_feature(enable = "neon,fp16")]
58710#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58711pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
58712    unsafe extern "unadjusted" {
58713        #[cfg_attr(
58714            any(target_arch = "aarch64", target_arch = "arm64ec"),
58715            link_name = "llvm.aarch64.neon.frintn.v4f16"
58716        )]
58717        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
58718        fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
58719    }
58720    unsafe { _vrndn_f16(a) }
58721}
58722#[doc = "Floating-point round to integral, to nearest with ties to even"]
58723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
58724#[inline]
58725#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58727#[cfg_attr(
58728    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58729    assert_instr(frintn)
58730)]
58731#[target_feature(enable = "neon,fp16")]
58732#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58733pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
58734    unsafe extern "unadjusted" {
58735        #[cfg_attr(
58736            any(target_arch = "aarch64", target_arch = "arm64ec"),
58737            link_name = "llvm.aarch64.neon.frintn.v8f16"
58738        )]
58739        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
58740        fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
58741    }
58742    unsafe { _vrndnq_f16(a) }
58743}
58744#[doc = "Floating-point round to integral, to nearest with ties to even"]
58745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
58746#[inline]
58747#[target_feature(enable = "neon")]
58748#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58750#[cfg_attr(
58751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58752    assert_instr(frintn)
58753)]
58754#[cfg_attr(
58755    not(target_arch = "arm"),
58756    stable(feature = "neon_intrinsics", since = "1.59.0")
58757)]
58758#[cfg_attr(
58759    target_arch = "arm",
58760    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58761)]
58762pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
58763    unsafe extern "unadjusted" {
58764        #[cfg_attr(
58765            any(target_arch = "aarch64", target_arch = "arm64ec"),
58766            link_name = "llvm.aarch64.neon.frintn.v2f32"
58767        )]
58768        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
58769        fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
58770    }
58771    unsafe { _vrndn_f32(a) }
58772}
58773#[doc = "Floating-point round to integral, to nearest with ties to even"]
58774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
58775#[inline]
58776#[target_feature(enable = "neon")]
58777#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58779#[cfg_attr(
58780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58781    assert_instr(frintn)
58782)]
58783#[cfg_attr(
58784    not(target_arch = "arm"),
58785    stable(feature = "neon_intrinsics", since = "1.59.0")
58786)]
58787#[cfg_attr(
58788    target_arch = "arm",
58789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58790)]
58791pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
58792    unsafe extern "unadjusted" {
58793        #[cfg_attr(
58794            any(target_arch = "aarch64", target_arch = "arm64ec"),
58795            link_name = "llvm.aarch64.neon.frintn.v4f32"
58796        )]
58797        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
58798        fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
58799    }
58800    unsafe { _vrndnq_f32(a) }
58801}
58802#[doc = "Signed rounding shift left"]
58803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
58804#[inline]
58805#[target_feature(enable = "neon")]
58806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58808#[cfg_attr(
58809    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58810    assert_instr(srshl)
58811)]
58812#[cfg_attr(
58813    not(target_arch = "arm"),
58814    stable(feature = "neon_intrinsics", since = "1.59.0")
58815)]
58816#[cfg_attr(
58817    target_arch = "arm",
58818    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58819)]
58820pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58821    unsafe extern "unadjusted" {
58822        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")]
58823        #[cfg_attr(
58824            any(target_arch = "aarch64", target_arch = "arm64ec"),
58825            link_name = "llvm.aarch64.neon.srshl.v8i8"
58826        )]
58827        fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58828    }
58829    unsafe { _vrshl_s8(a, b) }
58830}
58831#[doc = "Signed rounding shift left"]
58832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
58833#[inline]
58834#[target_feature(enable = "neon")]
58835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58837#[cfg_attr(
58838    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58839    assert_instr(srshl)
58840)]
58841#[cfg_attr(
58842    not(target_arch = "arm"),
58843    stable(feature = "neon_intrinsics", since = "1.59.0")
58844)]
58845#[cfg_attr(
58846    target_arch = "arm",
58847    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58848)]
58849pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58850    unsafe extern "unadjusted" {
58851        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")]
58852        #[cfg_attr(
58853            any(target_arch = "aarch64", target_arch = "arm64ec"),
58854            link_name = "llvm.aarch64.neon.srshl.v16i8"
58855        )]
58856        fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58857    }
58858    unsafe { _vrshlq_s8(a, b) }
58859}
58860#[doc = "Signed rounding shift left"]
58861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
58862#[inline]
58863#[target_feature(enable = "neon")]
58864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58866#[cfg_attr(
58867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58868    assert_instr(srshl)
58869)]
58870#[cfg_attr(
58871    not(target_arch = "arm"),
58872    stable(feature = "neon_intrinsics", since = "1.59.0")
58873)]
58874#[cfg_attr(
58875    target_arch = "arm",
58876    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58877)]
58878pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58879    unsafe extern "unadjusted" {
58880        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")]
58881        #[cfg_attr(
58882            any(target_arch = "aarch64", target_arch = "arm64ec"),
58883            link_name = "llvm.aarch64.neon.srshl.v4i16"
58884        )]
58885        fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58886    }
58887    unsafe { _vrshl_s16(a, b) }
58888}
58889#[doc = "Signed rounding shift left"]
58890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
58891#[inline]
58892#[target_feature(enable = "neon")]
58893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58895#[cfg_attr(
58896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58897    assert_instr(srshl)
58898)]
58899#[cfg_attr(
58900    not(target_arch = "arm"),
58901    stable(feature = "neon_intrinsics", since = "1.59.0")
58902)]
58903#[cfg_attr(
58904    target_arch = "arm",
58905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58906)]
58907pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58908    unsafe extern "unadjusted" {
58909        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")]
58910        #[cfg_attr(
58911            any(target_arch = "aarch64", target_arch = "arm64ec"),
58912            link_name = "llvm.aarch64.neon.srshl.v8i16"
58913        )]
58914        fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58915    }
58916    unsafe { _vrshlq_s16(a, b) }
58917}
58918#[doc = "Signed rounding shift left"]
58919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
58920#[inline]
58921#[target_feature(enable = "neon")]
58922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58924#[cfg_attr(
58925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58926    assert_instr(srshl)
58927)]
58928#[cfg_attr(
58929    not(target_arch = "arm"),
58930    stable(feature = "neon_intrinsics", since = "1.59.0")
58931)]
58932#[cfg_attr(
58933    target_arch = "arm",
58934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58935)]
58936pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58937    unsafe extern "unadjusted" {
58938        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")]
58939        #[cfg_attr(
58940            any(target_arch = "aarch64", target_arch = "arm64ec"),
58941            link_name = "llvm.aarch64.neon.srshl.v2i32"
58942        )]
58943        fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58944    }
58945    unsafe { _vrshl_s32(a, b) }
58946}
58947#[doc = "Signed rounding shift left"]
58948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
58949#[inline]
58950#[target_feature(enable = "neon")]
58951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58953#[cfg_attr(
58954    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58955    assert_instr(srshl)
58956)]
58957#[cfg_attr(
58958    not(target_arch = "arm"),
58959    stable(feature = "neon_intrinsics", since = "1.59.0")
58960)]
58961#[cfg_attr(
58962    target_arch = "arm",
58963    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58964)]
58965pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58966    unsafe extern "unadjusted" {
58967        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")]
58968        #[cfg_attr(
58969            any(target_arch = "aarch64", target_arch = "arm64ec"),
58970            link_name = "llvm.aarch64.neon.srshl.v4i32"
58971        )]
58972        fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58973    }
58974    unsafe { _vrshlq_s32(a, b) }
58975}
58976#[doc = "Signed rounding shift left"]
58977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
58978#[inline]
58979#[target_feature(enable = "neon")]
58980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58982#[cfg_attr(
58983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58984    assert_instr(srshl)
58985)]
58986#[cfg_attr(
58987    not(target_arch = "arm"),
58988    stable(feature = "neon_intrinsics", since = "1.59.0")
58989)]
58990#[cfg_attr(
58991    target_arch = "arm",
58992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58993)]
58994pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
58995    unsafe extern "unadjusted" {
58996        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")]
58997        #[cfg_attr(
58998            any(target_arch = "aarch64", target_arch = "arm64ec"),
58999            link_name = "llvm.aarch64.neon.srshl.v1i64"
59000        )]
59001        fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
59002    }
59003    unsafe { _vrshl_s64(a, b) }
59004}
59005#[doc = "Signed rounding shift left"]
59006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
59007#[inline]
59008#[target_feature(enable = "neon")]
59009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59011#[cfg_attr(
59012    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59013    assert_instr(srshl)
59014)]
59015#[cfg_attr(
59016    not(target_arch = "arm"),
59017    stable(feature = "neon_intrinsics", since = "1.59.0")
59018)]
59019#[cfg_attr(
59020    target_arch = "arm",
59021    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59022)]
59023pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
59024    unsafe extern "unadjusted" {
59025        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")]
59026        #[cfg_attr(
59027            any(target_arch = "aarch64", target_arch = "arm64ec"),
59028            link_name = "llvm.aarch64.neon.srshl.v2i64"
59029        )]
59030        fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
59031    }
59032    unsafe { _vrshlq_s64(a, b) }
59033}
59034#[doc = "Unsigned rounding shift left"]
59035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
59036#[inline]
59037#[target_feature(enable = "neon")]
59038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59040#[cfg_attr(
59041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59042    assert_instr(urshl)
59043)]
59044#[cfg_attr(
59045    not(target_arch = "arm"),
59046    stable(feature = "neon_intrinsics", since = "1.59.0")
59047)]
59048#[cfg_attr(
59049    target_arch = "arm",
59050    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59051)]
59052pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
59053    unsafe extern "unadjusted" {
59054        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")]
59055        #[cfg_attr(
59056            any(target_arch = "aarch64", target_arch = "arm64ec"),
59057            link_name = "llvm.aarch64.neon.urshl.v8i8"
59058        )]
59059        fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
59060    }
59061    unsafe { _vrshl_u8(a, b) }
59062}
59063#[doc = "Unsigned rounding shift left"]
59064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
59065#[inline]
59066#[target_feature(enable = "neon")]
59067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59069#[cfg_attr(
59070    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59071    assert_instr(urshl)
59072)]
59073#[cfg_attr(
59074    not(target_arch = "arm"),
59075    stable(feature = "neon_intrinsics", since = "1.59.0")
59076)]
59077#[cfg_attr(
59078    target_arch = "arm",
59079    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59080)]
59081pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
59082    unsafe extern "unadjusted" {
59083        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")]
59084        #[cfg_attr(
59085            any(target_arch = "aarch64", target_arch = "arm64ec"),
59086            link_name = "llvm.aarch64.neon.urshl.v16i8"
59087        )]
59088        fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
59089    }
59090    unsafe { _vrshlq_u8(a, b) }
59091}
59092#[doc = "Unsigned rounding shift left"]
59093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
59094#[inline]
59095#[target_feature(enable = "neon")]
59096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59098#[cfg_attr(
59099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59100    assert_instr(urshl)
59101)]
59102#[cfg_attr(
59103    not(target_arch = "arm"),
59104    stable(feature = "neon_intrinsics", since = "1.59.0")
59105)]
59106#[cfg_attr(
59107    target_arch = "arm",
59108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59109)]
59110pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
59111    unsafe extern "unadjusted" {
59112        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")]
59113        #[cfg_attr(
59114            any(target_arch = "aarch64", target_arch = "arm64ec"),
59115            link_name = "llvm.aarch64.neon.urshl.v4i16"
59116        )]
59117        fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
59118    }
59119    unsafe { _vrshl_u16(a, b) }
59120}
59121#[doc = "Unsigned rounding shift left"]
59122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
59123#[inline]
59124#[target_feature(enable = "neon")]
59125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59127#[cfg_attr(
59128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59129    assert_instr(urshl)
59130)]
59131#[cfg_attr(
59132    not(target_arch = "arm"),
59133    stable(feature = "neon_intrinsics", since = "1.59.0")
59134)]
59135#[cfg_attr(
59136    target_arch = "arm",
59137    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59138)]
59139pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
59140    unsafe extern "unadjusted" {
59141        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")]
59142        #[cfg_attr(
59143            any(target_arch = "aarch64", target_arch = "arm64ec"),
59144            link_name = "llvm.aarch64.neon.urshl.v8i16"
59145        )]
59146        fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
59147    }
59148    unsafe { _vrshlq_u16(a, b) }
59149}
59150#[doc = "Unsigned rounding shift left"]
59151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
59152#[inline]
59153#[target_feature(enable = "neon")]
59154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59156#[cfg_attr(
59157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59158    assert_instr(urshl)
59159)]
59160#[cfg_attr(
59161    not(target_arch = "arm"),
59162    stable(feature = "neon_intrinsics", since = "1.59.0")
59163)]
59164#[cfg_attr(
59165    target_arch = "arm",
59166    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59167)]
59168pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
59169    unsafe extern "unadjusted" {
59170        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")]
59171        #[cfg_attr(
59172            any(target_arch = "aarch64", target_arch = "arm64ec"),
59173            link_name = "llvm.aarch64.neon.urshl.v2i32"
59174        )]
59175        fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
59176    }
59177    unsafe { _vrshl_u32(a, b) }
59178}
59179#[doc = "Unsigned rounding shift left"]
59180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
59181#[inline]
59182#[target_feature(enable = "neon")]
59183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59185#[cfg_attr(
59186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59187    assert_instr(urshl)
59188)]
59189#[cfg_attr(
59190    not(target_arch = "arm"),
59191    stable(feature = "neon_intrinsics", since = "1.59.0")
59192)]
59193#[cfg_attr(
59194    target_arch = "arm",
59195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59196)]
59197pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
59198    unsafe extern "unadjusted" {
59199        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")]
59200        #[cfg_attr(
59201            any(target_arch = "aarch64", target_arch = "arm64ec"),
59202            link_name = "llvm.aarch64.neon.urshl.v4i32"
59203        )]
59204        fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
59205    }
59206    unsafe { _vrshlq_u32(a, b) }
59207}
59208#[doc = "Unsigned rounding shift left"]
59209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
59210#[inline]
59211#[target_feature(enable = "neon")]
59212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59214#[cfg_attr(
59215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59216    assert_instr(urshl)
59217)]
59218#[cfg_attr(
59219    not(target_arch = "arm"),
59220    stable(feature = "neon_intrinsics", since = "1.59.0")
59221)]
59222#[cfg_attr(
59223    target_arch = "arm",
59224    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59225)]
59226pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
59227    unsafe extern "unadjusted" {
59228        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")]
59229        #[cfg_attr(
59230            any(target_arch = "aarch64", target_arch = "arm64ec"),
59231            link_name = "llvm.aarch64.neon.urshl.v1i64"
59232        )]
59233        fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
59234    }
59235    unsafe { _vrshl_u64(a, b) }
59236}
59237#[doc = "Unsigned rounding shift left"]
59238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
59239#[inline]
59240#[target_feature(enable = "neon")]
59241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59243#[cfg_attr(
59244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59245    assert_instr(urshl)
59246)]
59247#[cfg_attr(
59248    not(target_arch = "arm"),
59249    stable(feature = "neon_intrinsics", since = "1.59.0")
59250)]
59251#[cfg_attr(
59252    target_arch = "arm",
59253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59254)]
59255pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
59256    unsafe extern "unadjusted" {
59257        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")]
59258        #[cfg_attr(
59259            any(target_arch = "aarch64", target_arch = "arm64ec"),
59260            link_name = "llvm.aarch64.neon.urshl.v2i64"
59261        )]
59262        fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
59263    }
59264    unsafe { _vrshlq_u64(a, b) }
59265}
59266#[doc = "Signed rounding shift right"]
59267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
59268#[inline]
59269#[target_feature(enable = "neon")]
59270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59272#[cfg_attr(
59273    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59274    assert_instr(srshr, N = 2)
59275)]
59276#[rustc_legacy_const_generics(1)]
59277#[cfg_attr(
59278    not(target_arch = "arm"),
59279    stable(feature = "neon_intrinsics", since = "1.59.0")
59280)]
59281#[cfg_attr(
59282    target_arch = "arm",
59283    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59284)]
59285pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
59286    static_assert!(N >= 1 && N <= 8);
59287    vrshl_s8(a, vdup_n_s8(-N as _))
59288}
59289#[doc = "Signed rounding shift right"]
59290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
59291#[inline]
59292#[target_feature(enable = "neon")]
59293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59295#[cfg_attr(
59296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59297    assert_instr(srshr, N = 2)
59298)]
59299#[rustc_legacy_const_generics(1)]
59300#[cfg_attr(
59301    not(target_arch = "arm"),
59302    stable(feature = "neon_intrinsics", since = "1.59.0")
59303)]
59304#[cfg_attr(
59305    target_arch = "arm",
59306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59307)]
59308pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
59309    static_assert!(N >= 1 && N <= 8);
59310    vrshlq_s8(a, vdupq_n_s8(-N as _))
59311}
59312#[doc = "Signed rounding shift right"]
59313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
59314#[inline]
59315#[target_feature(enable = "neon")]
59316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59318#[cfg_attr(
59319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59320    assert_instr(srshr, N = 2)
59321)]
59322#[rustc_legacy_const_generics(1)]
59323#[cfg_attr(
59324    not(target_arch = "arm"),
59325    stable(feature = "neon_intrinsics", since = "1.59.0")
59326)]
59327#[cfg_attr(
59328    target_arch = "arm",
59329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59330)]
59331pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
59332    static_assert!(N >= 1 && N <= 16);
59333    vrshl_s16(a, vdup_n_s16(-N as _))
59334}
59335#[doc = "Signed rounding shift right"]
59336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
59337#[inline]
59338#[target_feature(enable = "neon")]
59339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59341#[cfg_attr(
59342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59343    assert_instr(srshr, N = 2)
59344)]
59345#[rustc_legacy_const_generics(1)]
59346#[cfg_attr(
59347    not(target_arch = "arm"),
59348    stable(feature = "neon_intrinsics", since = "1.59.0")
59349)]
59350#[cfg_attr(
59351    target_arch = "arm",
59352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59353)]
59354pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
59355    static_assert!(N >= 1 && N <= 16);
59356    vrshlq_s16(a, vdupq_n_s16(-N as _))
59357}
59358#[doc = "Signed rounding shift right"]
59359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
59360#[inline]
59361#[target_feature(enable = "neon")]
59362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59364#[cfg_attr(
59365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59366    assert_instr(srshr, N = 2)
59367)]
59368#[rustc_legacy_const_generics(1)]
59369#[cfg_attr(
59370    not(target_arch = "arm"),
59371    stable(feature = "neon_intrinsics", since = "1.59.0")
59372)]
59373#[cfg_attr(
59374    target_arch = "arm",
59375    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59376)]
59377pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
59378    static_assert!(N >= 1 && N <= 32);
59379    vrshl_s32(a, vdup_n_s32(-N as _))
59380}
59381#[doc = "Signed rounding shift right"]
59382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
59383#[inline]
59384#[target_feature(enable = "neon")]
59385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59387#[cfg_attr(
59388    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59389    assert_instr(srshr, N = 2)
59390)]
59391#[rustc_legacy_const_generics(1)]
59392#[cfg_attr(
59393    not(target_arch = "arm"),
59394    stable(feature = "neon_intrinsics", since = "1.59.0")
59395)]
59396#[cfg_attr(
59397    target_arch = "arm",
59398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59399)]
59400pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
59401    static_assert!(N >= 1 && N <= 32);
59402    vrshlq_s32(a, vdupq_n_s32(-N as _))
59403}
59404#[doc = "Signed rounding shift right"]
59405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
59406#[inline]
59407#[target_feature(enable = "neon")]
59408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59410#[cfg_attr(
59411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59412    assert_instr(srshr, N = 2)
59413)]
59414#[rustc_legacy_const_generics(1)]
59415#[cfg_attr(
59416    not(target_arch = "arm"),
59417    stable(feature = "neon_intrinsics", since = "1.59.0")
59418)]
59419#[cfg_attr(
59420    target_arch = "arm",
59421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59422)]
59423pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
59424    static_assert!(N >= 1 && N <= 64);
59425    vrshl_s64(a, vdup_n_s64(-N as _))
59426}
59427#[doc = "Signed rounding shift right"]
59428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
59429#[inline]
59430#[target_feature(enable = "neon")]
59431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59433#[cfg_attr(
59434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59435    assert_instr(srshr, N = 2)
59436)]
59437#[rustc_legacy_const_generics(1)]
59438#[cfg_attr(
59439    not(target_arch = "arm"),
59440    stable(feature = "neon_intrinsics", since = "1.59.0")
59441)]
59442#[cfg_attr(
59443    target_arch = "arm",
59444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59445)]
59446pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
59447    static_assert!(N >= 1 && N <= 64);
59448    vrshlq_s64(a, vdupq_n_s64(-N as _))
59449}
59450#[doc = "Unsigned rounding shift right"]
59451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
59452#[inline]
59453#[target_feature(enable = "neon")]
59454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59456#[cfg_attr(
59457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59458    assert_instr(urshr, N = 2)
59459)]
59460#[rustc_legacy_const_generics(1)]
59461#[cfg_attr(
59462    not(target_arch = "arm"),
59463    stable(feature = "neon_intrinsics", since = "1.59.0")
59464)]
59465#[cfg_attr(
59466    target_arch = "arm",
59467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59468)]
59469pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
59470    static_assert!(N >= 1 && N <= 8);
59471    vrshl_u8(a, vdup_n_s8(-N as _))
59472}
59473#[doc = "Unsigned rounding shift right"]
59474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
59475#[inline]
59476#[target_feature(enable = "neon")]
59477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59479#[cfg_attr(
59480    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59481    assert_instr(urshr, N = 2)
59482)]
59483#[rustc_legacy_const_generics(1)]
59484#[cfg_attr(
59485    not(target_arch = "arm"),
59486    stable(feature = "neon_intrinsics", since = "1.59.0")
59487)]
59488#[cfg_attr(
59489    target_arch = "arm",
59490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59491)]
59492pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
59493    static_assert!(N >= 1 && N <= 8);
59494    vrshlq_u8(a, vdupq_n_s8(-N as _))
59495}
59496#[doc = "Unsigned rounding shift right"]
59497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
59498#[inline]
59499#[target_feature(enable = "neon")]
59500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59502#[cfg_attr(
59503    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59504    assert_instr(urshr, N = 2)
59505)]
59506#[rustc_legacy_const_generics(1)]
59507#[cfg_attr(
59508    not(target_arch = "arm"),
59509    stable(feature = "neon_intrinsics", since = "1.59.0")
59510)]
59511#[cfg_attr(
59512    target_arch = "arm",
59513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59514)]
59515pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
59516    static_assert!(N >= 1 && N <= 16);
59517    vrshl_u16(a, vdup_n_s16(-N as _))
59518}
59519#[doc = "Unsigned rounding shift right"]
59520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
59521#[inline]
59522#[target_feature(enable = "neon")]
59523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59525#[cfg_attr(
59526    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59527    assert_instr(urshr, N = 2)
59528)]
59529#[rustc_legacy_const_generics(1)]
59530#[cfg_attr(
59531    not(target_arch = "arm"),
59532    stable(feature = "neon_intrinsics", since = "1.59.0")
59533)]
59534#[cfg_attr(
59535    target_arch = "arm",
59536    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59537)]
59538pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
59539    static_assert!(N >= 1 && N <= 16);
59540    vrshlq_u16(a, vdupq_n_s16(-N as _))
59541}
59542#[doc = "Unsigned rounding shift right"]
59543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
59544#[inline]
59545#[target_feature(enable = "neon")]
59546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59548#[cfg_attr(
59549    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59550    assert_instr(urshr, N = 2)
59551)]
59552#[rustc_legacy_const_generics(1)]
59553#[cfg_attr(
59554    not(target_arch = "arm"),
59555    stable(feature = "neon_intrinsics", since = "1.59.0")
59556)]
59557#[cfg_attr(
59558    target_arch = "arm",
59559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59560)]
59561pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
59562    static_assert!(N >= 1 && N <= 32);
59563    vrshl_u32(a, vdup_n_s32(-N as _))
59564}
59565#[doc = "Unsigned rounding shift right"]
59566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
59567#[inline]
59568#[target_feature(enable = "neon")]
59569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59571#[cfg_attr(
59572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59573    assert_instr(urshr, N = 2)
59574)]
59575#[rustc_legacy_const_generics(1)]
59576#[cfg_attr(
59577    not(target_arch = "arm"),
59578    stable(feature = "neon_intrinsics", since = "1.59.0")
59579)]
59580#[cfg_attr(
59581    target_arch = "arm",
59582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59583)]
59584pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
59585    static_assert!(N >= 1 && N <= 32);
59586    vrshlq_u32(a, vdupq_n_s32(-N as _))
59587}
59588#[doc = "Unsigned rounding shift right"]
59589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
59590#[inline]
59591#[target_feature(enable = "neon")]
59592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59594#[cfg_attr(
59595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59596    assert_instr(urshr, N = 2)
59597)]
59598#[rustc_legacy_const_generics(1)]
59599#[cfg_attr(
59600    not(target_arch = "arm"),
59601    stable(feature = "neon_intrinsics", since = "1.59.0")
59602)]
59603#[cfg_attr(
59604    target_arch = "arm",
59605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59606)]
59607pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
59608    static_assert!(N >= 1 && N <= 64);
59609    vrshl_u64(a, vdup_n_s64(-N as _))
59610}
59611#[doc = "Unsigned rounding shift right"]
59612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
59613#[inline]
59614#[target_feature(enable = "neon")]
59615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59617#[cfg_attr(
59618    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59619    assert_instr(urshr, N = 2)
59620)]
59621#[rustc_legacy_const_generics(1)]
59622#[cfg_attr(
59623    not(target_arch = "arm"),
59624    stable(feature = "neon_intrinsics", since = "1.59.0")
59625)]
59626#[cfg_attr(
59627    target_arch = "arm",
59628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59629)]
59630pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
59631    static_assert!(N >= 1 && N <= 64);
59632    vrshlq_u64(a, vdupq_n_s64(-N as _))
59633}
59634#[doc = "Rounding shift right narrow"]
59635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59636#[inline]
59637#[cfg(target_arch = "arm")]
59638#[target_feature(enable = "neon,v7")]
59639#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59640#[rustc_legacy_const_generics(1)]
59641#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59642pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59643    static_assert!(N >= 1 && N <= 8);
59644    unsafe extern "unadjusted" {
59645        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
59646        fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
59647    }
59648    unsafe {
59649        _vrshrn_n_s16(
59650            a,
59651            const {
59652                int16x8_t([
59653                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
59654                    -N as i16,
59655                ])
59656            },
59657        )
59658    }
59659}
59660#[doc = "Rounding shift right narrow"]
59661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59662#[inline]
59663#[cfg(target_arch = "arm")]
59664#[target_feature(enable = "neon,v7")]
59665#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59666#[rustc_legacy_const_generics(1)]
59667#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59668pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59669    static_assert!(N >= 1 && N <= 16);
59670    unsafe extern "unadjusted" {
59671        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
59672        fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
59673    }
59674    unsafe {
59675        _vrshrn_n_s32(
59676            a,
59677            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
59678        )
59679    }
59680}
59681#[doc = "Rounding shift right narrow"]
59682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59683#[inline]
59684#[cfg(target_arch = "arm")]
59685#[target_feature(enable = "neon,v7")]
59686#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59687#[rustc_legacy_const_generics(1)]
59688#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59689pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59690    static_assert!(N >= 1 && N <= 32);
59691    unsafe extern "unadjusted" {
59692        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
59693        fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
59694    }
59695    unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
59696}
59697#[doc = "Rounding shift right narrow"]
59698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59699#[inline]
59700#[target_feature(enable = "neon")]
59701#[cfg(not(target_arch = "arm"))]
59702#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59703#[rustc_legacy_const_generics(1)]
59704#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59705pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59706    static_assert!(N >= 1 && N <= 8);
59707    unsafe extern "unadjusted" {
59708        #[cfg_attr(
59709            any(target_arch = "aarch64", target_arch = "arm64ec"),
59710            link_name = "llvm.aarch64.neon.rshrn.v8i8"
59711        )]
59712        fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
59713    }
59714    unsafe { _vrshrn_n_s16(a, N) }
59715}
59716#[doc = "Rounding shift right narrow"]
59717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59718#[inline]
59719#[target_feature(enable = "neon")]
59720#[cfg(not(target_arch = "arm"))]
59721#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59722#[rustc_legacy_const_generics(1)]
59723#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59724pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59725    static_assert!(N >= 1 && N <= 16);
59726    unsafe extern "unadjusted" {
59727        #[cfg_attr(
59728            any(target_arch = "aarch64", target_arch = "arm64ec"),
59729            link_name = "llvm.aarch64.neon.rshrn.v4i16"
59730        )]
59731        fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
59732    }
59733    unsafe { _vrshrn_n_s32(a, N) }
59734}
59735#[doc = "Rounding shift right narrow"]
59736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59737#[inline]
59738#[target_feature(enable = "neon")]
59739#[cfg(not(target_arch = "arm"))]
59740#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59741#[rustc_legacy_const_generics(1)]
59742#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59743pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59744    static_assert!(N >= 1 && N <= 32);
59745    unsafe extern "unadjusted" {
59746        #[cfg_attr(
59747            any(target_arch = "aarch64", target_arch = "arm64ec"),
59748            link_name = "llvm.aarch64.neon.rshrn.v2i32"
59749        )]
59750        fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
59751    }
59752    unsafe { _vrshrn_n_s64(a, N) }
59753}
59754#[doc = "Rounding shift right narrow"]
59755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
59756#[inline]
59757#[target_feature(enable = "neon")]
59758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59760#[cfg_attr(
59761    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59762    assert_instr(rshrn, N = 2)
59763)]
59764#[rustc_legacy_const_generics(1)]
59765#[cfg_attr(
59766    not(target_arch = "arm"),
59767    stable(feature = "neon_intrinsics", since = "1.59.0")
59768)]
59769#[cfg_attr(
59770    target_arch = "arm",
59771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59772)]
59773pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
59774    static_assert!(N >= 1 && N <= 8);
59775    unsafe { transmute(vrshrn_n_s16::<N>(transmute(a))) }
59776}
59777#[doc = "Rounding shift right narrow"]
59778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
59779#[inline]
59780#[target_feature(enable = "neon")]
59781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59783#[cfg_attr(
59784    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59785    assert_instr(rshrn, N = 2)
59786)]
59787#[rustc_legacy_const_generics(1)]
59788#[cfg_attr(
59789    not(target_arch = "arm"),
59790    stable(feature = "neon_intrinsics", since = "1.59.0")
59791)]
59792#[cfg_attr(
59793    target_arch = "arm",
59794    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59795)]
59796pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
59797    static_assert!(N >= 1 && N <= 16);
59798    unsafe { transmute(vrshrn_n_s32::<N>(transmute(a))) }
59799}
59800#[doc = "Rounding shift right narrow"]
59801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
59802#[inline]
59803#[target_feature(enable = "neon")]
59804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59806#[cfg_attr(
59807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59808    assert_instr(rshrn, N = 2)
59809)]
59810#[rustc_legacy_const_generics(1)]
59811#[cfg_attr(
59812    not(target_arch = "arm"),
59813    stable(feature = "neon_intrinsics", since = "1.59.0")
59814)]
59815#[cfg_attr(
59816    target_arch = "arm",
59817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59818)]
59819pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
59820    static_assert!(N >= 1 && N <= 32);
59821    unsafe { transmute(vrshrn_n_s64::<N>(transmute(a))) }
59822}
59823#[doc = "Reciprocal square-root estimate."]
59824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
59825#[inline]
59826#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59827#[target_feature(enable = "neon,fp16")]
59828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59829#[cfg_attr(
59830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59831    assert_instr(frsqrte)
59832)]
59833#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59834pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
59835    unsafe extern "unadjusted" {
59836        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")]
59837        #[cfg_attr(
59838            any(target_arch = "aarch64", target_arch = "arm64ec"),
59839            link_name = "llvm.aarch64.neon.frsqrte.v4f16"
59840        )]
59841        fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t;
59842    }
59843    unsafe { _vrsqrte_f16(a) }
59844}
59845#[doc = "Reciprocal square-root estimate."]
59846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
59847#[inline]
59848#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59849#[target_feature(enable = "neon,fp16")]
59850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59851#[cfg_attr(
59852    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59853    assert_instr(frsqrte)
59854)]
59855#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59856pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
59857    unsafe extern "unadjusted" {
59858        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")]
59859        #[cfg_attr(
59860            any(target_arch = "aarch64", target_arch = "arm64ec"),
59861            link_name = "llvm.aarch64.neon.frsqrte.v8f16"
59862        )]
59863        fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t;
59864    }
59865    unsafe { _vrsqrteq_f16(a) }
59866}
59867#[doc = "Reciprocal square-root estimate."]
59868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
59869#[inline]
59870#[target_feature(enable = "neon")]
59871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59873#[cfg_attr(
59874    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59875    assert_instr(frsqrte)
59876)]
59877#[cfg_attr(
59878    not(target_arch = "arm"),
59879    stable(feature = "neon_intrinsics", since = "1.59.0")
59880)]
59881#[cfg_attr(
59882    target_arch = "arm",
59883    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59884)]
59885pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
59886    unsafe extern "unadjusted" {
59887        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
59888        #[cfg_attr(
59889            any(target_arch = "aarch64", target_arch = "arm64ec"),
59890            link_name = "llvm.aarch64.neon.frsqrte.v2f32"
59891        )]
59892        fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t;
59893    }
59894    unsafe { _vrsqrte_f32(a) }
59895}
59896#[doc = "Reciprocal square-root estimate."]
59897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
59898#[inline]
59899#[target_feature(enable = "neon")]
59900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59901#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59902#[cfg_attr(
59903    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59904    assert_instr(frsqrte)
59905)]
59906#[cfg_attr(
59907    not(target_arch = "arm"),
59908    stable(feature = "neon_intrinsics", since = "1.59.0")
59909)]
59910#[cfg_attr(
59911    target_arch = "arm",
59912    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59913)]
59914pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
59915    unsafe extern "unadjusted" {
59916        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")]
59917        #[cfg_attr(
59918            any(target_arch = "aarch64", target_arch = "arm64ec"),
59919            link_name = "llvm.aarch64.neon.frsqrte.v4f32"
59920        )]
59921        fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t;
59922    }
59923    unsafe { _vrsqrteq_f32(a) }
59924}
59925#[doc = "Unsigned reciprocal square root estimate"]
59926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
59927#[inline]
59928#[target_feature(enable = "neon")]
59929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59931#[cfg_attr(
59932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59933    assert_instr(ursqrte)
59934)]
59935#[cfg_attr(
59936    not(target_arch = "arm"),
59937    stable(feature = "neon_intrinsics", since = "1.59.0")
59938)]
59939#[cfg_attr(
59940    target_arch = "arm",
59941    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59942)]
59943pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
59944    unsafe extern "unadjusted" {
59945        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")]
59946        #[cfg_attr(
59947            any(target_arch = "aarch64", target_arch = "arm64ec"),
59948            link_name = "llvm.aarch64.neon.ursqrte.v2i32"
59949        )]
59950        fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t;
59951    }
59952    unsafe { _vrsqrte_u32(a) }
59953}
59954#[doc = "Unsigned reciprocal square root estimate"]
59955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
59956#[inline]
59957#[target_feature(enable = "neon")]
59958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59960#[cfg_attr(
59961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59962    assert_instr(ursqrte)
59963)]
59964#[cfg_attr(
59965    not(target_arch = "arm"),
59966    stable(feature = "neon_intrinsics", since = "1.59.0")
59967)]
59968#[cfg_attr(
59969    target_arch = "arm",
59970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59971)]
59972pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
59973    unsafe extern "unadjusted" {
59974        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")]
59975        #[cfg_attr(
59976            any(target_arch = "aarch64", target_arch = "arm64ec"),
59977            link_name = "llvm.aarch64.neon.ursqrte.v4i32"
59978        )]
59979        fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t;
59980    }
59981    unsafe { _vrsqrteq_u32(a) }
59982}
59983#[doc = "Floating-point reciprocal square root step"]
59984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
59985#[inline]
59986#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59987#[target_feature(enable = "neon,fp16")]
59988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59989#[cfg_attr(
59990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59991    assert_instr(frsqrts)
59992)]
59993#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59994pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
59995    unsafe extern "unadjusted" {
59996        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")]
59997        #[cfg_attr(
59998            any(target_arch = "aarch64", target_arch = "arm64ec"),
59999            link_name = "llvm.aarch64.neon.frsqrts.v4f16"
60000        )]
60001        fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
60002    }
60003    unsafe { _vrsqrts_f16(a, b) }
60004}
60005#[doc = "Floating-point reciprocal square root step"]
60006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
60007#[inline]
60008#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60009#[target_feature(enable = "neon,fp16")]
60010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
60011#[cfg_attr(
60012    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60013    assert_instr(frsqrts)
60014)]
60015#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60016pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
60017    unsafe extern "unadjusted" {
60018        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")]
60019        #[cfg_attr(
60020            any(target_arch = "aarch64", target_arch = "arm64ec"),
60021            link_name = "llvm.aarch64.neon.frsqrts.v8f16"
60022        )]
60023        fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
60024    }
60025    unsafe { _vrsqrtsq_f16(a, b) }
60026}
60027#[doc = "Floating-point reciprocal square root step"]
60028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
60029#[inline]
60030#[target_feature(enable = "neon")]
60031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
60033#[cfg_attr(
60034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60035    assert_instr(frsqrts)
60036)]
60037#[cfg_attr(
60038    not(target_arch = "arm"),
60039    stable(feature = "neon_intrinsics", since = "1.59.0")
60040)]
60041#[cfg_attr(
60042    target_arch = "arm",
60043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60044)]
60045pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
60046    unsafe extern "unadjusted" {
60047        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")]
60048        #[cfg_attr(
60049            any(target_arch = "aarch64", target_arch = "arm64ec"),
60050            link_name = "llvm.aarch64.neon.frsqrts.v2f32"
60051        )]
60052        fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
60053    }
60054    unsafe { _vrsqrts_f32(a, b) }
60055}
60056#[doc = "Floating-point reciprocal square root step"]
60057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
60058#[inline]
60059#[target_feature(enable = "neon")]
60060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
60062#[cfg_attr(
60063    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60064    assert_instr(frsqrts)
60065)]
60066#[cfg_attr(
60067    not(target_arch = "arm"),
60068    stable(feature = "neon_intrinsics", since = "1.59.0")
60069)]
60070#[cfg_attr(
60071    target_arch = "arm",
60072    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60073)]
60074pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
60075    unsafe extern "unadjusted" {
60076        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")]
60077        #[cfg_attr(
60078            any(target_arch = "aarch64", target_arch = "arm64ec"),
60079            link_name = "llvm.aarch64.neon.frsqrts.v4f32"
60080        )]
60081        fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
60082    }
60083    unsafe { _vrsqrtsq_f32(a, b) }
60084}
60085#[doc = "Signed rounding shift right and accumulate"]
60086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
60087#[inline]
60088#[target_feature(enable = "neon")]
60089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60091#[cfg_attr(
60092    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60093    assert_instr(srsra, N = 2)
60094)]
60095#[rustc_legacy_const_generics(2)]
60096#[cfg_attr(
60097    not(target_arch = "arm"),
60098    stable(feature = "neon_intrinsics", since = "1.59.0")
60099)]
60100#[cfg_attr(
60101    target_arch = "arm",
60102    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60103)]
60104pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
60105    static_assert!(N >= 1 && N <= 8);
60106    unsafe { simd_add(a, vrshr_n_s8::<N>(b)) }
60107}
60108#[doc = "Signed rounding shift right and accumulate"]
60109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
60110#[inline]
60111#[target_feature(enable = "neon")]
60112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60114#[cfg_attr(
60115    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60116    assert_instr(srsra, N = 2)
60117)]
60118#[rustc_legacy_const_generics(2)]
60119#[cfg_attr(
60120    not(target_arch = "arm"),
60121    stable(feature = "neon_intrinsics", since = "1.59.0")
60122)]
60123#[cfg_attr(
60124    target_arch = "arm",
60125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60126)]
60127pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
60128    static_assert!(N >= 1 && N <= 8);
60129    unsafe { simd_add(a, vrshrq_n_s8::<N>(b)) }
60130}
60131#[doc = "Signed rounding shift right and accumulate"]
60132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
60133#[inline]
60134#[target_feature(enable = "neon")]
60135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60137#[cfg_attr(
60138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60139    assert_instr(srsra, N = 2)
60140)]
60141#[rustc_legacy_const_generics(2)]
60142#[cfg_attr(
60143    not(target_arch = "arm"),
60144    stable(feature = "neon_intrinsics", since = "1.59.0")
60145)]
60146#[cfg_attr(
60147    target_arch = "arm",
60148    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60149)]
60150pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
60151    static_assert!(N >= 1 && N <= 16);
60152    unsafe { simd_add(a, vrshr_n_s16::<N>(b)) }
60153}
60154#[doc = "Signed rounding shift right and accumulate"]
60155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
60156#[inline]
60157#[target_feature(enable = "neon")]
60158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60160#[cfg_attr(
60161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60162    assert_instr(srsra, N = 2)
60163)]
60164#[rustc_legacy_const_generics(2)]
60165#[cfg_attr(
60166    not(target_arch = "arm"),
60167    stable(feature = "neon_intrinsics", since = "1.59.0")
60168)]
60169#[cfg_attr(
60170    target_arch = "arm",
60171    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60172)]
60173pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
60174    static_assert!(N >= 1 && N <= 16);
60175    unsafe { simd_add(a, vrshrq_n_s16::<N>(b)) }
60176}
60177#[doc = "Signed rounding shift right and accumulate"]
60178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
60179#[inline]
60180#[target_feature(enable = "neon")]
60181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60183#[cfg_attr(
60184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60185    assert_instr(srsra, N = 2)
60186)]
60187#[rustc_legacy_const_generics(2)]
60188#[cfg_attr(
60189    not(target_arch = "arm"),
60190    stable(feature = "neon_intrinsics", since = "1.59.0")
60191)]
60192#[cfg_attr(
60193    target_arch = "arm",
60194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60195)]
60196pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
60197    static_assert!(N >= 1 && N <= 32);
60198    unsafe { simd_add(a, vrshr_n_s32::<N>(b)) }
60199}
60200#[doc = "Signed rounding shift right and accumulate"]
60201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
60202#[inline]
60203#[target_feature(enable = "neon")]
60204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60206#[cfg_attr(
60207    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60208    assert_instr(srsra, N = 2)
60209)]
60210#[rustc_legacy_const_generics(2)]
60211#[cfg_attr(
60212    not(target_arch = "arm"),
60213    stable(feature = "neon_intrinsics", since = "1.59.0")
60214)]
60215#[cfg_attr(
60216    target_arch = "arm",
60217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60218)]
60219pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
60220    static_assert!(N >= 1 && N <= 32);
60221    unsafe { simd_add(a, vrshrq_n_s32::<N>(b)) }
60222}
60223#[doc = "Signed rounding shift right and accumulate"]
60224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
60225#[inline]
60226#[target_feature(enable = "neon")]
60227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60229#[cfg_attr(
60230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60231    assert_instr(srsra, N = 2)
60232)]
60233#[rustc_legacy_const_generics(2)]
60234#[cfg_attr(
60235    not(target_arch = "arm"),
60236    stable(feature = "neon_intrinsics", since = "1.59.0")
60237)]
60238#[cfg_attr(
60239    target_arch = "arm",
60240    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60241)]
60242pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
60243    static_assert!(N >= 1 && N <= 64);
60244    unsafe { simd_add(a, vrshr_n_s64::<N>(b)) }
60245}
60246#[doc = "Signed rounding shift right and accumulate"]
60247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
60248#[inline]
60249#[target_feature(enable = "neon")]
60250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60252#[cfg_attr(
60253    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60254    assert_instr(srsra, N = 2)
60255)]
60256#[rustc_legacy_const_generics(2)]
60257#[cfg_attr(
60258    not(target_arch = "arm"),
60259    stable(feature = "neon_intrinsics", since = "1.59.0")
60260)]
60261#[cfg_attr(
60262    target_arch = "arm",
60263    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60264)]
60265pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
60266    static_assert!(N >= 1 && N <= 64);
60267    unsafe { simd_add(a, vrshrq_n_s64::<N>(b)) }
60268}
60269#[doc = "Unsigned rounding shift right and accumulate"]
60270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
60271#[inline]
60272#[target_feature(enable = "neon")]
60273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60275#[cfg_attr(
60276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60277    assert_instr(ursra, N = 2)
60278)]
60279#[rustc_legacy_const_generics(2)]
60280#[cfg_attr(
60281    not(target_arch = "arm"),
60282    stable(feature = "neon_intrinsics", since = "1.59.0")
60283)]
60284#[cfg_attr(
60285    target_arch = "arm",
60286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60287)]
60288pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
60289    static_assert!(N >= 1 && N <= 8);
60290    unsafe { simd_add(a, vrshr_n_u8::<N>(b)) }
60291}
60292#[doc = "Unsigned rounding shift right and accumulate"]
60293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
60294#[inline]
60295#[target_feature(enable = "neon")]
60296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60298#[cfg_attr(
60299    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60300    assert_instr(ursra, N = 2)
60301)]
60302#[rustc_legacy_const_generics(2)]
60303#[cfg_attr(
60304    not(target_arch = "arm"),
60305    stable(feature = "neon_intrinsics", since = "1.59.0")
60306)]
60307#[cfg_attr(
60308    target_arch = "arm",
60309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60310)]
60311pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
60312    static_assert!(N >= 1 && N <= 8);
60313    unsafe { simd_add(a, vrshrq_n_u8::<N>(b)) }
60314}
60315#[doc = "Unsigned rounding shift right and accumulate"]
60316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
60317#[inline]
60318#[target_feature(enable = "neon")]
60319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60321#[cfg_attr(
60322    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60323    assert_instr(ursra, N = 2)
60324)]
60325#[rustc_legacy_const_generics(2)]
60326#[cfg_attr(
60327    not(target_arch = "arm"),
60328    stable(feature = "neon_intrinsics", since = "1.59.0")
60329)]
60330#[cfg_attr(
60331    target_arch = "arm",
60332    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60333)]
60334pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
60335    static_assert!(N >= 1 && N <= 16);
60336    unsafe { simd_add(a, vrshr_n_u16::<N>(b)) }
60337}
60338#[doc = "Unsigned rounding shift right and accumulate"]
60339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
60340#[inline]
60341#[target_feature(enable = "neon")]
60342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60343#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60344#[cfg_attr(
60345    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60346    assert_instr(ursra, N = 2)
60347)]
60348#[rustc_legacy_const_generics(2)]
60349#[cfg_attr(
60350    not(target_arch = "arm"),
60351    stable(feature = "neon_intrinsics", since = "1.59.0")
60352)]
60353#[cfg_attr(
60354    target_arch = "arm",
60355    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60356)]
60357pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
60358    static_assert!(N >= 1 && N <= 16);
60359    unsafe { simd_add(a, vrshrq_n_u16::<N>(b)) }
60360}
60361#[doc = "Unsigned rounding shift right and accumulate"]
60362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
60363#[inline]
60364#[target_feature(enable = "neon")]
60365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60367#[cfg_attr(
60368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60369    assert_instr(ursra, N = 2)
60370)]
60371#[rustc_legacy_const_generics(2)]
60372#[cfg_attr(
60373    not(target_arch = "arm"),
60374    stable(feature = "neon_intrinsics", since = "1.59.0")
60375)]
60376#[cfg_attr(
60377    target_arch = "arm",
60378    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60379)]
60380pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
60381    static_assert!(N >= 1 && N <= 32);
60382    unsafe { simd_add(a, vrshr_n_u32::<N>(b)) }
60383}
60384#[doc = "Unsigned rounding shift right and accumulate"]
60385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
60386#[inline]
60387#[target_feature(enable = "neon")]
60388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60390#[cfg_attr(
60391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60392    assert_instr(ursra, N = 2)
60393)]
60394#[rustc_legacy_const_generics(2)]
60395#[cfg_attr(
60396    not(target_arch = "arm"),
60397    stable(feature = "neon_intrinsics", since = "1.59.0")
60398)]
60399#[cfg_attr(
60400    target_arch = "arm",
60401    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60402)]
60403pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
60404    static_assert!(N >= 1 && N <= 32);
60405    unsafe { simd_add(a, vrshrq_n_u32::<N>(b)) }
60406}
60407#[doc = "Unsigned rounding shift right and accumulate"]
60408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
60409#[inline]
60410#[target_feature(enable = "neon")]
60411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60413#[cfg_attr(
60414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60415    assert_instr(ursra, N = 2)
60416)]
60417#[rustc_legacy_const_generics(2)]
60418#[cfg_attr(
60419    not(target_arch = "arm"),
60420    stable(feature = "neon_intrinsics", since = "1.59.0")
60421)]
60422#[cfg_attr(
60423    target_arch = "arm",
60424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60425)]
60426pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
60427    static_assert!(N >= 1 && N <= 64);
60428    unsafe { simd_add(a, vrshr_n_u64::<N>(b)) }
60429}
60430#[doc = "Unsigned rounding shift right and accumulate"]
60431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
60432#[inline]
60433#[target_feature(enable = "neon")]
60434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60436#[cfg_attr(
60437    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60438    assert_instr(ursra, N = 2)
60439)]
60440#[rustc_legacy_const_generics(2)]
60441#[cfg_attr(
60442    not(target_arch = "arm"),
60443    stable(feature = "neon_intrinsics", since = "1.59.0")
60444)]
60445#[cfg_attr(
60446    target_arch = "arm",
60447    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60448)]
60449pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
60450    static_assert!(N >= 1 && N <= 64);
60451    unsafe { simd_add(a, vrshrq_n_u64::<N>(b)) }
60452}
60453#[doc = "Rounding subtract returning high narrow"]
60454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
60455#[inline]
60456#[target_feature(enable = "neon")]
60457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60459#[cfg_attr(
60460    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60461    assert_instr(rsubhn)
60462)]
60463#[cfg_attr(
60464    not(target_arch = "arm"),
60465    stable(feature = "neon_intrinsics", since = "1.59.0")
60466)]
60467#[cfg_attr(
60468    target_arch = "arm",
60469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60470)]
60471pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
60472    unsafe extern "unadjusted" {
60473        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")]
60474        #[cfg_attr(
60475            any(target_arch = "aarch64", target_arch = "arm64ec"),
60476            link_name = "llvm.aarch64.neon.rsubhn.v8i8"
60477        )]
60478        fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
60479    }
60480    unsafe { _vrsubhn_s16(a, b) }
60481}
60482#[doc = "Rounding subtract returning high narrow"]
60483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
60484#[inline]
60485#[target_feature(enable = "neon")]
60486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60488#[cfg_attr(
60489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60490    assert_instr(rsubhn)
60491)]
60492#[cfg_attr(
60493    not(target_arch = "arm"),
60494    stable(feature = "neon_intrinsics", since = "1.59.0")
60495)]
60496#[cfg_attr(
60497    target_arch = "arm",
60498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60499)]
60500pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
60501    unsafe extern "unadjusted" {
60502        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")]
60503        #[cfg_attr(
60504            any(target_arch = "aarch64", target_arch = "arm64ec"),
60505            link_name = "llvm.aarch64.neon.rsubhn.v4i16"
60506        )]
60507        fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
60508    }
60509    unsafe { _vrsubhn_s32(a, b) }
60510}
60511#[doc = "Rounding subtract returning high narrow"]
60512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
60513#[inline]
60514#[target_feature(enable = "neon")]
60515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60517#[cfg_attr(
60518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60519    assert_instr(rsubhn)
60520)]
60521#[cfg_attr(
60522    not(target_arch = "arm"),
60523    stable(feature = "neon_intrinsics", since = "1.59.0")
60524)]
60525#[cfg_attr(
60526    target_arch = "arm",
60527    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60528)]
60529pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
60530    unsafe extern "unadjusted" {
60531        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")]
60532        #[cfg_attr(
60533            any(target_arch = "aarch64", target_arch = "arm64ec"),
60534            link_name = "llvm.aarch64.neon.rsubhn.v2i32"
60535        )]
60536        fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
60537    }
60538    unsafe { _vrsubhn_s64(a, b) }
60539}
60540#[doc = "Rounding subtract returning high narrow"]
60541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60542#[inline]
60543#[cfg(target_endian = "little")]
60544#[target_feature(enable = "neon")]
60545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60547#[cfg_attr(
60548    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60549    assert_instr(rsubhn)
60550)]
60551#[cfg_attr(
60552    not(target_arch = "arm"),
60553    stable(feature = "neon_intrinsics", since = "1.59.0")
60554)]
60555#[cfg_attr(
60556    target_arch = "arm",
60557    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60558)]
60559pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60560    unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
60561}
60562#[doc = "Rounding subtract returning high narrow"]
60563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60564#[inline]
60565#[cfg(target_endian = "big")]
60566#[target_feature(enable = "neon")]
60567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60569#[cfg_attr(
60570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60571    assert_instr(rsubhn)
60572)]
60573#[cfg_attr(
60574    not(target_arch = "arm"),
60575    stable(feature = "neon_intrinsics", since = "1.59.0")
60576)]
60577#[cfg_attr(
60578    target_arch = "arm",
60579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60580)]
60581pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60582    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
60583    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
60584    unsafe {
60585        let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
60586        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
60587    }
60588}
60589#[doc = "Rounding subtract returning high narrow"]
60590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60591#[inline]
60592#[cfg(target_endian = "little")]
60593#[target_feature(enable = "neon")]
60594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60596#[cfg_attr(
60597    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60598    assert_instr(rsubhn)
60599)]
60600#[cfg_attr(
60601    not(target_arch = "arm"),
60602    stable(feature = "neon_intrinsics", since = "1.59.0")
60603)]
60604#[cfg_attr(
60605    target_arch = "arm",
60606    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60607)]
60608pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60609    unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
60610}
60611#[doc = "Rounding subtract returning high narrow"]
60612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60613#[inline]
60614#[cfg(target_endian = "big")]
60615#[target_feature(enable = "neon")]
60616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60618#[cfg_attr(
60619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60620    assert_instr(rsubhn)
60621)]
60622#[cfg_attr(
60623    not(target_arch = "arm"),
60624    stable(feature = "neon_intrinsics", since = "1.59.0")
60625)]
60626#[cfg_attr(
60627    target_arch = "arm",
60628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60629)]
60630pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60631    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
60632    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
60633    unsafe {
60634        let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
60635        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
60636    }
60637}
60638#[doc = "Rounding subtract returning high narrow"]
60639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60640#[inline]
60641#[cfg(target_endian = "little")]
60642#[target_feature(enable = "neon")]
60643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60645#[cfg_attr(
60646    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60647    assert_instr(rsubhn)
60648)]
60649#[cfg_attr(
60650    not(target_arch = "arm"),
60651    stable(feature = "neon_intrinsics", since = "1.59.0")
60652)]
60653#[cfg_attr(
60654    target_arch = "arm",
60655    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60656)]
60657pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60658    unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
60659}
60660#[doc = "Rounding subtract returning high narrow"]
60661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60662#[inline]
60663#[cfg(target_endian = "big")]
60664#[target_feature(enable = "neon")]
60665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60667#[cfg_attr(
60668    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60669    assert_instr(rsubhn)
60670)]
60671#[cfg_attr(
60672    not(target_arch = "arm"),
60673    stable(feature = "neon_intrinsics", since = "1.59.0")
60674)]
60675#[cfg_attr(
60676    target_arch = "arm",
60677    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60678)]
60679pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60680    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
60681    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
60682    unsafe {
60683        let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
60684        simd_shuffle!(ret_val, ret_val, [1, 0])
60685    }
60686}
60687#[doc = "Insert vector element from another vector element"]
60688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
60689#[inline]
60690#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60692#[cfg_attr(
60693    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60694    assert_instr(nop, LANE = 0)
60695)]
60696#[rustc_legacy_const_generics(2)]
60697#[target_feature(enable = "neon,fp16")]
60698#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60699pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
60700    static_assert_uimm_bits!(LANE, 2);
60701    unsafe { simd_insert!(b, LANE as u32, a) }
60702}
60703#[doc = "Insert vector element from another vector element"]
60704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
60705#[inline]
60706#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60708#[cfg_attr(
60709    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60710    assert_instr(nop, LANE = 0)
60711)]
60712#[rustc_legacy_const_generics(2)]
60713#[target_feature(enable = "neon,fp16")]
60714#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60715pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
60716    static_assert_uimm_bits!(LANE, 3);
60717    unsafe { simd_insert!(b, LANE as u32, a) }
60718}
60719#[doc = "Insert vector element from another vector element"]
60720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
60721#[inline]
60722#[target_feature(enable = "neon")]
60723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60725#[cfg_attr(
60726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60727    assert_instr(nop, LANE = 0)
60728)]
60729#[rustc_legacy_const_generics(2)]
60730#[cfg_attr(
60731    not(target_arch = "arm"),
60732    stable(feature = "neon_intrinsics", since = "1.59.0")
60733)]
60734#[cfg_attr(
60735    target_arch = "arm",
60736    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60737)]
60738pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
60739    static_assert_uimm_bits!(LANE, 1);
60740    unsafe { simd_insert!(b, LANE as u32, a) }
60741}
60742#[doc = "Insert vector element from another vector element"]
60743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
60744#[inline]
60745#[target_feature(enable = "neon")]
60746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60748#[cfg_attr(
60749    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60750    assert_instr(nop, LANE = 0)
60751)]
60752#[rustc_legacy_const_generics(2)]
60753#[cfg_attr(
60754    not(target_arch = "arm"),
60755    stable(feature = "neon_intrinsics", since = "1.59.0")
60756)]
60757#[cfg_attr(
60758    target_arch = "arm",
60759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60760)]
60761pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
60762    static_assert_uimm_bits!(LANE, 2);
60763    unsafe { simd_insert!(b, LANE as u32, a) }
60764}
60765#[doc = "Insert vector element from another vector element"]
60766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
60767#[inline]
60768#[target_feature(enable = "neon")]
60769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60771#[cfg_attr(
60772    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60773    assert_instr(nop, LANE = 0)
60774)]
60775#[rustc_legacy_const_generics(2)]
60776#[cfg_attr(
60777    not(target_arch = "arm"),
60778    stable(feature = "neon_intrinsics", since = "1.59.0")
60779)]
60780#[cfg_attr(
60781    target_arch = "arm",
60782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60783)]
60784pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
60785    static_assert_uimm_bits!(LANE, 3);
60786    unsafe { simd_insert!(b, LANE as u32, a) }
60787}
60788#[doc = "Insert vector element from another vector element"]
60789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
60790#[inline]
60791#[target_feature(enable = "neon")]
60792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60794#[cfg_attr(
60795    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60796    assert_instr(nop, LANE = 0)
60797)]
60798#[rustc_legacy_const_generics(2)]
60799#[cfg_attr(
60800    not(target_arch = "arm"),
60801    stable(feature = "neon_intrinsics", since = "1.59.0")
60802)]
60803#[cfg_attr(
60804    target_arch = "arm",
60805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60806)]
60807pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
60808    static_assert_uimm_bits!(LANE, 4);
60809    unsafe { simd_insert!(b, LANE as u32, a) }
60810}
60811#[doc = "Insert vector element from another vector element"]
60812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
60813#[inline]
60814#[target_feature(enable = "neon")]
60815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60817#[cfg_attr(
60818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60819    assert_instr(nop, LANE = 0)
60820)]
60821#[rustc_legacy_const_generics(2)]
60822#[cfg_attr(
60823    not(target_arch = "arm"),
60824    stable(feature = "neon_intrinsics", since = "1.59.0")
60825)]
60826#[cfg_attr(
60827    target_arch = "arm",
60828    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60829)]
60830pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
60831    static_assert_uimm_bits!(LANE, 2);
60832    unsafe { simd_insert!(b, LANE as u32, a) }
60833}
60834#[doc = "Insert vector element from another vector element"]
60835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
60836#[inline]
60837#[target_feature(enable = "neon")]
60838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60840#[cfg_attr(
60841    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60842    assert_instr(nop, LANE = 0)
60843)]
60844#[rustc_legacy_const_generics(2)]
60845#[cfg_attr(
60846    not(target_arch = "arm"),
60847    stable(feature = "neon_intrinsics", since = "1.59.0")
60848)]
60849#[cfg_attr(
60850    target_arch = "arm",
60851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60852)]
60853pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
60854    static_assert_uimm_bits!(LANE, 3);
60855    unsafe { simd_insert!(b, LANE as u32, a) }
60856}
60857#[doc = "Insert vector element from another vector element"]
60858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
60859#[inline]
60860#[target_feature(enable = "neon")]
60861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60863#[cfg_attr(
60864    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60865    assert_instr(nop, LANE = 0)
60866)]
60867#[rustc_legacy_const_generics(2)]
60868#[cfg_attr(
60869    not(target_arch = "arm"),
60870    stable(feature = "neon_intrinsics", since = "1.59.0")
60871)]
60872#[cfg_attr(
60873    target_arch = "arm",
60874    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60875)]
60876pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
60877    static_assert_uimm_bits!(LANE, 1);
60878    unsafe { simd_insert!(b, LANE as u32, a) }
60879}
60880#[doc = "Insert vector element from another vector element"]
60881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
60882#[inline]
60883#[target_feature(enable = "neon")]
60884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60885#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60886#[cfg_attr(
60887    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60888    assert_instr(nop, LANE = 0)
60889)]
60890#[rustc_legacy_const_generics(2)]
60891#[cfg_attr(
60892    not(target_arch = "arm"),
60893    stable(feature = "neon_intrinsics", since = "1.59.0")
60894)]
60895#[cfg_attr(
60896    target_arch = "arm",
60897    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60898)]
60899pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
60900    static_assert_uimm_bits!(LANE, 2);
60901    unsafe { simd_insert!(b, LANE as u32, a) }
60902}
60903#[doc = "Insert vector element from another vector element"]
60904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
60905#[inline]
60906#[target_feature(enable = "neon")]
60907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60909#[cfg_attr(
60910    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60911    assert_instr(nop, LANE = 0)
60912)]
60913#[rustc_legacy_const_generics(2)]
60914#[cfg_attr(
60915    not(target_arch = "arm"),
60916    stable(feature = "neon_intrinsics", since = "1.59.0")
60917)]
60918#[cfg_attr(
60919    target_arch = "arm",
60920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60921)]
60922pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
60923    static_assert_uimm_bits!(LANE, 1);
60924    unsafe { simd_insert!(b, LANE as u32, a) }
60925}
60926#[doc = "Insert vector element from another vector element"]
60927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
60928#[inline]
60929#[target_feature(enable = "neon")]
60930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60932#[cfg_attr(
60933    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60934    assert_instr(nop, LANE = 0)
60935)]
60936#[rustc_legacy_const_generics(2)]
60937#[cfg_attr(
60938    not(target_arch = "arm"),
60939    stable(feature = "neon_intrinsics", since = "1.59.0")
60940)]
60941#[cfg_attr(
60942    target_arch = "arm",
60943    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60944)]
60945pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
60946    static_assert_uimm_bits!(LANE, 3);
60947    unsafe { simd_insert!(b, LANE as u32, a) }
60948}
60949#[doc = "Insert vector element from another vector element"]
60950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
60951#[inline]
60952#[target_feature(enable = "neon")]
60953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60955#[cfg_attr(
60956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60957    assert_instr(nop, LANE = 0)
60958)]
60959#[rustc_legacy_const_generics(2)]
60960#[cfg_attr(
60961    not(target_arch = "arm"),
60962    stable(feature = "neon_intrinsics", since = "1.59.0")
60963)]
60964#[cfg_attr(
60965    target_arch = "arm",
60966    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60967)]
60968pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
60969    static_assert_uimm_bits!(LANE, 4);
60970    unsafe { simd_insert!(b, LANE as u32, a) }
60971}
60972#[doc = "Insert vector element from another vector element"]
60973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
60974#[inline]
60975#[target_feature(enable = "neon")]
60976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60978#[cfg_attr(
60979    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60980    assert_instr(nop, LANE = 0)
60981)]
60982#[rustc_legacy_const_generics(2)]
60983#[cfg_attr(
60984    not(target_arch = "arm"),
60985    stable(feature = "neon_intrinsics", since = "1.59.0")
60986)]
60987#[cfg_attr(
60988    target_arch = "arm",
60989    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60990)]
60991pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
60992    static_assert_uimm_bits!(LANE, 2);
60993    unsafe { simd_insert!(b, LANE as u32, a) }
60994}
60995#[doc = "Insert vector element from another vector element"]
60996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
60997#[inline]
60998#[target_feature(enable = "neon")]
60999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61001#[cfg_attr(
61002    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61003    assert_instr(nop, LANE = 0)
61004)]
61005#[rustc_legacy_const_generics(2)]
61006#[cfg_attr(
61007    not(target_arch = "arm"),
61008    stable(feature = "neon_intrinsics", since = "1.59.0")
61009)]
61010#[cfg_attr(
61011    target_arch = "arm",
61012    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61013)]
61014pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
61015    static_assert_uimm_bits!(LANE, 3);
61016    unsafe { simd_insert!(b, LANE as u32, a) }
61017}
61018#[doc = "Insert vector element from another vector element"]
61019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
61020#[inline]
61021#[target_feature(enable = "neon")]
61022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61024#[cfg_attr(
61025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61026    assert_instr(nop, LANE = 0)
61027)]
61028#[rustc_legacy_const_generics(2)]
61029#[cfg_attr(
61030    not(target_arch = "arm"),
61031    stable(feature = "neon_intrinsics", since = "1.59.0")
61032)]
61033#[cfg_attr(
61034    target_arch = "arm",
61035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61036)]
61037pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
61038    static_assert_uimm_bits!(LANE, 1);
61039    unsafe { simd_insert!(b, LANE as u32, a) }
61040}
61041#[doc = "Insert vector element from another vector element"]
61042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
61043#[inline]
61044#[target_feature(enable = "neon")]
61045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61047#[cfg_attr(
61048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61049    assert_instr(nop, LANE = 0)
61050)]
61051#[rustc_legacy_const_generics(2)]
61052#[cfg_attr(
61053    not(target_arch = "arm"),
61054    stable(feature = "neon_intrinsics", since = "1.59.0")
61055)]
61056#[cfg_attr(
61057    target_arch = "arm",
61058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61059)]
61060pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
61061    static_assert_uimm_bits!(LANE, 2);
61062    unsafe { simd_insert!(b, LANE as u32, a) }
61063}
61064#[doc = "Insert vector element from another vector element"]
61065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
61066#[inline]
61067#[target_feature(enable = "neon")]
61068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61070#[cfg_attr(
61071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61072    assert_instr(nop, LANE = 0)
61073)]
61074#[rustc_legacy_const_generics(2)]
61075#[cfg_attr(
61076    not(target_arch = "arm"),
61077    stable(feature = "neon_intrinsics", since = "1.59.0")
61078)]
61079#[cfg_attr(
61080    target_arch = "arm",
61081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61082)]
61083pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
61084    static_assert_uimm_bits!(LANE, 1);
61085    unsafe { simd_insert!(b, LANE as u32, a) }
61086}
61087#[doc = "Insert vector element from another vector element"]
61088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
61089#[inline]
61090#[target_feature(enable = "neon")]
61091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61093#[cfg_attr(
61094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61095    assert_instr(nop, LANE = 0)
61096)]
61097#[rustc_legacy_const_generics(2)]
61098#[cfg_attr(
61099    not(target_arch = "arm"),
61100    stable(feature = "neon_intrinsics", since = "1.59.0")
61101)]
61102#[cfg_attr(
61103    target_arch = "arm",
61104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61105)]
61106pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
61107    static_assert_uimm_bits!(LANE, 3);
61108    unsafe { simd_insert!(b, LANE as u32, a) }
61109}
61110#[doc = "Insert vector element from another vector element"]
61111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
61112#[inline]
61113#[target_feature(enable = "neon")]
61114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61116#[cfg_attr(
61117    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61118    assert_instr(nop, LANE = 0)
61119)]
61120#[rustc_legacy_const_generics(2)]
61121#[cfg_attr(
61122    not(target_arch = "arm"),
61123    stable(feature = "neon_intrinsics", since = "1.59.0")
61124)]
61125#[cfg_attr(
61126    target_arch = "arm",
61127    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61128)]
61129pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
61130    static_assert_uimm_bits!(LANE, 4);
61131    unsafe { simd_insert!(b, LANE as u32, a) }
61132}
61133#[doc = "Insert vector element from another vector element"]
61134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
61135#[inline]
61136#[target_feature(enable = "neon")]
61137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61139#[cfg_attr(
61140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61141    assert_instr(nop, LANE = 0)
61142)]
61143#[rustc_legacy_const_generics(2)]
61144#[cfg_attr(
61145    not(target_arch = "arm"),
61146    stable(feature = "neon_intrinsics", since = "1.59.0")
61147)]
61148#[cfg_attr(
61149    target_arch = "arm",
61150    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61151)]
61152pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
61153    static_assert_uimm_bits!(LANE, 2);
61154    unsafe { simd_insert!(b, LANE as u32, a) }
61155}
61156#[doc = "Insert vector element from another vector element"]
61157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
61158#[inline]
61159#[target_feature(enable = "neon")]
61160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61162#[cfg_attr(
61163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61164    assert_instr(nop, LANE = 0)
61165)]
61166#[rustc_legacy_const_generics(2)]
61167#[cfg_attr(
61168    not(target_arch = "arm"),
61169    stable(feature = "neon_intrinsics", since = "1.59.0")
61170)]
61171#[cfg_attr(
61172    target_arch = "arm",
61173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61174)]
61175pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
61176    static_assert_uimm_bits!(LANE, 3);
61177    unsafe { simd_insert!(b, LANE as u32, a) }
61178}
61179#[doc = "Insert vector element from another vector element"]
61180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
61181#[inline]
61182#[target_feature(enable = "neon,aes")]
61183#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61185#[cfg_attr(
61186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61187    assert_instr(nop, LANE = 0)
61188)]
61189#[rustc_legacy_const_generics(2)]
61190#[cfg_attr(
61191    not(target_arch = "arm"),
61192    stable(feature = "neon_intrinsics", since = "1.59.0")
61193)]
61194#[cfg_attr(
61195    target_arch = "arm",
61196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61197)]
61198pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
61199    static_assert!(LANE == 0);
61200    unsafe { simd_insert!(b, LANE as u32, a) }
61201}
61202#[doc = "Insert vector element from another vector element"]
61203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
61204#[inline]
61205#[target_feature(enable = "neon")]
61206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61208#[cfg_attr(
61209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61210    assert_instr(nop, LANE = 0)
61211)]
61212#[rustc_legacy_const_generics(2)]
61213#[cfg_attr(
61214    not(target_arch = "arm"),
61215    stable(feature = "neon_intrinsics", since = "1.59.0")
61216)]
61217#[cfg_attr(
61218    target_arch = "arm",
61219    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61220)]
61221pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
61222    static_assert!(LANE == 0);
61223    unsafe { simd_insert!(b, LANE as u32, a) }
61224}
61225#[doc = "Insert vector element from another vector element"]
61226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
61227#[inline]
61228#[target_feature(enable = "neon")]
61229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61231#[cfg_attr(
61232    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61233    assert_instr(nop, LANE = 0)
61234)]
61235#[rustc_legacy_const_generics(2)]
61236#[cfg_attr(
61237    not(target_arch = "arm"),
61238    stable(feature = "neon_intrinsics", since = "1.59.0")
61239)]
61240#[cfg_attr(
61241    target_arch = "arm",
61242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61243)]
61244pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
61245    static_assert!(LANE == 0);
61246    unsafe { simd_insert!(b, LANE as u32, a) }
61247}
61248#[doc = "Insert vector element from another vector element"]
61249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
61250#[inline]
61251#[target_feature(enable = "neon,aes")]
61252#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61254#[cfg_attr(
61255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61256    assert_instr(nop, LANE = 0)
61257)]
61258#[rustc_legacy_const_generics(2)]
61259#[cfg_attr(
61260    not(target_arch = "arm"),
61261    stable(feature = "neon_intrinsics", since = "1.59.0")
61262)]
61263#[cfg_attr(
61264    target_arch = "arm",
61265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61266)]
61267pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
61268    static_assert_uimm_bits!(LANE, 1);
61269    unsafe { simd_insert!(b, LANE as u32, a) }
61270}
61271#[doc = "SHA1 hash update accelerator, choose."]
61272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
61273#[inline]
61274#[target_feature(enable = "sha2")]
61275#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61276#[cfg_attr(test, assert_instr(sha1c))]
61277#[cfg_attr(
61278    target_arch = "arm",
61279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61280)]
61281#[cfg_attr(
61282    not(target_arch = "arm"),
61283    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61284)]
61285pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61286    unsafe extern "unadjusted" {
61287        #[cfg_attr(
61288            any(target_arch = "aarch64", target_arch = "arm64ec"),
61289            link_name = "llvm.aarch64.crypto.sha1c"
61290        )]
61291        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
61292        fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61293    }
61294    unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) }
61295}
61296#[doc = "SHA1 fixed rotate."]
61297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
61298#[inline]
61299#[target_feature(enable = "sha2")]
61300#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61301#[cfg_attr(test, assert_instr(sha1h))]
61302#[cfg_attr(
61303    target_arch = "arm",
61304    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61305)]
61306#[cfg_attr(
61307    not(target_arch = "arm"),
61308    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61309)]
61310pub fn vsha1h_u32(hash_e: u32) -> u32 {
61311    unsafe extern "unadjusted" {
61312        #[cfg_attr(
61313            any(target_arch = "aarch64", target_arch = "arm64ec"),
61314            link_name = "llvm.aarch64.crypto.sha1h"
61315        )]
61316        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
61317        fn _vsha1h_u32(hash_e: u32) -> u32;
61318    }
61319    unsafe { _vsha1h_u32(hash_e) }
61320}
61321#[doc = "SHA1 hash update accelerator, majority"]
61322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
61323#[inline]
61324#[target_feature(enable = "sha2")]
61325#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61326#[cfg_attr(test, assert_instr(sha1m))]
61327#[cfg_attr(
61328    target_arch = "arm",
61329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61330)]
61331#[cfg_attr(
61332    not(target_arch = "arm"),
61333    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61334)]
61335pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61336    unsafe extern "unadjusted" {
61337        #[cfg_attr(
61338            any(target_arch = "aarch64", target_arch = "arm64ec"),
61339            link_name = "llvm.aarch64.crypto.sha1m"
61340        )]
61341        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
61342        fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61343    }
61344    unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) }
61345}
61346#[doc = "SHA1 hash update accelerator, parity"]
61347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
61348#[inline]
61349#[target_feature(enable = "sha2")]
61350#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61351#[cfg_attr(test, assert_instr(sha1p))]
61352#[cfg_attr(
61353    target_arch = "arm",
61354    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61355)]
61356#[cfg_attr(
61357    not(target_arch = "arm"),
61358    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61359)]
61360pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61361    unsafe extern "unadjusted" {
61362        #[cfg_attr(
61363            any(target_arch = "aarch64", target_arch = "arm64ec"),
61364            link_name = "llvm.aarch64.crypto.sha1p"
61365        )]
61366        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
61367        fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61368    }
61369    unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) }
61370}
61371#[doc = "SHA1 schedule update accelerator, first part."]
61372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
61373#[inline]
61374#[target_feature(enable = "sha2")]
61375#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61376#[cfg_attr(test, assert_instr(sha1su0))]
61377#[cfg_attr(
61378    target_arch = "arm",
61379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61380)]
61381#[cfg_attr(
61382    not(target_arch = "arm"),
61383    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61384)]
61385pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
61386    unsafe extern "unadjusted" {
61387        #[cfg_attr(
61388            any(target_arch = "aarch64", target_arch = "arm64ec"),
61389            link_name = "llvm.aarch64.crypto.sha1su0"
61390        )]
61391        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
61392        fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
61393    }
61394    unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) }
61395}
61396#[doc = "SHA1 schedule update accelerator, second part."]
61397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
61398#[inline]
61399#[target_feature(enable = "sha2")]
61400#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61401#[cfg_attr(test, assert_instr(sha1su1))]
61402#[cfg_attr(
61403    target_arch = "arm",
61404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61405)]
61406#[cfg_attr(
61407    not(target_arch = "arm"),
61408    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61409)]
61410pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61411    unsafe extern "unadjusted" {
61412        #[cfg_attr(
61413            any(target_arch = "aarch64", target_arch = "arm64ec"),
61414            link_name = "llvm.aarch64.crypto.sha1su1"
61415        )]
61416        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
61417        fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
61418    }
61419    unsafe { _vsha1su1q_u32(tw0_3, w12_15) }
61420}
61421#[doc = "SHA1 schedule update accelerator, upper part."]
61422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
61423#[inline]
61424#[target_feature(enable = "sha2")]
61425#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61426#[cfg_attr(test, assert_instr(sha256h2))]
61427#[cfg_attr(
61428    target_arch = "arm",
61429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61430)]
61431#[cfg_attr(
61432    not(target_arch = "arm"),
61433    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61434)]
61435pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61436    unsafe extern "unadjusted" {
61437        #[cfg_attr(
61438            any(target_arch = "aarch64", target_arch = "arm64ec"),
61439            link_name = "llvm.aarch64.crypto.sha256h2"
61440        )]
61441        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
61442        fn _vsha256h2q_u32(
61443            hash_abcd: uint32x4_t,
61444            hash_efgh: uint32x4_t,
61445            wk: uint32x4_t,
61446        ) -> uint32x4_t;
61447    }
61448    unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) }
61449}
61450#[doc = "SHA1 schedule update accelerator, first part."]
61451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
61452#[inline]
61453#[target_feature(enable = "sha2")]
61454#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61455#[cfg_attr(test, assert_instr(sha256h))]
61456#[cfg_attr(
61457    target_arch = "arm",
61458    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61459)]
61460#[cfg_attr(
61461    not(target_arch = "arm"),
61462    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61463)]
61464pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61465    unsafe extern "unadjusted" {
61466        #[cfg_attr(
61467            any(target_arch = "aarch64", target_arch = "arm64ec"),
61468            link_name = "llvm.aarch64.crypto.sha256h"
61469        )]
61470        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
61471        fn _vsha256hq_u32(
61472            hash_abcd: uint32x4_t,
61473            hash_efgh: uint32x4_t,
61474            wk: uint32x4_t,
61475        ) -> uint32x4_t;
61476    }
61477    unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) }
61478}
61479#[doc = "SHA256 schedule update accelerator, first part."]
61480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
61481#[inline]
61482#[target_feature(enable = "sha2")]
61483#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61484#[cfg_attr(test, assert_instr(sha256su0))]
61485#[cfg_attr(
61486    target_arch = "arm",
61487    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61488)]
61489#[cfg_attr(
61490    not(target_arch = "arm"),
61491    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61492)]
61493pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
61494    unsafe extern "unadjusted" {
61495        #[cfg_attr(
61496            any(target_arch = "aarch64", target_arch = "arm64ec"),
61497            link_name = "llvm.aarch64.crypto.sha256su0"
61498        )]
61499        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
61500        fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
61501    }
61502    unsafe { _vsha256su0q_u32(w0_3, w4_7) }
61503}
61504#[doc = "SHA256 schedule update accelerator, second part."]
61505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
61506#[inline]
61507#[target_feature(enable = "sha2")]
61508#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61509#[cfg_attr(test, assert_instr(sha256su1))]
61510#[cfg_attr(
61511    target_arch = "arm",
61512    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61513)]
61514#[cfg_attr(
61515    not(target_arch = "arm"),
61516    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61517)]
61518pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61519    unsafe extern "unadjusted" {
61520        #[cfg_attr(
61521            any(target_arch = "aarch64", target_arch = "arm64ec"),
61522            link_name = "llvm.aarch64.crypto.sha256su1"
61523        )]
61524        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
61525        fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
61526            -> uint32x4_t;
61527    }
61528    unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
61529}
61530#[doc = "Shift Right and Insert (immediate)"]
61531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
61532#[inline]
61533#[target_feature(enable = "neon")]
61534#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61535fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
61536    unsafe extern "unadjusted" {
61537        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
61538        fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
61539    }
61540    unsafe { _vshiftins_v16i8(a, b, c) }
61541}
61542#[doc = "Shift Right and Insert (immediate)"]
61543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
61544#[inline]
61545#[target_feature(enable = "neon")]
61546#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61547fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
61548    unsafe extern "unadjusted" {
61549        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
61550        fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
61551    }
61552    unsafe { _vshiftins_v1i64(a, b, c) }
61553}
61554#[doc = "Shift Right and Insert (immediate)"]
61555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
61556#[inline]
61557#[target_feature(enable = "neon")]
61558#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61559fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
61560    unsafe extern "unadjusted" {
61561        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
61562        fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
61563    }
61564    unsafe { _vshiftins_v2i32(a, b, c) }
61565}
61566#[doc = "Shift Right and Insert (immediate)"]
61567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
61568#[inline]
61569#[target_feature(enable = "neon")]
61570#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61571fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
61572    unsafe extern "unadjusted" {
61573        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
61574        fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
61575    }
61576    unsafe { _vshiftins_v2i64(a, b, c) }
61577}
61578#[doc = "Shift Right and Insert (immediate)"]
61579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
61580#[inline]
61581#[target_feature(enable = "neon")]
61582#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61583fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
61584    unsafe extern "unadjusted" {
61585        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
61586        fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
61587    }
61588    unsafe { _vshiftins_v4i16(a, b, c) }
61589}
61590#[doc = "Shift Right and Insert (immediate)"]
61591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
61592#[inline]
61593#[target_feature(enable = "neon")]
61594#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61595fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
61596    unsafe extern "unadjusted" {
61597        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
61598        fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
61599    }
61600    unsafe { _vshiftins_v4i32(a, b, c) }
61601}
61602#[doc = "Shift Right and Insert (immediate)"]
61603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
61604#[inline]
61605#[target_feature(enable = "neon")]
61606#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61607fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
61608    unsafe extern "unadjusted" {
61609        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
61610        fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
61611    }
61612    unsafe { _vshiftins_v8i16(a, b, c) }
61613}
61614#[doc = "Shift Right and Insert (immediate)"]
61615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
61616#[inline]
61617#[target_feature(enable = "neon")]
61618#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61619fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
61620    unsafe extern "unadjusted" {
61621        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
61622        fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
61623    }
61624    unsafe { _vshiftins_v8i8(a, b, c) }
61625}
61626#[doc = "Shift left"]
61627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
61628#[inline]
61629#[target_feature(enable = "neon")]
61630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61632#[cfg_attr(
61633    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61634    assert_instr(shl, N = 2)
61635)]
61636#[rustc_legacy_const_generics(1)]
61637#[cfg_attr(
61638    not(target_arch = "arm"),
61639    stable(feature = "neon_intrinsics", since = "1.59.0")
61640)]
61641#[cfg_attr(
61642    target_arch = "arm",
61643    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61644)]
61645pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
61646    static_assert_uimm_bits!(N, 3);
61647    unsafe { simd_shl(a, vdup_n_s8(N as _)) }
61648}
61649#[doc = "Shift left"]
61650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
61651#[inline]
61652#[target_feature(enable = "neon")]
61653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61655#[cfg_attr(
61656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61657    assert_instr(shl, N = 2)
61658)]
61659#[rustc_legacy_const_generics(1)]
61660#[cfg_attr(
61661    not(target_arch = "arm"),
61662    stable(feature = "neon_intrinsics", since = "1.59.0")
61663)]
61664#[cfg_attr(
61665    target_arch = "arm",
61666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61667)]
61668pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
61669    static_assert_uimm_bits!(N, 3);
61670    unsafe { simd_shl(a, vdupq_n_s8(N as _)) }
61671}
61672#[doc = "Shift left"]
61673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
61674#[inline]
61675#[target_feature(enable = "neon")]
61676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61677#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61678#[cfg_attr(
61679    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61680    assert_instr(shl, N = 2)
61681)]
61682#[rustc_legacy_const_generics(1)]
61683#[cfg_attr(
61684    not(target_arch = "arm"),
61685    stable(feature = "neon_intrinsics", since = "1.59.0")
61686)]
61687#[cfg_attr(
61688    target_arch = "arm",
61689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61690)]
61691pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
61692    static_assert_uimm_bits!(N, 4);
61693    unsafe { simd_shl(a, vdup_n_s16(N as _)) }
61694}
61695#[doc = "Shift left"]
61696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
61697#[inline]
61698#[target_feature(enable = "neon")]
61699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61701#[cfg_attr(
61702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61703    assert_instr(shl, N = 2)
61704)]
61705#[rustc_legacy_const_generics(1)]
61706#[cfg_attr(
61707    not(target_arch = "arm"),
61708    stable(feature = "neon_intrinsics", since = "1.59.0")
61709)]
61710#[cfg_attr(
61711    target_arch = "arm",
61712    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61713)]
61714pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
61715    static_assert_uimm_bits!(N, 4);
61716    unsafe { simd_shl(a, vdupq_n_s16(N as _)) }
61717}
61718#[doc = "Shift left"]
61719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
61720#[inline]
61721#[target_feature(enable = "neon")]
61722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61724#[cfg_attr(
61725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61726    assert_instr(shl, N = 2)
61727)]
61728#[rustc_legacy_const_generics(1)]
61729#[cfg_attr(
61730    not(target_arch = "arm"),
61731    stable(feature = "neon_intrinsics", since = "1.59.0")
61732)]
61733#[cfg_attr(
61734    target_arch = "arm",
61735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61736)]
61737pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
61738    static_assert_uimm_bits!(N, 5);
61739    unsafe { simd_shl(a, vdup_n_s32(N as _)) }
61740}
61741#[doc = "Shift left"]
61742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
61743#[inline]
61744#[target_feature(enable = "neon")]
61745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61747#[cfg_attr(
61748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61749    assert_instr(shl, N = 2)
61750)]
61751#[rustc_legacy_const_generics(1)]
61752#[cfg_attr(
61753    not(target_arch = "arm"),
61754    stable(feature = "neon_intrinsics", since = "1.59.0")
61755)]
61756#[cfg_attr(
61757    target_arch = "arm",
61758    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61759)]
61760pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
61761    static_assert_uimm_bits!(N, 5);
61762    unsafe { simd_shl(a, vdupq_n_s32(N as _)) }
61763}
61764#[doc = "Shift left"]
61765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
61766#[inline]
61767#[target_feature(enable = "neon")]
61768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61770#[cfg_attr(
61771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61772    assert_instr(shl, N = 2)
61773)]
61774#[rustc_legacy_const_generics(1)]
61775#[cfg_attr(
61776    not(target_arch = "arm"),
61777    stable(feature = "neon_intrinsics", since = "1.59.0")
61778)]
61779#[cfg_attr(
61780    target_arch = "arm",
61781    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61782)]
61783pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
61784    static_assert_uimm_bits!(N, 6);
61785    unsafe { simd_shl(a, vdup_n_s64(N as _)) }
61786}
61787#[doc = "Shift left"]
61788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
61789#[inline]
61790#[target_feature(enable = "neon")]
61791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61793#[cfg_attr(
61794    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61795    assert_instr(shl, N = 2)
61796)]
61797#[rustc_legacy_const_generics(1)]
61798#[cfg_attr(
61799    not(target_arch = "arm"),
61800    stable(feature = "neon_intrinsics", since = "1.59.0")
61801)]
61802#[cfg_attr(
61803    target_arch = "arm",
61804    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61805)]
61806pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
61807    static_assert_uimm_bits!(N, 6);
61808    unsafe { simd_shl(a, vdupq_n_s64(N as _)) }
61809}
61810#[doc = "Shift left"]
61811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
61812#[inline]
61813#[target_feature(enable = "neon")]
61814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61816#[cfg_attr(
61817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61818    assert_instr(shl, N = 2)
61819)]
61820#[rustc_legacy_const_generics(1)]
61821#[cfg_attr(
61822    not(target_arch = "arm"),
61823    stable(feature = "neon_intrinsics", since = "1.59.0")
61824)]
61825#[cfg_attr(
61826    target_arch = "arm",
61827    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61828)]
61829pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
61830    static_assert_uimm_bits!(N, 3);
61831    unsafe { simd_shl(a, vdup_n_u8(N as _)) }
61832}
61833#[doc = "Shift left"]
61834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
61835#[inline]
61836#[target_feature(enable = "neon")]
61837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61839#[cfg_attr(
61840    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61841    assert_instr(shl, N = 2)
61842)]
61843#[rustc_legacy_const_generics(1)]
61844#[cfg_attr(
61845    not(target_arch = "arm"),
61846    stable(feature = "neon_intrinsics", since = "1.59.0")
61847)]
61848#[cfg_attr(
61849    target_arch = "arm",
61850    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61851)]
61852pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
61853    static_assert_uimm_bits!(N, 3);
61854    unsafe { simd_shl(a, vdupq_n_u8(N as _)) }
61855}
61856#[doc = "Shift left"]
61857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
61858#[inline]
61859#[target_feature(enable = "neon")]
61860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61862#[cfg_attr(
61863    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61864    assert_instr(shl, N = 2)
61865)]
61866#[rustc_legacy_const_generics(1)]
61867#[cfg_attr(
61868    not(target_arch = "arm"),
61869    stable(feature = "neon_intrinsics", since = "1.59.0")
61870)]
61871#[cfg_attr(
61872    target_arch = "arm",
61873    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61874)]
61875pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
61876    static_assert_uimm_bits!(N, 4);
61877    unsafe { simd_shl(a, vdup_n_u16(N as _)) }
61878}
61879#[doc = "Shift left"]
61880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
61881#[inline]
61882#[target_feature(enable = "neon")]
61883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61885#[cfg_attr(
61886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61887    assert_instr(shl, N = 2)
61888)]
61889#[rustc_legacy_const_generics(1)]
61890#[cfg_attr(
61891    not(target_arch = "arm"),
61892    stable(feature = "neon_intrinsics", since = "1.59.0")
61893)]
61894#[cfg_attr(
61895    target_arch = "arm",
61896    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61897)]
61898pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
61899    static_assert_uimm_bits!(N, 4);
61900    unsafe { simd_shl(a, vdupq_n_u16(N as _)) }
61901}
61902#[doc = "Shift left"]
61903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
61904#[inline]
61905#[target_feature(enable = "neon")]
61906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61908#[cfg_attr(
61909    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61910    assert_instr(shl, N = 2)
61911)]
61912#[rustc_legacy_const_generics(1)]
61913#[cfg_attr(
61914    not(target_arch = "arm"),
61915    stable(feature = "neon_intrinsics", since = "1.59.0")
61916)]
61917#[cfg_attr(
61918    target_arch = "arm",
61919    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61920)]
61921pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
61922    static_assert_uimm_bits!(N, 5);
61923    unsafe { simd_shl(a, vdup_n_u32(N as _)) }
61924}
61925#[doc = "Shift left"]
61926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
61927#[inline]
61928#[target_feature(enable = "neon")]
61929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61931#[cfg_attr(
61932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61933    assert_instr(shl, N = 2)
61934)]
61935#[rustc_legacy_const_generics(1)]
61936#[cfg_attr(
61937    not(target_arch = "arm"),
61938    stable(feature = "neon_intrinsics", since = "1.59.0")
61939)]
61940#[cfg_attr(
61941    target_arch = "arm",
61942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61943)]
61944pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
61945    static_assert_uimm_bits!(N, 5);
61946    unsafe { simd_shl(a, vdupq_n_u32(N as _)) }
61947}
61948#[doc = "Shift left"]
61949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
61950#[inline]
61951#[target_feature(enable = "neon")]
61952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61954#[cfg_attr(
61955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61956    assert_instr(shl, N = 2)
61957)]
61958#[rustc_legacy_const_generics(1)]
61959#[cfg_attr(
61960    not(target_arch = "arm"),
61961    stable(feature = "neon_intrinsics", since = "1.59.0")
61962)]
61963#[cfg_attr(
61964    target_arch = "arm",
61965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61966)]
61967pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
61968    static_assert_uimm_bits!(N, 6);
61969    unsafe { simd_shl(a, vdup_n_u64(N as _)) }
61970}
61971#[doc = "Shift left"]
61972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
61973#[inline]
61974#[target_feature(enable = "neon")]
61975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61977#[cfg_attr(
61978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61979    assert_instr(shl, N = 2)
61980)]
61981#[rustc_legacy_const_generics(1)]
61982#[cfg_attr(
61983    not(target_arch = "arm"),
61984    stable(feature = "neon_intrinsics", since = "1.59.0")
61985)]
61986#[cfg_attr(
61987    target_arch = "arm",
61988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61989)]
61990pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
61991    static_assert_uimm_bits!(N, 6);
61992    unsafe { simd_shl(a, vdupq_n_u64(N as _)) }
61993}
61994#[doc = "Signed Shift left"]
61995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
61996#[inline]
61997#[target_feature(enable = "neon")]
61998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62000#[cfg_attr(
62001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62002    assert_instr(sshl)
62003)]
62004#[cfg_attr(
62005    not(target_arch = "arm"),
62006    stable(feature = "neon_intrinsics", since = "1.59.0")
62007)]
62008#[cfg_attr(
62009    target_arch = "arm",
62010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62011)]
62012pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
62013    unsafe extern "unadjusted" {
62014        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")]
62015        #[cfg_attr(
62016            any(target_arch = "aarch64", target_arch = "arm64ec"),
62017            link_name = "llvm.aarch64.neon.sshl.v8i8"
62018        )]
62019        fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
62020    }
62021    unsafe { _vshl_s8(a, b) }
62022}
62023#[doc = "Signed Shift left"]
62024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
62025#[inline]
62026#[target_feature(enable = "neon")]
62027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62029#[cfg_attr(
62030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62031    assert_instr(sshl)
62032)]
62033#[cfg_attr(
62034    not(target_arch = "arm"),
62035    stable(feature = "neon_intrinsics", since = "1.59.0")
62036)]
62037#[cfg_attr(
62038    target_arch = "arm",
62039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62040)]
62041pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
62042    unsafe extern "unadjusted" {
62043        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")]
62044        #[cfg_attr(
62045            any(target_arch = "aarch64", target_arch = "arm64ec"),
62046            link_name = "llvm.aarch64.neon.sshl.v16i8"
62047        )]
62048        fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
62049    }
62050    unsafe { _vshlq_s8(a, b) }
62051}
62052#[doc = "Signed Shift left"]
62053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
62054#[inline]
62055#[target_feature(enable = "neon")]
62056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62058#[cfg_attr(
62059    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62060    assert_instr(sshl)
62061)]
62062#[cfg_attr(
62063    not(target_arch = "arm"),
62064    stable(feature = "neon_intrinsics", since = "1.59.0")
62065)]
62066#[cfg_attr(
62067    target_arch = "arm",
62068    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62069)]
62070pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
62071    unsafe extern "unadjusted" {
62072        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")]
62073        #[cfg_attr(
62074            any(target_arch = "aarch64", target_arch = "arm64ec"),
62075            link_name = "llvm.aarch64.neon.sshl.v4i16"
62076        )]
62077        fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
62078    }
62079    unsafe { _vshl_s16(a, b) }
62080}
62081#[doc = "Signed Shift left"]
62082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
62083#[inline]
62084#[target_feature(enable = "neon")]
62085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62087#[cfg_attr(
62088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62089    assert_instr(sshl)
62090)]
62091#[cfg_attr(
62092    not(target_arch = "arm"),
62093    stable(feature = "neon_intrinsics", since = "1.59.0")
62094)]
62095#[cfg_attr(
62096    target_arch = "arm",
62097    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62098)]
62099pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
62100    unsafe extern "unadjusted" {
62101        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")]
62102        #[cfg_attr(
62103            any(target_arch = "aarch64", target_arch = "arm64ec"),
62104            link_name = "llvm.aarch64.neon.sshl.v8i16"
62105        )]
62106        fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
62107    }
62108    unsafe { _vshlq_s16(a, b) }
62109}
62110#[doc = "Signed Shift left"]
62111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
62112#[inline]
62113#[target_feature(enable = "neon")]
62114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62116#[cfg_attr(
62117    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62118    assert_instr(sshl)
62119)]
62120#[cfg_attr(
62121    not(target_arch = "arm"),
62122    stable(feature = "neon_intrinsics", since = "1.59.0")
62123)]
62124#[cfg_attr(
62125    target_arch = "arm",
62126    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62127)]
62128pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
62129    unsafe extern "unadjusted" {
62130        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")]
62131        #[cfg_attr(
62132            any(target_arch = "aarch64", target_arch = "arm64ec"),
62133            link_name = "llvm.aarch64.neon.sshl.v2i32"
62134        )]
62135        fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
62136    }
62137    unsafe { _vshl_s32(a, b) }
62138}
62139#[doc = "Signed Shift left"]
62140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
62141#[inline]
62142#[target_feature(enable = "neon")]
62143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62145#[cfg_attr(
62146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62147    assert_instr(sshl)
62148)]
62149#[cfg_attr(
62150    not(target_arch = "arm"),
62151    stable(feature = "neon_intrinsics", since = "1.59.0")
62152)]
62153#[cfg_attr(
62154    target_arch = "arm",
62155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62156)]
62157pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
62158    unsafe extern "unadjusted" {
62159        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")]
62160        #[cfg_attr(
62161            any(target_arch = "aarch64", target_arch = "arm64ec"),
62162            link_name = "llvm.aarch64.neon.sshl.v4i32"
62163        )]
62164        fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
62165    }
62166    unsafe { _vshlq_s32(a, b) }
62167}
62168#[doc = "Signed Shift left"]
62169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
62170#[inline]
62171#[target_feature(enable = "neon")]
62172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62174#[cfg_attr(
62175    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62176    assert_instr(sshl)
62177)]
62178#[cfg_attr(
62179    not(target_arch = "arm"),
62180    stable(feature = "neon_intrinsics", since = "1.59.0")
62181)]
62182#[cfg_attr(
62183    target_arch = "arm",
62184    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62185)]
62186pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
62187    unsafe extern "unadjusted" {
62188        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")]
62189        #[cfg_attr(
62190            any(target_arch = "aarch64", target_arch = "arm64ec"),
62191            link_name = "llvm.aarch64.neon.sshl.v1i64"
62192        )]
62193        fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
62194    }
62195    unsafe { _vshl_s64(a, b) }
62196}
62197#[doc = "Signed Shift left"]
62198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
62199#[inline]
62200#[target_feature(enable = "neon")]
62201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62203#[cfg_attr(
62204    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62205    assert_instr(sshl)
62206)]
62207#[cfg_attr(
62208    not(target_arch = "arm"),
62209    stable(feature = "neon_intrinsics", since = "1.59.0")
62210)]
62211#[cfg_attr(
62212    target_arch = "arm",
62213    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62214)]
62215pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
62216    unsafe extern "unadjusted" {
62217        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")]
62218        #[cfg_attr(
62219            any(target_arch = "aarch64", target_arch = "arm64ec"),
62220            link_name = "llvm.aarch64.neon.sshl.v2i64"
62221        )]
62222        fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
62223    }
62224    unsafe { _vshlq_s64(a, b) }
62225}
62226#[doc = "Unsigned Shift left"]
62227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
62228#[inline]
62229#[target_feature(enable = "neon")]
62230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62232#[cfg_attr(
62233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62234    assert_instr(ushl)
62235)]
62236#[cfg_attr(
62237    not(target_arch = "arm"),
62238    stable(feature = "neon_intrinsics", since = "1.59.0")
62239)]
62240#[cfg_attr(
62241    target_arch = "arm",
62242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62243)]
62244pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
62245    unsafe extern "unadjusted" {
62246        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")]
62247        #[cfg_attr(
62248            any(target_arch = "aarch64", target_arch = "arm64ec"),
62249            link_name = "llvm.aarch64.neon.ushl.v8i8"
62250        )]
62251        fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
62252    }
62253    unsafe { _vshl_u8(a, b) }
62254}
62255#[doc = "Unsigned Shift left"]
62256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
62257#[inline]
62258#[target_feature(enable = "neon")]
62259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62261#[cfg_attr(
62262    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62263    assert_instr(ushl)
62264)]
62265#[cfg_attr(
62266    not(target_arch = "arm"),
62267    stable(feature = "neon_intrinsics", since = "1.59.0")
62268)]
62269#[cfg_attr(
62270    target_arch = "arm",
62271    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62272)]
62273pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
62274    unsafe extern "unadjusted" {
62275        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")]
62276        #[cfg_attr(
62277            any(target_arch = "aarch64", target_arch = "arm64ec"),
62278            link_name = "llvm.aarch64.neon.ushl.v16i8"
62279        )]
62280        fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
62281    }
62282    unsafe { _vshlq_u8(a, b) }
62283}
62284#[doc = "Unsigned Shift left"]
62285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
62286#[inline]
62287#[target_feature(enable = "neon")]
62288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62290#[cfg_attr(
62291    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62292    assert_instr(ushl)
62293)]
62294#[cfg_attr(
62295    not(target_arch = "arm"),
62296    stable(feature = "neon_intrinsics", since = "1.59.0")
62297)]
62298#[cfg_attr(
62299    target_arch = "arm",
62300    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62301)]
62302pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
62303    unsafe extern "unadjusted" {
62304        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")]
62305        #[cfg_attr(
62306            any(target_arch = "aarch64", target_arch = "arm64ec"),
62307            link_name = "llvm.aarch64.neon.ushl.v4i16"
62308        )]
62309        fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
62310    }
62311    unsafe { _vshl_u16(a, b) }
62312}
62313#[doc = "Unsigned Shift left"]
62314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
62315#[inline]
62316#[target_feature(enable = "neon")]
62317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62319#[cfg_attr(
62320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62321    assert_instr(ushl)
62322)]
62323#[cfg_attr(
62324    not(target_arch = "arm"),
62325    stable(feature = "neon_intrinsics", since = "1.59.0")
62326)]
62327#[cfg_attr(
62328    target_arch = "arm",
62329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62330)]
62331pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
62332    unsafe extern "unadjusted" {
62333        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")]
62334        #[cfg_attr(
62335            any(target_arch = "aarch64", target_arch = "arm64ec"),
62336            link_name = "llvm.aarch64.neon.ushl.v8i16"
62337        )]
62338        fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
62339    }
62340    unsafe { _vshlq_u16(a, b) }
62341}
62342#[doc = "Unsigned Shift left"]
62343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
62344#[inline]
62345#[target_feature(enable = "neon")]
62346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62348#[cfg_attr(
62349    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62350    assert_instr(ushl)
62351)]
62352#[cfg_attr(
62353    not(target_arch = "arm"),
62354    stable(feature = "neon_intrinsics", since = "1.59.0")
62355)]
62356#[cfg_attr(
62357    target_arch = "arm",
62358    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62359)]
62360pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
62361    unsafe extern "unadjusted" {
62362        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")]
62363        #[cfg_attr(
62364            any(target_arch = "aarch64", target_arch = "arm64ec"),
62365            link_name = "llvm.aarch64.neon.ushl.v2i32"
62366        )]
62367        fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
62368    }
62369    unsafe { _vshl_u32(a, b) }
62370}
62371#[doc = "Unsigned Shift left"]
62372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
62373#[inline]
62374#[target_feature(enable = "neon")]
62375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62377#[cfg_attr(
62378    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62379    assert_instr(ushl)
62380)]
62381#[cfg_attr(
62382    not(target_arch = "arm"),
62383    stable(feature = "neon_intrinsics", since = "1.59.0")
62384)]
62385#[cfg_attr(
62386    target_arch = "arm",
62387    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62388)]
62389pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
62390    unsafe extern "unadjusted" {
62391        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")]
62392        #[cfg_attr(
62393            any(target_arch = "aarch64", target_arch = "arm64ec"),
62394            link_name = "llvm.aarch64.neon.ushl.v4i32"
62395        )]
62396        fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
62397    }
62398    unsafe { _vshlq_u32(a, b) }
62399}
62400#[doc = "Unsigned Shift left"]
62401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
62402#[inline]
62403#[target_feature(enable = "neon")]
62404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62405#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62406#[cfg_attr(
62407    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62408    assert_instr(ushl)
62409)]
62410#[cfg_attr(
62411    not(target_arch = "arm"),
62412    stable(feature = "neon_intrinsics", since = "1.59.0")
62413)]
62414#[cfg_attr(
62415    target_arch = "arm",
62416    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62417)]
62418pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
62419    unsafe extern "unadjusted" {
62420        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")]
62421        #[cfg_attr(
62422            any(target_arch = "aarch64", target_arch = "arm64ec"),
62423            link_name = "llvm.aarch64.neon.ushl.v1i64"
62424        )]
62425        fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
62426    }
62427    unsafe { _vshl_u64(a, b) }
62428}
62429#[doc = "Unsigned Shift left"]
62430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
62431#[inline]
62432#[target_feature(enable = "neon")]
62433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62435#[cfg_attr(
62436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62437    assert_instr(ushl)
62438)]
62439#[cfg_attr(
62440    not(target_arch = "arm"),
62441    stable(feature = "neon_intrinsics", since = "1.59.0")
62442)]
62443#[cfg_attr(
62444    target_arch = "arm",
62445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62446)]
62447pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
62448    unsafe extern "unadjusted" {
62449        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")]
62450        #[cfg_attr(
62451            any(target_arch = "aarch64", target_arch = "arm64ec"),
62452            link_name = "llvm.aarch64.neon.ushl.v2i64"
62453        )]
62454        fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
62455    }
62456    unsafe { _vshlq_u64(a, b) }
62457}
62458#[doc = "Signed shift left long"]
62459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
62460#[inline]
62461#[target_feature(enable = "neon")]
62462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62463#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
62464#[cfg_attr(
62465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62466    assert_instr(sshll, N = 2)
62467)]
62468#[rustc_legacy_const_generics(1)]
62469#[cfg_attr(
62470    not(target_arch = "arm"),
62471    stable(feature = "neon_intrinsics", since = "1.59.0")
62472)]
62473#[cfg_attr(
62474    target_arch = "arm",
62475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62476)]
62477pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
62478    static_assert!(N >= 0 && N <= 16);
62479    unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) }
62480}
62481#[doc = "Signed shift left long"]
62482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
62483#[inline]
62484#[target_feature(enable = "neon")]
62485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62486#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
62487#[cfg_attr(
62488    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62489    assert_instr(sshll, N = 2)
62490)]
62491#[rustc_legacy_const_generics(1)]
62492#[cfg_attr(
62493    not(target_arch = "arm"),
62494    stable(feature = "neon_intrinsics", since = "1.59.0")
62495)]
62496#[cfg_attr(
62497    target_arch = "arm",
62498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62499)]
62500pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
62501    static_assert!(N >= 0 && N <= 32);
62502    unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) }
62503}
62504#[doc = "Signed shift left long"]
62505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
62506#[inline]
62507#[target_feature(enable = "neon")]
62508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62509#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
62510#[cfg_attr(
62511    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62512    assert_instr(sshll, N = 2)
62513)]
62514#[rustc_legacy_const_generics(1)]
62515#[cfg_attr(
62516    not(target_arch = "arm"),
62517    stable(feature = "neon_intrinsics", since = "1.59.0")
62518)]
62519#[cfg_attr(
62520    target_arch = "arm",
62521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62522)]
62523pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
62524    static_assert!(N >= 0 && N <= 8);
62525    unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) }
62526}
62527#[doc = "Signed shift left long"]
62528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
62529#[inline]
62530#[target_feature(enable = "neon")]
62531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62532#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
62533#[cfg_attr(
62534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62535    assert_instr(ushll, N = 2)
62536)]
62537#[rustc_legacy_const_generics(1)]
62538#[cfg_attr(
62539    not(target_arch = "arm"),
62540    stable(feature = "neon_intrinsics", since = "1.59.0")
62541)]
62542#[cfg_attr(
62543    target_arch = "arm",
62544    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62545)]
62546pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
62547    static_assert!(N >= 0 && N <= 16);
62548    unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) }
62549}
62550#[doc = "Signed shift left long"]
62551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
62552#[inline]
62553#[target_feature(enable = "neon")]
62554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
62556#[cfg_attr(
62557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62558    assert_instr(ushll, N = 2)
62559)]
62560#[rustc_legacy_const_generics(1)]
62561#[cfg_attr(
62562    not(target_arch = "arm"),
62563    stable(feature = "neon_intrinsics", since = "1.59.0")
62564)]
62565#[cfg_attr(
62566    target_arch = "arm",
62567    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62568)]
62569pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
62570    static_assert!(N >= 0 && N <= 32);
62571    unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) }
62572}
62573#[doc = "Signed shift left long"]
62574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
62575#[inline]
62576#[target_feature(enable = "neon")]
62577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62578#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
62579#[cfg_attr(
62580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62581    assert_instr(ushll, N = 2)
62582)]
62583#[rustc_legacy_const_generics(1)]
62584#[cfg_attr(
62585    not(target_arch = "arm"),
62586    stable(feature = "neon_intrinsics", since = "1.59.0")
62587)]
62588#[cfg_attr(
62589    target_arch = "arm",
62590    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62591)]
62592pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
62593    static_assert!(N >= 0 && N <= 8);
62594    unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) }
62595}
62596#[doc = "Shift right"]
62597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
62598#[inline]
62599#[target_feature(enable = "neon")]
62600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62601#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62602#[cfg_attr(
62603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62604    assert_instr(sshr, N = 2)
62605)]
62606#[rustc_legacy_const_generics(1)]
62607#[cfg_attr(
62608    not(target_arch = "arm"),
62609    stable(feature = "neon_intrinsics", since = "1.59.0")
62610)]
62611#[cfg_attr(
62612    target_arch = "arm",
62613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62614)]
62615pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
62616    static_assert!(N >= 1 && N <= 8);
62617    let n: i32 = if N == 8 { 7 } else { N };
62618    unsafe { simd_shr(a, vdup_n_s8(n as _)) }
62619}
62620#[doc = "Shift right"]
62621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
62622#[inline]
62623#[target_feature(enable = "neon")]
62624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62626#[cfg_attr(
62627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62628    assert_instr(sshr, N = 2)
62629)]
62630#[rustc_legacy_const_generics(1)]
62631#[cfg_attr(
62632    not(target_arch = "arm"),
62633    stable(feature = "neon_intrinsics", since = "1.59.0")
62634)]
62635#[cfg_attr(
62636    target_arch = "arm",
62637    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62638)]
62639pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
62640    static_assert!(N >= 1 && N <= 8);
62641    let n: i32 = if N == 8 { 7 } else { N };
62642    unsafe { simd_shr(a, vdupq_n_s8(n as _)) }
62643}
62644#[doc = "Shift right"]
62645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
62646#[inline]
62647#[target_feature(enable = "neon")]
62648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62649#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62650#[cfg_attr(
62651    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62652    assert_instr(sshr, N = 2)
62653)]
62654#[rustc_legacy_const_generics(1)]
62655#[cfg_attr(
62656    not(target_arch = "arm"),
62657    stable(feature = "neon_intrinsics", since = "1.59.0")
62658)]
62659#[cfg_attr(
62660    target_arch = "arm",
62661    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62662)]
62663pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
62664    static_assert!(N >= 1 && N <= 16);
62665    let n: i32 = if N == 16 { 15 } else { N };
62666    unsafe { simd_shr(a, vdup_n_s16(n as _)) }
62667}
62668#[doc = "Shift right"]
62669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
62670#[inline]
62671#[target_feature(enable = "neon")]
62672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62673#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62674#[cfg_attr(
62675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62676    assert_instr(sshr, N = 2)
62677)]
62678#[rustc_legacy_const_generics(1)]
62679#[cfg_attr(
62680    not(target_arch = "arm"),
62681    stable(feature = "neon_intrinsics", since = "1.59.0")
62682)]
62683#[cfg_attr(
62684    target_arch = "arm",
62685    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62686)]
62687pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
62688    static_assert!(N >= 1 && N <= 16);
62689    let n: i32 = if N == 16 { 15 } else { N };
62690    unsafe { simd_shr(a, vdupq_n_s16(n as _)) }
62691}
62692#[doc = "Shift right"]
62693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
62694#[inline]
62695#[target_feature(enable = "neon")]
62696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62698#[cfg_attr(
62699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62700    assert_instr(sshr, N = 2)
62701)]
62702#[rustc_legacy_const_generics(1)]
62703#[cfg_attr(
62704    not(target_arch = "arm"),
62705    stable(feature = "neon_intrinsics", since = "1.59.0")
62706)]
62707#[cfg_attr(
62708    target_arch = "arm",
62709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62710)]
62711pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
62712    static_assert!(N >= 1 && N <= 32);
62713    let n: i32 = if N == 32 { 31 } else { N };
62714    unsafe { simd_shr(a, vdup_n_s32(n as _)) }
62715}
62716#[doc = "Shift right"]
62717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
62718#[inline]
62719#[target_feature(enable = "neon")]
62720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62722#[cfg_attr(
62723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62724    assert_instr(sshr, N = 2)
62725)]
62726#[rustc_legacy_const_generics(1)]
62727#[cfg_attr(
62728    not(target_arch = "arm"),
62729    stable(feature = "neon_intrinsics", since = "1.59.0")
62730)]
62731#[cfg_attr(
62732    target_arch = "arm",
62733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62734)]
62735pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
62736    static_assert!(N >= 1 && N <= 32);
62737    let n: i32 = if N == 32 { 31 } else { N };
62738    unsafe { simd_shr(a, vdupq_n_s32(n as _)) }
62739}
62740#[doc = "Shift right"]
62741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
62742#[inline]
62743#[target_feature(enable = "neon")]
62744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62746#[cfg_attr(
62747    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62748    assert_instr(sshr, N = 2)
62749)]
62750#[rustc_legacy_const_generics(1)]
62751#[cfg_attr(
62752    not(target_arch = "arm"),
62753    stable(feature = "neon_intrinsics", since = "1.59.0")
62754)]
62755#[cfg_attr(
62756    target_arch = "arm",
62757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62758)]
62759pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
62760    static_assert!(N >= 1 && N <= 64);
62761    let n: i32 = if N == 64 { 63 } else { N };
62762    unsafe { simd_shr(a, vdup_n_s64(n as _)) }
62763}
62764#[doc = "Shift right"]
62765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
62766#[inline]
62767#[target_feature(enable = "neon")]
62768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62770#[cfg_attr(
62771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62772    assert_instr(sshr, N = 2)
62773)]
62774#[rustc_legacy_const_generics(1)]
62775#[cfg_attr(
62776    not(target_arch = "arm"),
62777    stable(feature = "neon_intrinsics", since = "1.59.0")
62778)]
62779#[cfg_attr(
62780    target_arch = "arm",
62781    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62782)]
62783pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
62784    static_assert!(N >= 1 && N <= 64);
62785    let n: i32 = if N == 64 { 63 } else { N };
62786    unsafe { simd_shr(a, vdupq_n_s64(n as _)) }
62787}
62788#[doc = "Shift right"]
62789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
62790#[inline]
62791#[target_feature(enable = "neon")]
62792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62793#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62794#[cfg_attr(
62795    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62796    assert_instr(ushr, N = 2)
62797)]
62798#[rustc_legacy_const_generics(1)]
62799#[cfg_attr(
62800    not(target_arch = "arm"),
62801    stable(feature = "neon_intrinsics", since = "1.59.0")
62802)]
62803#[cfg_attr(
62804    target_arch = "arm",
62805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62806)]
62807pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
62808    static_assert!(N >= 1 && N <= 8);
62809    let n: i32 = if N == 8 {
62810        return vdup_n_u8(0);
62811    } else {
62812        N
62813    };
62814    unsafe { simd_shr(a, vdup_n_u8(n as _)) }
62815}
62816#[doc = "Shift right"]
62817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
62818#[inline]
62819#[target_feature(enable = "neon")]
62820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62821#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62822#[cfg_attr(
62823    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62824    assert_instr(ushr, N = 2)
62825)]
62826#[rustc_legacy_const_generics(1)]
62827#[cfg_attr(
62828    not(target_arch = "arm"),
62829    stable(feature = "neon_intrinsics", since = "1.59.0")
62830)]
62831#[cfg_attr(
62832    target_arch = "arm",
62833    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62834)]
62835pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
62836    static_assert!(N >= 1 && N <= 8);
62837    let n: i32 = if N == 8 {
62838        return vdupq_n_u8(0);
62839    } else {
62840        N
62841    };
62842    unsafe { simd_shr(a, vdupq_n_u8(n as _)) }
62843}
62844#[doc = "Shift right"]
62845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
62846#[inline]
62847#[target_feature(enable = "neon")]
62848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62849#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62850#[cfg_attr(
62851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62852    assert_instr(ushr, N = 2)
62853)]
62854#[rustc_legacy_const_generics(1)]
62855#[cfg_attr(
62856    not(target_arch = "arm"),
62857    stable(feature = "neon_intrinsics", since = "1.59.0")
62858)]
62859#[cfg_attr(
62860    target_arch = "arm",
62861    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62862)]
62863pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
62864    static_assert!(N >= 1 && N <= 16);
62865    let n: i32 = if N == 16 {
62866        return vdup_n_u16(0);
62867    } else {
62868        N
62869    };
62870    unsafe { simd_shr(a, vdup_n_u16(n as _)) }
62871}
62872#[doc = "Shift right"]
62873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
62874#[inline]
62875#[target_feature(enable = "neon")]
62876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62877#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62878#[cfg_attr(
62879    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62880    assert_instr(ushr, N = 2)
62881)]
62882#[rustc_legacy_const_generics(1)]
62883#[cfg_attr(
62884    not(target_arch = "arm"),
62885    stable(feature = "neon_intrinsics", since = "1.59.0")
62886)]
62887#[cfg_attr(
62888    target_arch = "arm",
62889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62890)]
62891pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
62892    static_assert!(N >= 1 && N <= 16);
62893    let n: i32 = if N == 16 {
62894        return vdupq_n_u16(0);
62895    } else {
62896        N
62897    };
62898    unsafe { simd_shr(a, vdupq_n_u16(n as _)) }
62899}
62900#[doc = "Shift right"]
62901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
62902#[inline]
62903#[target_feature(enable = "neon")]
62904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62905#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62906#[cfg_attr(
62907    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62908    assert_instr(ushr, N = 2)
62909)]
62910#[rustc_legacy_const_generics(1)]
62911#[cfg_attr(
62912    not(target_arch = "arm"),
62913    stable(feature = "neon_intrinsics", since = "1.59.0")
62914)]
62915#[cfg_attr(
62916    target_arch = "arm",
62917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62918)]
62919pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
62920    static_assert!(N >= 1 && N <= 32);
62921    let n: i32 = if N == 32 {
62922        return vdup_n_u32(0);
62923    } else {
62924        N
62925    };
62926    unsafe { simd_shr(a, vdup_n_u32(n as _)) }
62927}
62928#[doc = "Shift right"]
62929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
62930#[inline]
62931#[target_feature(enable = "neon")]
62932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62933#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62934#[cfg_attr(
62935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62936    assert_instr(ushr, N = 2)
62937)]
62938#[rustc_legacy_const_generics(1)]
62939#[cfg_attr(
62940    not(target_arch = "arm"),
62941    stable(feature = "neon_intrinsics", since = "1.59.0")
62942)]
62943#[cfg_attr(
62944    target_arch = "arm",
62945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62946)]
62947pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
62948    static_assert!(N >= 1 && N <= 32);
62949    let n: i32 = if N == 32 {
62950        return vdupq_n_u32(0);
62951    } else {
62952        N
62953    };
62954    unsafe { simd_shr(a, vdupq_n_u32(n as _)) }
62955}
62956#[doc = "Shift right"]
62957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
62958#[inline]
62959#[target_feature(enable = "neon")]
62960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62961#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62962#[cfg_attr(
62963    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62964    assert_instr(ushr, N = 2)
62965)]
62966#[rustc_legacy_const_generics(1)]
62967#[cfg_attr(
62968    not(target_arch = "arm"),
62969    stable(feature = "neon_intrinsics", since = "1.59.0")
62970)]
62971#[cfg_attr(
62972    target_arch = "arm",
62973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62974)]
62975pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
62976    static_assert!(N >= 1 && N <= 64);
62977    let n: i32 = if N == 64 {
62978        return vdup_n_u64(0);
62979    } else {
62980        N
62981    };
62982    unsafe { simd_shr(a, vdup_n_u64(n as _)) }
62983}
62984#[doc = "Shift right"]
62985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
62986#[inline]
62987#[target_feature(enable = "neon")]
62988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62989#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62990#[cfg_attr(
62991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62992    assert_instr(ushr, N = 2)
62993)]
62994#[rustc_legacy_const_generics(1)]
62995#[cfg_attr(
62996    not(target_arch = "arm"),
62997    stable(feature = "neon_intrinsics", since = "1.59.0")
62998)]
62999#[cfg_attr(
63000    target_arch = "arm",
63001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63002)]
63003pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
63004    static_assert!(N >= 1 && N <= 64);
63005    let n: i32 = if N == 64 {
63006        return vdupq_n_u64(0);
63007    } else {
63008        N
63009    };
63010    unsafe { simd_shr(a, vdupq_n_u64(n as _)) }
63011}
63012#[doc = "Shift right narrow"]
63013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
63014#[inline]
63015#[target_feature(enable = "neon")]
63016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
63018#[cfg_attr(
63019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63020    assert_instr(shrn, N = 2)
63021)]
63022#[rustc_legacy_const_generics(1)]
63023#[cfg_attr(
63024    not(target_arch = "arm"),
63025    stable(feature = "neon_intrinsics", since = "1.59.0")
63026)]
63027#[cfg_attr(
63028    target_arch = "arm",
63029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63030)]
63031pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
63032    static_assert!(N >= 1 && N <= 8);
63033    unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) }
63034}
63035#[doc = "Shift right narrow"]
63036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
63037#[inline]
63038#[target_feature(enable = "neon")]
63039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
63041#[cfg_attr(
63042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63043    assert_instr(shrn, N = 2)
63044)]
63045#[rustc_legacy_const_generics(1)]
63046#[cfg_attr(
63047    not(target_arch = "arm"),
63048    stable(feature = "neon_intrinsics", since = "1.59.0")
63049)]
63050#[cfg_attr(
63051    target_arch = "arm",
63052    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63053)]
63054pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
63055    static_assert!(N >= 1 && N <= 16);
63056    unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) }
63057}
63058#[doc = "Shift right narrow"]
63059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
63060#[inline]
63061#[target_feature(enable = "neon")]
63062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63063#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
63064#[cfg_attr(
63065    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63066    assert_instr(shrn, N = 2)
63067)]
63068#[rustc_legacy_const_generics(1)]
63069#[cfg_attr(
63070    not(target_arch = "arm"),
63071    stable(feature = "neon_intrinsics", since = "1.59.0")
63072)]
63073#[cfg_attr(
63074    target_arch = "arm",
63075    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63076)]
63077pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
63078    static_assert!(N >= 1 && N <= 32);
63079    unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) }
63080}
63081#[doc = "Shift right narrow"]
63082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
63083#[inline]
63084#[target_feature(enable = "neon")]
63085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63086#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
63087#[cfg_attr(
63088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63089    assert_instr(shrn, N = 2)
63090)]
63091#[rustc_legacy_const_generics(1)]
63092#[cfg_attr(
63093    not(target_arch = "arm"),
63094    stable(feature = "neon_intrinsics", since = "1.59.0")
63095)]
63096#[cfg_attr(
63097    target_arch = "arm",
63098    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63099)]
63100pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
63101    static_assert!(N >= 1 && N <= 8);
63102    unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) }
63103}
63104#[doc = "Shift right narrow"]
63105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
63106#[inline]
63107#[target_feature(enable = "neon")]
63108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
63110#[cfg_attr(
63111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63112    assert_instr(shrn, N = 2)
63113)]
63114#[rustc_legacy_const_generics(1)]
63115#[cfg_attr(
63116    not(target_arch = "arm"),
63117    stable(feature = "neon_intrinsics", since = "1.59.0")
63118)]
63119#[cfg_attr(
63120    target_arch = "arm",
63121    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63122)]
63123pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
63124    static_assert!(N >= 1 && N <= 16);
63125    unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) }
63126}
63127#[doc = "Shift right narrow"]
63128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
63129#[inline]
63130#[target_feature(enable = "neon")]
63131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63132#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
63133#[cfg_attr(
63134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63135    assert_instr(shrn, N = 2)
63136)]
63137#[rustc_legacy_const_generics(1)]
63138#[cfg_attr(
63139    not(target_arch = "arm"),
63140    stable(feature = "neon_intrinsics", since = "1.59.0")
63141)]
63142#[cfg_attr(
63143    target_arch = "arm",
63144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63145)]
63146pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
63147    static_assert!(N >= 1 && N <= 32);
63148    unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) }
63149}
63150#[doc = "Shift Left and Insert (immediate)"]
63151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
63152#[inline]
63153#[cfg(target_arch = "arm")]
63154#[target_feature(enable = "neon,v7")]
63155#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63157#[rustc_legacy_const_generics(2)]
63158pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63159    static_assert_uimm_bits!(N, 3);
63160    vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
63161}
63162#[doc = "Shift Left and Insert (immediate)"]
63163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
63164#[inline]
63165#[cfg(target_arch = "arm")]
63166#[target_feature(enable = "neon,v7")]
63167#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63169#[rustc_legacy_const_generics(2)]
63170pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63171    static_assert_uimm_bits!(N, 3);
63172    vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
63173}
63174#[doc = "Shift Left and Insert (immediate)"]
63175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
63176#[inline]
63177#[cfg(target_arch = "arm")]
63178#[target_feature(enable = "neon,v7")]
63179#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63181#[rustc_legacy_const_generics(2)]
63182pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63183    static_assert_uimm_bits!(N, 4);
63184    vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
63185}
63186#[doc = "Shift Left and Insert (immediate)"]
63187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
63188#[inline]
63189#[cfg(target_arch = "arm")]
63190#[target_feature(enable = "neon,v7")]
63191#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63193#[rustc_legacy_const_generics(2)]
63194pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63195    static_assert_uimm_bits!(N, 4);
63196    vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
63197}
63198#[doc = "Shift Left and Insert (immediate)"]
63199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
63200#[inline]
63201#[cfg(target_arch = "arm")]
63202#[target_feature(enable = "neon,v7")]
63203#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63204#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63205#[rustc_legacy_const_generics(2)]
63206pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63207    static_assert!(N >= 0 && N <= 31);
63208    vshiftins_v2i32(a, b, int32x2_t::splat(N))
63209}
63210#[doc = "Shift Left and Insert (immediate)"]
63211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
63212#[inline]
63213#[cfg(target_arch = "arm")]
63214#[target_feature(enable = "neon,v7")]
63215#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63217#[rustc_legacy_const_generics(2)]
63218pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63219    static_assert!(N >= 0 && N <= 31);
63220    vshiftins_v4i32(a, b, int32x4_t::splat(N))
63221}
63222#[doc = "Shift Left and Insert (immediate)"]
63223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
63224#[inline]
63225#[cfg(target_arch = "arm")]
63226#[target_feature(enable = "neon,v7")]
63227#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63229#[rustc_legacy_const_generics(2)]
63230pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63231    static_assert!(N >= 0 && N <= 63);
63232    vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
63233}
63234#[doc = "Shift Left and Insert (immediate)"]
63235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
63236#[inline]
63237#[cfg(target_arch = "arm")]
63238#[target_feature(enable = "neon,v7")]
63239#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63241#[rustc_legacy_const_generics(2)]
63242pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63243    static_assert!(N >= 0 && N <= 63);
63244    vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
63245}
63246#[doc = "Shift Left and Insert (immediate)"]
63247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
63248#[inline]
63249#[cfg(target_arch = "arm")]
63250#[target_feature(enable = "neon,v7")]
63251#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63252#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63253#[rustc_legacy_const_generics(2)]
63254pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63255    static_assert_uimm_bits!(N, 3);
63256    unsafe {
63257        transmute(vshiftins_v8i8(
63258            transmute(a),
63259            transmute(b),
63260            int8x8_t::splat(N as i8),
63261        ))
63262    }
63263}
63264#[doc = "Shift Left and Insert (immediate)"]
63265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
63266#[inline]
63267#[cfg(target_arch = "arm")]
63268#[target_feature(enable = "neon,v7")]
63269#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63270#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63271#[rustc_legacy_const_generics(2)]
63272pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63273    static_assert_uimm_bits!(N, 3);
63274    unsafe {
63275        transmute(vshiftins_v16i8(
63276            transmute(a),
63277            transmute(b),
63278            int8x16_t::splat(N as i8),
63279        ))
63280    }
63281}
63282#[doc = "Shift Left and Insert (immediate)"]
63283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
63284#[inline]
63285#[cfg(target_arch = "arm")]
63286#[target_feature(enable = "neon,v7")]
63287#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63288#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63289#[rustc_legacy_const_generics(2)]
63290pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63291    static_assert_uimm_bits!(N, 4);
63292    unsafe {
63293        transmute(vshiftins_v4i16(
63294            transmute(a),
63295            transmute(b),
63296            int16x4_t::splat(N as i16),
63297        ))
63298    }
63299}
63300#[doc = "Shift Left and Insert (immediate)"]
63301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
63302#[inline]
63303#[cfg(target_arch = "arm")]
63304#[target_feature(enable = "neon,v7")]
63305#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63306#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63307#[rustc_legacy_const_generics(2)]
63308pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63309    static_assert_uimm_bits!(N, 4);
63310    unsafe {
63311        transmute(vshiftins_v8i16(
63312            transmute(a),
63313            transmute(b),
63314            int16x8_t::splat(N as i16),
63315        ))
63316    }
63317}
63318#[doc = "Shift Left and Insert (immediate)"]
63319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
63320#[inline]
63321#[cfg(target_arch = "arm")]
63322#[target_feature(enable = "neon,v7")]
63323#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63325#[rustc_legacy_const_generics(2)]
63326pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63327    static_assert!(N >= 0 && N <= 31);
63328    unsafe {
63329        transmute(vshiftins_v2i32(
63330            transmute(a),
63331            transmute(b),
63332            int32x2_t::splat(N as i32),
63333        ))
63334    }
63335}
63336#[doc = "Shift Left and Insert (immediate)"]
63337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
63338#[inline]
63339#[cfg(target_arch = "arm")]
63340#[target_feature(enable = "neon,v7")]
63341#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63342#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63343#[rustc_legacy_const_generics(2)]
63344pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63345    static_assert!(N >= 0 && N <= 31);
63346    unsafe {
63347        transmute(vshiftins_v4i32(
63348            transmute(a),
63349            transmute(b),
63350            int32x4_t::splat(N as i32),
63351        ))
63352    }
63353}
63354#[doc = "Shift Left and Insert (immediate)"]
63355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
63356#[inline]
63357#[cfg(target_arch = "arm")]
63358#[target_feature(enable = "neon,v7")]
63359#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63361#[rustc_legacy_const_generics(2)]
63362pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63363    static_assert!(N >= 0 && N <= 63);
63364    unsafe {
63365        transmute(vshiftins_v1i64(
63366            transmute(a),
63367            transmute(b),
63368            int64x1_t::splat(N as i64),
63369        ))
63370    }
63371}
63372#[doc = "Shift Left and Insert (immediate)"]
63373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
63374#[inline]
63375#[cfg(target_arch = "arm")]
63376#[target_feature(enable = "neon,v7")]
63377#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63379#[rustc_legacy_const_generics(2)]
63380pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63381    static_assert!(N >= 0 && N <= 63);
63382    unsafe {
63383        transmute(vshiftins_v2i64(
63384            transmute(a),
63385            transmute(b),
63386            int64x2_t::splat(N as i64),
63387        ))
63388    }
63389}
63390#[doc = "Shift Left and Insert (immediate)"]
63391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
63392#[inline]
63393#[cfg(target_arch = "arm")]
63394#[target_feature(enable = "neon,v7")]
63395#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63396#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63397#[rustc_legacy_const_generics(2)]
63398pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
63399    static_assert_uimm_bits!(N, 3);
63400    unsafe {
63401        transmute(vshiftins_v8i8(
63402            transmute(a),
63403            transmute(b),
63404            int8x8_t::splat(N as i8),
63405        ))
63406    }
63407}
63408#[doc = "Shift Left and Insert (immediate)"]
63409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
63410#[inline]
63411#[cfg(target_arch = "arm")]
63412#[target_feature(enable = "neon,v7")]
63413#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63414#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63415#[rustc_legacy_const_generics(2)]
63416pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
63417    static_assert_uimm_bits!(N, 3);
63418    unsafe {
63419        transmute(vshiftins_v16i8(
63420            transmute(a),
63421            transmute(b),
63422            int8x16_t::splat(N as i8),
63423        ))
63424    }
63425}
63426#[doc = "Shift Left and Insert (immediate)"]
63427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
63428#[inline]
63429#[cfg(target_arch = "arm")]
63430#[target_feature(enable = "neon,v7")]
63431#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63432#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63433#[rustc_legacy_const_generics(2)]
63434pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
63435    static_assert_uimm_bits!(N, 4);
63436    unsafe {
63437        transmute(vshiftins_v4i16(
63438            transmute(a),
63439            transmute(b),
63440            int16x4_t::splat(N as i16),
63441        ))
63442    }
63443}
63444#[doc = "Shift Left and Insert (immediate)"]
63445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
63446#[inline]
63447#[cfg(target_arch = "arm")]
63448#[target_feature(enable = "neon,v7")]
63449#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63450#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63451#[rustc_legacy_const_generics(2)]
63452pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
63453    static_assert_uimm_bits!(N, 4);
63454    unsafe {
63455        transmute(vshiftins_v8i16(
63456            transmute(a),
63457            transmute(b),
63458            int16x8_t::splat(N as i16),
63459        ))
63460    }
63461}
63462#[doc = "Signed shift right and accumulate"]
63463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
63464#[inline]
63465#[target_feature(enable = "neon")]
63466#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63468#[cfg_attr(
63469    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63470    assert_instr(ssra, N = 2)
63471)]
63472#[rustc_legacy_const_generics(2)]
63473#[cfg_attr(
63474    not(target_arch = "arm"),
63475    stable(feature = "neon_intrinsics", since = "1.59.0")
63476)]
63477#[cfg_attr(
63478    target_arch = "arm",
63479    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63480)]
63481pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63482    static_assert!(N >= 1 && N <= 8);
63483    unsafe { simd_add(a, vshr_n_s8::<N>(b)) }
63484}
63485#[doc = "Signed shift right and accumulate"]
63486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
63487#[inline]
63488#[target_feature(enable = "neon")]
63489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63491#[cfg_attr(
63492    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63493    assert_instr(ssra, N = 2)
63494)]
63495#[rustc_legacy_const_generics(2)]
63496#[cfg_attr(
63497    not(target_arch = "arm"),
63498    stable(feature = "neon_intrinsics", since = "1.59.0")
63499)]
63500#[cfg_attr(
63501    target_arch = "arm",
63502    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63503)]
63504pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63505    static_assert!(N >= 1 && N <= 8);
63506    unsafe { simd_add(a, vshrq_n_s8::<N>(b)) }
63507}
63508#[doc = "Signed shift right and accumulate"]
63509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
63510#[inline]
63511#[target_feature(enable = "neon")]
63512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63514#[cfg_attr(
63515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63516    assert_instr(ssra, N = 2)
63517)]
63518#[rustc_legacy_const_generics(2)]
63519#[cfg_attr(
63520    not(target_arch = "arm"),
63521    stable(feature = "neon_intrinsics", since = "1.59.0")
63522)]
63523#[cfg_attr(
63524    target_arch = "arm",
63525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63526)]
63527pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63528    static_assert!(N >= 1 && N <= 16);
63529    unsafe { simd_add(a, vshr_n_s16::<N>(b)) }
63530}
63531#[doc = "Signed shift right and accumulate"]
63532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
63533#[inline]
63534#[target_feature(enable = "neon")]
63535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63537#[cfg_attr(
63538    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63539    assert_instr(ssra, N = 2)
63540)]
63541#[rustc_legacy_const_generics(2)]
63542#[cfg_attr(
63543    not(target_arch = "arm"),
63544    stable(feature = "neon_intrinsics", since = "1.59.0")
63545)]
63546#[cfg_attr(
63547    target_arch = "arm",
63548    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63549)]
63550pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63551    static_assert!(N >= 1 && N <= 16);
63552    unsafe { simd_add(a, vshrq_n_s16::<N>(b)) }
63553}
63554#[doc = "Signed shift right and accumulate"]
63555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
63556#[inline]
63557#[target_feature(enable = "neon")]
63558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63560#[cfg_attr(
63561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63562    assert_instr(ssra, N = 2)
63563)]
63564#[rustc_legacy_const_generics(2)]
63565#[cfg_attr(
63566    not(target_arch = "arm"),
63567    stable(feature = "neon_intrinsics", since = "1.59.0")
63568)]
63569#[cfg_attr(
63570    target_arch = "arm",
63571    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63572)]
63573pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63574    static_assert!(N >= 1 && N <= 32);
63575    unsafe { simd_add(a, vshr_n_s32::<N>(b)) }
63576}
63577#[doc = "Signed shift right and accumulate"]
63578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
63579#[inline]
63580#[target_feature(enable = "neon")]
63581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63583#[cfg_attr(
63584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63585    assert_instr(ssra, N = 2)
63586)]
63587#[rustc_legacy_const_generics(2)]
63588#[cfg_attr(
63589    not(target_arch = "arm"),
63590    stable(feature = "neon_intrinsics", since = "1.59.0")
63591)]
63592#[cfg_attr(
63593    target_arch = "arm",
63594    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63595)]
63596pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63597    static_assert!(N >= 1 && N <= 32);
63598    unsafe { simd_add(a, vshrq_n_s32::<N>(b)) }
63599}
63600#[doc = "Signed shift right and accumulate"]
63601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
63602#[inline]
63603#[target_feature(enable = "neon")]
63604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63606#[cfg_attr(
63607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63608    assert_instr(ssra, N = 2)
63609)]
63610#[rustc_legacy_const_generics(2)]
63611#[cfg_attr(
63612    not(target_arch = "arm"),
63613    stable(feature = "neon_intrinsics", since = "1.59.0")
63614)]
63615#[cfg_attr(
63616    target_arch = "arm",
63617    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63618)]
63619pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63620    static_assert!(N >= 1 && N <= 64);
63621    unsafe { simd_add(a, vshr_n_s64::<N>(b)) }
63622}
63623#[doc = "Signed shift right and accumulate"]
63624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
63625#[inline]
63626#[target_feature(enable = "neon")]
63627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63629#[cfg_attr(
63630    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63631    assert_instr(ssra, N = 2)
63632)]
63633#[rustc_legacy_const_generics(2)]
63634#[cfg_attr(
63635    not(target_arch = "arm"),
63636    stable(feature = "neon_intrinsics", since = "1.59.0")
63637)]
63638#[cfg_attr(
63639    target_arch = "arm",
63640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63641)]
63642pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63643    static_assert!(N >= 1 && N <= 64);
63644    unsafe { simd_add(a, vshrq_n_s64::<N>(b)) }
63645}
63646#[doc = "Unsigned shift right and accumulate"]
63647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
63648#[inline]
63649#[target_feature(enable = "neon")]
63650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63652#[cfg_attr(
63653    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63654    assert_instr(usra, N = 2)
63655)]
63656#[rustc_legacy_const_generics(2)]
63657#[cfg_attr(
63658    not(target_arch = "arm"),
63659    stable(feature = "neon_intrinsics", since = "1.59.0")
63660)]
63661#[cfg_attr(
63662    target_arch = "arm",
63663    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63664)]
63665pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63666    static_assert!(N >= 1 && N <= 8);
63667    unsafe { simd_add(a, vshr_n_u8::<N>(b)) }
63668}
63669#[doc = "Unsigned shift right and accumulate"]
63670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
63671#[inline]
63672#[target_feature(enable = "neon")]
63673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63675#[cfg_attr(
63676    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63677    assert_instr(usra, N = 2)
63678)]
63679#[rustc_legacy_const_generics(2)]
63680#[cfg_attr(
63681    not(target_arch = "arm"),
63682    stable(feature = "neon_intrinsics", since = "1.59.0")
63683)]
63684#[cfg_attr(
63685    target_arch = "arm",
63686    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63687)]
63688pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63689    static_assert!(N >= 1 && N <= 8);
63690    unsafe { simd_add(a, vshrq_n_u8::<N>(b)) }
63691}
63692#[doc = "Unsigned shift right and accumulate"]
63693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
63694#[inline]
63695#[target_feature(enable = "neon")]
63696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63698#[cfg_attr(
63699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63700    assert_instr(usra, N = 2)
63701)]
63702#[rustc_legacy_const_generics(2)]
63703#[cfg_attr(
63704    not(target_arch = "arm"),
63705    stable(feature = "neon_intrinsics", since = "1.59.0")
63706)]
63707#[cfg_attr(
63708    target_arch = "arm",
63709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63710)]
63711pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63712    static_assert!(N >= 1 && N <= 16);
63713    unsafe { simd_add(a, vshr_n_u16::<N>(b)) }
63714}
63715#[doc = "Unsigned shift right and accumulate"]
63716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
63717#[inline]
63718#[target_feature(enable = "neon")]
63719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63721#[cfg_attr(
63722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63723    assert_instr(usra, N = 2)
63724)]
63725#[rustc_legacy_const_generics(2)]
63726#[cfg_attr(
63727    not(target_arch = "arm"),
63728    stable(feature = "neon_intrinsics", since = "1.59.0")
63729)]
63730#[cfg_attr(
63731    target_arch = "arm",
63732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63733)]
63734pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63735    static_assert!(N >= 1 && N <= 16);
63736    unsafe { simd_add(a, vshrq_n_u16::<N>(b)) }
63737}
63738#[doc = "Unsigned shift right and accumulate"]
63739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
63740#[inline]
63741#[target_feature(enable = "neon")]
63742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63744#[cfg_attr(
63745    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63746    assert_instr(usra, N = 2)
63747)]
63748#[rustc_legacy_const_generics(2)]
63749#[cfg_attr(
63750    not(target_arch = "arm"),
63751    stable(feature = "neon_intrinsics", since = "1.59.0")
63752)]
63753#[cfg_attr(
63754    target_arch = "arm",
63755    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63756)]
63757pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63758    static_assert!(N >= 1 && N <= 32);
63759    unsafe { simd_add(a, vshr_n_u32::<N>(b)) }
63760}
63761#[doc = "Unsigned shift right and accumulate"]
63762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
63763#[inline]
63764#[target_feature(enable = "neon")]
63765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63767#[cfg_attr(
63768    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63769    assert_instr(usra, N = 2)
63770)]
63771#[rustc_legacy_const_generics(2)]
63772#[cfg_attr(
63773    not(target_arch = "arm"),
63774    stable(feature = "neon_intrinsics", since = "1.59.0")
63775)]
63776#[cfg_attr(
63777    target_arch = "arm",
63778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63779)]
63780pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63781    static_assert!(N >= 1 && N <= 32);
63782    unsafe { simd_add(a, vshrq_n_u32::<N>(b)) }
63783}
63784#[doc = "Unsigned shift right and accumulate"]
63785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
63786#[inline]
63787#[target_feature(enable = "neon")]
63788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63790#[cfg_attr(
63791    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63792    assert_instr(usra, N = 2)
63793)]
63794#[rustc_legacy_const_generics(2)]
63795#[cfg_attr(
63796    not(target_arch = "arm"),
63797    stable(feature = "neon_intrinsics", since = "1.59.0")
63798)]
63799#[cfg_attr(
63800    target_arch = "arm",
63801    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63802)]
63803pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63804    static_assert!(N >= 1 && N <= 64);
63805    unsafe { simd_add(a, vshr_n_u64::<N>(b)) }
63806}
63807#[doc = "Unsigned shift right and accumulate"]
63808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
63809#[inline]
63810#[target_feature(enable = "neon")]
63811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63813#[cfg_attr(
63814    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63815    assert_instr(usra, N = 2)
63816)]
63817#[rustc_legacy_const_generics(2)]
63818#[cfg_attr(
63819    not(target_arch = "arm"),
63820    stable(feature = "neon_intrinsics", since = "1.59.0")
63821)]
63822#[cfg_attr(
63823    target_arch = "arm",
63824    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63825)]
63826pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63827    static_assert!(N >= 1 && N <= 64);
63828    unsafe { simd_add(a, vshrq_n_u64::<N>(b)) }
63829}
63830#[doc = "Shift Right and Insert (immediate)"]
63831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
63832#[inline]
63833#[target_feature(enable = "neon,v7")]
63834#[cfg(target_arch = "arm")]
63835#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63836#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63837#[rustc_legacy_const_generics(2)]
63838pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63839    static_assert!(1 <= N && N <= 8);
63840    vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
63841}
63842#[doc = "Shift Right and Insert (immediate)"]
63843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
63844#[inline]
63845#[target_feature(enable = "neon,v7")]
63846#[cfg(target_arch = "arm")]
63847#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63848#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63849#[rustc_legacy_const_generics(2)]
63850pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63851    static_assert!(1 <= N && N <= 8);
63852    vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
63853}
63854#[doc = "Shift Right and Insert (immediate)"]
63855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
63856#[inline]
63857#[target_feature(enable = "neon,v7")]
63858#[cfg(target_arch = "arm")]
63859#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63860#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63861#[rustc_legacy_const_generics(2)]
63862pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63863    static_assert!(1 <= N && N <= 16);
63864    vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
63865}
63866#[doc = "Shift Right and Insert (immediate)"]
63867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
63868#[inline]
63869#[target_feature(enable = "neon,v7")]
63870#[cfg(target_arch = "arm")]
63871#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63872#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63873#[rustc_legacy_const_generics(2)]
63874pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63875    static_assert!(1 <= N && N <= 16);
63876    vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
63877}
63878#[doc = "Shift Right and Insert (immediate)"]
63879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
63880#[inline]
63881#[target_feature(enable = "neon,v7")]
63882#[cfg(target_arch = "arm")]
63883#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63885#[rustc_legacy_const_generics(2)]
63886pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63887    static_assert!(1 <= N && N <= 32);
63888    vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32))
63889}
63890#[doc = "Shift Right and Insert (immediate)"]
63891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
63892#[inline]
63893#[target_feature(enable = "neon,v7")]
63894#[cfg(target_arch = "arm")]
63895#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63896#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63897#[rustc_legacy_const_generics(2)]
63898pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63899    static_assert!(1 <= N && N <= 32);
63900    vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32))
63901}
63902#[doc = "Shift Right and Insert (immediate)"]
63903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
63904#[inline]
63905#[target_feature(enable = "neon,v7")]
63906#[cfg(target_arch = "arm")]
63907#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63908#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63909#[rustc_legacy_const_generics(2)]
63910pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63911    static_assert!(1 <= N && N <= 64);
63912    vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
63913}
63914#[doc = "Shift Right and Insert (immediate)"]
63915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
63916#[inline]
63917#[target_feature(enable = "neon,v7")]
63918#[cfg(target_arch = "arm")]
63919#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63921#[rustc_legacy_const_generics(2)]
63922pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63923    static_assert!(1 <= N && N <= 64);
63924    vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
63925}
63926#[doc = "Shift Right and Insert (immediate)"]
63927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
63928#[inline]
63929#[cfg(target_arch = "arm")]
63930#[target_feature(enable = "neon,v7")]
63931#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63933#[rustc_legacy_const_generics(2)]
63934pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63935    static_assert!(1 <= N && N <= 8);
63936    unsafe {
63937        transmute(vshiftins_v8i8(
63938            transmute(a),
63939            transmute(b),
63940            int8x8_t::splat(-N as i8),
63941        ))
63942    }
63943}
63944#[doc = "Shift Right and Insert (immediate)"]
63945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
63946#[inline]
63947#[cfg(target_arch = "arm")]
63948#[target_feature(enable = "neon,v7")]
63949#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63950#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63951#[rustc_legacy_const_generics(2)]
63952pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63953    static_assert!(1 <= N && N <= 8);
63954    unsafe {
63955        transmute(vshiftins_v16i8(
63956            transmute(a),
63957            transmute(b),
63958            int8x16_t::splat(-N as i8),
63959        ))
63960    }
63961}
63962#[doc = "Shift Right and Insert (immediate)"]
63963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
63964#[inline]
63965#[cfg(target_arch = "arm")]
63966#[target_feature(enable = "neon,v7")]
63967#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63968#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63969#[rustc_legacy_const_generics(2)]
63970pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63971    static_assert!(1 <= N && N <= 16);
63972    unsafe {
63973        transmute(vshiftins_v4i16(
63974            transmute(a),
63975            transmute(b),
63976            int16x4_t::splat(-N as i16),
63977        ))
63978    }
63979}
63980#[doc = "Shift Right and Insert (immediate)"]
63981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
63982#[inline]
63983#[cfg(target_arch = "arm")]
63984#[target_feature(enable = "neon,v7")]
63985#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63986#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63987#[rustc_legacy_const_generics(2)]
63988pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63989    static_assert!(1 <= N && N <= 16);
63990    unsafe {
63991        transmute(vshiftins_v8i16(
63992            transmute(a),
63993            transmute(b),
63994            int16x8_t::splat(-N as i16),
63995        ))
63996    }
63997}
63998#[doc = "Shift Right and Insert (immediate)"]
63999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
64000#[inline]
64001#[cfg(target_arch = "arm")]
64002#[target_feature(enable = "neon,v7")]
64003#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
64005#[rustc_legacy_const_generics(2)]
64006pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
64007    static_assert!(1 <= N && N <= 32);
64008    unsafe {
64009        transmute(vshiftins_v2i32(
64010            transmute(a),
64011            transmute(b),
64012            int32x2_t::splat(-N),
64013        ))
64014    }
64015}
64016#[doc = "Shift Right and Insert (immediate)"]
64017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
64018#[inline]
64019#[cfg(target_arch = "arm")]
64020#[target_feature(enable = "neon,v7")]
64021#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
64023#[rustc_legacy_const_generics(2)]
64024pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
64025    static_assert!(1 <= N && N <= 32);
64026    unsafe {
64027        transmute(vshiftins_v4i32(
64028            transmute(a),
64029            transmute(b),
64030            int32x4_t::splat(-N),
64031        ))
64032    }
64033}
64034#[doc = "Shift Right and Insert (immediate)"]
64035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
64036#[inline]
64037#[cfg(target_arch = "arm")]
64038#[target_feature(enable = "neon,v7")]
64039#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
64041#[rustc_legacy_const_generics(2)]
64042pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
64043    static_assert!(1 <= N && N <= 64);
64044    unsafe {
64045        transmute(vshiftins_v1i64(
64046            transmute(a),
64047            transmute(b),
64048            int64x1_t::splat(-N as i64),
64049        ))
64050    }
64051}
64052#[doc = "Shift Right and Insert (immediate)"]
64053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
64054#[inline]
64055#[cfg(target_arch = "arm")]
64056#[target_feature(enable = "neon,v7")]
64057#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64058#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
64059#[rustc_legacy_const_generics(2)]
64060pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
64061    static_assert!(1 <= N && N <= 64);
64062    unsafe {
64063        transmute(vshiftins_v2i64(
64064            transmute(a),
64065            transmute(b),
64066            int64x2_t::splat(-N as i64),
64067        ))
64068    }
64069}
64070#[doc = "Shift Right and Insert (immediate)"]
64071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
64072#[inline]
64073#[cfg(target_arch = "arm")]
64074#[target_feature(enable = "neon,v7")]
64075#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64076#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64077#[rustc_legacy_const_generics(2)]
64078pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
64079    static_assert!(1 <= N && N <= 8);
64080    unsafe {
64081        transmute(vshiftins_v8i8(
64082            transmute(a),
64083            transmute(b),
64084            int8x8_t::splat(-N as i8),
64085        ))
64086    }
64087}
64088#[doc = "Shift Right and Insert (immediate)"]
64089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
64090#[inline]
64091#[cfg(target_arch = "arm")]
64092#[target_feature(enable = "neon,v7")]
64093#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64095#[rustc_legacy_const_generics(2)]
64096pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
64097    static_assert!(1 <= N && N <= 8);
64098    unsafe {
64099        transmute(vshiftins_v16i8(
64100            transmute(a),
64101            transmute(b),
64102            int8x16_t::splat(-N as i8),
64103        ))
64104    }
64105}
64106#[doc = "Shift Right and Insert (immediate)"]
64107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
64108#[inline]
64109#[cfg(target_arch = "arm")]
64110#[target_feature(enable = "neon,v7")]
64111#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64113#[rustc_legacy_const_generics(2)]
64114pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
64115    static_assert!(1 <= N && N <= 16);
64116    unsafe {
64117        transmute(vshiftins_v4i16(
64118            transmute(a),
64119            transmute(b),
64120            int16x4_t::splat(-N as i16),
64121        ))
64122    }
64123}
64124#[doc = "Shift Right and Insert (immediate)"]
64125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
64126#[inline]
64127#[cfg(target_arch = "arm")]
64128#[target_feature(enable = "neon,v7")]
64129#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64130#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64131#[rustc_legacy_const_generics(2)]
64132pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
64133    static_assert!(1 <= N && N <= 16);
64134    unsafe {
64135        transmute(vshiftins_v8i16(
64136            transmute(a),
64137            transmute(b),
64138            int16x8_t::splat(-N as i16),
64139        ))
64140    }
64141}
64142#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
64144#[doc = "## Safety"]
64145#[doc = "  * Neon instrinsic unsafe"]
64146#[inline]
64147#[cfg(target_arch = "arm")]
64148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64149#[target_feature(enable = "neon,fp16")]
64150#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64152pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
64153    vst1_v4f16(
64154        ptr as *const i8,
64155        transmute(a),
64156        crate::mem::align_of::<f16>() as i32,
64157    )
64158}
64159#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
64161#[doc = "## Safety"]
64162#[doc = "  * Neon instrinsic unsafe"]
64163#[inline]
64164#[cfg(target_arch = "arm")]
64165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64166#[target_feature(enable = "neon,fp16")]
64167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64169pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
64170    vst1q_v8f16(
64171        ptr as *const i8,
64172        transmute(a),
64173        crate::mem::align_of::<f16>() as i32,
64174    )
64175}
64176#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64178#[doc = "## Safety"]
64179#[doc = "  * Neon instrinsic unsafe"]
64180#[inline]
64181#[cfg(target_arch = "arm")]
64182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64183#[cfg_attr(test, assert_instr(vst1))]
64184#[target_feature(enable = "neon,fp16")]
64185#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64186pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64187    unsafe extern "unadjusted" {
64188        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v4f16")]
64189        fn _vst1_f16_x2(ptr: *mut f16, a: float16x4_t, b: float16x4_t);
64190    }
64191    _vst1_f16_x2(a, b.0, b.1)
64192}
64193#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64195#[doc = "## Safety"]
64196#[doc = "  * Neon instrinsic unsafe"]
64197#[inline]
64198#[cfg(target_arch = "arm")]
64199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64200#[cfg_attr(test, assert_instr(vst1))]
64201#[target_feature(enable = "neon,fp16")]
64202#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64203pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64204    unsafe extern "unadjusted" {
64205        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v8f16")]
64206        fn _vst1q_f16_x2(ptr: *mut f16, a: float16x8_t, b: float16x8_t);
64207    }
64208    _vst1q_f16_x2(a, b.0, b.1)
64209}
64210#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64212#[doc = "## Safety"]
64213#[doc = "  * Neon instrinsic unsafe"]
64214#[inline]
64215#[cfg(not(target_arch = "arm"))]
64216#[cfg_attr(test, assert_instr(st1))]
64217#[target_feature(enable = "neon,fp16")]
64218#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64219pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64220    unsafe extern "unadjusted" {
64221        #[cfg_attr(
64222            any(target_arch = "aarch64", target_arch = "arm64ec"),
64223            link_name = "llvm.aarch64.neon.st1x2.v4f16.p0f16"
64224        )]
64225        fn _vst1_f16_x2(a: float16x4_t, b: float16x4_t, ptr: *mut f16);
64226    }
64227    _vst1_f16_x2(b.0, b.1, a)
64228}
64229#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64231#[doc = "## Safety"]
64232#[doc = "  * Neon instrinsic unsafe"]
64233#[inline]
64234#[cfg(not(target_arch = "arm"))]
64235#[cfg_attr(test, assert_instr(st1))]
64236#[target_feature(enable = "neon,fp16")]
64237#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64238pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64239    unsafe extern "unadjusted" {
64240        #[cfg_attr(
64241            any(target_arch = "aarch64", target_arch = "arm64ec"),
64242            link_name = "llvm.aarch64.neon.st1x2.v8f16.p0f16"
64243        )]
64244        fn _vst1q_f16_x2(a: float16x8_t, b: float16x8_t, ptr: *mut f16);
64245    }
64246    _vst1q_f16_x2(b.0, b.1, a)
64247}
64248#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64250#[doc = "## Safety"]
64251#[doc = "  * Neon instrinsic unsafe"]
64252#[inline]
64253#[cfg(target_arch = "arm")]
64254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64255#[cfg_attr(test, assert_instr(vst1))]
64256#[target_feature(enable = "neon,fp16")]
64257#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64258pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64259    unsafe extern "unadjusted" {
64260        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v4f16")]
64261        fn _vst1_f16_x3(ptr: *mut f16, a: float16x4_t, b: float16x4_t, c: float16x4_t);
64262    }
64263    _vst1_f16_x3(a, b.0, b.1, b.2)
64264}
64265#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64267#[doc = "## Safety"]
64268#[doc = "  * Neon instrinsic unsafe"]
64269#[inline]
64270#[cfg(target_arch = "arm")]
64271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64272#[cfg_attr(test, assert_instr(vst1))]
64273#[target_feature(enable = "neon,fp16")]
64274#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64275pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64276    unsafe extern "unadjusted" {
64277        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v8f16")]
64278        fn _vst1q_f16_x3(ptr: *mut f16, a: float16x8_t, b: float16x8_t, c: float16x8_t);
64279    }
64280    _vst1q_f16_x3(a, b.0, b.1, b.2)
64281}
64282#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64284#[doc = "## Safety"]
64285#[doc = "  * Neon instrinsic unsafe"]
64286#[inline]
64287#[cfg(not(target_arch = "arm"))]
64288#[cfg_attr(test, assert_instr(st1))]
64289#[target_feature(enable = "neon,fp16")]
64290#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64291pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64292    unsafe extern "unadjusted" {
64293        #[cfg_attr(
64294            any(target_arch = "aarch64", target_arch = "arm64ec"),
64295            link_name = "llvm.aarch64.neon.st1x3.v4f16.p0f16"
64296        )]
64297        fn _vst1_f16_x3(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut f16);
64298    }
64299    _vst1_f16_x3(b.0, b.1, b.2, a)
64300}
64301#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64303#[doc = "## Safety"]
64304#[doc = "  * Neon instrinsic unsafe"]
64305#[inline]
64306#[cfg(not(target_arch = "arm"))]
64307#[cfg_attr(test, assert_instr(st1))]
64308#[target_feature(enable = "neon,fp16")]
64309#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64310pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64311    unsafe extern "unadjusted" {
64312        #[cfg_attr(
64313            any(target_arch = "aarch64", target_arch = "arm64ec"),
64314            link_name = "llvm.aarch64.neon.st1x3.v8f16.p0f16"
64315        )]
64316        fn _vst1q_f16_x3(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut f16);
64317    }
64318    _vst1q_f16_x3(b.0, b.1, b.2, a)
64319}
64320#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64322#[doc = "## Safety"]
64323#[doc = "  * Neon instrinsic unsafe"]
64324#[inline]
64325#[cfg(target_arch = "arm")]
64326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64327#[target_feature(enable = "neon,fp16")]
64328#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64329#[cfg_attr(test, assert_instr(vst1))]
64330pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64331    unsafe extern "unadjusted" {
64332        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v4f16")]
64333        fn _vst1_f16_x4(
64334            ptr: *mut f16,
64335            a: float16x4_t,
64336            b: float16x4_t,
64337            c: float16x4_t,
64338            d: float16x4_t,
64339        );
64340    }
64341    _vst1_f16_x4(a, b.0, b.1, b.2, b.3)
64342}
64343#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64345#[doc = "## Safety"]
64346#[doc = "  * Neon instrinsic unsafe"]
64347#[inline]
64348#[cfg(target_arch = "arm")]
64349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64350#[target_feature(enable = "neon,fp16")]
64351#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64352#[cfg_attr(test, assert_instr(vst1))]
64353pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64354    unsafe extern "unadjusted" {
64355        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v8f16")]
64356        fn _vst1q_f16_x4(
64357            ptr: *mut f16,
64358            a: float16x8_t,
64359            b: float16x8_t,
64360            c: float16x8_t,
64361            d: float16x8_t,
64362        );
64363    }
64364    _vst1q_f16_x4(a, b.0, b.1, b.2, b.3)
64365}
64366#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64368#[doc = "## Safety"]
64369#[doc = "  * Neon instrinsic unsafe"]
64370#[inline]
64371#[cfg(not(target_arch = "arm"))]
64372#[cfg_attr(test, assert_instr(st1))]
64373#[target_feature(enable = "neon,fp16")]
64374#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64375pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64376    unsafe extern "unadjusted" {
64377        #[cfg_attr(
64378            any(target_arch = "aarch64", target_arch = "arm64ec"),
64379            link_name = "llvm.aarch64.neon.st1x4.v4f16.p0f16"
64380        )]
64381        fn _vst1_f16_x4(
64382            a: float16x4_t,
64383            b: float16x4_t,
64384            c: float16x4_t,
64385            d: float16x4_t,
64386            ptr: *mut f16,
64387        );
64388    }
64389    _vst1_f16_x4(b.0, b.1, b.2, b.3, a)
64390}
64391#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64393#[doc = "## Safety"]
64394#[doc = "  * Neon instrinsic unsafe"]
64395#[inline]
64396#[cfg(not(target_arch = "arm"))]
64397#[cfg_attr(test, assert_instr(st1))]
64398#[target_feature(enable = "neon,fp16")]
64399#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64400pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64401    unsafe extern "unadjusted" {
64402        #[cfg_attr(
64403            any(target_arch = "aarch64", target_arch = "arm64ec"),
64404            link_name = "llvm.aarch64.neon.st1x4.v8f16.p0f16"
64405        )]
64406        fn _vst1q_f16_x4(
64407            a: float16x8_t,
64408            b: float16x8_t,
64409            c: float16x8_t,
64410            d: float16x8_t,
64411            ptr: *mut f16,
64412        );
64413    }
64414    _vst1q_f16_x4(b.0, b.1, b.2, b.3, a)
64415}
64416#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
64418#[doc = "## Safety"]
64419#[doc = "  * Neon instrinsic unsafe"]
64420#[inline]
64421#[target_feature(enable = "neon")]
64422#[cfg(target_arch = "arm")]
64423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64424#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64425#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64426pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
64427    vst1_v2f32(
64428        ptr as *const i8,
64429        transmute(a),
64430        crate::mem::align_of::<f32>() as i32,
64431    )
64432}
64433#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
64435#[doc = "## Safety"]
64436#[doc = "  * Neon instrinsic unsafe"]
64437#[inline]
64438#[target_feature(enable = "neon")]
64439#[cfg(target_arch = "arm")]
64440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64441#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64442#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64443pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
64444    vst1q_v4f32(
64445        ptr as *const i8,
64446        transmute(a),
64447        crate::mem::align_of::<f32>() as i32,
64448    )
64449}
64450#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
64452#[doc = "## Safety"]
64453#[doc = "  * Neon instrinsic unsafe"]
64454#[inline]
64455#[target_feature(enable = "neon")]
64456#[cfg(target_arch = "arm")]
64457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64458#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64460pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
64461    vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64462}
64463#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
64465#[doc = "## Safety"]
64466#[doc = "  * Neon instrinsic unsafe"]
64467#[inline]
64468#[target_feature(enable = "neon")]
64469#[cfg(target_arch = "arm")]
64470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64471#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64472#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64473pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
64474    vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64475}
64476#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
64478#[doc = "## Safety"]
64479#[doc = "  * Neon instrinsic unsafe"]
64480#[inline]
64481#[target_feature(enable = "neon")]
64482#[cfg(target_arch = "arm")]
64483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64484#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64486pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
64487    vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64488}
64489#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
64491#[doc = "## Safety"]
64492#[doc = "  * Neon instrinsic unsafe"]
64493#[inline]
64494#[target_feature(enable = "neon")]
64495#[cfg(target_arch = "arm")]
64496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64497#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64498#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64499pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
64500    vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64501}
64502#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
64504#[doc = "## Safety"]
64505#[doc = "  * Neon instrinsic unsafe"]
64506#[inline]
64507#[target_feature(enable = "neon")]
64508#[cfg(target_arch = "arm")]
64509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64510#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64511#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64512pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
64513    vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64514}
64515#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
64517#[doc = "## Safety"]
64518#[doc = "  * Neon instrinsic unsafe"]
64519#[inline]
64520#[target_feature(enable = "neon")]
64521#[cfg(target_arch = "arm")]
64522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64523#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64525pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
64526    vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64527}
64528#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
64530#[doc = "## Safety"]
64531#[doc = "  * Neon instrinsic unsafe"]
64532#[inline]
64533#[target_feature(enable = "neon")]
64534#[cfg(target_arch = "arm")]
64535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64536#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64537#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64538pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
64539    vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64540}
64541#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
64543#[doc = "## Safety"]
64544#[doc = "  * Neon instrinsic unsafe"]
64545#[inline]
64546#[target_feature(enable = "neon")]
64547#[cfg(target_arch = "arm")]
64548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64549#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64551pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
64552    vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64553}
64554#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
64556#[doc = "## Safety"]
64557#[doc = "  * Neon instrinsic unsafe"]
64558#[inline]
64559#[target_feature(enable = "neon")]
64560#[cfg(target_arch = "arm")]
64561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64562#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64564pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
64565    vst1_v8i8(
64566        ptr as *const i8,
64567        transmute(a),
64568        crate::mem::align_of::<u8>() as i32,
64569    )
64570}
64571#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
64573#[doc = "## Safety"]
64574#[doc = "  * Neon instrinsic unsafe"]
64575#[inline]
64576#[target_feature(enable = "neon")]
64577#[cfg(target_arch = "arm")]
64578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64579#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64581pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
64582    vst1q_v16i8(
64583        ptr as *const i8,
64584        transmute(a),
64585        crate::mem::align_of::<u8>() as i32,
64586    )
64587}
64588#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
64590#[doc = "## Safety"]
64591#[doc = "  * Neon instrinsic unsafe"]
64592#[inline]
64593#[target_feature(enable = "neon")]
64594#[cfg(target_arch = "arm")]
64595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64596#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64597#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64598pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
64599    vst1_v4i16(
64600        ptr as *const i8,
64601        transmute(a),
64602        crate::mem::align_of::<u16>() as i32,
64603    )
64604}
64605#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
64607#[doc = "## Safety"]
64608#[doc = "  * Neon instrinsic unsafe"]
64609#[inline]
64610#[target_feature(enable = "neon")]
64611#[cfg(target_arch = "arm")]
64612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64613#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64615pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
64616    vst1q_v8i16(
64617        ptr as *const i8,
64618        transmute(a),
64619        crate::mem::align_of::<u16>() as i32,
64620    )
64621}
64622#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
64624#[doc = "## Safety"]
64625#[doc = "  * Neon instrinsic unsafe"]
64626#[inline]
64627#[target_feature(enable = "neon")]
64628#[cfg(target_arch = "arm")]
64629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64630#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64631#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64632pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
64633    vst1_v2i32(
64634        ptr as *const i8,
64635        transmute(a),
64636        crate::mem::align_of::<u32>() as i32,
64637    )
64638}
64639#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
64641#[doc = "## Safety"]
64642#[doc = "  * Neon instrinsic unsafe"]
64643#[inline]
64644#[target_feature(enable = "neon")]
64645#[cfg(target_arch = "arm")]
64646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64647#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64648#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64649pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
64650    vst1q_v4i32(
64651        ptr as *const i8,
64652        transmute(a),
64653        crate::mem::align_of::<u32>() as i32,
64654    )
64655}
64656#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
64658#[doc = "## Safety"]
64659#[doc = "  * Neon instrinsic unsafe"]
64660#[inline]
64661#[target_feature(enable = "neon")]
64662#[cfg(target_arch = "arm")]
64663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64664#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64665#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64666pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
64667    vst1_v1i64(
64668        ptr as *const i8,
64669        transmute(a),
64670        crate::mem::align_of::<u64>() as i32,
64671    )
64672}
64673#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
64675#[doc = "## Safety"]
64676#[doc = "  * Neon instrinsic unsafe"]
64677#[inline]
64678#[target_feature(enable = "neon")]
64679#[cfg(target_arch = "arm")]
64680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64681#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64683pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
64684    vst1q_v2i64(
64685        ptr as *const i8,
64686        transmute(a),
64687        crate::mem::align_of::<u64>() as i32,
64688    )
64689}
64690#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
64692#[doc = "## Safety"]
64693#[doc = "  * Neon instrinsic unsafe"]
64694#[inline]
64695#[target_feature(enable = "neon")]
64696#[cfg(target_arch = "arm")]
64697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64698#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64700pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
64701    vst1_v8i8(
64702        ptr as *const i8,
64703        transmute(a),
64704        crate::mem::align_of::<p8>() as i32,
64705    )
64706}
64707#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
64709#[doc = "## Safety"]
64710#[doc = "  * Neon instrinsic unsafe"]
64711#[inline]
64712#[target_feature(enable = "neon")]
64713#[cfg(target_arch = "arm")]
64714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64715#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64716#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64717pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
64718    vst1q_v16i8(
64719        ptr as *const i8,
64720        transmute(a),
64721        crate::mem::align_of::<p8>() as i32,
64722    )
64723}
64724#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
64726#[doc = "## Safety"]
64727#[doc = "  * Neon instrinsic unsafe"]
64728#[inline]
64729#[target_feature(enable = "neon")]
64730#[cfg(target_arch = "arm")]
64731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64732#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64733#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64734pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
64735    vst1_v4i16(
64736        ptr as *const i8,
64737        transmute(a),
64738        crate::mem::align_of::<p16>() as i32,
64739    )
64740}
64741#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
64743#[doc = "## Safety"]
64744#[doc = "  * Neon instrinsic unsafe"]
64745#[inline]
64746#[target_feature(enable = "neon")]
64747#[cfg(target_arch = "arm")]
64748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64749#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64750#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64751pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
64752    vst1q_v8i16(
64753        ptr as *const i8,
64754        transmute(a),
64755        crate::mem::align_of::<p16>() as i32,
64756    )
64757}
64758#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
64760#[doc = "## Safety"]
64761#[doc = "  * Neon instrinsic unsafe"]
64762#[inline]
64763#[target_feature(enable = "neon")]
64764#[cfg(target_arch = "arm")]
64765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64766#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64768pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
64769    vst1_v1i64(
64770        ptr as *const i8,
64771        transmute(a),
64772        crate::mem::align_of::<p64>() as i32,
64773    )
64774}
64775#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
64777#[doc = "## Safety"]
64778#[doc = "  * Neon instrinsic unsafe"]
64779#[inline]
64780#[target_feature(enable = "neon")]
64781#[cfg(target_arch = "arm")]
64782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64783#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64785pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
64786    vst1q_v2i64(
64787        ptr as *const i8,
64788        transmute(a),
64789        crate::mem::align_of::<p64>() as i32,
64790    )
64791}
64792#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64794#[doc = "## Safety"]
64795#[doc = "  * Neon instrinsic unsafe"]
64796#[inline]
64797#[cfg(target_arch = "arm")]
64798#[target_feature(enable = "neon,v7")]
64799#[cfg_attr(test, assert_instr(vst1))]
64800#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64801pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64802    unsafe extern "unadjusted" {
64803        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2f32.p0")]
64804        fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t);
64805    }
64806    _vst1_f32_x2(a, b.0, b.1)
64807}
64808#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64810#[doc = "## Safety"]
64811#[doc = "  * Neon instrinsic unsafe"]
64812#[inline]
64813#[cfg(target_arch = "arm")]
64814#[target_feature(enable = "neon,v7")]
64815#[cfg_attr(test, assert_instr(vst1))]
64816#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64817pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64818    unsafe extern "unadjusted" {
64819        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4f32.p0")]
64820        fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t);
64821    }
64822    _vst1q_f32_x2(a, b.0, b.1)
64823}
64824#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64826#[doc = "## Safety"]
64827#[doc = "  * Neon instrinsic unsafe"]
64828#[inline]
64829#[target_feature(enable = "neon")]
64830#[cfg(not(target_arch = "arm"))]
64831#[cfg_attr(test, assert_instr(st1))]
64832#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64833pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64834    unsafe extern "unadjusted" {
64835        #[cfg_attr(
64836            any(target_arch = "aarch64", target_arch = "arm64ec"),
64837            link_name = "llvm.aarch64.neon.st1x2.v2f32.p0f32"
64838        )]
64839        fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32);
64840    }
64841    _vst1_f32_x2(b.0, b.1, a)
64842}
64843#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64845#[doc = "## Safety"]
64846#[doc = "  * Neon instrinsic unsafe"]
64847#[inline]
64848#[target_feature(enable = "neon")]
64849#[cfg(not(target_arch = "arm"))]
64850#[cfg_attr(test, assert_instr(st1))]
64851#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64852pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64853    unsafe extern "unadjusted" {
64854        #[cfg_attr(
64855            any(target_arch = "aarch64", target_arch = "arm64ec"),
64856            link_name = "llvm.aarch64.neon.st1x2.v4f32.p0f32"
64857        )]
64858        fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32);
64859    }
64860    _vst1q_f32_x2(b.0, b.1, a)
64861}
64862#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
64864#[doc = "## Safety"]
64865#[doc = "  * Neon instrinsic unsafe"]
64866#[inline]
64867#[target_feature(enable = "neon")]
64868#[cfg(not(target_arch = "arm"))]
64869#[cfg_attr(test, assert_instr(st1))]
64870#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64871pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
64872    unsafe extern "unadjusted" {
64873        #[cfg_attr(
64874            any(target_arch = "aarch64", target_arch = "arm64ec"),
64875            link_name = "llvm.aarch64.neon.st1x3.v2f32.p0f32"
64876        )]
64877        fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32);
64878    }
64879    _vst1_f32_x3(b.0, b.1, b.2, a)
64880}
64881#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
64883#[doc = "## Safety"]
64884#[doc = "  * Neon instrinsic unsafe"]
64885#[inline]
64886#[target_feature(enable = "neon")]
64887#[cfg(not(target_arch = "arm"))]
64888#[cfg_attr(test, assert_instr(st1))]
64889#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64890pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
64891    unsafe extern "unadjusted" {
64892        #[cfg_attr(
64893            any(target_arch = "aarch64", target_arch = "arm64ec"),
64894            link_name = "llvm.aarch64.neon.st1x3.v4f32.p0f32"
64895        )]
64896        fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32);
64897    }
64898    _vst1q_f32_x3(b.0, b.1, b.2, a)
64899}
64900#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64902#[doc = "## Safety"]
64903#[doc = "  * Neon instrinsic unsafe"]
64904#[inline]
64905#[cfg(target_arch = "arm")]
64906#[target_feature(enable = "neon,v7")]
64907#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64908#[cfg_attr(test, assert_instr(vst1))]
64909pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64910    unsafe extern "unadjusted" {
64911        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v2f32.p0")]
64912        fn _vst1_f32_x4(
64913            ptr: *mut f32,
64914            a: float32x2_t,
64915            b: float32x2_t,
64916            c: float32x2_t,
64917            d: float32x2_t,
64918        );
64919    }
64920    _vst1_f32_x4(a, b.0, b.1, b.2, b.3)
64921}
64922#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64924#[doc = "## Safety"]
64925#[doc = "  * Neon instrinsic unsafe"]
64926#[inline]
64927#[cfg(target_arch = "arm")]
64928#[target_feature(enable = "neon,v7")]
64929#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64930#[cfg_attr(test, assert_instr(vst1))]
64931pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64932    unsafe extern "unadjusted" {
64933        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v4f32.p0")]
64934        fn _vst1q_f32_x4(
64935            ptr: *mut f32,
64936            a: float32x4_t,
64937            b: float32x4_t,
64938            c: float32x4_t,
64939            d: float32x4_t,
64940        );
64941    }
64942    _vst1q_f32_x4(a, b.0, b.1, b.2, b.3)
64943}
64944#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64946#[doc = "## Safety"]
64947#[doc = "  * Neon instrinsic unsafe"]
64948#[inline]
64949#[target_feature(enable = "neon")]
64950#[cfg(not(target_arch = "arm"))]
64951#[cfg_attr(test, assert_instr(st1))]
64952#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64953pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64954    unsafe extern "unadjusted" {
64955        #[cfg_attr(
64956            any(target_arch = "aarch64", target_arch = "arm64ec"),
64957            link_name = "llvm.aarch64.neon.st1x4.v2f32.p0f32"
64958        )]
64959        fn _vst1_f32_x4(
64960            a: float32x2_t,
64961            b: float32x2_t,
64962            c: float32x2_t,
64963            d: float32x2_t,
64964            ptr: *mut f32,
64965        );
64966    }
64967    _vst1_f32_x4(b.0, b.1, b.2, b.3, a)
64968}
64969#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64971#[doc = "## Safety"]
64972#[doc = "  * Neon instrinsic unsafe"]
64973#[inline]
64974#[target_feature(enable = "neon")]
64975#[cfg(not(target_arch = "arm"))]
64976#[cfg_attr(test, assert_instr(st1))]
64977#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64978pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64979    unsafe extern "unadjusted" {
64980        #[cfg_attr(
64981            any(target_arch = "aarch64", target_arch = "arm64ec"),
64982            link_name = "llvm.aarch64.neon.st1x4.v4f32.p0f32"
64983        )]
64984        fn _vst1q_f32_x4(
64985            a: float32x4_t,
64986            b: float32x4_t,
64987            c: float32x4_t,
64988            d: float32x4_t,
64989            ptr: *mut f32,
64990        );
64991    }
64992    _vst1q_f32_x4(b.0, b.1, b.2, b.3, a)
64993}
64994#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
64996#[doc = "## Safety"]
64997#[doc = "  * Neon instrinsic unsafe"]
64998#[inline]
64999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65001#[cfg_attr(
65002    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65003    assert_instr(nop, LANE = 0)
65004)]
65005#[rustc_legacy_const_generics(2)]
65006#[target_feature(enable = "neon,fp16")]
65007#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
65008pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
65009    static_assert_uimm_bits!(LANE, 2);
65010    *a = simd_extract!(b, LANE as u32);
65011}
65012#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
65014#[doc = "## Safety"]
65015#[doc = "  * Neon instrinsic unsafe"]
65016#[inline]
65017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65019#[cfg_attr(
65020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65021    assert_instr(nop, LANE = 0)
65022)]
65023#[rustc_legacy_const_generics(2)]
65024#[target_feature(enable = "neon,fp16")]
65025#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
65026pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
65027    static_assert_uimm_bits!(LANE, 3);
65028    *a = simd_extract!(b, LANE as u32);
65029}
65030#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
65032#[doc = "## Safety"]
65033#[doc = "  * Neon instrinsic unsafe"]
65034#[inline]
65035#[target_feature(enable = "neon")]
65036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65038#[cfg_attr(
65039    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65040    assert_instr(nop, LANE = 0)
65041)]
65042#[rustc_legacy_const_generics(2)]
65043#[cfg_attr(
65044    not(target_arch = "arm"),
65045    stable(feature = "neon_intrinsics", since = "1.59.0")
65046)]
65047#[cfg_attr(
65048    target_arch = "arm",
65049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65050)]
65051pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
65052    static_assert_uimm_bits!(LANE, 1);
65053    *a = simd_extract!(b, LANE as u32);
65054}
65055#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
65057#[doc = "## Safety"]
65058#[doc = "  * Neon instrinsic unsafe"]
65059#[inline]
65060#[target_feature(enable = "neon")]
65061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65063#[cfg_attr(
65064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65065    assert_instr(nop, LANE = 0)
65066)]
65067#[rustc_legacy_const_generics(2)]
65068#[cfg_attr(
65069    not(target_arch = "arm"),
65070    stable(feature = "neon_intrinsics", since = "1.59.0")
65071)]
65072#[cfg_attr(
65073    target_arch = "arm",
65074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65075)]
65076pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
65077    static_assert_uimm_bits!(LANE, 2);
65078    *a = simd_extract!(b, LANE as u32);
65079}
65080#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
65082#[doc = "## Safety"]
65083#[doc = "  * Neon instrinsic unsafe"]
65084#[inline]
65085#[target_feature(enable = "neon")]
65086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65088#[cfg_attr(
65089    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65090    assert_instr(nop, LANE = 0)
65091)]
65092#[rustc_legacy_const_generics(2)]
65093#[cfg_attr(
65094    not(target_arch = "arm"),
65095    stable(feature = "neon_intrinsics", since = "1.59.0")
65096)]
65097#[cfg_attr(
65098    target_arch = "arm",
65099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65100)]
65101pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
65102    static_assert_uimm_bits!(LANE, 3);
65103    *a = simd_extract!(b, LANE as u32);
65104}
65105#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
65107#[doc = "## Safety"]
65108#[doc = "  * Neon instrinsic unsafe"]
65109#[inline]
65110#[target_feature(enable = "neon")]
65111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65113#[cfg_attr(
65114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65115    assert_instr(nop, LANE = 0)
65116)]
65117#[rustc_legacy_const_generics(2)]
65118#[cfg_attr(
65119    not(target_arch = "arm"),
65120    stable(feature = "neon_intrinsics", since = "1.59.0")
65121)]
65122#[cfg_attr(
65123    target_arch = "arm",
65124    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65125)]
65126pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
65127    static_assert_uimm_bits!(LANE, 4);
65128    *a = simd_extract!(b, LANE as u32);
65129}
65130#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
65132#[doc = "## Safety"]
65133#[doc = "  * Neon instrinsic unsafe"]
65134#[inline]
65135#[target_feature(enable = "neon")]
65136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65138#[cfg_attr(
65139    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65140    assert_instr(nop, LANE = 0)
65141)]
65142#[rustc_legacy_const_generics(2)]
65143#[cfg_attr(
65144    not(target_arch = "arm"),
65145    stable(feature = "neon_intrinsics", since = "1.59.0")
65146)]
65147#[cfg_attr(
65148    target_arch = "arm",
65149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65150)]
65151pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
65152    static_assert_uimm_bits!(LANE, 2);
65153    *a = simd_extract!(b, LANE as u32);
65154}
65155#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
65157#[doc = "## Safety"]
65158#[doc = "  * Neon instrinsic unsafe"]
65159#[inline]
65160#[target_feature(enable = "neon")]
65161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65163#[cfg_attr(
65164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65165    assert_instr(nop, LANE = 0)
65166)]
65167#[rustc_legacy_const_generics(2)]
65168#[cfg_attr(
65169    not(target_arch = "arm"),
65170    stable(feature = "neon_intrinsics", since = "1.59.0")
65171)]
65172#[cfg_attr(
65173    target_arch = "arm",
65174    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65175)]
65176pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
65177    static_assert_uimm_bits!(LANE, 3);
65178    *a = simd_extract!(b, LANE as u32);
65179}
65180#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
65182#[doc = "## Safety"]
65183#[doc = "  * Neon instrinsic unsafe"]
65184#[inline]
65185#[target_feature(enable = "neon")]
65186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65188#[cfg_attr(
65189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65190    assert_instr(nop, LANE = 0)
65191)]
65192#[rustc_legacy_const_generics(2)]
65193#[cfg_attr(
65194    not(target_arch = "arm"),
65195    stable(feature = "neon_intrinsics", since = "1.59.0")
65196)]
65197#[cfg_attr(
65198    target_arch = "arm",
65199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65200)]
65201pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
65202    static_assert_uimm_bits!(LANE, 1);
65203    *a = simd_extract!(b, LANE as u32);
65204}
65205#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
65207#[doc = "## Safety"]
65208#[doc = "  * Neon instrinsic unsafe"]
65209#[inline]
65210#[target_feature(enable = "neon")]
65211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65213#[cfg_attr(
65214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65215    assert_instr(nop, LANE = 0)
65216)]
65217#[rustc_legacy_const_generics(2)]
65218#[cfg_attr(
65219    not(target_arch = "arm"),
65220    stable(feature = "neon_intrinsics", since = "1.59.0")
65221)]
65222#[cfg_attr(
65223    target_arch = "arm",
65224    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65225)]
65226pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
65227    static_assert_uimm_bits!(LANE, 2);
65228    *a = simd_extract!(b, LANE as u32);
65229}
65230#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
65232#[doc = "## Safety"]
65233#[doc = "  * Neon instrinsic unsafe"]
65234#[inline]
65235#[target_feature(enable = "neon")]
65236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65238#[cfg_attr(
65239    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65240    assert_instr(nop, LANE = 0)
65241)]
65242#[rustc_legacy_const_generics(2)]
65243#[cfg_attr(
65244    not(target_arch = "arm"),
65245    stable(feature = "neon_intrinsics", since = "1.59.0")
65246)]
65247#[cfg_attr(
65248    target_arch = "arm",
65249    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65250)]
65251pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
65252    static_assert_uimm_bits!(LANE, 1);
65253    *a = simd_extract!(b, LANE as u32);
65254}
65255#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
65257#[doc = "## Safety"]
65258#[doc = "  * Neon instrinsic unsafe"]
65259#[inline]
65260#[target_feature(enable = "neon")]
65261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65263#[cfg_attr(
65264    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65265    assert_instr(nop, LANE = 0)
65266)]
65267#[rustc_legacy_const_generics(2)]
65268#[cfg_attr(
65269    not(target_arch = "arm"),
65270    stable(feature = "neon_intrinsics", since = "1.59.0")
65271)]
65272#[cfg_attr(
65273    target_arch = "arm",
65274    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65275)]
65276pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
65277    static_assert_uimm_bits!(LANE, 3);
65278    *a = simd_extract!(b, LANE as u32);
65279}
65280#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
65282#[doc = "## Safety"]
65283#[doc = "  * Neon instrinsic unsafe"]
65284#[inline]
65285#[target_feature(enable = "neon")]
65286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65288#[cfg_attr(
65289    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65290    assert_instr(nop, LANE = 0)
65291)]
65292#[rustc_legacy_const_generics(2)]
65293#[cfg_attr(
65294    not(target_arch = "arm"),
65295    stable(feature = "neon_intrinsics", since = "1.59.0")
65296)]
65297#[cfg_attr(
65298    target_arch = "arm",
65299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65300)]
65301pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
65302    static_assert_uimm_bits!(LANE, 4);
65303    *a = simd_extract!(b, LANE as u32);
65304}
65305#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
65307#[doc = "## Safety"]
65308#[doc = "  * Neon instrinsic unsafe"]
65309#[inline]
65310#[target_feature(enable = "neon")]
65311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65313#[cfg_attr(
65314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65315    assert_instr(nop, LANE = 0)
65316)]
65317#[rustc_legacy_const_generics(2)]
65318#[cfg_attr(
65319    not(target_arch = "arm"),
65320    stable(feature = "neon_intrinsics", since = "1.59.0")
65321)]
65322#[cfg_attr(
65323    target_arch = "arm",
65324    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65325)]
65326pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
65327    static_assert_uimm_bits!(LANE, 2);
65328    *a = simd_extract!(b, LANE as u32);
65329}
65330#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
65332#[doc = "## Safety"]
65333#[doc = "  * Neon instrinsic unsafe"]
65334#[inline]
65335#[target_feature(enable = "neon")]
65336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65338#[cfg_attr(
65339    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65340    assert_instr(nop, LANE = 0)
65341)]
65342#[rustc_legacy_const_generics(2)]
65343#[cfg_attr(
65344    not(target_arch = "arm"),
65345    stable(feature = "neon_intrinsics", since = "1.59.0")
65346)]
65347#[cfg_attr(
65348    target_arch = "arm",
65349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65350)]
65351pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
65352    static_assert_uimm_bits!(LANE, 3);
65353    *a = simd_extract!(b, LANE as u32);
65354}
65355#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
65357#[doc = "## Safety"]
65358#[doc = "  * Neon instrinsic unsafe"]
65359#[inline]
65360#[target_feature(enable = "neon")]
65361#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65363#[cfg_attr(
65364    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65365    assert_instr(nop, LANE = 0)
65366)]
65367#[rustc_legacy_const_generics(2)]
65368#[cfg_attr(
65369    not(target_arch = "arm"),
65370    stable(feature = "neon_intrinsics", since = "1.59.0")
65371)]
65372#[cfg_attr(
65373    target_arch = "arm",
65374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65375)]
65376pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
65377    static_assert_uimm_bits!(LANE, 1);
65378    *a = simd_extract!(b, LANE as u32);
65379}
65380#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
65382#[doc = "## Safety"]
65383#[doc = "  * Neon instrinsic unsafe"]
65384#[inline]
65385#[target_feature(enable = "neon")]
65386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65388#[cfg_attr(
65389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65390    assert_instr(nop, LANE = 0)
65391)]
65392#[rustc_legacy_const_generics(2)]
65393#[cfg_attr(
65394    not(target_arch = "arm"),
65395    stable(feature = "neon_intrinsics", since = "1.59.0")
65396)]
65397#[cfg_attr(
65398    target_arch = "arm",
65399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65400)]
65401pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
65402    static_assert_uimm_bits!(LANE, 2);
65403    *a = simd_extract!(b, LANE as u32);
65404}
65405#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
65407#[doc = "## Safety"]
65408#[doc = "  * Neon instrinsic unsafe"]
65409#[inline]
65410#[target_feature(enable = "neon")]
65411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65413#[cfg_attr(
65414    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65415    assert_instr(nop, LANE = 0)
65416)]
65417#[rustc_legacy_const_generics(2)]
65418#[cfg_attr(
65419    not(target_arch = "arm"),
65420    stable(feature = "neon_intrinsics", since = "1.59.0")
65421)]
65422#[cfg_attr(
65423    target_arch = "arm",
65424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65425)]
65426pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
65427    static_assert_uimm_bits!(LANE, 1);
65428    *a = simd_extract!(b, LANE as u32);
65429}
65430#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
65432#[doc = "## Safety"]
65433#[doc = "  * Neon instrinsic unsafe"]
65434#[inline]
65435#[target_feature(enable = "neon")]
65436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65438#[cfg_attr(
65439    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65440    assert_instr(nop, LANE = 0)
65441)]
65442#[rustc_legacy_const_generics(2)]
65443#[cfg_attr(
65444    not(target_arch = "arm"),
65445    stable(feature = "neon_intrinsics", since = "1.59.0")
65446)]
65447#[cfg_attr(
65448    target_arch = "arm",
65449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65450)]
65451pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
65452    static_assert_uimm_bits!(LANE, 3);
65453    *a = simd_extract!(b, LANE as u32);
65454}
65455#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
65457#[doc = "## Safety"]
65458#[doc = "  * Neon instrinsic unsafe"]
65459#[inline]
65460#[target_feature(enable = "neon")]
65461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65463#[cfg_attr(
65464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65465    assert_instr(nop, LANE = 0)
65466)]
65467#[rustc_legacy_const_generics(2)]
65468#[cfg_attr(
65469    not(target_arch = "arm"),
65470    stable(feature = "neon_intrinsics", since = "1.59.0")
65471)]
65472#[cfg_attr(
65473    target_arch = "arm",
65474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65475)]
65476pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
65477    static_assert_uimm_bits!(LANE, 4);
65478    *a = simd_extract!(b, LANE as u32);
65479}
65480#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
65482#[doc = "## Safety"]
65483#[doc = "  * Neon instrinsic unsafe"]
65484#[inline]
65485#[target_feature(enable = "neon")]
65486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65488#[cfg_attr(
65489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65490    assert_instr(nop, LANE = 0)
65491)]
65492#[rustc_legacy_const_generics(2)]
65493#[cfg_attr(
65494    not(target_arch = "arm"),
65495    stable(feature = "neon_intrinsics", since = "1.59.0")
65496)]
65497#[cfg_attr(
65498    target_arch = "arm",
65499    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65500)]
65501pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
65502    static_assert_uimm_bits!(LANE, 2);
65503    *a = simd_extract!(b, LANE as u32);
65504}
65505#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
65507#[doc = "## Safety"]
65508#[doc = "  * Neon instrinsic unsafe"]
65509#[inline]
65510#[target_feature(enable = "neon")]
65511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65513#[cfg_attr(
65514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65515    assert_instr(nop, LANE = 0)
65516)]
65517#[rustc_legacy_const_generics(2)]
65518#[cfg_attr(
65519    not(target_arch = "arm"),
65520    stable(feature = "neon_intrinsics", since = "1.59.0")
65521)]
65522#[cfg_attr(
65523    target_arch = "arm",
65524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65525)]
65526pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
65527    static_assert_uimm_bits!(LANE, 3);
65528    *a = simd_extract!(b, LANE as u32);
65529}
65530#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
65532#[doc = "## Safety"]
65533#[doc = "  * Neon instrinsic unsafe"]
65534#[inline]
65535#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65536#[target_feature(enable = "neon,aes")]
65537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65538#[cfg_attr(
65539    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65540    assert_instr(nop, LANE = 0)
65541)]
65542#[rustc_legacy_const_generics(2)]
65543#[cfg_attr(
65544    not(target_arch = "arm"),
65545    stable(feature = "neon_intrinsics", since = "1.59.0")
65546)]
65547#[cfg_attr(
65548    target_arch = "arm",
65549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65550)]
65551pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
65552    static_assert!(LANE == 0);
65553    *a = simd_extract!(b, LANE as u32);
65554}
65555#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
65557#[doc = "## Safety"]
65558#[doc = "  * Neon instrinsic unsafe"]
65559#[inline]
65560#[target_feature(enable = "neon")]
65561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65563#[cfg_attr(
65564    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65565    assert_instr(nop, LANE = 0)
65566)]
65567#[rustc_legacy_const_generics(2)]
65568#[cfg_attr(
65569    not(target_arch = "arm"),
65570    stable(feature = "neon_intrinsics", since = "1.59.0")
65571)]
65572#[cfg_attr(
65573    target_arch = "arm",
65574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65575)]
65576pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
65577    static_assert!(LANE == 0);
65578    *a = simd_extract!(b, LANE as u32);
65579}
65580#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
65582#[doc = "## Safety"]
65583#[doc = "  * Neon instrinsic unsafe"]
65584#[inline]
65585#[target_feature(enable = "neon")]
65586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65588#[cfg_attr(
65589    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65590    assert_instr(nop, LANE = 0)
65591)]
65592#[rustc_legacy_const_generics(2)]
65593#[cfg_attr(
65594    not(target_arch = "arm"),
65595    stable(feature = "neon_intrinsics", since = "1.59.0")
65596)]
65597#[cfg_attr(
65598    target_arch = "arm",
65599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65600)]
65601pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
65602    static_assert!(LANE == 0);
65603    *a = simd_extract!(b, LANE as u32);
65604}
65605#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
65607#[doc = "## Safety"]
65608#[doc = "  * Neon instrinsic unsafe"]
65609#[inline]
65610#[target_feature(enable = "neon,aes")]
65611#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
65613#[cfg_attr(
65614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65615    assert_instr(st1)
65616)]
65617#[cfg_attr(
65618    not(target_arch = "arm"),
65619    stable(feature = "neon_intrinsics", since = "1.59.0")
65620)]
65621#[cfg_attr(
65622    target_arch = "arm",
65623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65624)]
65625pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
65626    vst1_s64_x2(transmute(a), transmute(b))
65627}
65628#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
65630#[doc = "## Safety"]
65631#[doc = "  * Neon instrinsic unsafe"]
65632#[inline]
65633#[target_feature(enable = "neon,aes")]
65634#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65636#[cfg_attr(
65637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65638    assert_instr(st1)
65639)]
65640#[cfg_attr(
65641    not(target_arch = "arm"),
65642    stable(feature = "neon_intrinsics", since = "1.59.0")
65643)]
65644#[cfg_attr(
65645    target_arch = "arm",
65646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65647)]
65648pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
65649    vst1_s64_x3(transmute(a), transmute(b))
65650}
65651#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
65653#[doc = "## Safety"]
65654#[doc = "  * Neon instrinsic unsafe"]
65655#[inline]
65656#[target_feature(enable = "neon,aes")]
65657#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65659#[cfg_attr(
65660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65661    assert_instr(st1)
65662)]
65663#[cfg_attr(
65664    not(target_arch = "arm"),
65665    stable(feature = "neon_intrinsics", since = "1.59.0")
65666)]
65667#[cfg_attr(
65668    target_arch = "arm",
65669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65670)]
65671pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
65672    vst1_s64_x4(transmute(a), transmute(b))
65673}
65674#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
65676#[doc = "## Safety"]
65677#[doc = "  * Neon instrinsic unsafe"]
65678#[inline]
65679#[target_feature(enable = "neon,aes")]
65680#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65682#[cfg_attr(
65683    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65684    assert_instr(st1)
65685)]
65686#[cfg_attr(
65687    not(target_arch = "arm"),
65688    stable(feature = "neon_intrinsics", since = "1.59.0")
65689)]
65690#[cfg_attr(
65691    target_arch = "arm",
65692    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65693)]
65694pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
65695    vst1q_s64_x2(transmute(a), transmute(b))
65696}
65697#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
65699#[doc = "## Safety"]
65700#[doc = "  * Neon instrinsic unsafe"]
65701#[inline]
65702#[target_feature(enable = "neon,aes")]
65703#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65705#[cfg_attr(
65706    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65707    assert_instr(st1)
65708)]
65709#[cfg_attr(
65710    not(target_arch = "arm"),
65711    stable(feature = "neon_intrinsics", since = "1.59.0")
65712)]
65713#[cfg_attr(
65714    target_arch = "arm",
65715    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65716)]
65717pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
65718    vst1q_s64_x3(transmute(a), transmute(b))
65719}
65720#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
65722#[doc = "## Safety"]
65723#[doc = "  * Neon instrinsic unsafe"]
65724#[inline]
65725#[target_feature(enable = "neon,aes")]
65726#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65728#[cfg_attr(
65729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65730    assert_instr(st1)
65731)]
65732#[cfg_attr(
65733    not(target_arch = "arm"),
65734    stable(feature = "neon_intrinsics", since = "1.59.0")
65735)]
65736#[cfg_attr(
65737    target_arch = "arm",
65738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65739)]
65740pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
65741    vst1q_s64_x4(transmute(a), transmute(b))
65742}
65743#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65745#[doc = "## Safety"]
65746#[doc = "  * Neon instrinsic unsafe"]
65747#[inline]
65748#[target_feature(enable = "neon")]
65749#[cfg(not(target_arch = "arm"))]
65750#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65751#[cfg_attr(test, assert_instr(st1))]
65752pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65753    unsafe extern "unadjusted" {
65754        #[cfg_attr(
65755            any(target_arch = "aarch64", target_arch = "arm64ec"),
65756            link_name = "llvm.aarch64.neon.st1x2.v8i8.p0i8"
65757        )]
65758        fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
65759    }
65760    _vst1_s8_x2(b.0, b.1, a)
65761}
65762#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65764#[doc = "## Safety"]
65765#[doc = "  * Neon instrinsic unsafe"]
65766#[inline]
65767#[target_feature(enable = "neon")]
65768#[cfg(not(target_arch = "arm"))]
65769#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65770#[cfg_attr(test, assert_instr(st1))]
65771pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65772    unsafe extern "unadjusted" {
65773        #[cfg_attr(
65774            any(target_arch = "aarch64", target_arch = "arm64ec"),
65775            link_name = "llvm.aarch64.neon.st1x2.v16i8.p0i8"
65776        )]
65777        fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
65778    }
65779    _vst1q_s8_x2(b.0, b.1, a)
65780}
65781#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65783#[doc = "## Safety"]
65784#[doc = "  * Neon instrinsic unsafe"]
65785#[inline]
65786#[target_feature(enable = "neon")]
65787#[cfg(not(target_arch = "arm"))]
65788#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65789#[cfg_attr(test, assert_instr(st1))]
65790pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65791    unsafe extern "unadjusted" {
65792        #[cfg_attr(
65793            any(target_arch = "aarch64", target_arch = "arm64ec"),
65794            link_name = "llvm.aarch64.neon.st1x2.v4i16.p0i16"
65795        )]
65796        fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16);
65797    }
65798    _vst1_s16_x2(b.0, b.1, a)
65799}
65800#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65802#[doc = "## Safety"]
65803#[doc = "  * Neon instrinsic unsafe"]
65804#[inline]
65805#[target_feature(enable = "neon")]
65806#[cfg(not(target_arch = "arm"))]
65807#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65808#[cfg_attr(test, assert_instr(st1))]
65809pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65810    unsafe extern "unadjusted" {
65811        #[cfg_attr(
65812            any(target_arch = "aarch64", target_arch = "arm64ec"),
65813            link_name = "llvm.aarch64.neon.st1x2.v8i16.p0i16"
65814        )]
65815        fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16);
65816    }
65817    _vst1q_s16_x2(b.0, b.1, a)
65818}
65819#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65821#[doc = "## Safety"]
65822#[doc = "  * Neon instrinsic unsafe"]
65823#[inline]
65824#[target_feature(enable = "neon")]
65825#[cfg(not(target_arch = "arm"))]
65826#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65827#[cfg_attr(test, assert_instr(st1))]
65828pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65829    unsafe extern "unadjusted" {
65830        #[cfg_attr(
65831            any(target_arch = "aarch64", target_arch = "arm64ec"),
65832            link_name = "llvm.aarch64.neon.st1x2.v2i32.p0i32"
65833        )]
65834        fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32);
65835    }
65836    _vst1_s32_x2(b.0, b.1, a)
65837}
65838#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65840#[doc = "## Safety"]
65841#[doc = "  * Neon instrinsic unsafe"]
65842#[inline]
65843#[target_feature(enable = "neon")]
65844#[cfg(not(target_arch = "arm"))]
65845#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65846#[cfg_attr(test, assert_instr(st1))]
65847pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65848    unsafe extern "unadjusted" {
65849        #[cfg_attr(
65850            any(target_arch = "aarch64", target_arch = "arm64ec"),
65851            link_name = "llvm.aarch64.neon.st1x2.v4i32.p0i32"
65852        )]
65853        fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32);
65854    }
65855    _vst1q_s32_x2(b.0, b.1, a)
65856}
65857#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65859#[doc = "## Safety"]
65860#[doc = "  * Neon instrinsic unsafe"]
65861#[inline]
65862#[target_feature(enable = "neon")]
65863#[cfg(not(target_arch = "arm"))]
65864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65865#[cfg_attr(test, assert_instr(st1))]
65866pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65867    unsafe extern "unadjusted" {
65868        #[cfg_attr(
65869            any(target_arch = "aarch64", target_arch = "arm64ec"),
65870            link_name = "llvm.aarch64.neon.st1x2.v1i64.p0i64"
65871        )]
65872        fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64);
65873    }
65874    _vst1_s64_x2(b.0, b.1, a)
65875}
65876#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65878#[doc = "## Safety"]
65879#[doc = "  * Neon instrinsic unsafe"]
65880#[inline]
65881#[target_feature(enable = "neon")]
65882#[cfg(not(target_arch = "arm"))]
65883#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65884#[cfg_attr(test, assert_instr(st1))]
65885pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65886    unsafe extern "unadjusted" {
65887        #[cfg_attr(
65888            any(target_arch = "aarch64", target_arch = "arm64ec"),
65889            link_name = "llvm.aarch64.neon.st1x2.v2i64.p0i64"
65890        )]
65891        fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64);
65892    }
65893    _vst1q_s64_x2(b.0, b.1, a)
65894}
65895#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65897#[doc = "## Safety"]
65898#[doc = "  * Neon instrinsic unsafe"]
65899#[inline]
65900#[target_feature(enable = "neon,v7")]
65901#[cfg(target_arch = "arm")]
65902#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65903#[cfg_attr(test, assert_instr(vst1))]
65904pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65905    unsafe extern "unadjusted" {
65906        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i8.p0")]
65907        fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t);
65908    }
65909    _vst1_s8_x2(a, b.0, b.1)
65910}
65911#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65913#[doc = "## Safety"]
65914#[doc = "  * Neon instrinsic unsafe"]
65915#[inline]
65916#[target_feature(enable = "neon,v7")]
65917#[cfg(target_arch = "arm")]
65918#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65919#[cfg_attr(test, assert_instr(vst1))]
65920pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65921    unsafe extern "unadjusted" {
65922        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v16i8.p0")]
65923        fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t);
65924    }
65925    _vst1q_s8_x2(a, b.0, b.1)
65926}
65927#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65929#[doc = "## Safety"]
65930#[doc = "  * Neon instrinsic unsafe"]
65931#[inline]
65932#[target_feature(enable = "neon,v7")]
65933#[cfg(target_arch = "arm")]
65934#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65935#[cfg_attr(test, assert_instr(vst1))]
65936pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65937    unsafe extern "unadjusted" {
65938        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i16.p0")]
65939        fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t);
65940    }
65941    _vst1_s16_x2(a, b.0, b.1)
65942}
65943#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65945#[doc = "## Safety"]
65946#[doc = "  * Neon instrinsic unsafe"]
65947#[inline]
65948#[target_feature(enable = "neon,v7")]
65949#[cfg(target_arch = "arm")]
65950#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65951#[cfg_attr(test, assert_instr(vst1))]
65952pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65953    unsafe extern "unadjusted" {
65954        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i16.p0")]
65955        fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t);
65956    }
65957    _vst1q_s16_x2(a, b.0, b.1)
65958}
65959#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65961#[doc = "## Safety"]
65962#[doc = "  * Neon instrinsic unsafe"]
65963#[inline]
65964#[target_feature(enable = "neon,v7")]
65965#[cfg(target_arch = "arm")]
65966#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65967#[cfg_attr(test, assert_instr(vst1))]
65968pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65969    unsafe extern "unadjusted" {
65970        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i32.p0")]
65971        fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t);
65972    }
65973    _vst1_s32_x2(a, b.0, b.1)
65974}
65975#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65977#[doc = "## Safety"]
65978#[doc = "  * Neon instrinsic unsafe"]
65979#[inline]
65980#[target_feature(enable = "neon,v7")]
65981#[cfg(target_arch = "arm")]
65982#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65983#[cfg_attr(test, assert_instr(vst1))]
65984pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65985    unsafe extern "unadjusted" {
65986        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i32.p0")]
65987        fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t);
65988    }
65989    _vst1q_s32_x2(a, b.0, b.1)
65990}
65991#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65993#[doc = "## Safety"]
65994#[doc = "  * Neon instrinsic unsafe"]
65995#[inline]
65996#[target_feature(enable = "neon,v7")]
65997#[cfg(target_arch = "arm")]
65998#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65999#[cfg_attr(test, assert_instr(vst1))]
66000pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
66001    unsafe extern "unadjusted" {
66002        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v1i64.p0")]
66003        fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t);
66004    }
66005    _vst1_s64_x2(a, b.0, b.1)
66006}
66007#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
66009#[doc = "## Safety"]
66010#[doc = "  * Neon instrinsic unsafe"]
66011#[inline]
66012#[target_feature(enable = "neon,v7")]
66013#[cfg(target_arch = "arm")]
66014#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66015#[cfg_attr(test, assert_instr(vst1))]
66016pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
66017    unsafe extern "unadjusted" {
66018        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i64.p0")]
66019        fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t);
66020    }
66021    _vst1q_s64_x2(a, b.0, b.1)
66022}
66023#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
66025#[doc = "## Safety"]
66026#[doc = "  * Neon instrinsic unsafe"]
66027#[inline]
66028#[target_feature(enable = "neon")]
66029#[cfg(not(target_arch = "arm"))]
66030#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66031#[cfg_attr(test, assert_instr(st1))]
66032pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
66033    unsafe extern "unadjusted" {
66034        #[cfg_attr(
66035            any(target_arch = "aarch64", target_arch = "arm64ec"),
66036            link_name = "llvm.aarch64.neon.st1x3.v8i8.p0i8"
66037        )]
66038        fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
66039    }
66040    _vst1_s8_x3(b.0, b.1, b.2, a)
66041}
66042#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
66044#[doc = "## Safety"]
66045#[doc = "  * Neon instrinsic unsafe"]
66046#[inline]
66047#[target_feature(enable = "neon")]
66048#[cfg(not(target_arch = "arm"))]
66049#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66050#[cfg_attr(test, assert_instr(st1))]
66051pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
66052    unsafe extern "unadjusted" {
66053        #[cfg_attr(
66054            any(target_arch = "aarch64", target_arch = "arm64ec"),
66055            link_name = "llvm.aarch64.neon.st1x3.v16i8.p0i8"
66056        )]
66057        fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
66058    }
66059    _vst1q_s8_x3(b.0, b.1, b.2, a)
66060}
66061#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
66063#[doc = "## Safety"]
66064#[doc = "  * Neon instrinsic unsafe"]
66065#[inline]
66066#[target_feature(enable = "neon")]
66067#[cfg(not(target_arch = "arm"))]
66068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66069#[cfg_attr(test, assert_instr(st1))]
66070pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66071    unsafe extern "unadjusted" {
66072        #[cfg_attr(
66073            any(target_arch = "aarch64", target_arch = "arm64ec"),
66074            link_name = "llvm.aarch64.neon.st1x3.v4i16.p0i16"
66075        )]
66076        fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16);
66077    }
66078    _vst1_s16_x3(b.0, b.1, b.2, a)
66079}
66080#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66082#[doc = "## Safety"]
66083#[doc = "  * Neon instrinsic unsafe"]
66084#[inline]
66085#[target_feature(enable = "neon")]
66086#[cfg(not(target_arch = "arm"))]
66087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66088#[cfg_attr(test, assert_instr(st1))]
66089pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66090    unsafe extern "unadjusted" {
66091        #[cfg_attr(
66092            any(target_arch = "aarch64", target_arch = "arm64ec"),
66093            link_name = "llvm.aarch64.neon.st1x3.v8i16.p0i16"
66094        )]
66095        fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16);
66096    }
66097    _vst1q_s16_x3(b.0, b.1, b.2, a)
66098}
66099#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66101#[doc = "## Safety"]
66102#[doc = "  * Neon instrinsic unsafe"]
66103#[inline]
66104#[target_feature(enable = "neon")]
66105#[cfg(not(target_arch = "arm"))]
66106#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66107#[cfg_attr(test, assert_instr(st1))]
66108pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66109    unsafe extern "unadjusted" {
66110        #[cfg_attr(
66111            any(target_arch = "aarch64", target_arch = "arm64ec"),
66112            link_name = "llvm.aarch64.neon.st1x3.v2i32.p0i32"
66113        )]
66114        fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32);
66115    }
66116    _vst1_s32_x3(b.0, b.1, b.2, a)
66117}
66118#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66120#[doc = "## Safety"]
66121#[doc = "  * Neon instrinsic unsafe"]
66122#[inline]
66123#[target_feature(enable = "neon")]
66124#[cfg(not(target_arch = "arm"))]
66125#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66126#[cfg_attr(test, assert_instr(st1))]
66127pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66128    unsafe extern "unadjusted" {
66129        #[cfg_attr(
66130            any(target_arch = "aarch64", target_arch = "arm64ec"),
66131            link_name = "llvm.aarch64.neon.st1x3.v4i32.p0i32"
66132        )]
66133        fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32);
66134    }
66135    _vst1q_s32_x3(b.0, b.1, b.2, a)
66136}
66137#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66139#[doc = "## Safety"]
66140#[doc = "  * Neon instrinsic unsafe"]
66141#[inline]
66142#[target_feature(enable = "neon")]
66143#[cfg(not(target_arch = "arm"))]
66144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66145#[cfg_attr(test, assert_instr(st1))]
66146pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66147    unsafe extern "unadjusted" {
66148        #[cfg_attr(
66149            any(target_arch = "aarch64", target_arch = "arm64ec"),
66150            link_name = "llvm.aarch64.neon.st1x3.v1i64.p0i64"
66151        )]
66152        fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64);
66153    }
66154    _vst1_s64_x3(b.0, b.1, b.2, a)
66155}
66156#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66158#[doc = "## Safety"]
66159#[doc = "  * Neon instrinsic unsafe"]
66160#[inline]
66161#[target_feature(enable = "neon")]
66162#[cfg(not(target_arch = "arm"))]
66163#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66164#[cfg_attr(test, assert_instr(st1))]
66165pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66166    unsafe extern "unadjusted" {
66167        #[cfg_attr(
66168            any(target_arch = "aarch64", target_arch = "arm64ec"),
66169            link_name = "llvm.aarch64.neon.st1x3.v2i64.p0i64"
66170        )]
66171        fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64);
66172    }
66173    _vst1q_s64_x3(b.0, b.1, b.2, a)
66174}
66175#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
66177#[doc = "## Safety"]
66178#[doc = "  * Neon instrinsic unsafe"]
66179#[inline]
66180#[target_feature(enable = "neon,v7")]
66181#[cfg(target_arch = "arm")]
66182#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66183#[cfg_attr(test, assert_instr(vst1))]
66184pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
66185    unsafe extern "unadjusted" {
66186        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v8i8.p0")]
66187        fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t);
66188    }
66189    _vst1_s8_x3(a, b.0, b.1, b.2)
66190}
66191#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
66193#[doc = "## Safety"]
66194#[doc = "  * Neon instrinsic unsafe"]
66195#[inline]
66196#[target_feature(enable = "neon,v7")]
66197#[cfg(target_arch = "arm")]
66198#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66199#[cfg_attr(test, assert_instr(vst1))]
66200pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
66201    unsafe extern "unadjusted" {
66202        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v16i8.p0")]
66203        fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t);
66204    }
66205    _vst1q_s8_x3(a, b.0, b.1, b.2)
66206}
66207#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
66209#[doc = "## Safety"]
66210#[doc = "  * Neon instrinsic unsafe"]
66211#[inline]
66212#[target_feature(enable = "neon,v7")]
66213#[cfg(target_arch = "arm")]
66214#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66215#[cfg_attr(test, assert_instr(vst1))]
66216pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66217    unsafe extern "unadjusted" {
66218        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v4i16.p0")]
66219        fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t);
66220    }
66221    _vst1_s16_x3(a, b.0, b.1, b.2)
66222}
66223#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66225#[doc = "## Safety"]
66226#[doc = "  * Neon instrinsic unsafe"]
66227#[inline]
66228#[target_feature(enable = "neon,v7")]
66229#[cfg(target_arch = "arm")]
66230#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66231#[cfg_attr(test, assert_instr(vst1))]
66232pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66233    unsafe extern "unadjusted" {
66234        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v8i16.p0")]
66235        fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t);
66236    }
66237    _vst1q_s16_x3(a, b.0, b.1, b.2)
66238}
66239#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66241#[doc = "## Safety"]
66242#[doc = "  * Neon instrinsic unsafe"]
66243#[inline]
66244#[target_feature(enable = "neon,v7")]
66245#[cfg(target_arch = "arm")]
66246#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66247#[cfg_attr(test, assert_instr(vst1))]
66248pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66249    unsafe extern "unadjusted" {
66250        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v2i32.p0")]
66251        fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t);
66252    }
66253    _vst1_s32_x3(a, b.0, b.1, b.2)
66254}
66255#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66257#[doc = "## Safety"]
66258#[doc = "  * Neon instrinsic unsafe"]
66259#[inline]
66260#[target_feature(enable = "neon,v7")]
66261#[cfg(target_arch = "arm")]
66262#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66263#[cfg_attr(test, assert_instr(vst1))]
66264pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66265    unsafe extern "unadjusted" {
66266        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v4i32.p0")]
66267        fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t);
66268    }
66269    _vst1q_s32_x3(a, b.0, b.1, b.2)
66270}
66271#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66273#[doc = "## Safety"]
66274#[doc = "  * Neon instrinsic unsafe"]
66275#[inline]
66276#[target_feature(enable = "neon,v7")]
66277#[cfg(target_arch = "arm")]
66278#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66279#[cfg_attr(test, assert_instr(vst1))]
66280pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66281    unsafe extern "unadjusted" {
66282        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v1i64.p0")]
66283        fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t);
66284    }
66285    _vst1_s64_x3(a, b.0, b.1, b.2)
66286}
66287#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66289#[doc = "## Safety"]
66290#[doc = "  * Neon instrinsic unsafe"]
66291#[inline]
66292#[target_feature(enable = "neon,v7")]
66293#[cfg(target_arch = "arm")]
66294#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66295#[cfg_attr(test, assert_instr(vst1))]
66296pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66297    unsafe extern "unadjusted" {
66298        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v2i64.p0")]
66299        fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t);
66300    }
66301    _vst1q_s64_x3(a, b.0, b.1, b.2)
66302}
66303#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66305#[doc = "## Safety"]
66306#[doc = "  * Neon instrinsic unsafe"]
66307#[inline]
66308#[target_feature(enable = "neon")]
66309#[cfg(not(target_arch = "arm"))]
66310#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66311#[cfg_attr(test, assert_instr(st1))]
66312pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66313    unsafe extern "unadjusted" {
66314        #[cfg_attr(
66315            any(target_arch = "aarch64", target_arch = "arm64ec"),
66316            link_name = "llvm.aarch64.neon.st1x4.v8i8.p0i8"
66317        )]
66318        fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
66319    }
66320    _vst1_s8_x4(b.0, b.1, b.2, b.3, a)
66321}
66322#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66324#[doc = "## Safety"]
66325#[doc = "  * Neon instrinsic unsafe"]
66326#[inline]
66327#[target_feature(enable = "neon")]
66328#[cfg(not(target_arch = "arm"))]
66329#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66330#[cfg_attr(test, assert_instr(st1))]
66331pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66332    unsafe extern "unadjusted" {
66333        #[cfg_attr(
66334            any(target_arch = "aarch64", target_arch = "arm64ec"),
66335            link_name = "llvm.aarch64.neon.st1x4.v16i8.p0i8"
66336        )]
66337        fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
66338    }
66339    _vst1q_s8_x4(b.0, b.1, b.2, b.3, a)
66340}
66341#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66343#[doc = "## Safety"]
66344#[doc = "  * Neon instrinsic unsafe"]
66345#[inline]
66346#[target_feature(enable = "neon")]
66347#[cfg(not(target_arch = "arm"))]
66348#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66349#[cfg_attr(test, assert_instr(st1))]
66350pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66351    unsafe extern "unadjusted" {
66352        #[cfg_attr(
66353            any(target_arch = "aarch64", target_arch = "arm64ec"),
66354            link_name = "llvm.aarch64.neon.st1x4.v4i16.p0i16"
66355        )]
66356        fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16);
66357    }
66358    _vst1_s16_x4(b.0, b.1, b.2, b.3, a)
66359}
66360#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66362#[doc = "## Safety"]
66363#[doc = "  * Neon instrinsic unsafe"]
66364#[inline]
66365#[target_feature(enable = "neon")]
66366#[cfg(not(target_arch = "arm"))]
66367#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66368#[cfg_attr(test, assert_instr(st1))]
66369pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66370    unsafe extern "unadjusted" {
66371        #[cfg_attr(
66372            any(target_arch = "aarch64", target_arch = "arm64ec"),
66373            link_name = "llvm.aarch64.neon.st1x4.v8i16.p0i16"
66374        )]
66375        fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16);
66376    }
66377    _vst1q_s16_x4(b.0, b.1, b.2, b.3, a)
66378}
66379#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66381#[doc = "## Safety"]
66382#[doc = "  * Neon instrinsic unsafe"]
66383#[inline]
66384#[target_feature(enable = "neon")]
66385#[cfg(not(target_arch = "arm"))]
66386#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66387#[cfg_attr(test, assert_instr(st1))]
66388pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66389    unsafe extern "unadjusted" {
66390        #[cfg_attr(
66391            any(target_arch = "aarch64", target_arch = "arm64ec"),
66392            link_name = "llvm.aarch64.neon.st1x4.v2i32.p0i32"
66393        )]
66394        fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32);
66395    }
66396    _vst1_s32_x4(b.0, b.1, b.2, b.3, a)
66397}
66398#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66400#[doc = "## Safety"]
66401#[doc = "  * Neon instrinsic unsafe"]
66402#[inline]
66403#[target_feature(enable = "neon")]
66404#[cfg(not(target_arch = "arm"))]
66405#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66406#[cfg_attr(test, assert_instr(st1))]
66407pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66408    unsafe extern "unadjusted" {
66409        #[cfg_attr(
66410            any(target_arch = "aarch64", target_arch = "arm64ec"),
66411            link_name = "llvm.aarch64.neon.st1x4.v4i32.p0i32"
66412        )]
66413        fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32);
66414    }
66415    _vst1q_s32_x4(b.0, b.1, b.2, b.3, a)
66416}
66417#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66419#[doc = "## Safety"]
66420#[doc = "  * Neon instrinsic unsafe"]
66421#[inline]
66422#[target_feature(enable = "neon")]
66423#[cfg(not(target_arch = "arm"))]
66424#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66425#[cfg_attr(test, assert_instr(st1))]
66426pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66427    unsafe extern "unadjusted" {
66428        #[cfg_attr(
66429            any(target_arch = "aarch64", target_arch = "arm64ec"),
66430            link_name = "llvm.aarch64.neon.st1x4.v1i64.p0i64"
66431        )]
66432        fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64);
66433    }
66434    _vst1_s64_x4(b.0, b.1, b.2, b.3, a)
66435}
66436#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66438#[doc = "## Safety"]
66439#[doc = "  * Neon instrinsic unsafe"]
66440#[inline]
66441#[target_feature(enable = "neon")]
66442#[cfg(not(target_arch = "arm"))]
66443#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66444#[cfg_attr(test, assert_instr(st1))]
66445pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66446    unsafe extern "unadjusted" {
66447        #[cfg_attr(
66448            any(target_arch = "aarch64", target_arch = "arm64ec"),
66449            link_name = "llvm.aarch64.neon.st1x4.v2i64.p0i64"
66450        )]
66451        fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64);
66452    }
66453    _vst1q_s64_x4(b.0, b.1, b.2, b.3, a)
66454}
66455#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66457#[doc = "## Safety"]
66458#[doc = "  * Neon instrinsic unsafe"]
66459#[inline]
66460#[cfg(target_arch = "arm")]
66461#[target_feature(enable = "neon,v7")]
66462#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66463#[cfg_attr(test, assert_instr(vst1))]
66464pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66465    unsafe extern "unadjusted" {
66466        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v8i8.p0")]
66467        fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t);
66468    }
66469    _vst1_s8_x4(a, b.0, b.1, b.2, b.3)
66470}
66471#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66473#[doc = "## Safety"]
66474#[doc = "  * Neon instrinsic unsafe"]
66475#[inline]
66476#[cfg(target_arch = "arm")]
66477#[target_feature(enable = "neon,v7")]
66478#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66479#[cfg_attr(test, assert_instr(vst1))]
66480pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66481    unsafe extern "unadjusted" {
66482        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v16i8.p0")]
66483        fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t);
66484    }
66485    _vst1q_s8_x4(a, b.0, b.1, b.2, b.3)
66486}
66487#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66489#[doc = "## Safety"]
66490#[doc = "  * Neon instrinsic unsafe"]
66491#[inline]
66492#[cfg(target_arch = "arm")]
66493#[target_feature(enable = "neon,v7")]
66494#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66495#[cfg_attr(test, assert_instr(vst1))]
66496pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66497    unsafe extern "unadjusted" {
66498        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v4i16.p0")]
66499        fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t);
66500    }
66501    _vst1_s16_x4(a, b.0, b.1, b.2, b.3)
66502}
66503#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66505#[doc = "## Safety"]
66506#[doc = "  * Neon instrinsic unsafe"]
66507#[inline]
66508#[cfg(target_arch = "arm")]
66509#[target_feature(enable = "neon,v7")]
66510#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66511#[cfg_attr(test, assert_instr(vst1))]
66512pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66513    unsafe extern "unadjusted" {
66514        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v8i16.p0")]
66515        fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t);
66516    }
66517    _vst1q_s16_x4(a, b.0, b.1, b.2, b.3)
66518}
66519#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66521#[doc = "## Safety"]
66522#[doc = "  * Neon instrinsic unsafe"]
66523#[inline]
66524#[cfg(target_arch = "arm")]
66525#[target_feature(enable = "neon,v7")]
66526#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66527#[cfg_attr(test, assert_instr(vst1))]
66528pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66529    unsafe extern "unadjusted" {
66530        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v2i32.p0")]
66531        fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t);
66532    }
66533    _vst1_s32_x4(a, b.0, b.1, b.2, b.3)
66534}
66535#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66537#[doc = "## Safety"]
66538#[doc = "  * Neon instrinsic unsafe"]
66539#[inline]
66540#[cfg(target_arch = "arm")]
66541#[target_feature(enable = "neon,v7")]
66542#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66543#[cfg_attr(test, assert_instr(vst1))]
66544pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66545    unsafe extern "unadjusted" {
66546        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v4i32.p0")]
66547        fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t);
66548    }
66549    _vst1q_s32_x4(a, b.0, b.1, b.2, b.3)
66550}
66551#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66553#[doc = "## Safety"]
66554#[doc = "  * Neon instrinsic unsafe"]
66555#[inline]
66556#[cfg(target_arch = "arm")]
66557#[target_feature(enable = "neon,v7")]
66558#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66559#[cfg_attr(test, assert_instr(vst1))]
66560pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66561    unsafe extern "unadjusted" {
66562        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v1i64.p0")]
66563        fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t);
66564    }
66565    _vst1_s64_x4(a, b.0, b.1, b.2, b.3)
66566}
66567#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66569#[doc = "## Safety"]
66570#[doc = "  * Neon instrinsic unsafe"]
66571#[inline]
66572#[cfg(target_arch = "arm")]
66573#[target_feature(enable = "neon,v7")]
66574#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66575#[cfg_attr(test, assert_instr(vst1))]
66576pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66577    unsafe extern "unadjusted" {
66578        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v2i64.p0")]
66579        fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t);
66580    }
66581    _vst1q_s64_x4(a, b.0, b.1, b.2, b.3)
66582}
66583#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
66585#[doc = "## Safety"]
66586#[doc = "  * Neon instrinsic unsafe"]
66587#[inline]
66588#[target_feature(enable = "neon")]
66589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66591#[cfg_attr(
66592    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66593    assert_instr(st1)
66594)]
66595#[cfg_attr(
66596    not(target_arch = "arm"),
66597    stable(feature = "neon_intrinsics", since = "1.59.0")
66598)]
66599#[cfg_attr(
66600    target_arch = "arm",
66601    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66602)]
66603pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
66604    vst1_s8_x2(transmute(a), transmute(b))
66605}
66606#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
66608#[doc = "## Safety"]
66609#[doc = "  * Neon instrinsic unsafe"]
66610#[inline]
66611#[target_feature(enable = "neon")]
66612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66614#[cfg_attr(
66615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66616    assert_instr(st1)
66617)]
66618#[cfg_attr(
66619    not(target_arch = "arm"),
66620    stable(feature = "neon_intrinsics", since = "1.59.0")
66621)]
66622#[cfg_attr(
66623    target_arch = "arm",
66624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66625)]
66626pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
66627    vst1_s8_x3(transmute(a), transmute(b))
66628}
66629#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
66631#[doc = "## Safety"]
66632#[doc = "  * Neon instrinsic unsafe"]
66633#[inline]
66634#[target_feature(enable = "neon")]
66635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66637#[cfg_attr(
66638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66639    assert_instr(st1)
66640)]
66641#[cfg_attr(
66642    not(target_arch = "arm"),
66643    stable(feature = "neon_intrinsics", since = "1.59.0")
66644)]
66645#[cfg_attr(
66646    target_arch = "arm",
66647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66648)]
66649pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
66650    vst1_s8_x4(transmute(a), transmute(b))
66651}
66652#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
66654#[doc = "## Safety"]
66655#[doc = "  * Neon instrinsic unsafe"]
66656#[inline]
66657#[target_feature(enable = "neon")]
66658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66660#[cfg_attr(
66661    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66662    assert_instr(st1)
66663)]
66664#[cfg_attr(
66665    not(target_arch = "arm"),
66666    stable(feature = "neon_intrinsics", since = "1.59.0")
66667)]
66668#[cfg_attr(
66669    target_arch = "arm",
66670    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66671)]
66672pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
66673    vst1q_s8_x2(transmute(a), transmute(b))
66674}
66675#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
66677#[doc = "## Safety"]
66678#[doc = "  * Neon instrinsic unsafe"]
66679#[inline]
66680#[target_feature(enable = "neon")]
66681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66683#[cfg_attr(
66684    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66685    assert_instr(st1)
66686)]
66687#[cfg_attr(
66688    not(target_arch = "arm"),
66689    stable(feature = "neon_intrinsics", since = "1.59.0")
66690)]
66691#[cfg_attr(
66692    target_arch = "arm",
66693    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66694)]
66695pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
66696    vst1q_s8_x3(transmute(a), transmute(b))
66697}
66698#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
66700#[doc = "## Safety"]
66701#[doc = "  * Neon instrinsic unsafe"]
66702#[inline]
66703#[target_feature(enable = "neon")]
66704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66706#[cfg_attr(
66707    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66708    assert_instr(st1)
66709)]
66710#[cfg_attr(
66711    not(target_arch = "arm"),
66712    stable(feature = "neon_intrinsics", since = "1.59.0")
66713)]
66714#[cfg_attr(
66715    target_arch = "arm",
66716    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66717)]
66718pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
66719    vst1q_s8_x4(transmute(a), transmute(b))
66720}
66721#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
66723#[doc = "## Safety"]
66724#[doc = "  * Neon instrinsic unsafe"]
66725#[inline]
66726#[target_feature(enable = "neon")]
66727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66729#[cfg_attr(
66730    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66731    assert_instr(st1)
66732)]
66733#[cfg_attr(
66734    not(target_arch = "arm"),
66735    stable(feature = "neon_intrinsics", since = "1.59.0")
66736)]
66737#[cfg_attr(
66738    target_arch = "arm",
66739    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66740)]
66741pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
66742    vst1_s16_x2(transmute(a), transmute(b))
66743}
66744#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
66746#[doc = "## Safety"]
66747#[doc = "  * Neon instrinsic unsafe"]
66748#[inline]
66749#[target_feature(enable = "neon")]
66750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66752#[cfg_attr(
66753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66754    assert_instr(st1)
66755)]
66756#[cfg_attr(
66757    not(target_arch = "arm"),
66758    stable(feature = "neon_intrinsics", since = "1.59.0")
66759)]
66760#[cfg_attr(
66761    target_arch = "arm",
66762    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66763)]
66764pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
66765    vst1_s16_x3(transmute(a), transmute(b))
66766}
66767#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
66769#[doc = "## Safety"]
66770#[doc = "  * Neon instrinsic unsafe"]
66771#[inline]
66772#[target_feature(enable = "neon")]
66773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66775#[cfg_attr(
66776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66777    assert_instr(st1)
66778)]
66779#[cfg_attr(
66780    not(target_arch = "arm"),
66781    stable(feature = "neon_intrinsics", since = "1.59.0")
66782)]
66783#[cfg_attr(
66784    target_arch = "arm",
66785    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66786)]
66787pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
66788    vst1_s16_x4(transmute(a), transmute(b))
66789}
66790#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
66792#[doc = "## Safety"]
66793#[doc = "  * Neon instrinsic unsafe"]
66794#[inline]
66795#[target_feature(enable = "neon")]
66796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66798#[cfg_attr(
66799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66800    assert_instr(st1)
66801)]
66802#[cfg_attr(
66803    not(target_arch = "arm"),
66804    stable(feature = "neon_intrinsics", since = "1.59.0")
66805)]
66806#[cfg_attr(
66807    target_arch = "arm",
66808    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66809)]
66810pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
66811    vst1q_s16_x2(transmute(a), transmute(b))
66812}
66813#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
66815#[doc = "## Safety"]
66816#[doc = "  * Neon instrinsic unsafe"]
66817#[inline]
66818#[target_feature(enable = "neon")]
66819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66821#[cfg_attr(
66822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66823    assert_instr(st1)
66824)]
66825#[cfg_attr(
66826    not(target_arch = "arm"),
66827    stable(feature = "neon_intrinsics", since = "1.59.0")
66828)]
66829#[cfg_attr(
66830    target_arch = "arm",
66831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66832)]
66833pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
66834    vst1q_s16_x3(transmute(a), transmute(b))
66835}
66836#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
66838#[doc = "## Safety"]
66839#[doc = "  * Neon instrinsic unsafe"]
66840#[inline]
66841#[target_feature(enable = "neon")]
66842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66844#[cfg_attr(
66845    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66846    assert_instr(st1)
66847)]
66848#[cfg_attr(
66849    not(target_arch = "arm"),
66850    stable(feature = "neon_intrinsics", since = "1.59.0")
66851)]
66852#[cfg_attr(
66853    target_arch = "arm",
66854    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66855)]
66856pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
66857    vst1q_s16_x4(transmute(a), transmute(b))
66858}
66859#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
66861#[doc = "## Safety"]
66862#[doc = "  * Neon instrinsic unsafe"]
66863#[inline]
66864#[target_feature(enable = "neon")]
66865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66867#[cfg_attr(
66868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66869    assert_instr(st1)
66870)]
66871#[cfg_attr(
66872    not(target_arch = "arm"),
66873    stable(feature = "neon_intrinsics", since = "1.59.0")
66874)]
66875#[cfg_attr(
66876    target_arch = "arm",
66877    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66878)]
66879pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
66880    vst1_s32_x2(transmute(a), transmute(b))
66881}
66882#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
66884#[doc = "## Safety"]
66885#[doc = "  * Neon instrinsic unsafe"]
66886#[inline]
66887#[target_feature(enable = "neon")]
66888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66890#[cfg_attr(
66891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66892    assert_instr(st1)
66893)]
66894#[cfg_attr(
66895    not(target_arch = "arm"),
66896    stable(feature = "neon_intrinsics", since = "1.59.0")
66897)]
66898#[cfg_attr(
66899    target_arch = "arm",
66900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66901)]
66902pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
66903    vst1_s32_x3(transmute(a), transmute(b))
66904}
66905#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
66907#[doc = "## Safety"]
66908#[doc = "  * Neon instrinsic unsafe"]
66909#[inline]
66910#[target_feature(enable = "neon")]
66911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66913#[cfg_attr(
66914    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66915    assert_instr(st1)
66916)]
66917#[cfg_attr(
66918    not(target_arch = "arm"),
66919    stable(feature = "neon_intrinsics", since = "1.59.0")
66920)]
66921#[cfg_attr(
66922    target_arch = "arm",
66923    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66924)]
66925pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
66926    vst1_s32_x4(transmute(a), transmute(b))
66927}
66928#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
66930#[doc = "## Safety"]
66931#[doc = "  * Neon instrinsic unsafe"]
66932#[inline]
66933#[target_feature(enable = "neon")]
66934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66936#[cfg_attr(
66937    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66938    assert_instr(st1)
66939)]
66940#[cfg_attr(
66941    not(target_arch = "arm"),
66942    stable(feature = "neon_intrinsics", since = "1.59.0")
66943)]
66944#[cfg_attr(
66945    target_arch = "arm",
66946    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66947)]
66948pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
66949    vst1q_s32_x2(transmute(a), transmute(b))
66950}
66951#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
66953#[doc = "## Safety"]
66954#[doc = "  * Neon instrinsic unsafe"]
66955#[inline]
66956#[target_feature(enable = "neon")]
66957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66959#[cfg_attr(
66960    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66961    assert_instr(st1)
66962)]
66963#[cfg_attr(
66964    not(target_arch = "arm"),
66965    stable(feature = "neon_intrinsics", since = "1.59.0")
66966)]
66967#[cfg_attr(
66968    target_arch = "arm",
66969    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66970)]
66971pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
66972    vst1q_s32_x3(transmute(a), transmute(b))
66973}
66974#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
66976#[doc = "## Safety"]
66977#[doc = "  * Neon instrinsic unsafe"]
66978#[inline]
66979#[target_feature(enable = "neon")]
66980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66982#[cfg_attr(
66983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66984    assert_instr(st1)
66985)]
66986#[cfg_attr(
66987    not(target_arch = "arm"),
66988    stable(feature = "neon_intrinsics", since = "1.59.0")
66989)]
66990#[cfg_attr(
66991    target_arch = "arm",
66992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66993)]
66994pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
66995    vst1q_s32_x4(transmute(a), transmute(b))
66996}
66997#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
66999#[doc = "## Safety"]
67000#[doc = "  * Neon instrinsic unsafe"]
67001#[inline]
67002#[target_feature(enable = "neon")]
67003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67005#[cfg_attr(
67006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67007    assert_instr(st1)
67008)]
67009#[cfg_attr(
67010    not(target_arch = "arm"),
67011    stable(feature = "neon_intrinsics", since = "1.59.0")
67012)]
67013#[cfg_attr(
67014    target_arch = "arm",
67015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67016)]
67017pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
67018    vst1_s64_x2(transmute(a), transmute(b))
67019}
67020#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
67022#[doc = "## Safety"]
67023#[doc = "  * Neon instrinsic unsafe"]
67024#[inline]
67025#[target_feature(enable = "neon")]
67026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67028#[cfg_attr(
67029    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67030    assert_instr(st1)
67031)]
67032#[cfg_attr(
67033    not(target_arch = "arm"),
67034    stable(feature = "neon_intrinsics", since = "1.59.0")
67035)]
67036#[cfg_attr(
67037    target_arch = "arm",
67038    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67039)]
67040pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
67041    vst1_s64_x3(transmute(a), transmute(b))
67042}
67043#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
67045#[doc = "## Safety"]
67046#[doc = "  * Neon instrinsic unsafe"]
67047#[inline]
67048#[target_feature(enable = "neon")]
67049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67051#[cfg_attr(
67052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67053    assert_instr(st1)
67054)]
67055#[cfg_attr(
67056    not(target_arch = "arm"),
67057    stable(feature = "neon_intrinsics", since = "1.59.0")
67058)]
67059#[cfg_attr(
67060    target_arch = "arm",
67061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67062)]
67063pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
67064    vst1_s64_x4(transmute(a), transmute(b))
67065}
67066#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
67068#[doc = "## Safety"]
67069#[doc = "  * Neon instrinsic unsafe"]
67070#[inline]
67071#[target_feature(enable = "neon")]
67072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67074#[cfg_attr(
67075    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67076    assert_instr(st1)
67077)]
67078#[cfg_attr(
67079    not(target_arch = "arm"),
67080    stable(feature = "neon_intrinsics", since = "1.59.0")
67081)]
67082#[cfg_attr(
67083    target_arch = "arm",
67084    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67085)]
67086pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
67087    vst1q_s64_x2(transmute(a), transmute(b))
67088}
67089#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
67091#[doc = "## Safety"]
67092#[doc = "  * Neon instrinsic unsafe"]
67093#[inline]
67094#[target_feature(enable = "neon")]
67095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67097#[cfg_attr(
67098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67099    assert_instr(st1)
67100)]
67101#[cfg_attr(
67102    not(target_arch = "arm"),
67103    stable(feature = "neon_intrinsics", since = "1.59.0")
67104)]
67105#[cfg_attr(
67106    target_arch = "arm",
67107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67108)]
67109pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
67110    vst1q_s64_x3(transmute(a), transmute(b))
67111}
67112#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
67114#[doc = "## Safety"]
67115#[doc = "  * Neon instrinsic unsafe"]
67116#[inline]
67117#[target_feature(enable = "neon")]
67118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67120#[cfg_attr(
67121    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67122    assert_instr(st1)
67123)]
67124#[cfg_attr(
67125    not(target_arch = "arm"),
67126    stable(feature = "neon_intrinsics", since = "1.59.0")
67127)]
67128#[cfg_attr(
67129    target_arch = "arm",
67130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67131)]
67132pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
67133    vst1q_s64_x4(transmute(a), transmute(b))
67134}
67135#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
67137#[doc = "## Safety"]
67138#[doc = "  * Neon instrinsic unsafe"]
67139#[inline]
67140#[target_feature(enable = "neon")]
67141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67143#[cfg_attr(
67144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67145    assert_instr(st1)
67146)]
67147#[cfg_attr(
67148    not(target_arch = "arm"),
67149    stable(feature = "neon_intrinsics", since = "1.59.0")
67150)]
67151#[cfg_attr(
67152    target_arch = "arm",
67153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67154)]
67155pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
67156    vst1_s8_x2(transmute(a), transmute(b))
67157}
67158#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
67160#[doc = "## Safety"]
67161#[doc = "  * Neon instrinsic unsafe"]
67162#[inline]
67163#[target_feature(enable = "neon")]
67164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67166#[cfg_attr(
67167    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67168    assert_instr(st1)
67169)]
67170#[cfg_attr(
67171    not(target_arch = "arm"),
67172    stable(feature = "neon_intrinsics", since = "1.59.0")
67173)]
67174#[cfg_attr(
67175    target_arch = "arm",
67176    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67177)]
67178pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
67179    vst1_s8_x3(transmute(a), transmute(b))
67180}
67181#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
67183#[doc = "## Safety"]
67184#[doc = "  * Neon instrinsic unsafe"]
67185#[inline]
67186#[target_feature(enable = "neon")]
67187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67189#[cfg_attr(
67190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67191    assert_instr(st1)
67192)]
67193#[cfg_attr(
67194    not(target_arch = "arm"),
67195    stable(feature = "neon_intrinsics", since = "1.59.0")
67196)]
67197#[cfg_attr(
67198    target_arch = "arm",
67199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67200)]
67201pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
67202    vst1_s8_x4(transmute(a), transmute(b))
67203}
67204#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
67206#[doc = "## Safety"]
67207#[doc = "  * Neon instrinsic unsafe"]
67208#[inline]
67209#[target_feature(enable = "neon")]
67210#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67212#[cfg_attr(
67213    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67214    assert_instr(st1)
67215)]
67216#[cfg_attr(
67217    not(target_arch = "arm"),
67218    stable(feature = "neon_intrinsics", since = "1.59.0")
67219)]
67220#[cfg_attr(
67221    target_arch = "arm",
67222    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67223)]
67224pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
67225    vst1q_s8_x2(transmute(a), transmute(b))
67226}
67227#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
67229#[doc = "## Safety"]
67230#[doc = "  * Neon instrinsic unsafe"]
67231#[inline]
67232#[target_feature(enable = "neon")]
67233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67235#[cfg_attr(
67236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67237    assert_instr(st1)
67238)]
67239#[cfg_attr(
67240    not(target_arch = "arm"),
67241    stable(feature = "neon_intrinsics", since = "1.59.0")
67242)]
67243#[cfg_attr(
67244    target_arch = "arm",
67245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67246)]
67247pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
67248    vst1q_s8_x3(transmute(a), transmute(b))
67249}
67250#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
67252#[doc = "## Safety"]
67253#[doc = "  * Neon instrinsic unsafe"]
67254#[inline]
67255#[target_feature(enable = "neon")]
67256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67258#[cfg_attr(
67259    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67260    assert_instr(st1)
67261)]
67262#[cfg_attr(
67263    not(target_arch = "arm"),
67264    stable(feature = "neon_intrinsics", since = "1.59.0")
67265)]
67266#[cfg_attr(
67267    target_arch = "arm",
67268    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67269)]
67270pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
67271    vst1q_s8_x4(transmute(a), transmute(b))
67272}
67273#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
67275#[doc = "## Safety"]
67276#[doc = "  * Neon instrinsic unsafe"]
67277#[inline]
67278#[target_feature(enable = "neon")]
67279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67281#[cfg_attr(
67282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67283    assert_instr(st1)
67284)]
67285#[cfg_attr(
67286    not(target_arch = "arm"),
67287    stable(feature = "neon_intrinsics", since = "1.59.0")
67288)]
67289#[cfg_attr(
67290    target_arch = "arm",
67291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67292)]
67293pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
67294    vst1_s16_x2(transmute(a), transmute(b))
67295}
67296#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
67298#[doc = "## Safety"]
67299#[doc = "  * Neon instrinsic unsafe"]
67300#[inline]
67301#[target_feature(enable = "neon")]
67302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67304#[cfg_attr(
67305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67306    assert_instr(st1)
67307)]
67308#[cfg_attr(
67309    not(target_arch = "arm"),
67310    stable(feature = "neon_intrinsics", since = "1.59.0")
67311)]
67312#[cfg_attr(
67313    target_arch = "arm",
67314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67315)]
67316pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
67317    vst1_s16_x3(transmute(a), transmute(b))
67318}
67319#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
67321#[doc = "## Safety"]
67322#[doc = "  * Neon instrinsic unsafe"]
67323#[inline]
67324#[target_feature(enable = "neon")]
67325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67327#[cfg_attr(
67328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67329    assert_instr(st1)
67330)]
67331#[cfg_attr(
67332    not(target_arch = "arm"),
67333    stable(feature = "neon_intrinsics", since = "1.59.0")
67334)]
67335#[cfg_attr(
67336    target_arch = "arm",
67337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67338)]
67339pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
67340    vst1_s16_x4(transmute(a), transmute(b))
67341}
67342#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
67344#[doc = "## Safety"]
67345#[doc = "  * Neon instrinsic unsafe"]
67346#[inline]
67347#[target_feature(enable = "neon")]
67348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67350#[cfg_attr(
67351    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67352    assert_instr(st1)
67353)]
67354#[cfg_attr(
67355    not(target_arch = "arm"),
67356    stable(feature = "neon_intrinsics", since = "1.59.0")
67357)]
67358#[cfg_attr(
67359    target_arch = "arm",
67360    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67361)]
67362pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
67363    vst1q_s16_x2(transmute(a), transmute(b))
67364}
67365#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
67367#[doc = "## Safety"]
67368#[doc = "  * Neon instrinsic unsafe"]
67369#[inline]
67370#[target_feature(enable = "neon")]
67371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67373#[cfg_attr(
67374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67375    assert_instr(st1)
67376)]
67377#[cfg_attr(
67378    not(target_arch = "arm"),
67379    stable(feature = "neon_intrinsics", since = "1.59.0")
67380)]
67381#[cfg_attr(
67382    target_arch = "arm",
67383    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67384)]
67385pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
67386    vst1q_s16_x3(transmute(a), transmute(b))
67387}
67388#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
67390#[doc = "## Safety"]
67391#[doc = "  * Neon instrinsic unsafe"]
67392#[inline]
67393#[target_feature(enable = "neon")]
67394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67396#[cfg_attr(
67397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67398    assert_instr(st1)
67399)]
67400#[cfg_attr(
67401    not(target_arch = "arm"),
67402    stable(feature = "neon_intrinsics", since = "1.59.0")
67403)]
67404#[cfg_attr(
67405    target_arch = "arm",
67406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67407)]
67408pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
67409    vst1q_s16_x4(transmute(a), transmute(b))
67410}
67411#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
67413#[doc = "## Safety"]
67414#[doc = "  * Neon instrinsic unsafe"]
67415#[inline]
67416#[target_feature(enable = "neon")]
67417#[cfg(target_arch = "arm")]
67418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67419#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67420#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67421unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
67422    unsafe extern "unadjusted" {
67423        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
67424        fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
67425    }
67426    _vst1_v1i64(addr, val, align)
67427}
67428#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
67430#[doc = "## Safety"]
67431#[doc = "  * Neon instrinsic unsafe"]
67432#[inline]
67433#[target_feature(enable = "neon")]
67434#[cfg(target_arch = "arm")]
67435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67436#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67437#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67438unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
67439    unsafe extern "unadjusted" {
67440        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
67441        fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
67442    }
67443    _vst1_v2f32(addr, val, align)
67444}
67445#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
67447#[doc = "## Safety"]
67448#[doc = "  * Neon instrinsic unsafe"]
67449#[inline]
67450#[target_feature(enable = "neon")]
67451#[cfg(target_arch = "arm")]
67452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67453#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67455unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
67456    unsafe extern "unadjusted" {
67457        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
67458        fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
67459    }
67460    _vst1_v2i32(addr, val, align)
67461}
67462#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
67464#[doc = "## Safety"]
67465#[doc = "  * Neon instrinsic unsafe"]
67466#[inline]
67467#[target_feature(enable = "neon")]
67468#[cfg(target_arch = "arm")]
67469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67472unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
67473    unsafe extern "unadjusted" {
67474        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
67475        fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
67476    }
67477    _vst1_v4i16(addr, val, align)
67478}
67479#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
67481#[doc = "## Safety"]
67482#[doc = "  * Neon instrinsic unsafe"]
67483#[inline]
67484#[target_feature(enable = "neon")]
67485#[cfg(target_arch = "arm")]
67486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67487#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67489unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
67490    unsafe extern "unadjusted" {
67491        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
67492        fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
67493    }
67494    _vst1_v8i8(addr, val, align)
67495}
67496#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
67498#[doc = "## Safety"]
67499#[doc = "  * Neon instrinsic unsafe"]
67500#[inline]
67501#[target_feature(enable = "neon")]
67502#[cfg(target_arch = "arm")]
67503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67505#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67506unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
67507    unsafe extern "unadjusted" {
67508        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
67509        fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
67510    }
67511    _vst1q_v16i8(addr, val, align)
67512}
67513#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
67515#[doc = "## Safety"]
67516#[doc = "  * Neon instrinsic unsafe"]
67517#[inline]
67518#[target_feature(enable = "neon")]
67519#[cfg(target_arch = "arm")]
67520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67521#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67523unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
67524    unsafe extern "unadjusted" {
67525        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
67526        fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
67527    }
67528    _vst1q_v2i64(addr, val, align)
67529}
67530#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
67532#[doc = "## Safety"]
67533#[doc = "  * Neon instrinsic unsafe"]
67534#[inline]
67535#[target_feature(enable = "neon")]
67536#[cfg(target_arch = "arm")]
67537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67538#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67540unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
67541    unsafe extern "unadjusted" {
67542        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
67543        fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
67544    }
67545    _vst1q_v4f32(addr, val, align)
67546}
67547#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
67549#[doc = "## Safety"]
67550#[doc = "  * Neon instrinsic unsafe"]
67551#[inline]
67552#[target_feature(enable = "neon")]
67553#[cfg(target_arch = "arm")]
67554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67555#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67557unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
67558    unsafe extern "unadjusted" {
67559        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
67560        fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
67561    }
67562    _vst1q_v4i32(addr, val, align)
67563}
67564#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
67566#[doc = "## Safety"]
67567#[doc = "  * Neon instrinsic unsafe"]
67568#[inline]
67569#[target_feature(enable = "neon")]
67570#[cfg(target_arch = "arm")]
67571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67572#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67574unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
67575    unsafe extern "unadjusted" {
67576        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
67577        fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
67578    }
67579    _vst1q_v8i16(addr, val, align)
67580}
67581#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
67583#[doc = "## Safety"]
67584#[doc = "  * Neon instrinsic unsafe"]
67585#[inline]
67586#[cfg(target_arch = "arm")]
67587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67588#[target_feature(enable = "neon,fp16")]
67589#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67590#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67591unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
67592    unsafe extern "unadjusted" {
67593        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f16.p0")]
67594        fn _vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32);
67595    }
67596    _vst1_v4f16(addr, val, align)
67597}
67598#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
67600#[doc = "## Safety"]
67601#[doc = "  * Neon instrinsic unsafe"]
67602#[inline]
67603#[cfg(target_arch = "arm")]
67604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67605#[target_feature(enable = "neon,fp16")]
67606#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67607#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67608unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
67609    unsafe extern "unadjusted" {
67610        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8f16.p0")]
67611        fn _vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32);
67612    }
67613    _vst1q_v8f16(addr, val, align)
67614}
67615#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
67616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
67617#[doc = "## Safety"]
67618#[doc = "  * Neon instrinsic unsafe"]
67619#[inline]
67620#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67621#[target_feature(enable = "neon,aes")]
67622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
67623#[cfg_attr(
67624    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67625    assert_instr(nop, LANE = 0)
67626)]
67627#[rustc_legacy_const_generics(2)]
67628#[cfg_attr(
67629    not(target_arch = "arm"),
67630    stable(feature = "neon_intrinsics", since = "1.59.0")
67631)]
67632#[cfg_attr(
67633    target_arch = "arm",
67634    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67635)]
67636pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
67637    static_assert_uimm_bits!(LANE, 1);
67638    *a = simd_extract!(b, LANE as u32);
67639}
67640#[doc = "Store multiple 2-element structures from two registers"]
67641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67642#[doc = "## Safety"]
67643#[doc = "  * Neon instrinsic unsafe"]
67644#[inline]
67645#[cfg(not(target_arch = "arm"))]
67646#[target_feature(enable = "neon,fp16")]
67647#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67648#[cfg_attr(test, assert_instr(st2))]
67649pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67650    unsafe extern "unadjusted" {
67651        #[cfg_attr(
67652            any(target_arch = "aarch64", target_arch = "arm64ec"),
67653            link_name = "llvm.aarch64.neon.st2.v4f16.p0i8"
67654        )]
67655        fn _vst2_f16(a: float16x4_t, b: float16x4_t, ptr: *mut i8);
67656    }
67657    _vst2_f16(b.0, b.1, a as _)
67658}
67659#[doc = "Store multiple 2-element structures from two registers"]
67660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67661#[doc = "## Safety"]
67662#[doc = "  * Neon instrinsic unsafe"]
67663#[inline]
67664#[cfg(not(target_arch = "arm"))]
67665#[target_feature(enable = "neon,fp16")]
67666#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67667#[cfg_attr(test, assert_instr(st2))]
67668pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67669    unsafe extern "unadjusted" {
67670        #[cfg_attr(
67671            any(target_arch = "aarch64", target_arch = "arm64ec"),
67672            link_name = "llvm.aarch64.neon.st2.v8f16.p0i8"
67673        )]
67674        fn _vst2q_f16(a: float16x8_t, b: float16x8_t, ptr: *mut i8);
67675    }
67676    _vst2q_f16(b.0, b.1, a as _)
67677}
67678#[doc = "Store multiple 2-element structures from two registers"]
67679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67680#[doc = "## Safety"]
67681#[doc = "  * Neon instrinsic unsafe"]
67682#[inline]
67683#[cfg(target_arch = "arm")]
67684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67685#[target_feature(enable = "neon,fp16")]
67686#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67687#[cfg_attr(test, assert_instr(vst2))]
67688pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67689    unsafe extern "unadjusted" {
67690        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4f16")]
67691        fn _vst2_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, size: i32);
67692    }
67693    _vst2_f16(a as _, b.0, b.1, 2)
67694}
67695#[doc = "Store multiple 2-element structures from two registers"]
67696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67697#[doc = "## Safety"]
67698#[doc = "  * Neon instrinsic unsafe"]
67699#[inline]
67700#[cfg(target_arch = "arm")]
67701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67702#[target_feature(enable = "neon,fp16")]
67703#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67704#[cfg_attr(test, assert_instr(vst2))]
67705pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67706    unsafe extern "unadjusted" {
67707        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8f16")]
67708        fn _vst2q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, size: i32);
67709    }
67710    _vst2q_f16(a as _, b.0, b.1, 2)
67711}
67712#[doc = "Store multiple 2-element structures from two registers"]
67713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67714#[doc = "## Safety"]
67715#[doc = "  * Neon instrinsic unsafe"]
67716#[inline]
67717#[target_feature(enable = "neon")]
67718#[cfg(not(target_arch = "arm"))]
67719#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67720#[cfg_attr(test, assert_instr(st2))]
67721pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67722    unsafe extern "unadjusted" {
67723        #[cfg_attr(
67724            any(target_arch = "aarch64", target_arch = "arm64ec"),
67725            link_name = "llvm.aarch64.neon.st2.v2f32.p0i8"
67726        )]
67727        fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
67728    }
67729    _vst2_f32(b.0, b.1, a as _)
67730}
67731#[doc = "Store multiple 2-element structures from two registers"]
67732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67733#[doc = "## Safety"]
67734#[doc = "  * Neon instrinsic unsafe"]
67735#[inline]
67736#[target_feature(enable = "neon")]
67737#[cfg(not(target_arch = "arm"))]
67738#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67739#[cfg_attr(test, assert_instr(st2))]
67740pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67741    unsafe extern "unadjusted" {
67742        #[cfg_attr(
67743            any(target_arch = "aarch64", target_arch = "arm64ec"),
67744            link_name = "llvm.aarch64.neon.st2.v4f32.p0i8"
67745        )]
67746        fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
67747    }
67748    _vst2q_f32(b.0, b.1, a as _)
67749}
67750#[doc = "Store multiple 2-element structures from two registers"]
67751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67752#[doc = "## Safety"]
67753#[doc = "  * Neon instrinsic unsafe"]
67754#[inline]
67755#[target_feature(enable = "neon")]
67756#[cfg(not(target_arch = "arm"))]
67757#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67758#[cfg_attr(test, assert_instr(st2))]
67759pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67760    unsafe extern "unadjusted" {
67761        #[cfg_attr(
67762            any(target_arch = "aarch64", target_arch = "arm64ec"),
67763            link_name = "llvm.aarch64.neon.st2.v8i8.p0i8"
67764        )]
67765        fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
67766    }
67767    _vst2_s8(b.0, b.1, a as _)
67768}
67769#[doc = "Store multiple 2-element structures from two registers"]
67770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67771#[doc = "## Safety"]
67772#[doc = "  * Neon instrinsic unsafe"]
67773#[inline]
67774#[target_feature(enable = "neon")]
67775#[cfg(not(target_arch = "arm"))]
67776#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67777#[cfg_attr(test, assert_instr(st2))]
67778pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67779    unsafe extern "unadjusted" {
67780        #[cfg_attr(
67781            any(target_arch = "aarch64", target_arch = "arm64ec"),
67782            link_name = "llvm.aarch64.neon.st2.v16i8.p0i8"
67783        )]
67784        fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
67785    }
67786    _vst2q_s8(b.0, b.1, a as _)
67787}
67788#[doc = "Store multiple 2-element structures from two registers"]
67789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67790#[doc = "## Safety"]
67791#[doc = "  * Neon instrinsic unsafe"]
67792#[inline]
67793#[target_feature(enable = "neon")]
67794#[cfg(not(target_arch = "arm"))]
67795#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67796#[cfg_attr(test, assert_instr(st2))]
67797pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67798    unsafe extern "unadjusted" {
67799        #[cfg_attr(
67800            any(target_arch = "aarch64", target_arch = "arm64ec"),
67801            link_name = "llvm.aarch64.neon.st2.v4i16.p0i8"
67802        )]
67803        fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
67804    }
67805    _vst2_s16(b.0, b.1, a as _)
67806}
67807#[doc = "Store multiple 2-element structures from two registers"]
67808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67809#[doc = "## Safety"]
67810#[doc = "  * Neon instrinsic unsafe"]
67811#[inline]
67812#[target_feature(enable = "neon")]
67813#[cfg(not(target_arch = "arm"))]
67814#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67815#[cfg_attr(test, assert_instr(st2))]
67816pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67817    unsafe extern "unadjusted" {
67818        #[cfg_attr(
67819            any(target_arch = "aarch64", target_arch = "arm64ec"),
67820            link_name = "llvm.aarch64.neon.st2.v8i16.p0i8"
67821        )]
67822        fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
67823    }
67824    _vst2q_s16(b.0, b.1, a as _)
67825}
67826#[doc = "Store multiple 2-element structures from two registers"]
67827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67828#[doc = "## Safety"]
67829#[doc = "  * Neon instrinsic unsafe"]
67830#[inline]
67831#[target_feature(enable = "neon")]
67832#[cfg(not(target_arch = "arm"))]
67833#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67834#[cfg_attr(test, assert_instr(st2))]
67835pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67836    unsafe extern "unadjusted" {
67837        #[cfg_attr(
67838            any(target_arch = "aarch64", target_arch = "arm64ec"),
67839            link_name = "llvm.aarch64.neon.st2.v2i32.p0i8"
67840        )]
67841        fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
67842    }
67843    _vst2_s32(b.0, b.1, a as _)
67844}
67845#[doc = "Store multiple 2-element structures from two registers"]
67846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67847#[doc = "## Safety"]
67848#[doc = "  * Neon instrinsic unsafe"]
67849#[inline]
67850#[target_feature(enable = "neon")]
67851#[cfg(not(target_arch = "arm"))]
67852#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67853#[cfg_attr(test, assert_instr(st2))]
67854pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67855    unsafe extern "unadjusted" {
67856        #[cfg_attr(
67857            any(target_arch = "aarch64", target_arch = "arm64ec"),
67858            link_name = "llvm.aarch64.neon.st2.v4i32.p0i8"
67859        )]
67860        fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
67861    }
67862    _vst2q_s32(b.0, b.1, a as _)
67863}
67864#[doc = "Store multiple 2-element structures from two registers"]
67865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67866#[doc = "## Safety"]
67867#[doc = "  * Neon instrinsic unsafe"]
67868#[inline]
67869#[cfg(target_arch = "arm")]
67870#[target_feature(enable = "neon,v7")]
67871#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67872#[cfg_attr(test, assert_instr(vst2))]
67873pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67874    unsafe extern "unadjusted" {
67875        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2f32.p0")]
67876        fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32);
67877    }
67878    _vst2_f32(a as _, b.0, b.1, 4)
67879}
67880#[doc = "Store multiple 2-element structures from two registers"]
67881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67882#[doc = "## Safety"]
67883#[doc = "  * Neon instrinsic unsafe"]
67884#[inline]
67885#[cfg(target_arch = "arm")]
67886#[target_feature(enable = "neon,v7")]
67887#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67888#[cfg_attr(test, assert_instr(vst2))]
67889pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67890    unsafe extern "unadjusted" {
67891        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4f32.p0")]
67892        fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32);
67893    }
67894    _vst2q_f32(a as _, b.0, b.1, 4)
67895}
67896#[doc = "Store multiple 2-element structures from two registers"]
67897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67898#[doc = "## Safety"]
67899#[doc = "  * Neon instrinsic unsafe"]
67900#[inline]
67901#[cfg(target_arch = "arm")]
67902#[target_feature(enable = "neon,v7")]
67903#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67904#[cfg_attr(test, assert_instr(vst2))]
67905pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67906    unsafe extern "unadjusted" {
67907        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i8.p0")]
67908        fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32);
67909    }
67910    _vst2_s8(a as _, b.0, b.1, 1)
67911}
67912#[doc = "Store multiple 2-element structures from two registers"]
67913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67914#[doc = "## Safety"]
67915#[doc = "  * Neon instrinsic unsafe"]
67916#[inline]
67917#[cfg(target_arch = "arm")]
67918#[target_feature(enable = "neon,v7")]
67919#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67920#[cfg_attr(test, assert_instr(vst2))]
67921pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67922    unsafe extern "unadjusted" {
67923        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v16i8.p0")]
67924        fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32);
67925    }
67926    _vst2q_s8(a as _, b.0, b.1, 1)
67927}
67928#[doc = "Store multiple 2-element structures from two registers"]
67929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67930#[doc = "## Safety"]
67931#[doc = "  * Neon instrinsic unsafe"]
67932#[inline]
67933#[cfg(target_arch = "arm")]
67934#[target_feature(enable = "neon,v7")]
67935#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67936#[cfg_attr(test, assert_instr(vst2))]
67937pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67938    unsafe extern "unadjusted" {
67939        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i16.p0")]
67940        fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32);
67941    }
67942    _vst2_s16(a as _, b.0, b.1, 2)
67943}
67944#[doc = "Store multiple 2-element structures from two registers"]
67945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67946#[doc = "## Safety"]
67947#[doc = "  * Neon instrinsic unsafe"]
67948#[inline]
67949#[cfg(target_arch = "arm")]
67950#[target_feature(enable = "neon,v7")]
67951#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67952#[cfg_attr(test, assert_instr(vst2))]
67953pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67954    unsafe extern "unadjusted" {
67955        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i16.p0")]
67956        fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32);
67957    }
67958    _vst2q_s16(a as _, b.0, b.1, 2)
67959}
67960#[doc = "Store multiple 2-element structures from two registers"]
67961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67962#[doc = "## Safety"]
67963#[doc = "  * Neon instrinsic unsafe"]
67964#[inline]
67965#[cfg(target_arch = "arm")]
67966#[target_feature(enable = "neon,v7")]
67967#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67968#[cfg_attr(test, assert_instr(vst2))]
67969pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67970    unsafe extern "unadjusted" {
67971        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2i32.p0")]
67972        fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32);
67973    }
67974    _vst2_s32(a as _, b.0, b.1, 4)
67975}
67976#[doc = "Store multiple 2-element structures from two registers"]
67977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67978#[doc = "## Safety"]
67979#[doc = "  * Neon instrinsic unsafe"]
67980#[inline]
67981#[cfg(target_arch = "arm")]
67982#[target_feature(enable = "neon,v7")]
67983#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67984#[cfg_attr(test, assert_instr(vst2))]
67985pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67986    unsafe extern "unadjusted" {
67987        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i32.p0")]
67988        fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32);
67989    }
67990    _vst2q_s32(a as _, b.0, b.1, 4)
67991}
67992#[doc = "Store multiple 2-element structures from two registers"]
67993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67994#[doc = "## Safety"]
67995#[doc = "  * Neon instrinsic unsafe"]
67996#[inline]
67997#[cfg(not(target_arch = "arm"))]
67998#[rustc_legacy_const_generics(2)]
67999#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68000#[target_feature(enable = "neon,fp16")]
68001#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68002pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
68003    static_assert_uimm_bits!(LANE, 2);
68004    unsafe extern "unadjusted" {
68005        #[cfg_attr(
68006            any(target_arch = "aarch64", target_arch = "arm64ec"),
68007            link_name = "llvm.aarch64.neon.st2lane.v4f16.p0i8"
68008        )]
68009        fn _vst2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *mut i8);
68010    }
68011    _vst2_lane_f16(b.0, b.1, LANE as i64, a as _)
68012}
68013#[doc = "Store multiple 2-element structures from two registers"]
68014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
68015#[doc = "## Safety"]
68016#[doc = "  * Neon instrinsic unsafe"]
68017#[inline]
68018#[cfg(not(target_arch = "arm"))]
68019#[rustc_legacy_const_generics(2)]
68020#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68021#[target_feature(enable = "neon,fp16")]
68022#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68023pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
68024    static_assert_uimm_bits!(LANE, 3);
68025    unsafe extern "unadjusted" {
68026        #[cfg_attr(
68027            any(target_arch = "aarch64", target_arch = "arm64ec"),
68028            link_name = "llvm.aarch64.neon.st2lane.v8f16.p0i8"
68029        )]
68030        fn _vst2q_lane_f16(a: float16x8_t, b: float16x8_t, n: i64, ptr: *mut i8);
68031    }
68032    _vst2q_lane_f16(b.0, b.1, LANE as i64, a as _)
68033}
68034#[doc = "Store multiple 2-element structures from two registers"]
68035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
68036#[doc = "## Safety"]
68037#[doc = "  * Neon instrinsic unsafe"]
68038#[inline]
68039#[cfg(target_arch = "arm")]
68040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68041#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68042#[rustc_legacy_const_generics(2)]
68043#[target_feature(enable = "neon,fp16")]
68044#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68045pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
68046    static_assert_uimm_bits!(LANE, 2);
68047    unsafe extern "unadjusted" {
68048        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f16")]
68049        fn _vst2_lane_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, n: i32, size: i32);
68050    }
68051    _vst2_lane_f16(a as _, b.0, b.1, LANE, 2)
68052}
68053#[doc = "Store multiple 2-element structures from two registers"]
68054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
68055#[doc = "## Safety"]
68056#[doc = "  * Neon instrinsic unsafe"]
68057#[inline]
68058#[cfg(target_arch = "arm")]
68059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68060#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68061#[rustc_legacy_const_generics(2)]
68062#[target_feature(enable = "neon,fp16")]
68063#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68064pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
68065    static_assert_uimm_bits!(LANE, 1);
68066    unsafe extern "unadjusted" {
68067        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8f16")]
68068        fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
68069    }
68070    _vst2q_lane_f16(a as _, b.0, b.1, LANE, 2)
68071}
68072#[doc = "Store multiple 2-element structures from two registers"]
68073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68074#[doc = "## Safety"]
68075#[doc = "  * Neon instrinsic unsafe"]
68076#[inline]
68077#[target_feature(enable = "neon")]
68078#[cfg(not(target_arch = "arm"))]
68079#[rustc_legacy_const_generics(2)]
68080#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68082pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68083    static_assert_uimm_bits!(LANE, 1);
68084    unsafe extern "unadjusted" {
68085        #[cfg_attr(
68086            any(target_arch = "aarch64", target_arch = "arm64ec"),
68087            link_name = "llvm.aarch64.neon.st2lane.v2f32.p0i8"
68088        )]
68089        fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8);
68090    }
68091    _vst2_lane_f32(b.0, b.1, LANE as i64, a as _)
68092}
68093#[doc = "Store multiple 2-element structures from two registers"]
68094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68095#[doc = "## Safety"]
68096#[doc = "  * Neon instrinsic unsafe"]
68097#[inline]
68098#[target_feature(enable = "neon")]
68099#[cfg(not(target_arch = "arm"))]
68100#[rustc_legacy_const_generics(2)]
68101#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68102#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68103pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68104    static_assert_uimm_bits!(LANE, 2);
68105    unsafe extern "unadjusted" {
68106        #[cfg_attr(
68107            any(target_arch = "aarch64", target_arch = "arm64ec"),
68108            link_name = "llvm.aarch64.neon.st2lane.v4f32.p0i8"
68109        )]
68110        fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8);
68111    }
68112    _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _)
68113}
68114#[doc = "Store multiple 2-element structures from two registers"]
68115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68116#[doc = "## Safety"]
68117#[doc = "  * Neon instrinsic unsafe"]
68118#[inline]
68119#[target_feature(enable = "neon")]
68120#[cfg(not(target_arch = "arm"))]
68121#[rustc_legacy_const_generics(2)]
68122#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68123#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68124pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68125    static_assert_uimm_bits!(LANE, 3);
68126    unsafe extern "unadjusted" {
68127        #[cfg_attr(
68128            any(target_arch = "aarch64", target_arch = "arm64ec"),
68129            link_name = "llvm.aarch64.neon.st2lane.v8i8.p0i8"
68130        )]
68131        fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8);
68132    }
68133    _vst2_lane_s8(b.0, b.1, LANE as i64, a as _)
68134}
68135#[doc = "Store multiple 2-element structures from two registers"]
68136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68137#[doc = "## Safety"]
68138#[doc = "  * Neon instrinsic unsafe"]
68139#[inline]
68140#[target_feature(enable = "neon")]
68141#[cfg(not(target_arch = "arm"))]
68142#[rustc_legacy_const_generics(2)]
68143#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68145pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68146    static_assert_uimm_bits!(LANE, 2);
68147    unsafe extern "unadjusted" {
68148        #[cfg_attr(
68149            any(target_arch = "aarch64", target_arch = "arm64ec"),
68150            link_name = "llvm.aarch64.neon.st2lane.v4i16.p0i8"
68151        )]
68152        fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8);
68153    }
68154    _vst2_lane_s16(b.0, b.1, LANE as i64, a as _)
68155}
68156#[doc = "Store multiple 2-element structures from two registers"]
68157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68158#[doc = "## Safety"]
68159#[doc = "  * Neon instrinsic unsafe"]
68160#[inline]
68161#[target_feature(enable = "neon")]
68162#[cfg(not(target_arch = "arm"))]
68163#[rustc_legacy_const_generics(2)]
68164#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68165#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68166pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68167    static_assert_uimm_bits!(LANE, 3);
68168    unsafe extern "unadjusted" {
68169        #[cfg_attr(
68170            any(target_arch = "aarch64", target_arch = "arm64ec"),
68171            link_name = "llvm.aarch64.neon.st2lane.v8i16.p0i8"
68172        )]
68173        fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8);
68174    }
68175    _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _)
68176}
68177#[doc = "Store multiple 2-element structures from two registers"]
68178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68179#[doc = "## Safety"]
68180#[doc = "  * Neon instrinsic unsafe"]
68181#[inline]
68182#[target_feature(enable = "neon")]
68183#[cfg(not(target_arch = "arm"))]
68184#[rustc_legacy_const_generics(2)]
68185#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68186#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68187pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68188    static_assert_uimm_bits!(LANE, 1);
68189    unsafe extern "unadjusted" {
68190        #[cfg_attr(
68191            any(target_arch = "aarch64", target_arch = "arm64ec"),
68192            link_name = "llvm.aarch64.neon.st2lane.v2i32.p0i8"
68193        )]
68194        fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8);
68195    }
68196    _vst2_lane_s32(b.0, b.1, LANE as i64, a as _)
68197}
68198#[doc = "Store multiple 2-element structures from two registers"]
68199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68200#[doc = "## Safety"]
68201#[doc = "  * Neon instrinsic unsafe"]
68202#[inline]
68203#[target_feature(enable = "neon")]
68204#[cfg(not(target_arch = "arm"))]
68205#[rustc_legacy_const_generics(2)]
68206#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68208pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68209    static_assert_uimm_bits!(LANE, 2);
68210    unsafe extern "unadjusted" {
68211        #[cfg_attr(
68212            any(target_arch = "aarch64", target_arch = "arm64ec"),
68213            link_name = "llvm.aarch64.neon.st2lane.v4i32.p0i8"
68214        )]
68215        fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8);
68216    }
68217    _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _)
68218}
68219#[doc = "Store multiple 2-element structures from two registers"]
68220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68221#[doc = "## Safety"]
68222#[doc = "  * Neon instrinsic unsafe"]
68223#[inline]
68224#[cfg(target_arch = "arm")]
68225#[target_feature(enable = "neon,v7")]
68226#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68227#[rustc_legacy_const_generics(2)]
68228#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68229pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68230    static_assert_uimm_bits!(LANE, 1);
68231    unsafe extern "unadjusted" {
68232        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2f32.p0")]
68233        fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
68234    }
68235    _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
68236}
68237#[doc = "Store multiple 2-element structures from two registers"]
68238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68239#[doc = "## Safety"]
68240#[doc = "  * Neon instrinsic unsafe"]
68241#[inline]
68242#[cfg(target_arch = "arm")]
68243#[target_feature(enable = "neon,v7")]
68244#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68245#[rustc_legacy_const_generics(2)]
68246#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68247pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68248    static_assert_uimm_bits!(LANE, 2);
68249    unsafe extern "unadjusted" {
68250        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4f32.p0")]
68251        fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
68252    }
68253    _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
68254}
68255#[doc = "Store multiple 2-element structures from two registers"]
68256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68257#[doc = "## Safety"]
68258#[doc = "  * Neon instrinsic unsafe"]
68259#[inline]
68260#[cfg(target_arch = "arm")]
68261#[target_feature(enable = "neon,v7")]
68262#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68263#[rustc_legacy_const_generics(2)]
68264#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68265pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68266    static_assert_uimm_bits!(LANE, 3);
68267    unsafe extern "unadjusted" {
68268        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i8.p0")]
68269        fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
68270    }
68271    _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
68272}
68273#[doc = "Store multiple 2-element structures from two registers"]
68274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68275#[doc = "## Safety"]
68276#[doc = "  * Neon instrinsic unsafe"]
68277#[inline]
68278#[cfg(target_arch = "arm")]
68279#[target_feature(enable = "neon,v7")]
68280#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68281#[rustc_legacy_const_generics(2)]
68282#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68283pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68284    static_assert_uimm_bits!(LANE, 2);
68285    unsafe extern "unadjusted" {
68286        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i16.p0")]
68287        fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
68288    }
68289    _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
68290}
68291#[doc = "Store multiple 2-element structures from two registers"]
68292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68293#[doc = "## Safety"]
68294#[doc = "  * Neon instrinsic unsafe"]
68295#[inline]
68296#[cfg(target_arch = "arm")]
68297#[target_feature(enable = "neon,v7")]
68298#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68299#[rustc_legacy_const_generics(2)]
68300#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68301pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68302    static_assert_uimm_bits!(LANE, 3);
68303    unsafe extern "unadjusted" {
68304        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i16.p0")]
68305        fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
68306    }
68307    _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
68308}
68309#[doc = "Store multiple 2-element structures from two registers"]
68310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68311#[doc = "## Safety"]
68312#[doc = "  * Neon instrinsic unsafe"]
68313#[inline]
68314#[cfg(target_arch = "arm")]
68315#[target_feature(enable = "neon,v7")]
68316#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68317#[rustc_legacy_const_generics(2)]
68318#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68319pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68320    static_assert_uimm_bits!(LANE, 1);
68321    unsafe extern "unadjusted" {
68322        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2i32.p0")]
68323        fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
68324    }
68325    _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
68326}
68327#[doc = "Store multiple 2-element structures from two registers"]
68328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68329#[doc = "## Safety"]
68330#[doc = "  * Neon instrinsic unsafe"]
68331#[inline]
68332#[cfg(target_arch = "arm")]
68333#[target_feature(enable = "neon,v7")]
68334#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68335#[rustc_legacy_const_generics(2)]
68336#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68337pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68338    static_assert_uimm_bits!(LANE, 2);
68339    unsafe extern "unadjusted" {
68340        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i32.p0")]
68341        fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
68342    }
68343    _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
68344}
68345#[doc = "Store multiple 2-element structures from two registers"]
68346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
68347#[doc = "## Safety"]
68348#[doc = "  * Neon instrinsic unsafe"]
68349#[inline]
68350#[target_feature(enable = "neon")]
68351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68353#[cfg_attr(
68354    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68355    assert_instr(st2, LANE = 0)
68356)]
68357#[rustc_legacy_const_generics(2)]
68358#[cfg_attr(
68359    not(target_arch = "arm"),
68360    stable(feature = "neon_intrinsics", since = "1.59.0")
68361)]
68362#[cfg_attr(
68363    target_arch = "arm",
68364    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68365)]
68366pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
68367    static_assert_uimm_bits!(LANE, 3);
68368    vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68369}
68370#[doc = "Store multiple 2-element structures from two registers"]
68371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
68372#[doc = "## Safety"]
68373#[doc = "  * Neon instrinsic unsafe"]
68374#[inline]
68375#[target_feature(enable = "neon")]
68376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68378#[cfg_attr(
68379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68380    assert_instr(st2, LANE = 0)
68381)]
68382#[rustc_legacy_const_generics(2)]
68383#[cfg_attr(
68384    not(target_arch = "arm"),
68385    stable(feature = "neon_intrinsics", since = "1.59.0")
68386)]
68387#[cfg_attr(
68388    target_arch = "arm",
68389    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68390)]
68391pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
68392    static_assert_uimm_bits!(LANE, 2);
68393    vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68394}
68395#[doc = "Store multiple 2-element structures from two registers"]
68396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
68397#[doc = "## Safety"]
68398#[doc = "  * Neon instrinsic unsafe"]
68399#[inline]
68400#[target_feature(enable = "neon")]
68401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68403#[cfg_attr(
68404    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68405    assert_instr(st2, LANE = 0)
68406)]
68407#[rustc_legacy_const_generics(2)]
68408#[cfg_attr(
68409    not(target_arch = "arm"),
68410    stable(feature = "neon_intrinsics", since = "1.59.0")
68411)]
68412#[cfg_attr(
68413    target_arch = "arm",
68414    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68415)]
68416pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
68417    static_assert_uimm_bits!(LANE, 3);
68418    vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68419}
68420#[doc = "Store multiple 2-element structures from two registers"]
68421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
68422#[doc = "## Safety"]
68423#[doc = "  * Neon instrinsic unsafe"]
68424#[inline]
68425#[target_feature(enable = "neon")]
68426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68427#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68428#[cfg_attr(
68429    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68430    assert_instr(st2, LANE = 0)
68431)]
68432#[rustc_legacy_const_generics(2)]
68433#[cfg_attr(
68434    not(target_arch = "arm"),
68435    stable(feature = "neon_intrinsics", since = "1.59.0")
68436)]
68437#[cfg_attr(
68438    target_arch = "arm",
68439    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68440)]
68441pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
68442    static_assert_uimm_bits!(LANE, 1);
68443    vst2_lane_s32::<LANE>(transmute(a), transmute(b))
68444}
68445#[doc = "Store multiple 2-element structures from two registers"]
68446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
68447#[doc = "## Safety"]
68448#[doc = "  * Neon instrinsic unsafe"]
68449#[inline]
68450#[target_feature(enable = "neon")]
68451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68453#[cfg_attr(
68454    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68455    assert_instr(st2, LANE = 0)
68456)]
68457#[rustc_legacy_const_generics(2)]
68458#[cfg_attr(
68459    not(target_arch = "arm"),
68460    stable(feature = "neon_intrinsics", since = "1.59.0")
68461)]
68462#[cfg_attr(
68463    target_arch = "arm",
68464    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68465)]
68466pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
68467    static_assert_uimm_bits!(LANE, 2);
68468    vst2q_lane_s32::<LANE>(transmute(a), transmute(b))
68469}
68470#[doc = "Store multiple 2-element structures from two registers"]
68471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
68472#[doc = "## Safety"]
68473#[doc = "  * Neon instrinsic unsafe"]
68474#[inline]
68475#[target_feature(enable = "neon")]
68476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68478#[cfg_attr(
68479    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68480    assert_instr(st2, LANE = 0)
68481)]
68482#[rustc_legacy_const_generics(2)]
68483#[cfg_attr(
68484    not(target_arch = "arm"),
68485    stable(feature = "neon_intrinsics", since = "1.59.0")
68486)]
68487#[cfg_attr(
68488    target_arch = "arm",
68489    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68490)]
68491pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
68492    static_assert_uimm_bits!(LANE, 3);
68493    vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68494}
68495#[doc = "Store multiple 2-element structures from two registers"]
68496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
68497#[doc = "## Safety"]
68498#[doc = "  * Neon instrinsic unsafe"]
68499#[inline]
68500#[target_feature(enable = "neon")]
68501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68503#[cfg_attr(
68504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68505    assert_instr(st2, LANE = 0)
68506)]
68507#[rustc_legacy_const_generics(2)]
68508#[cfg_attr(
68509    not(target_arch = "arm"),
68510    stable(feature = "neon_intrinsics", since = "1.59.0")
68511)]
68512#[cfg_attr(
68513    target_arch = "arm",
68514    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68515)]
68516pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
68517    static_assert_uimm_bits!(LANE, 2);
68518    vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68519}
68520#[doc = "Store multiple 2-element structures from two registers"]
68521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
68522#[doc = "## Safety"]
68523#[doc = "  * Neon instrinsic unsafe"]
68524#[inline]
68525#[target_feature(enable = "neon")]
68526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68528#[cfg_attr(
68529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68530    assert_instr(st2, LANE = 0)
68531)]
68532#[rustc_legacy_const_generics(2)]
68533#[cfg_attr(
68534    not(target_arch = "arm"),
68535    stable(feature = "neon_intrinsics", since = "1.59.0")
68536)]
68537#[cfg_attr(
68538    target_arch = "arm",
68539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68540)]
68541pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
68542    static_assert_uimm_bits!(LANE, 3);
68543    vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68544}
68545#[doc = "Store multiple 2-element structures from two registers"]
68546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
68547#[doc = "## Safety"]
68548#[doc = "  * Neon instrinsic unsafe"]
68549#[inline]
68550#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
68551#[target_feature(enable = "neon,aes")]
68552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68553#[cfg_attr(
68554    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68555    assert_instr(nop)
68556)]
68557#[cfg_attr(
68558    not(target_arch = "arm"),
68559    stable(feature = "neon_intrinsics", since = "1.59.0")
68560)]
68561#[cfg_attr(
68562    target_arch = "arm",
68563    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68564)]
68565pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
68566    vst2_s64(transmute(a), transmute(b))
68567}
68568#[doc = "Store multiple 2-element structures from two registers"]
68569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68570#[doc = "## Safety"]
68571#[doc = "  * Neon instrinsic unsafe"]
68572#[inline]
68573#[cfg(target_arch = "arm")]
68574#[target_feature(enable = "neon,v7")]
68575#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68576#[cfg_attr(test, assert_instr(nop))]
68577pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68578    unsafe extern "unadjusted" {
68579        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
68580        fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
68581    }
68582    _vst2_s64(a as _, b.0, b.1, 8)
68583}
68584#[doc = "Store multiple 2-element structures from two registers"]
68585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68586#[doc = "## Safety"]
68587#[doc = "  * Neon instrinsic unsafe"]
68588#[inline]
68589#[target_feature(enable = "neon")]
68590#[cfg(not(target_arch = "arm"))]
68591#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68592#[cfg_attr(test, assert_instr(nop))]
68593pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68594    unsafe extern "unadjusted" {
68595        #[cfg_attr(
68596            any(target_arch = "aarch64", target_arch = "arm64ec"),
68597            link_name = "llvm.aarch64.neon.st2.v1i64.p0i8"
68598        )]
68599        fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
68600    }
68601    _vst2_s64(b.0, b.1, a as _)
68602}
68603#[doc = "Store multiple 2-element structures from two registers"]
68604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
68605#[doc = "## Safety"]
68606#[doc = "  * Neon instrinsic unsafe"]
68607#[inline]
68608#[target_feature(enable = "neon")]
68609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68611#[cfg_attr(
68612    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68613    assert_instr(nop)
68614)]
68615#[cfg_attr(
68616    not(target_arch = "arm"),
68617    stable(feature = "neon_intrinsics", since = "1.59.0")
68618)]
68619#[cfg_attr(
68620    target_arch = "arm",
68621    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68622)]
68623pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
68624    vst2_s64(transmute(a), transmute(b))
68625}
68626#[doc = "Store multiple 2-element structures from two registers"]
68627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
68628#[doc = "## Safety"]
68629#[doc = "  * Neon instrinsic unsafe"]
68630#[inline]
68631#[target_feature(enable = "neon")]
68632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68634#[cfg_attr(
68635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68636    assert_instr(st2)
68637)]
68638#[cfg_attr(
68639    not(target_arch = "arm"),
68640    stable(feature = "neon_intrinsics", since = "1.59.0")
68641)]
68642#[cfg_attr(
68643    target_arch = "arm",
68644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68645)]
68646pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
68647    vst2_s8(transmute(a), transmute(b))
68648}
68649#[doc = "Store multiple 2-element structures from two registers"]
68650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
68651#[doc = "## Safety"]
68652#[doc = "  * Neon instrinsic unsafe"]
68653#[inline]
68654#[target_feature(enable = "neon")]
68655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68657#[cfg_attr(
68658    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68659    assert_instr(st2)
68660)]
68661#[cfg_attr(
68662    not(target_arch = "arm"),
68663    stable(feature = "neon_intrinsics", since = "1.59.0")
68664)]
68665#[cfg_attr(
68666    target_arch = "arm",
68667    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68668)]
68669pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
68670    vst2q_s8(transmute(a), transmute(b))
68671}
68672#[doc = "Store multiple 2-element structures from two registers"]
68673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
68674#[doc = "## Safety"]
68675#[doc = "  * Neon instrinsic unsafe"]
68676#[inline]
68677#[target_feature(enable = "neon")]
68678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68680#[cfg_attr(
68681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68682    assert_instr(st2)
68683)]
68684#[cfg_attr(
68685    not(target_arch = "arm"),
68686    stable(feature = "neon_intrinsics", since = "1.59.0")
68687)]
68688#[cfg_attr(
68689    target_arch = "arm",
68690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68691)]
68692pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
68693    vst2_s16(transmute(a), transmute(b))
68694}
68695#[doc = "Store multiple 2-element structures from two registers"]
68696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
68697#[doc = "## Safety"]
68698#[doc = "  * Neon instrinsic unsafe"]
68699#[inline]
68700#[target_feature(enable = "neon")]
68701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68703#[cfg_attr(
68704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68705    assert_instr(st2)
68706)]
68707#[cfg_attr(
68708    not(target_arch = "arm"),
68709    stable(feature = "neon_intrinsics", since = "1.59.0")
68710)]
68711#[cfg_attr(
68712    target_arch = "arm",
68713    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68714)]
68715pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
68716    vst2q_s16(transmute(a), transmute(b))
68717}
68718#[doc = "Store multiple 2-element structures from two registers"]
68719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
68720#[doc = "## Safety"]
68721#[doc = "  * Neon instrinsic unsafe"]
68722#[inline]
68723#[target_feature(enable = "neon")]
68724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68726#[cfg_attr(
68727    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68728    assert_instr(st2)
68729)]
68730#[cfg_attr(
68731    not(target_arch = "arm"),
68732    stable(feature = "neon_intrinsics", since = "1.59.0")
68733)]
68734#[cfg_attr(
68735    target_arch = "arm",
68736    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68737)]
68738pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
68739    vst2_s32(transmute(a), transmute(b))
68740}
68741#[doc = "Store multiple 2-element structures from two registers"]
68742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
68743#[doc = "## Safety"]
68744#[doc = "  * Neon instrinsic unsafe"]
68745#[inline]
68746#[target_feature(enable = "neon")]
68747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68749#[cfg_attr(
68750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68751    assert_instr(st2)
68752)]
68753#[cfg_attr(
68754    not(target_arch = "arm"),
68755    stable(feature = "neon_intrinsics", since = "1.59.0")
68756)]
68757#[cfg_attr(
68758    target_arch = "arm",
68759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68760)]
68761pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
68762    vst2q_s32(transmute(a), transmute(b))
68763}
68764#[doc = "Store multiple 2-element structures from two registers"]
68765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
68766#[doc = "## Safety"]
68767#[doc = "  * Neon instrinsic unsafe"]
68768#[inline]
68769#[target_feature(enable = "neon")]
68770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68772#[cfg_attr(
68773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68774    assert_instr(st2)
68775)]
68776#[cfg_attr(
68777    not(target_arch = "arm"),
68778    stable(feature = "neon_intrinsics", since = "1.59.0")
68779)]
68780#[cfg_attr(
68781    target_arch = "arm",
68782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68783)]
68784pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
68785    vst2_s8(transmute(a), transmute(b))
68786}
68787#[doc = "Store multiple 2-element structures from two registers"]
68788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
68789#[doc = "## Safety"]
68790#[doc = "  * Neon instrinsic unsafe"]
68791#[inline]
68792#[target_feature(enable = "neon")]
68793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68795#[cfg_attr(
68796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68797    assert_instr(st2)
68798)]
68799#[cfg_attr(
68800    not(target_arch = "arm"),
68801    stable(feature = "neon_intrinsics", since = "1.59.0")
68802)]
68803#[cfg_attr(
68804    target_arch = "arm",
68805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68806)]
68807pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
68808    vst2q_s8(transmute(a), transmute(b))
68809}
68810#[doc = "Store multiple 2-element structures from two registers"]
68811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
68812#[doc = "## Safety"]
68813#[doc = "  * Neon instrinsic unsafe"]
68814#[inline]
68815#[target_feature(enable = "neon")]
68816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68818#[cfg_attr(
68819    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68820    assert_instr(st2)
68821)]
68822#[cfg_attr(
68823    not(target_arch = "arm"),
68824    stable(feature = "neon_intrinsics", since = "1.59.0")
68825)]
68826#[cfg_attr(
68827    target_arch = "arm",
68828    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68829)]
68830pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
68831    vst2_s16(transmute(a), transmute(b))
68832}
68833#[doc = "Store multiple 2-element structures from two registers"]
68834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
68835#[doc = "## Safety"]
68836#[doc = "  * Neon instrinsic unsafe"]
68837#[inline]
68838#[target_feature(enable = "neon")]
68839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68841#[cfg_attr(
68842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68843    assert_instr(st2)
68844)]
68845#[cfg_attr(
68846    not(target_arch = "arm"),
68847    stable(feature = "neon_intrinsics", since = "1.59.0")
68848)]
68849#[cfg_attr(
68850    target_arch = "arm",
68851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68852)]
68853pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
68854    vst2q_s16(transmute(a), transmute(b))
68855}
68856#[doc = "Store multiple 3-element structures from three registers"]
68857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68858#[doc = "## Safety"]
68859#[doc = "  * Neon instrinsic unsafe"]
68860#[inline]
68861#[cfg(target_arch = "arm")]
68862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68863#[target_feature(enable = "neon,fp16")]
68864#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68865#[cfg_attr(test, assert_instr(vst3))]
68866pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68867    unsafe extern "unadjusted" {
68868        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f16")]
68869        fn _vst3_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, c: float16x4_t, size: i32);
68870    }
68871    _vst3_f16(a as _, b.0, b.1, b.2, 2)
68872}
68873#[doc = "Store multiple 3-element structures from three registers"]
68874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68875#[doc = "## Safety"]
68876#[doc = "  * Neon instrinsic unsafe"]
68877#[inline]
68878#[cfg(target_arch = "arm")]
68879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68880#[target_feature(enable = "neon,fp16")]
68881#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68882#[cfg_attr(test, assert_instr(vst3))]
68883pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68884    unsafe extern "unadjusted" {
68885        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8f16")]
68886        fn _vst3q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, c: float16x8_t, size: i32);
68887    }
68888    _vst3q_f16(a as _, b.0, b.1, b.2, 2)
68889}
68890#[doc = "Store multiple 3-element structures from three registers"]
68891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68892#[doc = "## Safety"]
68893#[doc = "  * Neon instrinsic unsafe"]
68894#[inline]
68895#[cfg(not(target_arch = "arm"))]
68896#[target_feature(enable = "neon,fp16")]
68897#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68898#[cfg_attr(test, assert_instr(st3))]
68899pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68900    unsafe extern "unadjusted" {
68901        #[cfg_attr(
68902            any(target_arch = "aarch64", target_arch = "arm64ec"),
68903            link_name = "llvm.aarch64.neon.st3.v4f16.p0i8"
68904        )]
68905        fn _vst3_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut i8);
68906    }
68907    _vst3_f16(b.0, b.1, b.2, a as _)
68908}
68909#[doc = "Store multiple 3-element structures from three registers"]
68910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68911#[doc = "## Safety"]
68912#[doc = "  * Neon instrinsic unsafe"]
68913#[inline]
68914#[cfg(not(target_arch = "arm"))]
68915#[target_feature(enable = "neon,fp16")]
68916#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68917#[cfg_attr(test, assert_instr(st3))]
68918pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68919    unsafe extern "unadjusted" {
68920        #[cfg_attr(
68921            any(target_arch = "aarch64", target_arch = "arm64ec"),
68922            link_name = "llvm.aarch64.neon.st3.v8f16.p0i8"
68923        )]
68924        fn _vst3q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut i8);
68925    }
68926    _vst3q_f16(b.0, b.1, b.2, a as _)
68927}
68928#[doc = "Store multiple 3-element structures from three registers"]
68929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68930#[doc = "## Safety"]
68931#[doc = "  * Neon instrinsic unsafe"]
68932#[inline]
68933#[cfg(target_arch = "arm")]
68934#[target_feature(enable = "neon,v7")]
68935#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68936#[cfg_attr(test, assert_instr(vst3))]
68937pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68938    unsafe extern "unadjusted" {
68939        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2f32")]
68940        fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
68941    }
68942    _vst3_f32(a as _, b.0, b.1, b.2, 4)
68943}
68944#[doc = "Store multiple 3-element structures from three registers"]
68945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
68946#[doc = "## Safety"]
68947#[doc = "  * Neon instrinsic unsafe"]
68948#[inline]
68949#[cfg(target_arch = "arm")]
68950#[target_feature(enable = "neon,v7")]
68951#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68952#[cfg_attr(test, assert_instr(vst3))]
68953pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
68954    unsafe extern "unadjusted" {
68955        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f32")]
68956        fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
68957    }
68958    _vst3q_f32(a as _, b.0, b.1, b.2, 4)
68959}
68960#[doc = "Store multiple 3-element structures from three registers"]
68961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
68962#[doc = "## Safety"]
68963#[doc = "  * Neon instrinsic unsafe"]
68964#[inline]
68965#[cfg(target_arch = "arm")]
68966#[target_feature(enable = "neon,v7")]
68967#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68968#[cfg_attr(test, assert_instr(vst3))]
68969pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
68970    unsafe extern "unadjusted" {
68971        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i8")]
68972        fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
68973    }
68974    _vst3_s8(a as _, b.0, b.1, b.2, 1)
68975}
68976#[doc = "Store multiple 3-element structures from three registers"]
68977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
68978#[doc = "## Safety"]
68979#[doc = "  * Neon instrinsic unsafe"]
68980#[inline]
68981#[cfg(target_arch = "arm")]
68982#[target_feature(enable = "neon,v7")]
68983#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68984#[cfg_attr(test, assert_instr(vst3))]
68985pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
68986    unsafe extern "unadjusted" {
68987        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v16i8")]
68988        fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
68989    }
68990    _vst3q_s8(a as _, b.0, b.1, b.2, 1)
68991}
68992#[doc = "Store multiple 3-element structures from three registers"]
68993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
68994#[doc = "## Safety"]
68995#[doc = "  * Neon instrinsic unsafe"]
68996#[inline]
68997#[cfg(target_arch = "arm")]
68998#[target_feature(enable = "neon,v7")]
68999#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69000#[cfg_attr(test, assert_instr(vst3))]
69001pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
69002    unsafe extern "unadjusted" {
69003        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i16")]
69004        fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
69005    }
69006    _vst3_s16(a as _, b.0, b.1, b.2, 2)
69007}
69008#[doc = "Store multiple 3-element structures from three registers"]
69009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
69010#[doc = "## Safety"]
69011#[doc = "  * Neon instrinsic unsafe"]
69012#[inline]
69013#[cfg(target_arch = "arm")]
69014#[target_feature(enable = "neon,v7")]
69015#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69016#[cfg_attr(test, assert_instr(vst3))]
69017pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
69018    unsafe extern "unadjusted" {
69019        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i16")]
69020        fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
69021    }
69022    _vst3q_s16(a as _, b.0, b.1, b.2, 2)
69023}
69024#[doc = "Store multiple 3-element structures from three registers"]
69025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
69026#[doc = "## Safety"]
69027#[doc = "  * Neon instrinsic unsafe"]
69028#[inline]
69029#[cfg(target_arch = "arm")]
69030#[target_feature(enable = "neon,v7")]
69031#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69032#[cfg_attr(test, assert_instr(vst3))]
69033pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
69034    unsafe extern "unadjusted" {
69035        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2i32")]
69036        fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
69037    }
69038    _vst3_s32(a as _, b.0, b.1, b.2, 4)
69039}
69040#[doc = "Store multiple 3-element structures from three registers"]
69041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
69042#[doc = "## Safety"]
69043#[doc = "  * Neon instrinsic unsafe"]
69044#[inline]
69045#[cfg(target_arch = "arm")]
69046#[target_feature(enable = "neon,v7")]
69047#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69048#[cfg_attr(test, assert_instr(vst3))]
69049pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
69050    unsafe extern "unadjusted" {
69051        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i32")]
69052        fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
69053    }
69054    _vst3q_s32(a as _, b.0, b.1, b.2, 4)
69055}
69056#[doc = "Store multiple 3-element structures from three registers"]
69057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
69058#[doc = "## Safety"]
69059#[doc = "  * Neon instrinsic unsafe"]
69060#[inline]
69061#[target_feature(enable = "neon")]
69062#[cfg(not(target_arch = "arm"))]
69063#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69064#[cfg_attr(test, assert_instr(st3))]
69065pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
69066    unsafe extern "unadjusted" {
69067        #[cfg_attr(
69068            any(target_arch = "aarch64", target_arch = "arm64ec"),
69069            link_name = "llvm.aarch64.neon.st3.v2f32.p0i8"
69070        )]
69071        fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
69072    }
69073    _vst3_f32(b.0, b.1, b.2, a as _)
69074}
69075#[doc = "Store multiple 3-element structures from three registers"]
69076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
69077#[doc = "## Safety"]
69078#[doc = "  * Neon instrinsic unsafe"]
69079#[inline]
69080#[target_feature(enable = "neon")]
69081#[cfg(not(target_arch = "arm"))]
69082#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69083#[cfg_attr(test, assert_instr(st3))]
69084pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
69085    unsafe extern "unadjusted" {
69086        #[cfg_attr(
69087            any(target_arch = "aarch64", target_arch = "arm64ec"),
69088            link_name = "llvm.aarch64.neon.st3.v4f32.p0i8"
69089        )]
69090        fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
69091    }
69092    _vst3q_f32(b.0, b.1, b.2, a as _)
69093}
69094#[doc = "Store multiple 3-element structures from three registers"]
69095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
69096#[doc = "## Safety"]
69097#[doc = "  * Neon instrinsic unsafe"]
69098#[inline]
69099#[target_feature(enable = "neon")]
69100#[cfg(not(target_arch = "arm"))]
69101#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69102#[cfg_attr(test, assert_instr(st3))]
69103pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
69104    unsafe extern "unadjusted" {
69105        #[cfg_attr(
69106            any(target_arch = "aarch64", target_arch = "arm64ec"),
69107            link_name = "llvm.aarch64.neon.st3.v8i8.p0i8"
69108        )]
69109        fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
69110    }
69111    _vst3_s8(b.0, b.1, b.2, a as _)
69112}
69113#[doc = "Store multiple 3-element structures from three registers"]
69114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
69115#[doc = "## Safety"]
69116#[doc = "  * Neon instrinsic unsafe"]
69117#[inline]
69118#[target_feature(enable = "neon")]
69119#[cfg(not(target_arch = "arm"))]
69120#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69121#[cfg_attr(test, assert_instr(st3))]
69122pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
69123    unsafe extern "unadjusted" {
69124        #[cfg_attr(
69125            any(target_arch = "aarch64", target_arch = "arm64ec"),
69126            link_name = "llvm.aarch64.neon.st3.v16i8.p0i8"
69127        )]
69128        fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
69129    }
69130    _vst3q_s8(b.0, b.1, b.2, a as _)
69131}
69132#[doc = "Store multiple 3-element structures from three registers"]
69133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
69134#[doc = "## Safety"]
69135#[doc = "  * Neon instrinsic unsafe"]
69136#[inline]
69137#[target_feature(enable = "neon")]
69138#[cfg(not(target_arch = "arm"))]
69139#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69140#[cfg_attr(test, assert_instr(st3))]
69141pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
69142    unsafe extern "unadjusted" {
69143        #[cfg_attr(
69144            any(target_arch = "aarch64", target_arch = "arm64ec"),
69145            link_name = "llvm.aarch64.neon.st3.v4i16.p0i8"
69146        )]
69147        fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
69148    }
69149    _vst3_s16(b.0, b.1, b.2, a as _)
69150}
69151#[doc = "Store multiple 3-element structures from three registers"]
69152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
69153#[doc = "## Safety"]
69154#[doc = "  * Neon instrinsic unsafe"]
69155#[inline]
69156#[target_feature(enable = "neon")]
69157#[cfg(not(target_arch = "arm"))]
69158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69159#[cfg_attr(test, assert_instr(st3))]
69160pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
69161    unsafe extern "unadjusted" {
69162        #[cfg_attr(
69163            any(target_arch = "aarch64", target_arch = "arm64ec"),
69164            link_name = "llvm.aarch64.neon.st3.v8i16.p0i8"
69165        )]
69166        fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
69167    }
69168    _vst3q_s16(b.0, b.1, b.2, a as _)
69169}
69170#[doc = "Store multiple 3-element structures from three registers"]
69171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
69172#[doc = "## Safety"]
69173#[doc = "  * Neon instrinsic unsafe"]
69174#[inline]
69175#[target_feature(enable = "neon")]
69176#[cfg(not(target_arch = "arm"))]
69177#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69178#[cfg_attr(test, assert_instr(st3))]
69179pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
69180    unsafe extern "unadjusted" {
69181        #[cfg_attr(
69182            any(target_arch = "aarch64", target_arch = "arm64ec"),
69183            link_name = "llvm.aarch64.neon.st3.v2i32.p0i8"
69184        )]
69185        fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
69186    }
69187    _vst3_s32(b.0, b.1, b.2, a as _)
69188}
69189#[doc = "Store multiple 3-element structures from three registers"]
69190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
69191#[doc = "## Safety"]
69192#[doc = "  * Neon instrinsic unsafe"]
69193#[inline]
69194#[target_feature(enable = "neon")]
69195#[cfg(not(target_arch = "arm"))]
69196#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69197#[cfg_attr(test, assert_instr(st3))]
69198pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
69199    unsafe extern "unadjusted" {
69200        #[cfg_attr(
69201            any(target_arch = "aarch64", target_arch = "arm64ec"),
69202            link_name = "llvm.aarch64.neon.st3.v4i32.p0i8"
69203        )]
69204        fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
69205    }
69206    _vst3q_s32(b.0, b.1, b.2, a as _)
69207}
69208#[doc = "Store multiple 3-element structures from three registers"]
69209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69210#[doc = "## Safety"]
69211#[doc = "  * Neon instrinsic unsafe"]
69212#[inline]
69213#[cfg(target_arch = "arm")]
69214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69215#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69216#[rustc_legacy_const_generics(2)]
69217#[target_feature(enable = "neon,fp16")]
69218#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69219pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69220    static_assert_uimm_bits!(LANE, 2);
69221    unsafe extern "unadjusted" {
69222        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f16")]
69223        fn _vst3_lane_f16(
69224            ptr: *mut i8,
69225            a: float16x4_t,
69226            b: float16x4_t,
69227            c: float16x4_t,
69228            n: i32,
69229            size: i32,
69230        );
69231    }
69232    _vst3_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69233}
69234#[doc = "Store multiple 3-element structures from three registers"]
69235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69236#[doc = "## Safety"]
69237#[doc = "  * Neon instrinsic unsafe"]
69238#[inline]
69239#[cfg(target_arch = "arm")]
69240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69241#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69242#[rustc_legacy_const_generics(2)]
69243#[target_feature(enable = "neon,fp16")]
69244#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69245pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69246    static_assert_uimm_bits!(LANE, 3);
69247    unsafe extern "unadjusted" {
69248        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8f16")]
69249        fn _vst3q_lane_f16(
69250            ptr: *mut i8,
69251            a: float16x8_t,
69252            b: float16x8_t,
69253            c: float16x8_t,
69254            n: i32,
69255            size: i32,
69256        );
69257    }
69258    _vst3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69259}
69260#[doc = "Store multiple 3-element structures from three registers"]
69261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69262#[doc = "## Safety"]
69263#[doc = "  * Neon instrinsic unsafe"]
69264#[inline]
69265#[cfg(not(target_arch = "arm"))]
69266#[rustc_legacy_const_generics(2)]
69267#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69268#[target_feature(enable = "neon,fp16")]
69269#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69270pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69271    static_assert_uimm_bits!(LANE, 2);
69272    unsafe extern "unadjusted" {
69273        #[cfg_attr(
69274            any(target_arch = "aarch64", target_arch = "arm64ec"),
69275            link_name = "llvm.aarch64.neon.st3lane.v4f16.p0i8"
69276        )]
69277        fn _vst3_lane_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, n: i64, ptr: *mut i8);
69278    }
69279    _vst3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69280}
69281#[doc = "Store multiple 3-element structures from three registers"]
69282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69283#[doc = "## Safety"]
69284#[doc = "  * Neon instrinsic unsafe"]
69285#[inline]
69286#[cfg(not(target_arch = "arm"))]
69287#[rustc_legacy_const_generics(2)]
69288#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69289#[target_feature(enable = "neon,fp16")]
69290#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69291pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69292    static_assert_uimm_bits!(LANE, 3);
69293    unsafe extern "unadjusted" {
69294        #[cfg_attr(
69295            any(target_arch = "aarch64", target_arch = "arm64ec"),
69296            link_name = "llvm.aarch64.neon.st3lane.v8f16.p0i8"
69297        )]
69298        fn _vst3q_lane_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, n: i64, ptr: *mut i8);
69299    }
69300    _vst3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69301}
69302#[doc = "Store multiple 3-element structures from three registers"]
69303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69304#[doc = "## Safety"]
69305#[doc = "  * Neon instrinsic unsafe"]
69306#[inline]
69307#[cfg(target_arch = "arm")]
69308#[target_feature(enable = "neon,v7")]
69309#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69310#[rustc_legacy_const_generics(2)]
69311#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69312pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69313    static_assert_uimm_bits!(LANE, 1);
69314    unsafe extern "unadjusted" {
69315        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2f32")]
69316        fn _vst3_lane_f32(
69317            ptr: *mut i8,
69318            a: float32x2_t,
69319            b: float32x2_t,
69320            c: float32x2_t,
69321            n: i32,
69322            size: i32,
69323        );
69324    }
69325    _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69326}
69327#[doc = "Store multiple 3-element structures from three registers"]
69328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69329#[doc = "## Safety"]
69330#[doc = "  * Neon instrinsic unsafe"]
69331#[inline]
69332#[cfg(target_arch = "arm")]
69333#[target_feature(enable = "neon,v7")]
69334#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69335#[rustc_legacy_const_generics(2)]
69336#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69337pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69338    static_assert_uimm_bits!(LANE, 2);
69339    unsafe extern "unadjusted" {
69340        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f32")]
69341        fn _vst3q_lane_f32(
69342            ptr: *mut i8,
69343            a: float32x4_t,
69344            b: float32x4_t,
69345            c: float32x4_t,
69346            n: i32,
69347            size: i32,
69348        );
69349    }
69350    _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69351}
69352#[doc = "Store multiple 3-element structures from three registers"]
69353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69354#[doc = "## Safety"]
69355#[doc = "  * Neon instrinsic unsafe"]
69356#[inline]
69357#[cfg(target_arch = "arm")]
69358#[target_feature(enable = "neon,v7")]
69359#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69360#[rustc_legacy_const_generics(2)]
69361#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69362pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69363    static_assert_uimm_bits!(LANE, 3);
69364    unsafe extern "unadjusted" {
69365        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")]
69366        fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
69367    }
69368    _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
69369}
69370#[doc = "Store multiple 3-element structures from three registers"]
69371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69372#[doc = "## Safety"]
69373#[doc = "  * Neon instrinsic unsafe"]
69374#[inline]
69375#[cfg(target_arch = "arm")]
69376#[target_feature(enable = "neon,v7")]
69377#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69378#[rustc_legacy_const_generics(2)]
69379#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69380pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69381    static_assert_uimm_bits!(LANE, 2);
69382    unsafe extern "unadjusted" {
69383        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i16")]
69384        fn _vst3_lane_s16(
69385            ptr: *mut i8,
69386            a: int16x4_t,
69387            b: int16x4_t,
69388            c: int16x4_t,
69389            n: i32,
69390            size: i32,
69391        );
69392    }
69393    _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69394}
69395#[doc = "Store multiple 3-element structures from three registers"]
69396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69397#[doc = "## Safety"]
69398#[doc = "  * Neon instrinsic unsafe"]
69399#[inline]
69400#[cfg(target_arch = "arm")]
69401#[target_feature(enable = "neon,v7")]
69402#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69403#[rustc_legacy_const_generics(2)]
69404#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69405pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69406    static_assert_uimm_bits!(LANE, 3);
69407    unsafe extern "unadjusted" {
69408        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i16")]
69409        fn _vst3q_lane_s16(
69410            ptr: *mut i8,
69411            a: int16x8_t,
69412            b: int16x8_t,
69413            c: int16x8_t,
69414            n: i32,
69415            size: i32,
69416        );
69417    }
69418    _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69419}
69420#[doc = "Store multiple 3-element structures from three registers"]
69421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69422#[doc = "## Safety"]
69423#[doc = "  * Neon instrinsic unsafe"]
69424#[inline]
69425#[cfg(target_arch = "arm")]
69426#[target_feature(enable = "neon,v7")]
69427#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69428#[rustc_legacy_const_generics(2)]
69429#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69430pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69431    static_assert_uimm_bits!(LANE, 1);
69432    unsafe extern "unadjusted" {
69433        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2i32")]
69434        fn _vst3_lane_s32(
69435            ptr: *mut i8,
69436            a: int32x2_t,
69437            b: int32x2_t,
69438            c: int32x2_t,
69439            n: i32,
69440            size: i32,
69441        );
69442    }
69443    _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69444}
69445#[doc = "Store multiple 3-element structures from three registers"]
69446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69447#[doc = "## Safety"]
69448#[doc = "  * Neon instrinsic unsafe"]
69449#[inline]
69450#[cfg(target_arch = "arm")]
69451#[target_feature(enable = "neon,v7")]
69452#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69453#[rustc_legacy_const_generics(2)]
69454#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69455pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69456    static_assert_uimm_bits!(LANE, 2);
69457    unsafe extern "unadjusted" {
69458        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i32")]
69459        fn _vst3q_lane_s32(
69460            ptr: *mut i8,
69461            a: int32x4_t,
69462            b: int32x4_t,
69463            c: int32x4_t,
69464            n: i32,
69465            size: i32,
69466        );
69467    }
69468    _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69469}
69470#[doc = "Store multiple 3-element structures from three registers"]
69471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69472#[doc = "## Safety"]
69473#[doc = "  * Neon instrinsic unsafe"]
69474#[inline]
69475#[target_feature(enable = "neon")]
69476#[cfg(not(target_arch = "arm"))]
69477#[rustc_legacy_const_generics(2)]
69478#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69479#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69480pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69481    static_assert_uimm_bits!(LANE, 1);
69482    unsafe extern "unadjusted" {
69483        #[cfg_attr(
69484            any(target_arch = "aarch64", target_arch = "arm64ec"),
69485            link_name = "llvm.aarch64.neon.st3lane.v2f32.p0i8"
69486        )]
69487        fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8);
69488    }
69489    _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69490}
69491#[doc = "Store multiple 3-element structures from three registers"]
69492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69493#[doc = "## Safety"]
69494#[doc = "  * Neon instrinsic unsafe"]
69495#[inline]
69496#[target_feature(enable = "neon")]
69497#[cfg(not(target_arch = "arm"))]
69498#[rustc_legacy_const_generics(2)]
69499#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69500#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69501pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69502    static_assert_uimm_bits!(LANE, 2);
69503    unsafe extern "unadjusted" {
69504        #[cfg_attr(
69505            any(target_arch = "aarch64", target_arch = "arm64ec"),
69506            link_name = "llvm.aarch64.neon.st3lane.v4f32.p0i8"
69507        )]
69508        fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8);
69509    }
69510    _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69511}
69512#[doc = "Store multiple 3-element structures from three registers"]
69513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69514#[doc = "## Safety"]
69515#[doc = "  * Neon instrinsic unsafe"]
69516#[inline]
69517#[target_feature(enable = "neon")]
69518#[cfg(not(target_arch = "arm"))]
69519#[rustc_legacy_const_generics(2)]
69520#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69521#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69522pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69523    static_assert_uimm_bits!(LANE, 3);
69524    unsafe extern "unadjusted" {
69525        #[cfg_attr(
69526            any(target_arch = "aarch64", target_arch = "arm64ec"),
69527            link_name = "llvm.aarch64.neon.st3lane.v8i8.p0i8"
69528        )]
69529        fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8);
69530    }
69531    _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
69532}
69533#[doc = "Store multiple 3-element structures from three registers"]
69534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69535#[doc = "## Safety"]
69536#[doc = "  * Neon instrinsic unsafe"]
69537#[inline]
69538#[target_feature(enable = "neon")]
69539#[cfg(not(target_arch = "arm"))]
69540#[rustc_legacy_const_generics(2)]
69541#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69542#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69543pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69544    static_assert_uimm_bits!(LANE, 2);
69545    unsafe extern "unadjusted" {
69546        #[cfg_attr(
69547            any(target_arch = "aarch64", target_arch = "arm64ec"),
69548            link_name = "llvm.aarch64.neon.st3lane.v4i16.p0i8"
69549        )]
69550        fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8);
69551    }
69552    _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69553}
69554#[doc = "Store multiple 3-element structures from three registers"]
69555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69556#[doc = "## Safety"]
69557#[doc = "  * Neon instrinsic unsafe"]
69558#[inline]
69559#[target_feature(enable = "neon")]
69560#[cfg(not(target_arch = "arm"))]
69561#[rustc_legacy_const_generics(2)]
69562#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69563#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69564pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69565    static_assert_uimm_bits!(LANE, 3);
69566    unsafe extern "unadjusted" {
69567        #[cfg_attr(
69568            any(target_arch = "aarch64", target_arch = "arm64ec"),
69569            link_name = "llvm.aarch64.neon.st3lane.v8i16.p0i8"
69570        )]
69571        fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8);
69572    }
69573    _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69574}
69575#[doc = "Store multiple 3-element structures from three registers"]
69576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69577#[doc = "## Safety"]
69578#[doc = "  * Neon instrinsic unsafe"]
69579#[inline]
69580#[target_feature(enable = "neon")]
69581#[cfg(not(target_arch = "arm"))]
69582#[rustc_legacy_const_generics(2)]
69583#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69584#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69585pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69586    static_assert_uimm_bits!(LANE, 1);
69587    unsafe extern "unadjusted" {
69588        #[cfg_attr(
69589            any(target_arch = "aarch64", target_arch = "arm64ec"),
69590            link_name = "llvm.aarch64.neon.st3lane.v2i32.p0i8"
69591        )]
69592        fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8);
69593    }
69594    _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69595}
69596#[doc = "Store multiple 3-element structures from three registers"]
69597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69598#[doc = "## Safety"]
69599#[doc = "  * Neon instrinsic unsafe"]
69600#[inline]
69601#[target_feature(enable = "neon")]
69602#[cfg(not(target_arch = "arm"))]
69603#[rustc_legacy_const_generics(2)]
69604#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69605#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69606pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69607    static_assert_uimm_bits!(LANE, 2);
69608    unsafe extern "unadjusted" {
69609        #[cfg_attr(
69610            any(target_arch = "aarch64", target_arch = "arm64ec"),
69611            link_name = "llvm.aarch64.neon.st3lane.v4i32.p0i8"
69612        )]
69613        fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8);
69614    }
69615    _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69616}
69617#[doc = "Store multiple 3-element structures from three registers"]
69618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
69619#[doc = "## Safety"]
69620#[doc = "  * Neon instrinsic unsafe"]
69621#[inline]
69622#[target_feature(enable = "neon")]
69623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69625#[cfg_attr(
69626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69627    assert_instr(st3, LANE = 0)
69628)]
69629#[rustc_legacy_const_generics(2)]
69630#[cfg_attr(
69631    not(target_arch = "arm"),
69632    stable(feature = "neon_intrinsics", since = "1.59.0")
69633)]
69634#[cfg_attr(
69635    target_arch = "arm",
69636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69637)]
69638pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
69639    static_assert_uimm_bits!(LANE, 3);
69640    vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69641}
69642#[doc = "Store multiple 3-element structures from three registers"]
69643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
69644#[doc = "## Safety"]
69645#[doc = "  * Neon instrinsic unsafe"]
69646#[inline]
69647#[target_feature(enable = "neon")]
69648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69650#[cfg_attr(
69651    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69652    assert_instr(st3, LANE = 0)
69653)]
69654#[rustc_legacy_const_generics(2)]
69655#[cfg_attr(
69656    not(target_arch = "arm"),
69657    stable(feature = "neon_intrinsics", since = "1.59.0")
69658)]
69659#[cfg_attr(
69660    target_arch = "arm",
69661    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69662)]
69663pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
69664    static_assert_uimm_bits!(LANE, 2);
69665    vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69666}
69667#[doc = "Store multiple 3-element structures from three registers"]
69668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
69669#[doc = "## Safety"]
69670#[doc = "  * Neon instrinsic unsafe"]
69671#[inline]
69672#[target_feature(enable = "neon")]
69673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69675#[cfg_attr(
69676    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69677    assert_instr(st3, LANE = 0)
69678)]
69679#[rustc_legacy_const_generics(2)]
69680#[cfg_attr(
69681    not(target_arch = "arm"),
69682    stable(feature = "neon_intrinsics", since = "1.59.0")
69683)]
69684#[cfg_attr(
69685    target_arch = "arm",
69686    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69687)]
69688pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
69689    static_assert_uimm_bits!(LANE, 3);
69690    vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69691}
69692#[doc = "Store multiple 3-element structures from three registers"]
69693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
69694#[doc = "## Safety"]
69695#[doc = "  * Neon instrinsic unsafe"]
69696#[inline]
69697#[target_feature(enable = "neon")]
69698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69700#[cfg_attr(
69701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69702    assert_instr(st3, LANE = 0)
69703)]
69704#[rustc_legacy_const_generics(2)]
69705#[cfg_attr(
69706    not(target_arch = "arm"),
69707    stable(feature = "neon_intrinsics", since = "1.59.0")
69708)]
69709#[cfg_attr(
69710    target_arch = "arm",
69711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69712)]
69713pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
69714    static_assert_uimm_bits!(LANE, 1);
69715    vst3_lane_s32::<LANE>(transmute(a), transmute(b))
69716}
69717#[doc = "Store multiple 3-element structures from three registers"]
69718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
69719#[doc = "## Safety"]
69720#[doc = "  * Neon instrinsic unsafe"]
69721#[inline]
69722#[target_feature(enable = "neon")]
69723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69725#[cfg_attr(
69726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69727    assert_instr(st3, LANE = 0)
69728)]
69729#[rustc_legacy_const_generics(2)]
69730#[cfg_attr(
69731    not(target_arch = "arm"),
69732    stable(feature = "neon_intrinsics", since = "1.59.0")
69733)]
69734#[cfg_attr(
69735    target_arch = "arm",
69736    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69737)]
69738pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
69739    static_assert_uimm_bits!(LANE, 2);
69740    vst3q_lane_s32::<LANE>(transmute(a), transmute(b))
69741}
69742#[doc = "Store multiple 3-element structures from three registers"]
69743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
69744#[doc = "## Safety"]
69745#[doc = "  * Neon instrinsic unsafe"]
69746#[inline]
69747#[target_feature(enable = "neon")]
69748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69750#[cfg_attr(
69751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69752    assert_instr(st3, LANE = 0)
69753)]
69754#[rustc_legacy_const_generics(2)]
69755#[cfg_attr(
69756    not(target_arch = "arm"),
69757    stable(feature = "neon_intrinsics", since = "1.59.0")
69758)]
69759#[cfg_attr(
69760    target_arch = "arm",
69761    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69762)]
69763pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
69764    static_assert_uimm_bits!(LANE, 3);
69765    vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69766}
69767#[doc = "Store multiple 3-element structures from three registers"]
69768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
69769#[doc = "## Safety"]
69770#[doc = "  * Neon instrinsic unsafe"]
69771#[inline]
69772#[target_feature(enable = "neon")]
69773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69775#[cfg_attr(
69776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69777    assert_instr(st3, LANE = 0)
69778)]
69779#[rustc_legacy_const_generics(2)]
69780#[cfg_attr(
69781    not(target_arch = "arm"),
69782    stable(feature = "neon_intrinsics", since = "1.59.0")
69783)]
69784#[cfg_attr(
69785    target_arch = "arm",
69786    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69787)]
69788pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
69789    static_assert_uimm_bits!(LANE, 2);
69790    vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69791}
69792#[doc = "Store multiple 3-element structures from three registers"]
69793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
69794#[doc = "## Safety"]
69795#[doc = "  * Neon instrinsic unsafe"]
69796#[inline]
69797#[target_feature(enable = "neon")]
69798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69800#[cfg_attr(
69801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69802    assert_instr(st3, LANE = 0)
69803)]
69804#[rustc_legacy_const_generics(2)]
69805#[cfg_attr(
69806    not(target_arch = "arm"),
69807    stable(feature = "neon_intrinsics", since = "1.59.0")
69808)]
69809#[cfg_attr(
69810    target_arch = "arm",
69811    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69812)]
69813pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
69814    static_assert_uimm_bits!(LANE, 3);
69815    vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69816}
69817#[doc = "Store multiple 3-element structures from three registers"]
69818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
69819#[doc = "## Safety"]
69820#[doc = "  * Neon instrinsic unsafe"]
69821#[inline]
69822#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
69823#[target_feature(enable = "neon,aes")]
69824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69825#[cfg_attr(
69826    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69827    assert_instr(nop)
69828)]
69829#[cfg_attr(
69830    not(target_arch = "arm"),
69831    stable(feature = "neon_intrinsics", since = "1.59.0")
69832)]
69833#[cfg_attr(
69834    target_arch = "arm",
69835    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69836)]
69837pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
69838    vst3_s64(transmute(a), transmute(b))
69839}
69840#[doc = "Store multiple 3-element structures from three registers"]
69841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69842#[doc = "## Safety"]
69843#[doc = "  * Neon instrinsic unsafe"]
69844#[inline]
69845#[target_feature(enable = "neon")]
69846#[cfg(not(target_arch = "arm"))]
69847#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69848#[cfg_attr(test, assert_instr(nop))]
69849pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69850    unsafe extern "unadjusted" {
69851        #[cfg_attr(
69852            any(target_arch = "aarch64", target_arch = "arm64ec"),
69853            link_name = "llvm.aarch64.neon.st3.v1i64.p0i8"
69854        )]
69855        fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
69856    }
69857    _vst3_s64(b.0, b.1, b.2, a as _)
69858}
69859#[doc = "Store multiple 3-element structures from three registers"]
69860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69861#[doc = "## Safety"]
69862#[doc = "  * Neon instrinsic unsafe"]
69863#[inline]
69864#[cfg(target_arch = "arm")]
69865#[target_feature(enable = "neon,v7")]
69866#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69867#[cfg_attr(test, assert_instr(nop))]
69868pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69869    unsafe extern "unadjusted" {
69870        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v1i64")]
69871        fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
69872    }
69873    _vst3_s64(a as _, b.0, b.1, b.2, 8)
69874}
69875#[doc = "Store multiple 3-element structures from three registers"]
69876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
69877#[doc = "## Safety"]
69878#[doc = "  * Neon instrinsic unsafe"]
69879#[inline]
69880#[target_feature(enable = "neon")]
69881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69883#[cfg_attr(
69884    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69885    assert_instr(nop)
69886)]
69887#[cfg_attr(
69888    not(target_arch = "arm"),
69889    stable(feature = "neon_intrinsics", since = "1.59.0")
69890)]
69891#[cfg_attr(
69892    target_arch = "arm",
69893    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69894)]
69895pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
69896    vst3_s64(transmute(a), transmute(b))
69897}
69898#[doc = "Store multiple 3-element structures from three registers"]
69899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
69900#[doc = "## Safety"]
69901#[doc = "  * Neon instrinsic unsafe"]
69902#[inline]
69903#[target_feature(enable = "neon")]
69904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69906#[cfg_attr(
69907    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69908    assert_instr(st3)
69909)]
69910#[cfg_attr(
69911    not(target_arch = "arm"),
69912    stable(feature = "neon_intrinsics", since = "1.59.0")
69913)]
69914#[cfg_attr(
69915    target_arch = "arm",
69916    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69917)]
69918pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
69919    vst3_s8(transmute(a), transmute(b))
69920}
69921#[doc = "Store multiple 3-element structures from three registers"]
69922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
69923#[doc = "## Safety"]
69924#[doc = "  * Neon instrinsic unsafe"]
69925#[inline]
69926#[target_feature(enable = "neon")]
69927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69929#[cfg_attr(
69930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69931    assert_instr(st3)
69932)]
69933#[cfg_attr(
69934    not(target_arch = "arm"),
69935    stable(feature = "neon_intrinsics", since = "1.59.0")
69936)]
69937#[cfg_attr(
69938    target_arch = "arm",
69939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69940)]
69941pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
69942    vst3q_s8(transmute(a), transmute(b))
69943}
69944#[doc = "Store multiple 3-element structures from three registers"]
69945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
69946#[doc = "## Safety"]
69947#[doc = "  * Neon instrinsic unsafe"]
69948#[inline]
69949#[target_feature(enable = "neon")]
69950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69952#[cfg_attr(
69953    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69954    assert_instr(st3)
69955)]
69956#[cfg_attr(
69957    not(target_arch = "arm"),
69958    stable(feature = "neon_intrinsics", since = "1.59.0")
69959)]
69960#[cfg_attr(
69961    target_arch = "arm",
69962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69963)]
69964pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
69965    vst3_s16(transmute(a), transmute(b))
69966}
69967#[doc = "Store multiple 3-element structures from three registers"]
69968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
69969#[doc = "## Safety"]
69970#[doc = "  * Neon instrinsic unsafe"]
69971#[inline]
69972#[target_feature(enable = "neon")]
69973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69975#[cfg_attr(
69976    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69977    assert_instr(st3)
69978)]
69979#[cfg_attr(
69980    not(target_arch = "arm"),
69981    stable(feature = "neon_intrinsics", since = "1.59.0")
69982)]
69983#[cfg_attr(
69984    target_arch = "arm",
69985    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69986)]
69987pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
69988    vst3q_s16(transmute(a), transmute(b))
69989}
69990#[doc = "Store multiple 3-element structures from three registers"]
69991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
69992#[doc = "## Safety"]
69993#[doc = "  * Neon instrinsic unsafe"]
69994#[inline]
69995#[target_feature(enable = "neon")]
69996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69998#[cfg_attr(
69999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70000    assert_instr(st3)
70001)]
70002#[cfg_attr(
70003    not(target_arch = "arm"),
70004    stable(feature = "neon_intrinsics", since = "1.59.0")
70005)]
70006#[cfg_attr(
70007    target_arch = "arm",
70008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70009)]
70010pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
70011    vst3_s32(transmute(a), transmute(b))
70012}
70013#[doc = "Store multiple 3-element structures from three registers"]
70014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
70015#[doc = "## Safety"]
70016#[doc = "  * Neon instrinsic unsafe"]
70017#[inline]
70018#[target_feature(enable = "neon")]
70019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70021#[cfg_attr(
70022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70023    assert_instr(st3)
70024)]
70025#[cfg_attr(
70026    not(target_arch = "arm"),
70027    stable(feature = "neon_intrinsics", since = "1.59.0")
70028)]
70029#[cfg_attr(
70030    target_arch = "arm",
70031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70032)]
70033pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
70034    vst3q_s32(transmute(a), transmute(b))
70035}
70036#[doc = "Store multiple 3-element structures from three registers"]
70037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
70038#[doc = "## Safety"]
70039#[doc = "  * Neon instrinsic unsafe"]
70040#[inline]
70041#[target_feature(enable = "neon")]
70042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70044#[cfg_attr(
70045    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70046    assert_instr(st3)
70047)]
70048#[cfg_attr(
70049    not(target_arch = "arm"),
70050    stable(feature = "neon_intrinsics", since = "1.59.0")
70051)]
70052#[cfg_attr(
70053    target_arch = "arm",
70054    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70055)]
70056pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
70057    vst3_s8(transmute(a), transmute(b))
70058}
70059#[doc = "Store multiple 3-element structures from three registers"]
70060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
70061#[doc = "## Safety"]
70062#[doc = "  * Neon instrinsic unsafe"]
70063#[inline]
70064#[target_feature(enable = "neon")]
70065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70067#[cfg_attr(
70068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70069    assert_instr(st3)
70070)]
70071#[cfg_attr(
70072    not(target_arch = "arm"),
70073    stable(feature = "neon_intrinsics", since = "1.59.0")
70074)]
70075#[cfg_attr(
70076    target_arch = "arm",
70077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70078)]
70079pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
70080    vst3q_s8(transmute(a), transmute(b))
70081}
70082#[doc = "Store multiple 3-element structures from three registers"]
70083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
70084#[doc = "## Safety"]
70085#[doc = "  * Neon instrinsic unsafe"]
70086#[inline]
70087#[target_feature(enable = "neon")]
70088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70090#[cfg_attr(
70091    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70092    assert_instr(st3)
70093)]
70094#[cfg_attr(
70095    not(target_arch = "arm"),
70096    stable(feature = "neon_intrinsics", since = "1.59.0")
70097)]
70098#[cfg_attr(
70099    target_arch = "arm",
70100    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70101)]
70102pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
70103    vst3_s16(transmute(a), transmute(b))
70104}
70105#[doc = "Store multiple 3-element structures from three registers"]
70106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
70107#[doc = "## Safety"]
70108#[doc = "  * Neon instrinsic unsafe"]
70109#[inline]
70110#[target_feature(enable = "neon")]
70111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70113#[cfg_attr(
70114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70115    assert_instr(st3)
70116)]
70117#[cfg_attr(
70118    not(target_arch = "arm"),
70119    stable(feature = "neon_intrinsics", since = "1.59.0")
70120)]
70121#[cfg_attr(
70122    target_arch = "arm",
70123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70124)]
70125pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
70126    vst3q_s16(transmute(a), transmute(b))
70127}
70128#[doc = "Store multiple 4-element structures from four registers"]
70129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70130#[doc = "## Safety"]
70131#[doc = "  * Neon instrinsic unsafe"]
70132#[inline]
70133#[cfg(target_arch = "arm")]
70134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70135#[target_feature(enable = "neon,fp16")]
70136#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70137#[cfg_attr(test, assert_instr(vst4))]
70138pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70139    unsafe extern "unadjusted" {
70140        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f16")]
70141        fn _vst4_f16(
70142            ptr: *mut i8,
70143            a: float16x4_t,
70144            b: float16x4_t,
70145            c: float16x4_t,
70146            d: float16x4_t,
70147            size: i32,
70148        );
70149    }
70150    _vst4_f16(a as _, b.0, b.1, b.2, b.3, 2)
70151}
70152#[doc = "Store multiple 4-element structures from four registers"]
70153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70154#[doc = "## Safety"]
70155#[doc = "  * Neon instrinsic unsafe"]
70156#[inline]
70157#[cfg(target_arch = "arm")]
70158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70159#[target_feature(enable = "neon,fp16")]
70160#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70161#[cfg_attr(test, assert_instr(vst4))]
70162pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70163    unsafe extern "unadjusted" {
70164        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8f16")]
70165        fn _vst4q_f16(
70166            ptr: *mut i8,
70167            a: float16x8_t,
70168            b: float16x8_t,
70169            c: float16x8_t,
70170            d: float16x8_t,
70171            size: i32,
70172        );
70173    }
70174    _vst4q_f16(a as _, b.0, b.1, b.2, b.3, 2)
70175}
70176#[doc = "Store multiple 4-element structures from four registers"]
70177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70178#[doc = "## Safety"]
70179#[doc = "  * Neon instrinsic unsafe"]
70180#[inline]
70181#[cfg(not(target_arch = "arm"))]
70182#[target_feature(enable = "neon,fp16")]
70183#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70184#[cfg_attr(test, assert_instr(st4))]
70185pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70186    unsafe extern "unadjusted" {
70187        #[cfg_attr(
70188            any(target_arch = "aarch64", target_arch = "arm64ec"),
70189            link_name = "llvm.aarch64.neon.st4.v4f16.p0i8"
70190        )]
70191        fn _vst4_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, d: float16x4_t, ptr: *mut i8);
70192    }
70193    _vst4_f16(b.0, b.1, b.2, b.3, a as _)
70194}
70195#[doc = "Store multiple 4-element structures from four registers"]
70196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70197#[doc = "## Safety"]
70198#[doc = "  * Neon instrinsic unsafe"]
70199#[inline]
70200#[cfg(not(target_arch = "arm"))]
70201#[target_feature(enable = "neon,fp16")]
70202#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70203#[cfg_attr(test, assert_instr(st4))]
70204pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70205    unsafe extern "unadjusted" {
70206        #[cfg_attr(
70207            any(target_arch = "aarch64", target_arch = "arm64ec"),
70208            link_name = "llvm.aarch64.neon.st4.v8f16.p0i8"
70209        )]
70210        fn _vst4q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, d: float16x8_t, ptr: *mut i8);
70211    }
70212    _vst4q_f16(b.0, b.1, b.2, b.3, a as _)
70213}
70214#[doc = "Store multiple 4-element structures from four registers"]
70215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70216#[doc = "## Safety"]
70217#[doc = "  * Neon instrinsic unsafe"]
70218#[inline]
70219#[cfg(target_arch = "arm")]
70220#[target_feature(enable = "neon,v7")]
70221#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70222#[cfg_attr(test, assert_instr(vst4))]
70223pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70224    unsafe extern "unadjusted" {
70225        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2f32")]
70226        fn _vst4_f32(
70227            ptr: *mut i8,
70228            a: float32x2_t,
70229            b: float32x2_t,
70230            c: float32x2_t,
70231            d: float32x2_t,
70232            size: i32,
70233        );
70234    }
70235    _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4)
70236}
70237#[doc = "Store multiple 4-element structures from four registers"]
70238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70239#[doc = "## Safety"]
70240#[doc = "  * Neon instrinsic unsafe"]
70241#[inline]
70242#[cfg(target_arch = "arm")]
70243#[target_feature(enable = "neon,v7")]
70244#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70245#[cfg_attr(test, assert_instr(vst4))]
70246pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70247    unsafe extern "unadjusted" {
70248        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f32")]
70249        fn _vst4q_f32(
70250            ptr: *mut i8,
70251            a: float32x4_t,
70252            b: float32x4_t,
70253            c: float32x4_t,
70254            d: float32x4_t,
70255            size: i32,
70256        );
70257    }
70258    _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4)
70259}
70260#[doc = "Store multiple 4-element structures from four registers"]
70261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70262#[doc = "## Safety"]
70263#[doc = "  * Neon instrinsic unsafe"]
70264#[inline]
70265#[cfg(target_arch = "arm")]
70266#[target_feature(enable = "neon,v7")]
70267#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70268#[cfg_attr(test, assert_instr(vst4))]
70269pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70270    unsafe extern "unadjusted" {
70271        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i8")]
70272        fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32);
70273    }
70274    _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1)
70275}
70276#[doc = "Store multiple 4-element structures from four registers"]
70277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70278#[doc = "## Safety"]
70279#[doc = "  * Neon instrinsic unsafe"]
70280#[inline]
70281#[cfg(target_arch = "arm")]
70282#[target_feature(enable = "neon,v7")]
70283#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70284#[cfg_attr(test, assert_instr(vst4))]
70285pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70286    unsafe extern "unadjusted" {
70287        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v16i8")]
70288        fn _vst4q_s8(
70289            ptr: *mut i8,
70290            a: int8x16_t,
70291            b: int8x16_t,
70292            c: int8x16_t,
70293            d: int8x16_t,
70294            size: i32,
70295        );
70296    }
70297    _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1)
70298}
70299#[doc = "Store multiple 4-element structures from four registers"]
70300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70301#[doc = "## Safety"]
70302#[doc = "  * Neon instrinsic unsafe"]
70303#[inline]
70304#[cfg(target_arch = "arm")]
70305#[target_feature(enable = "neon,v7")]
70306#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70307#[cfg_attr(test, assert_instr(vst4))]
70308pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70309    unsafe extern "unadjusted" {
70310        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i16")]
70311        fn _vst4_s16(
70312            ptr: *mut i8,
70313            a: int16x4_t,
70314            b: int16x4_t,
70315            c: int16x4_t,
70316            d: int16x4_t,
70317            size: i32,
70318        );
70319    }
70320    _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2)
70321}
70322#[doc = "Store multiple 4-element structures from four registers"]
70323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70324#[doc = "## Safety"]
70325#[doc = "  * Neon instrinsic unsafe"]
70326#[inline]
70327#[cfg(target_arch = "arm")]
70328#[target_feature(enable = "neon,v7")]
70329#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70330#[cfg_attr(test, assert_instr(vst4))]
70331pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70332    unsafe extern "unadjusted" {
70333        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i16")]
70334        fn _vst4q_s16(
70335            ptr: *mut i8,
70336            a: int16x8_t,
70337            b: int16x8_t,
70338            c: int16x8_t,
70339            d: int16x8_t,
70340            size: i32,
70341        );
70342    }
70343    _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2)
70344}
70345#[doc = "Store multiple 4-element structures from four registers"]
70346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70347#[doc = "## Safety"]
70348#[doc = "  * Neon instrinsic unsafe"]
70349#[inline]
70350#[cfg(target_arch = "arm")]
70351#[target_feature(enable = "neon,v7")]
70352#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70353#[cfg_attr(test, assert_instr(vst4))]
70354pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70355    unsafe extern "unadjusted" {
70356        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2i32")]
70357        fn _vst4_s32(
70358            ptr: *mut i8,
70359            a: int32x2_t,
70360            b: int32x2_t,
70361            c: int32x2_t,
70362            d: int32x2_t,
70363            size: i32,
70364        );
70365    }
70366    _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4)
70367}
70368#[doc = "Store multiple 4-element structures from four registers"]
70369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70370#[doc = "## Safety"]
70371#[doc = "  * Neon instrinsic unsafe"]
70372#[inline]
70373#[cfg(target_arch = "arm")]
70374#[target_feature(enable = "neon,v7")]
70375#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70376#[cfg_attr(test, assert_instr(vst4))]
70377pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70378    unsafe extern "unadjusted" {
70379        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i32")]
70380        fn _vst4q_s32(
70381            ptr: *mut i8,
70382            a: int32x4_t,
70383            b: int32x4_t,
70384            c: int32x4_t,
70385            d: int32x4_t,
70386            size: i32,
70387        );
70388    }
70389    _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4)
70390}
70391#[doc = "Store multiple 4-element structures from four registers"]
70392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70393#[doc = "## Safety"]
70394#[doc = "  * Neon instrinsic unsafe"]
70395#[inline]
70396#[target_feature(enable = "neon")]
70397#[cfg(not(target_arch = "arm"))]
70398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70399#[cfg_attr(test, assert_instr(st4))]
70400pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70401    unsafe extern "unadjusted" {
70402        #[cfg_attr(
70403            any(target_arch = "aarch64", target_arch = "arm64ec"),
70404            link_name = "llvm.aarch64.neon.st4.v2f32.p0i8"
70405        )]
70406        fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
70407    }
70408    _vst4_f32(b.0, b.1, b.2, b.3, a as _)
70409}
70410#[doc = "Store multiple 4-element structures from four registers"]
70411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70412#[doc = "## Safety"]
70413#[doc = "  * Neon instrinsic unsafe"]
70414#[inline]
70415#[target_feature(enable = "neon")]
70416#[cfg(not(target_arch = "arm"))]
70417#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70418#[cfg_attr(test, assert_instr(st4))]
70419pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70420    unsafe extern "unadjusted" {
70421        #[cfg_attr(
70422            any(target_arch = "aarch64", target_arch = "arm64ec"),
70423            link_name = "llvm.aarch64.neon.st4.v4f32.p0i8"
70424        )]
70425        fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
70426    }
70427    _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
70428}
70429#[doc = "Store multiple 4-element structures from four registers"]
70430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70431#[doc = "## Safety"]
70432#[doc = "  * Neon instrinsic unsafe"]
70433#[inline]
70434#[target_feature(enable = "neon")]
70435#[cfg(not(target_arch = "arm"))]
70436#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70437#[cfg_attr(test, assert_instr(st4))]
70438pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70439    unsafe extern "unadjusted" {
70440        #[cfg_attr(
70441            any(target_arch = "aarch64", target_arch = "arm64ec"),
70442            link_name = "llvm.aarch64.neon.st4.v8i8.p0i8"
70443        )]
70444        fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
70445    }
70446    _vst4_s8(b.0, b.1, b.2, b.3, a as _)
70447}
70448#[doc = "Store multiple 4-element structures from four registers"]
70449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70450#[doc = "## Safety"]
70451#[doc = "  * Neon instrinsic unsafe"]
70452#[inline]
70453#[target_feature(enable = "neon")]
70454#[cfg(not(target_arch = "arm"))]
70455#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70456#[cfg_attr(test, assert_instr(st4))]
70457pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70458    unsafe extern "unadjusted" {
70459        #[cfg_attr(
70460            any(target_arch = "aarch64", target_arch = "arm64ec"),
70461            link_name = "llvm.aarch64.neon.st4.v16i8.p0i8"
70462        )]
70463        fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
70464    }
70465    _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
70466}
70467#[doc = "Store multiple 4-element structures from four registers"]
70468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70469#[doc = "## Safety"]
70470#[doc = "  * Neon instrinsic unsafe"]
70471#[inline]
70472#[target_feature(enable = "neon")]
70473#[cfg(not(target_arch = "arm"))]
70474#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70475#[cfg_attr(test, assert_instr(st4))]
70476pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70477    unsafe extern "unadjusted" {
70478        #[cfg_attr(
70479            any(target_arch = "aarch64", target_arch = "arm64ec"),
70480            link_name = "llvm.aarch64.neon.st4.v4i16.p0i8"
70481        )]
70482        fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
70483    }
70484    _vst4_s16(b.0, b.1, b.2, b.3, a as _)
70485}
70486#[doc = "Store multiple 4-element structures from four registers"]
70487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70488#[doc = "## Safety"]
70489#[doc = "  * Neon instrinsic unsafe"]
70490#[inline]
70491#[target_feature(enable = "neon")]
70492#[cfg(not(target_arch = "arm"))]
70493#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70494#[cfg_attr(test, assert_instr(st4))]
70495pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70496    unsafe extern "unadjusted" {
70497        #[cfg_attr(
70498            any(target_arch = "aarch64", target_arch = "arm64ec"),
70499            link_name = "llvm.aarch64.neon.st4.v8i16.p0i8"
70500        )]
70501        fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
70502    }
70503    _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
70504}
70505#[doc = "Store multiple 4-element structures from four registers"]
70506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70507#[doc = "## Safety"]
70508#[doc = "  * Neon instrinsic unsafe"]
70509#[inline]
70510#[target_feature(enable = "neon")]
70511#[cfg(not(target_arch = "arm"))]
70512#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70513#[cfg_attr(test, assert_instr(st4))]
70514pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70515    unsafe extern "unadjusted" {
70516        #[cfg_attr(
70517            any(target_arch = "aarch64", target_arch = "arm64ec"),
70518            link_name = "llvm.aarch64.neon.st4.v2i32.p0i8"
70519        )]
70520        fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
70521    }
70522    _vst4_s32(b.0, b.1, b.2, b.3, a as _)
70523}
70524#[doc = "Store multiple 4-element structures from four registers"]
70525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70526#[doc = "## Safety"]
70527#[doc = "  * Neon instrinsic unsafe"]
70528#[inline]
70529#[target_feature(enable = "neon")]
70530#[cfg(not(target_arch = "arm"))]
70531#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70532#[cfg_attr(test, assert_instr(st4))]
70533pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70534    unsafe extern "unadjusted" {
70535        #[cfg_attr(
70536            any(target_arch = "aarch64", target_arch = "arm64ec"),
70537            link_name = "llvm.aarch64.neon.st4.v4i32.p0i8"
70538        )]
70539        fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
70540    }
70541    _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
70542}
70543#[doc = "Store multiple 4-element structures from four registers"]
70544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70545#[doc = "## Safety"]
70546#[doc = "  * Neon instrinsic unsafe"]
70547#[inline]
70548#[cfg(target_arch = "arm")]
70549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70550#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70551#[rustc_legacy_const_generics(2)]
70552#[target_feature(enable = "neon,fp16")]
70553#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70554pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70555    static_assert_uimm_bits!(LANE, 2);
70556    unsafe extern "unadjusted" {
70557        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f16")]
70558        fn _vst4_lane_f16(
70559            ptr: *mut i8,
70560            a: float16x4_t,
70561            b: float16x4_t,
70562            c: float16x4_t,
70563            d: float16x4_t,
70564            n: i32,
70565            size: i32,
70566        );
70567    }
70568    _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70569}
70570#[doc = "Store multiple 4-element structures from four registers"]
70571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70572#[doc = "## Safety"]
70573#[doc = "  * Neon instrinsic unsafe"]
70574#[inline]
70575#[cfg(target_arch = "arm")]
70576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70577#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70578#[rustc_legacy_const_generics(2)]
70579#[target_feature(enable = "neon,fp16")]
70580#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70581pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70582    static_assert_uimm_bits!(LANE, 3);
70583    unsafe extern "unadjusted" {
70584        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8f16")]
70585        fn _vst4q_lane_f16(
70586            ptr: *mut i8,
70587            a: float16x8_t,
70588            b: float16x8_t,
70589            c: float16x8_t,
70590            d: float16x8_t,
70591            n: i32,
70592            size: i32,
70593        );
70594    }
70595    _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70596}
70597#[doc = "Store multiple 4-element structures from four registers"]
70598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70599#[doc = "## Safety"]
70600#[doc = "  * Neon instrinsic unsafe"]
70601#[inline]
70602#[cfg(not(target_arch = "arm"))]
70603#[rustc_legacy_const_generics(2)]
70604#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70605#[target_feature(enable = "neon,fp16")]
70606#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70607pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70608    static_assert_uimm_bits!(LANE, 2);
70609    unsafe extern "unadjusted" {
70610        #[cfg_attr(
70611            any(target_arch = "aarch64", target_arch = "arm64ec"),
70612            link_name = "llvm.aarch64.neon.st4lane.v4f16.p0i8"
70613        )]
70614        fn _vst4_lane_f16(
70615            a: float16x4_t,
70616            b: float16x4_t,
70617            c: float16x4_t,
70618            d: float16x4_t,
70619            n: i64,
70620            ptr: *mut i8,
70621        );
70622    }
70623    _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70624}
70625#[doc = "Store multiple 4-element structures from four registers"]
70626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70627#[doc = "## Safety"]
70628#[doc = "  * Neon instrinsic unsafe"]
70629#[inline]
70630#[cfg(not(target_arch = "arm"))]
70631#[rustc_legacy_const_generics(2)]
70632#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70633#[target_feature(enable = "neon,fp16")]
70634#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70635pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70636    static_assert_uimm_bits!(LANE, 3);
70637    unsafe extern "unadjusted" {
70638        #[cfg_attr(
70639            any(target_arch = "aarch64", target_arch = "arm64ec"),
70640            link_name = "llvm.aarch64.neon.st4lane.v8f16.p0i8"
70641        )]
70642        fn _vst4q_lane_f16(
70643            a: float16x8_t,
70644            b: float16x8_t,
70645            c: float16x8_t,
70646            d: float16x8_t,
70647            n: i64,
70648            ptr: *mut i8,
70649        );
70650    }
70651    _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70652}
70653#[doc = "Store multiple 4-element structures from four registers"]
70654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70655#[doc = "## Safety"]
70656#[doc = "  * Neon instrinsic unsafe"]
70657#[inline]
70658#[cfg(target_arch = "arm")]
70659#[target_feature(enable = "neon,v7")]
70660#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70661#[rustc_legacy_const_generics(2)]
70662#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70663pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70664    static_assert_uimm_bits!(LANE, 1);
70665    unsafe extern "unadjusted" {
70666        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2f32")]
70667        fn _vst4_lane_f32(
70668            ptr: *mut i8,
70669            a: float32x2_t,
70670            b: float32x2_t,
70671            c: float32x2_t,
70672            d: float32x2_t,
70673            n: i32,
70674            size: i32,
70675        );
70676    }
70677    _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70678}
70679#[doc = "Store multiple 4-element structures from four registers"]
70680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70681#[doc = "## Safety"]
70682#[doc = "  * Neon instrinsic unsafe"]
70683#[inline]
70684#[cfg(target_arch = "arm")]
70685#[target_feature(enable = "neon,v7")]
70686#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70687#[rustc_legacy_const_generics(2)]
70688#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70689pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70690    static_assert_uimm_bits!(LANE, 2);
70691    unsafe extern "unadjusted" {
70692        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f32")]
70693        fn _vst4q_lane_f32(
70694            ptr: *mut i8,
70695            a: float32x4_t,
70696            b: float32x4_t,
70697            c: float32x4_t,
70698            d: float32x4_t,
70699            n: i32,
70700            size: i32,
70701        );
70702    }
70703    _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70704}
70705#[doc = "Store multiple 4-element structures from four registers"]
70706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70707#[doc = "## Safety"]
70708#[doc = "  * Neon instrinsic unsafe"]
70709#[inline]
70710#[cfg(target_arch = "arm")]
70711#[target_feature(enable = "neon,v7")]
70712#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70713#[rustc_legacy_const_generics(2)]
70714#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70715pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70716    static_assert_uimm_bits!(LANE, 3);
70717    unsafe extern "unadjusted" {
70718        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i8")]
70719        fn _vst4_lane_s8(
70720            ptr: *mut i8,
70721            a: int8x8_t,
70722            b: int8x8_t,
70723            c: int8x8_t,
70724            d: int8x8_t,
70725            n: i32,
70726            size: i32,
70727        );
70728    }
70729    _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
70730}
70731#[doc = "Store multiple 4-element structures from four registers"]
70732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70733#[doc = "## Safety"]
70734#[doc = "  * Neon instrinsic unsafe"]
70735#[inline]
70736#[cfg(target_arch = "arm")]
70737#[target_feature(enable = "neon,v7")]
70738#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70739#[rustc_legacy_const_generics(2)]
70740#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70741pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70742    static_assert_uimm_bits!(LANE, 2);
70743    unsafe extern "unadjusted" {
70744        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i16")]
70745        fn _vst4_lane_s16(
70746            ptr: *mut i8,
70747            a: int16x4_t,
70748            b: int16x4_t,
70749            c: int16x4_t,
70750            d: int16x4_t,
70751            n: i32,
70752            size: i32,
70753        );
70754    }
70755    _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70756}
70757#[doc = "Store multiple 4-element structures from four registers"]
70758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70759#[doc = "## Safety"]
70760#[doc = "  * Neon instrinsic unsafe"]
70761#[inline]
70762#[cfg(target_arch = "arm")]
70763#[target_feature(enable = "neon,v7")]
70764#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70765#[rustc_legacy_const_generics(2)]
70766#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70767pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70768    static_assert_uimm_bits!(LANE, 3);
70769    unsafe extern "unadjusted" {
70770        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i16")]
70771        fn _vst4q_lane_s16(
70772            ptr: *mut i8,
70773            a: int16x8_t,
70774            b: int16x8_t,
70775            c: int16x8_t,
70776            d: int16x8_t,
70777            n: i32,
70778            size: i32,
70779        );
70780    }
70781    _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70782}
70783#[doc = "Store multiple 4-element structures from four registers"]
70784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70785#[doc = "## Safety"]
70786#[doc = "  * Neon instrinsic unsafe"]
70787#[inline]
70788#[cfg(target_arch = "arm")]
70789#[target_feature(enable = "neon,v7")]
70790#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70791#[rustc_legacy_const_generics(2)]
70792#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70793pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70794    static_assert_uimm_bits!(LANE, 1);
70795    unsafe extern "unadjusted" {
70796        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2i32")]
70797        fn _vst4_lane_s32(
70798            ptr: *mut i8,
70799            a: int32x2_t,
70800            b: int32x2_t,
70801            c: int32x2_t,
70802            d: int32x2_t,
70803            n: i32,
70804            size: i32,
70805        );
70806    }
70807    _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70808}
70809#[doc = "Store multiple 4-element structures from four registers"]
70810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70811#[doc = "## Safety"]
70812#[doc = "  * Neon instrinsic unsafe"]
70813#[inline]
70814#[cfg(target_arch = "arm")]
70815#[target_feature(enable = "neon,v7")]
70816#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70817#[rustc_legacy_const_generics(2)]
70818#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70819pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70820    static_assert_uimm_bits!(LANE, 2);
70821    unsafe extern "unadjusted" {
70822        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i32")]
70823        fn _vst4q_lane_s32(
70824            ptr: *mut i8,
70825            a: int32x4_t,
70826            b: int32x4_t,
70827            c: int32x4_t,
70828            d: int32x4_t,
70829            n: i32,
70830            size: i32,
70831        );
70832    }
70833    _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70834}
70835#[doc = "Store multiple 4-element structures from four registers"]
70836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70837#[doc = "## Safety"]
70838#[doc = "  * Neon instrinsic unsafe"]
70839#[inline]
70840#[target_feature(enable = "neon")]
70841#[cfg(not(target_arch = "arm"))]
70842#[rustc_legacy_const_generics(2)]
70843#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70844#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70845pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70846    static_assert_uimm_bits!(LANE, 1);
70847    unsafe extern "unadjusted" {
70848        #[cfg_attr(
70849            any(target_arch = "aarch64", target_arch = "arm64ec"),
70850            link_name = "llvm.aarch64.neon.st4lane.v2f32.p0i8"
70851        )]
70852        fn _vst4_lane_f32(
70853            a: float32x2_t,
70854            b: float32x2_t,
70855            c: float32x2_t,
70856            d: float32x2_t,
70857            n: i64,
70858            ptr: *mut i8,
70859        );
70860    }
70861    _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70862}
70863#[doc = "Store multiple 4-element structures from four registers"]
70864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70865#[doc = "## Safety"]
70866#[doc = "  * Neon instrinsic unsafe"]
70867#[inline]
70868#[target_feature(enable = "neon")]
70869#[cfg(not(target_arch = "arm"))]
70870#[rustc_legacy_const_generics(2)]
70871#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70872#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70873pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70874    static_assert_uimm_bits!(LANE, 2);
70875    unsafe extern "unadjusted" {
70876        #[cfg_attr(
70877            any(target_arch = "aarch64", target_arch = "arm64ec"),
70878            link_name = "llvm.aarch64.neon.st4lane.v4f32.p0i8"
70879        )]
70880        fn _vst4q_lane_f32(
70881            a: float32x4_t,
70882            b: float32x4_t,
70883            c: float32x4_t,
70884            d: float32x4_t,
70885            n: i64,
70886            ptr: *mut i8,
70887        );
70888    }
70889    _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70890}
70891#[doc = "Store multiple 4-element structures from four registers"]
70892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70893#[doc = "## Safety"]
70894#[doc = "  * Neon instrinsic unsafe"]
70895#[inline]
70896#[target_feature(enable = "neon")]
70897#[cfg(not(target_arch = "arm"))]
70898#[rustc_legacy_const_generics(2)]
70899#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70900#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70901pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70902    static_assert_uimm_bits!(LANE, 3);
70903    unsafe extern "unadjusted" {
70904        #[cfg_attr(
70905            any(target_arch = "aarch64", target_arch = "arm64ec"),
70906            link_name = "llvm.aarch64.neon.st4lane.v8i8.p0i8"
70907        )]
70908        fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8);
70909    }
70910    _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70911}
70912#[doc = "Store multiple 4-element structures from four registers"]
70913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70914#[doc = "## Safety"]
70915#[doc = "  * Neon instrinsic unsafe"]
70916#[inline]
70917#[target_feature(enable = "neon")]
70918#[cfg(not(target_arch = "arm"))]
70919#[rustc_legacy_const_generics(2)]
70920#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70921#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70922pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70923    static_assert_uimm_bits!(LANE, 2);
70924    unsafe extern "unadjusted" {
70925        #[cfg_attr(
70926            any(target_arch = "aarch64", target_arch = "arm64ec"),
70927            link_name = "llvm.aarch64.neon.st4lane.v4i16.p0i8"
70928        )]
70929        fn _vst4_lane_s16(
70930            a: int16x4_t,
70931            b: int16x4_t,
70932            c: int16x4_t,
70933            d: int16x4_t,
70934            n: i64,
70935            ptr: *mut i8,
70936        );
70937    }
70938    _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70939}
70940#[doc = "Store multiple 4-element structures from four registers"]
70941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70942#[doc = "## Safety"]
70943#[doc = "  * Neon instrinsic unsafe"]
70944#[inline]
70945#[target_feature(enable = "neon")]
70946#[cfg(not(target_arch = "arm"))]
70947#[rustc_legacy_const_generics(2)]
70948#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70949#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70950pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70951    static_assert_uimm_bits!(LANE, 3);
70952    unsafe extern "unadjusted" {
70953        #[cfg_attr(
70954            any(target_arch = "aarch64", target_arch = "arm64ec"),
70955            link_name = "llvm.aarch64.neon.st4lane.v8i16.p0i8"
70956        )]
70957        fn _vst4q_lane_s16(
70958            a: int16x8_t,
70959            b: int16x8_t,
70960            c: int16x8_t,
70961            d: int16x8_t,
70962            n: i64,
70963            ptr: *mut i8,
70964        );
70965    }
70966    _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70967}
70968#[doc = "Store multiple 4-element structures from four registers"]
70969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70970#[doc = "## Safety"]
70971#[doc = "  * Neon instrinsic unsafe"]
70972#[inline]
70973#[target_feature(enable = "neon")]
70974#[cfg(not(target_arch = "arm"))]
70975#[rustc_legacy_const_generics(2)]
70976#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70977#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70978pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70979    static_assert_uimm_bits!(LANE, 1);
70980    unsafe extern "unadjusted" {
70981        #[cfg_attr(
70982            any(target_arch = "aarch64", target_arch = "arm64ec"),
70983            link_name = "llvm.aarch64.neon.st4lane.v2i32.p0i8"
70984        )]
70985        fn _vst4_lane_s32(
70986            a: int32x2_t,
70987            b: int32x2_t,
70988            c: int32x2_t,
70989            d: int32x2_t,
70990            n: i64,
70991            ptr: *mut i8,
70992        );
70993    }
70994    _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70995}
70996#[doc = "Store multiple 4-element structures from four registers"]
70997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70998#[doc = "## Safety"]
70999#[doc = "  * Neon instrinsic unsafe"]
71000#[inline]
71001#[target_feature(enable = "neon")]
71002#[cfg(not(target_arch = "arm"))]
71003#[rustc_legacy_const_generics(2)]
71004#[cfg_attr(test, assert_instr(st4, LANE = 0))]
71005#[stable(feature = "neon_intrinsics", since = "1.59.0")]
71006pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
71007    static_assert_uimm_bits!(LANE, 2);
71008    unsafe extern "unadjusted" {
71009        #[cfg_attr(
71010            any(target_arch = "aarch64", target_arch = "arm64ec"),
71011            link_name = "llvm.aarch64.neon.st4lane.v4i32.p0i8"
71012        )]
71013        fn _vst4q_lane_s32(
71014            a: int32x4_t,
71015            b: int32x4_t,
71016            c: int32x4_t,
71017            d: int32x4_t,
71018            n: i64,
71019            ptr: *mut i8,
71020        );
71021    }
71022    _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
71023}
71024#[doc = "Store multiple 4-element structures from four registers"]
71025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
71026#[doc = "## Safety"]
71027#[doc = "  * Neon instrinsic unsafe"]
71028#[inline]
71029#[target_feature(enable = "neon")]
71030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71031#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71032#[cfg_attr(
71033    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71034    assert_instr(st4, LANE = 0)
71035)]
71036#[rustc_legacy_const_generics(2)]
71037#[cfg_attr(
71038    not(target_arch = "arm"),
71039    stable(feature = "neon_intrinsics", since = "1.59.0")
71040)]
71041#[cfg_attr(
71042    target_arch = "arm",
71043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71044)]
71045pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
71046    static_assert_uimm_bits!(LANE, 3);
71047    vst4_lane_s8::<LANE>(transmute(a), transmute(b))
71048}
71049#[doc = "Store multiple 4-element structures from four registers"]
71050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
71051#[doc = "## Safety"]
71052#[doc = "  * Neon instrinsic unsafe"]
71053#[inline]
71054#[target_feature(enable = "neon")]
71055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71057#[cfg_attr(
71058    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71059    assert_instr(st4, LANE = 0)
71060)]
71061#[rustc_legacy_const_generics(2)]
71062#[cfg_attr(
71063    not(target_arch = "arm"),
71064    stable(feature = "neon_intrinsics", since = "1.59.0")
71065)]
71066#[cfg_attr(
71067    target_arch = "arm",
71068    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71069)]
71070pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
71071    static_assert_uimm_bits!(LANE, 2);
71072    vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71073}
71074#[doc = "Store multiple 4-element structures from four registers"]
71075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
71076#[doc = "## Safety"]
71077#[doc = "  * Neon instrinsic unsafe"]
71078#[inline]
71079#[target_feature(enable = "neon")]
71080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71082#[cfg_attr(
71083    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71084    assert_instr(st4, LANE = 0)
71085)]
71086#[rustc_legacy_const_generics(2)]
71087#[cfg_attr(
71088    not(target_arch = "arm"),
71089    stable(feature = "neon_intrinsics", since = "1.59.0")
71090)]
71091#[cfg_attr(
71092    target_arch = "arm",
71093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71094)]
71095pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
71096    static_assert_uimm_bits!(LANE, 3);
71097    vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71098}
71099#[doc = "Store multiple 4-element structures from four registers"]
71100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
71101#[doc = "## Safety"]
71102#[doc = "  * Neon instrinsic unsafe"]
71103#[inline]
71104#[target_feature(enable = "neon")]
71105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71107#[cfg_attr(
71108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71109    assert_instr(st4, LANE = 0)
71110)]
71111#[rustc_legacy_const_generics(2)]
71112#[cfg_attr(
71113    not(target_arch = "arm"),
71114    stable(feature = "neon_intrinsics", since = "1.59.0")
71115)]
71116#[cfg_attr(
71117    target_arch = "arm",
71118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71119)]
71120pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
71121    static_assert_uimm_bits!(LANE, 1);
71122    vst4_lane_s32::<LANE>(transmute(a), transmute(b))
71123}
71124#[doc = "Store multiple 4-element structures from four registers"]
71125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
71126#[doc = "## Safety"]
71127#[doc = "  * Neon instrinsic unsafe"]
71128#[inline]
71129#[target_feature(enable = "neon")]
71130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71132#[cfg_attr(
71133    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71134    assert_instr(st4, LANE = 0)
71135)]
71136#[rustc_legacy_const_generics(2)]
71137#[cfg_attr(
71138    not(target_arch = "arm"),
71139    stable(feature = "neon_intrinsics", since = "1.59.0")
71140)]
71141#[cfg_attr(
71142    target_arch = "arm",
71143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71144)]
71145pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
71146    static_assert_uimm_bits!(LANE, 2);
71147    vst4q_lane_s32::<LANE>(transmute(a), transmute(b))
71148}
71149#[doc = "Store multiple 4-element structures from four registers"]
71150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
71151#[doc = "## Safety"]
71152#[doc = "  * Neon instrinsic unsafe"]
71153#[inline]
71154#[target_feature(enable = "neon")]
71155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71157#[cfg_attr(
71158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71159    assert_instr(st4, LANE = 0)
71160)]
71161#[rustc_legacy_const_generics(2)]
71162#[cfg_attr(
71163    not(target_arch = "arm"),
71164    stable(feature = "neon_intrinsics", since = "1.59.0")
71165)]
71166#[cfg_attr(
71167    target_arch = "arm",
71168    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71169)]
71170pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
71171    static_assert_uimm_bits!(LANE, 3);
71172    vst4_lane_s8::<LANE>(transmute(a), transmute(b))
71173}
71174#[doc = "Store multiple 4-element structures from four registers"]
71175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
71176#[doc = "## Safety"]
71177#[doc = "  * Neon instrinsic unsafe"]
71178#[inline]
71179#[target_feature(enable = "neon")]
71180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71182#[cfg_attr(
71183    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71184    assert_instr(st4, LANE = 0)
71185)]
71186#[rustc_legacy_const_generics(2)]
71187#[cfg_attr(
71188    not(target_arch = "arm"),
71189    stable(feature = "neon_intrinsics", since = "1.59.0")
71190)]
71191#[cfg_attr(
71192    target_arch = "arm",
71193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71194)]
71195pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
71196    static_assert_uimm_bits!(LANE, 2);
71197    vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71198}
71199#[doc = "Store multiple 4-element structures from four registers"]
71200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
71201#[doc = "## Safety"]
71202#[doc = "  * Neon instrinsic unsafe"]
71203#[inline]
71204#[target_feature(enable = "neon")]
71205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71207#[cfg_attr(
71208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71209    assert_instr(st4, LANE = 0)
71210)]
71211#[rustc_legacy_const_generics(2)]
71212#[cfg_attr(
71213    not(target_arch = "arm"),
71214    stable(feature = "neon_intrinsics", since = "1.59.0")
71215)]
71216#[cfg_attr(
71217    target_arch = "arm",
71218    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71219)]
71220pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
71221    static_assert_uimm_bits!(LANE, 3);
71222    vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71223}
71224#[doc = "Store multiple 4-element structures from four registers"]
71225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
71226#[doc = "## Safety"]
71227#[doc = "  * Neon instrinsic unsafe"]
71228#[inline]
71229#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71230#[target_feature(enable = "neon,aes")]
71231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71232#[cfg_attr(
71233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71234    assert_instr(nop)
71235)]
71236#[cfg_attr(
71237    not(target_arch = "arm"),
71238    stable(feature = "neon_intrinsics", since = "1.59.0")
71239)]
71240#[cfg_attr(
71241    target_arch = "arm",
71242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71243)]
71244pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
71245    vst4_s64(transmute(a), transmute(b))
71246}
71247#[doc = "Store multiple 4-element structures from four registers"]
71248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71249#[doc = "## Safety"]
71250#[doc = "  * Neon instrinsic unsafe"]
71251#[inline]
71252#[cfg(target_arch = "arm")]
71253#[target_feature(enable = "neon,v7")]
71254#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
71255#[cfg_attr(test, assert_instr(nop))]
71256pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71257    unsafe extern "unadjusted" {
71258        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v1i64")]
71259        fn _vst4_s64(
71260            ptr: *mut i8,
71261            a: int64x1_t,
71262            b: int64x1_t,
71263            c: int64x1_t,
71264            d: int64x1_t,
71265            size: i32,
71266        );
71267    }
71268    _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
71269}
71270#[doc = "Store multiple 4-element structures from four registers"]
71271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71272#[doc = "## Safety"]
71273#[doc = "  * Neon instrinsic unsafe"]
71274#[inline]
71275#[target_feature(enable = "neon")]
71276#[cfg(not(target_arch = "arm"))]
71277#[stable(feature = "neon_intrinsics", since = "1.59.0")]
71278#[cfg_attr(test, assert_instr(nop))]
71279pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71280    unsafe extern "unadjusted" {
71281        #[cfg_attr(
71282            any(target_arch = "aarch64", target_arch = "arm64ec"),
71283            link_name = "llvm.aarch64.neon.st4.v1i64.p0i8"
71284        )]
71285        fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
71286    }
71287    _vst4_s64(b.0, b.1, b.2, b.3, a as _)
71288}
71289#[doc = "Store multiple 4-element structures from four registers"]
71290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
71291#[doc = "## Safety"]
71292#[doc = "  * Neon instrinsic unsafe"]
71293#[inline]
71294#[target_feature(enable = "neon")]
71295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71297#[cfg_attr(
71298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71299    assert_instr(nop)
71300)]
71301#[cfg_attr(
71302    not(target_arch = "arm"),
71303    stable(feature = "neon_intrinsics", since = "1.59.0")
71304)]
71305#[cfg_attr(
71306    target_arch = "arm",
71307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71308)]
71309pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
71310    vst4_s64(transmute(a), transmute(b))
71311}
71312#[doc = "Store multiple 4-element structures from four registers"]
71313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
71314#[doc = "## Safety"]
71315#[doc = "  * Neon instrinsic unsafe"]
71316#[inline]
71317#[target_feature(enable = "neon")]
71318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71320#[cfg_attr(
71321    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71322    assert_instr(st4)
71323)]
71324#[cfg_attr(
71325    not(target_arch = "arm"),
71326    stable(feature = "neon_intrinsics", since = "1.59.0")
71327)]
71328#[cfg_attr(
71329    target_arch = "arm",
71330    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71331)]
71332pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
71333    vst4_s8(transmute(a), transmute(b))
71334}
71335#[doc = "Store multiple 4-element structures from four registers"]
71336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
71337#[doc = "## Safety"]
71338#[doc = "  * Neon instrinsic unsafe"]
71339#[inline]
71340#[target_feature(enable = "neon")]
71341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71343#[cfg_attr(
71344    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71345    assert_instr(st4)
71346)]
71347#[cfg_attr(
71348    not(target_arch = "arm"),
71349    stable(feature = "neon_intrinsics", since = "1.59.0")
71350)]
71351#[cfg_attr(
71352    target_arch = "arm",
71353    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71354)]
71355pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
71356    vst4q_s8(transmute(a), transmute(b))
71357}
71358#[doc = "Store multiple 4-element structures from four registers"]
71359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
71360#[doc = "## Safety"]
71361#[doc = "  * Neon instrinsic unsafe"]
71362#[inline]
71363#[target_feature(enable = "neon")]
71364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71366#[cfg_attr(
71367    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71368    assert_instr(st4)
71369)]
71370#[cfg_attr(
71371    not(target_arch = "arm"),
71372    stable(feature = "neon_intrinsics", since = "1.59.0")
71373)]
71374#[cfg_attr(
71375    target_arch = "arm",
71376    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71377)]
71378pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
71379    vst4_s16(transmute(a), transmute(b))
71380}
71381#[doc = "Store multiple 4-element structures from four registers"]
71382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
71383#[doc = "## Safety"]
71384#[doc = "  * Neon instrinsic unsafe"]
71385#[inline]
71386#[target_feature(enable = "neon")]
71387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71389#[cfg_attr(
71390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71391    assert_instr(st4)
71392)]
71393#[cfg_attr(
71394    not(target_arch = "arm"),
71395    stable(feature = "neon_intrinsics", since = "1.59.0")
71396)]
71397#[cfg_attr(
71398    target_arch = "arm",
71399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71400)]
71401pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
71402    vst4q_s16(transmute(a), transmute(b))
71403}
71404#[doc = "Store multiple 4-element structures from four registers"]
71405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
71406#[doc = "## Safety"]
71407#[doc = "  * Neon instrinsic unsafe"]
71408#[inline]
71409#[target_feature(enable = "neon")]
71410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71412#[cfg_attr(
71413    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71414    assert_instr(st4)
71415)]
71416#[cfg_attr(
71417    not(target_arch = "arm"),
71418    stable(feature = "neon_intrinsics", since = "1.59.0")
71419)]
71420#[cfg_attr(
71421    target_arch = "arm",
71422    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71423)]
71424pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
71425    vst4_s32(transmute(a), transmute(b))
71426}
71427#[doc = "Store multiple 4-element structures from four registers"]
71428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
71429#[doc = "## Safety"]
71430#[doc = "  * Neon instrinsic unsafe"]
71431#[inline]
71432#[target_feature(enable = "neon")]
71433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71435#[cfg_attr(
71436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71437    assert_instr(st4)
71438)]
71439#[cfg_attr(
71440    not(target_arch = "arm"),
71441    stable(feature = "neon_intrinsics", since = "1.59.0")
71442)]
71443#[cfg_attr(
71444    target_arch = "arm",
71445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71446)]
71447pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
71448    vst4q_s32(transmute(a), transmute(b))
71449}
71450#[doc = "Store multiple 4-element structures from four registers"]
71451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
71452#[doc = "## Safety"]
71453#[doc = "  * Neon instrinsic unsafe"]
71454#[inline]
71455#[target_feature(enable = "neon")]
71456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71458#[cfg_attr(
71459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71460    assert_instr(st4)
71461)]
71462#[cfg_attr(
71463    not(target_arch = "arm"),
71464    stable(feature = "neon_intrinsics", since = "1.59.0")
71465)]
71466#[cfg_attr(
71467    target_arch = "arm",
71468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71469)]
71470pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
71471    vst4_s8(transmute(a), transmute(b))
71472}
71473#[doc = "Store multiple 4-element structures from four registers"]
71474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
71475#[doc = "## Safety"]
71476#[doc = "  * Neon instrinsic unsafe"]
71477#[inline]
71478#[target_feature(enable = "neon")]
71479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71481#[cfg_attr(
71482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71483    assert_instr(st4)
71484)]
71485#[cfg_attr(
71486    not(target_arch = "arm"),
71487    stable(feature = "neon_intrinsics", since = "1.59.0")
71488)]
71489#[cfg_attr(
71490    target_arch = "arm",
71491    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71492)]
71493pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
71494    vst4q_s8(transmute(a), transmute(b))
71495}
71496#[doc = "Store multiple 4-element structures from four registers"]
71497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
71498#[doc = "## Safety"]
71499#[doc = "  * Neon instrinsic unsafe"]
71500#[inline]
71501#[target_feature(enable = "neon")]
71502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71504#[cfg_attr(
71505    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71506    assert_instr(st4)
71507)]
71508#[cfg_attr(
71509    not(target_arch = "arm"),
71510    stable(feature = "neon_intrinsics", since = "1.59.0")
71511)]
71512#[cfg_attr(
71513    target_arch = "arm",
71514    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71515)]
71516pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
71517    vst4_s16(transmute(a), transmute(b))
71518}
71519#[doc = "Store multiple 4-element structures from four registers"]
71520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
71521#[doc = "## Safety"]
71522#[doc = "  * Neon instrinsic unsafe"]
71523#[inline]
71524#[target_feature(enable = "neon")]
71525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71527#[cfg_attr(
71528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71529    assert_instr(st4)
71530)]
71531#[cfg_attr(
71532    not(target_arch = "arm"),
71533    stable(feature = "neon_intrinsics", since = "1.59.0")
71534)]
71535#[cfg_attr(
71536    target_arch = "arm",
71537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71538)]
71539pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
71540    vst4q_s16(transmute(a), transmute(b))
71541}
71542#[doc = "Store SIMD&FP register (immediate offset)"]
71543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
71544#[doc = "## Safety"]
71545#[doc = "  * Neon instrinsic unsafe"]
71546#[inline]
71547#[target_feature(enable = "neon")]
71548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71550#[cfg_attr(
71551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71552    assert_instr(nop)
71553)]
71554#[cfg_attr(
71555    not(target_arch = "arm"),
71556    stable(feature = "neon_intrinsics", since = "1.59.0")
71557)]
71558#[cfg_attr(
71559    target_arch = "arm",
71560    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71561)]
71562pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
71563    *a = b
71564}
71565#[doc = "Subtract"]
71566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
71567#[inline]
71568#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71569#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71570#[cfg_attr(
71571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71572    assert_instr(fsub)
71573)]
71574#[target_feature(enable = "neon,fp16")]
71575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71576pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
71577    unsafe { simd_sub(a, b) }
71578}
71579#[doc = "Subtract"]
71580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
71581#[inline]
71582#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71583#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71584#[cfg_attr(
71585    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71586    assert_instr(fsub)
71587)]
71588#[target_feature(enable = "neon,fp16")]
71589#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71590pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
71591    unsafe { simd_sub(a, b) }
71592}
71593#[doc = "Subtract"]
71594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
71595#[inline]
71596#[target_feature(enable = "neon")]
71597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71599#[cfg_attr(
71600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71601    assert_instr(fsub)
71602)]
71603#[cfg_attr(
71604    not(target_arch = "arm"),
71605    stable(feature = "neon_intrinsics", since = "1.59.0")
71606)]
71607#[cfg_attr(
71608    target_arch = "arm",
71609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71610)]
71611pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
71612    unsafe { simd_sub(a, b) }
71613}
71614#[doc = "Subtract"]
71615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
71616#[inline]
71617#[target_feature(enable = "neon")]
71618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71619#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71620#[cfg_attr(
71621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71622    assert_instr(fsub)
71623)]
71624#[cfg_attr(
71625    not(target_arch = "arm"),
71626    stable(feature = "neon_intrinsics", since = "1.59.0")
71627)]
71628#[cfg_attr(
71629    target_arch = "arm",
71630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71631)]
71632pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
71633    unsafe { simd_sub(a, b) }
71634}
71635#[doc = "Subtract"]
71636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
71637#[inline]
71638#[target_feature(enable = "neon")]
71639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71641#[cfg_attr(
71642    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71643    assert_instr(sub)
71644)]
71645#[cfg_attr(
71646    not(target_arch = "arm"),
71647    stable(feature = "neon_intrinsics", since = "1.59.0")
71648)]
71649#[cfg_attr(
71650    target_arch = "arm",
71651    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71652)]
71653pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
71654    unsafe { simd_sub(a, b) }
71655}
71656#[doc = "Subtract"]
71657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
71658#[inline]
71659#[target_feature(enable = "neon")]
71660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71662#[cfg_attr(
71663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71664    assert_instr(sub)
71665)]
71666#[cfg_attr(
71667    not(target_arch = "arm"),
71668    stable(feature = "neon_intrinsics", since = "1.59.0")
71669)]
71670#[cfg_attr(
71671    target_arch = "arm",
71672    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71673)]
71674pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
71675    unsafe { simd_sub(a, b) }
71676}
71677#[doc = "Subtract"]
71678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
71679#[inline]
71680#[target_feature(enable = "neon")]
71681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71683#[cfg_attr(
71684    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71685    assert_instr(sub)
71686)]
71687#[cfg_attr(
71688    not(target_arch = "arm"),
71689    stable(feature = "neon_intrinsics", since = "1.59.0")
71690)]
71691#[cfg_attr(
71692    target_arch = "arm",
71693    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71694)]
71695pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
71696    unsafe { simd_sub(a, b) }
71697}
71698#[doc = "Subtract"]
71699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
71700#[inline]
71701#[target_feature(enable = "neon")]
71702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71703#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71704#[cfg_attr(
71705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71706    assert_instr(sub)
71707)]
71708#[cfg_attr(
71709    not(target_arch = "arm"),
71710    stable(feature = "neon_intrinsics", since = "1.59.0")
71711)]
71712#[cfg_attr(
71713    target_arch = "arm",
71714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71715)]
71716pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
71717    unsafe { simd_sub(a, b) }
71718}
71719#[doc = "Subtract"]
71720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
71721#[inline]
71722#[target_feature(enable = "neon")]
71723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71725#[cfg_attr(
71726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71727    assert_instr(sub)
71728)]
71729#[cfg_attr(
71730    not(target_arch = "arm"),
71731    stable(feature = "neon_intrinsics", since = "1.59.0")
71732)]
71733#[cfg_attr(
71734    target_arch = "arm",
71735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71736)]
71737pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
71738    unsafe { simd_sub(a, b) }
71739}
71740#[doc = "Subtract"]
71741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
71742#[inline]
71743#[target_feature(enable = "neon")]
71744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71746#[cfg_attr(
71747    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71748    assert_instr(sub)
71749)]
71750#[cfg_attr(
71751    not(target_arch = "arm"),
71752    stable(feature = "neon_intrinsics", since = "1.59.0")
71753)]
71754#[cfg_attr(
71755    target_arch = "arm",
71756    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71757)]
71758pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
71759    unsafe { simd_sub(a, b) }
71760}
71761#[doc = "Subtract"]
71762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
71763#[inline]
71764#[target_feature(enable = "neon")]
71765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71767#[cfg_attr(
71768    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71769    assert_instr(sub)
71770)]
71771#[cfg_attr(
71772    not(target_arch = "arm"),
71773    stable(feature = "neon_intrinsics", since = "1.59.0")
71774)]
71775#[cfg_attr(
71776    target_arch = "arm",
71777    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71778)]
71779pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
71780    unsafe { simd_sub(a, b) }
71781}
71782#[doc = "Subtract"]
71783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
71784#[inline]
71785#[target_feature(enable = "neon")]
71786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71788#[cfg_attr(
71789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71790    assert_instr(sub)
71791)]
71792#[cfg_attr(
71793    not(target_arch = "arm"),
71794    stable(feature = "neon_intrinsics", since = "1.59.0")
71795)]
71796#[cfg_attr(
71797    target_arch = "arm",
71798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71799)]
71800pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
71801    unsafe { simd_sub(a, b) }
71802}
71803#[doc = "Subtract"]
71804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
71805#[inline]
71806#[target_feature(enable = "neon")]
71807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71809#[cfg_attr(
71810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71811    assert_instr(sub)
71812)]
71813#[cfg_attr(
71814    not(target_arch = "arm"),
71815    stable(feature = "neon_intrinsics", since = "1.59.0")
71816)]
71817#[cfg_attr(
71818    target_arch = "arm",
71819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71820)]
71821pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
71822    unsafe { simd_sub(a, b) }
71823}
71824#[doc = "Subtract"]
71825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
71826#[inline]
71827#[target_feature(enable = "neon")]
71828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71830#[cfg_attr(
71831    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71832    assert_instr(sub)
71833)]
71834#[cfg_attr(
71835    not(target_arch = "arm"),
71836    stable(feature = "neon_intrinsics", since = "1.59.0")
71837)]
71838#[cfg_attr(
71839    target_arch = "arm",
71840    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71841)]
71842pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
71843    unsafe { simd_sub(a, b) }
71844}
71845#[doc = "Subtract"]
71846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
71847#[inline]
71848#[target_feature(enable = "neon")]
71849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71851#[cfg_attr(
71852    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71853    assert_instr(sub)
71854)]
71855#[cfg_attr(
71856    not(target_arch = "arm"),
71857    stable(feature = "neon_intrinsics", since = "1.59.0")
71858)]
71859#[cfg_attr(
71860    target_arch = "arm",
71861    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71862)]
71863pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
71864    unsafe { simd_sub(a, b) }
71865}
71866#[doc = "Subtract"]
71867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
71868#[inline]
71869#[target_feature(enable = "neon")]
71870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71871#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71872#[cfg_attr(
71873    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71874    assert_instr(sub)
71875)]
71876#[cfg_attr(
71877    not(target_arch = "arm"),
71878    stable(feature = "neon_intrinsics", since = "1.59.0")
71879)]
71880#[cfg_attr(
71881    target_arch = "arm",
71882    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71883)]
71884pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
71885    unsafe { simd_sub(a, b) }
71886}
71887#[doc = "Subtract"]
71888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
71889#[inline]
71890#[target_feature(enable = "neon")]
71891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71893#[cfg_attr(
71894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71895    assert_instr(sub)
71896)]
71897#[cfg_attr(
71898    not(target_arch = "arm"),
71899    stable(feature = "neon_intrinsics", since = "1.59.0")
71900)]
71901#[cfg_attr(
71902    target_arch = "arm",
71903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71904)]
71905pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
71906    unsafe { simd_sub(a, b) }
71907}
71908#[doc = "Subtract"]
71909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
71910#[inline]
71911#[target_feature(enable = "neon")]
71912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71913#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71914#[cfg_attr(
71915    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71916    assert_instr(sub)
71917)]
71918#[cfg_attr(
71919    not(target_arch = "arm"),
71920    stable(feature = "neon_intrinsics", since = "1.59.0")
71921)]
71922#[cfg_attr(
71923    target_arch = "arm",
71924    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71925)]
71926pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
71927    unsafe { simd_sub(a, b) }
71928}
71929#[doc = "Subtract"]
71930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
71931#[inline]
71932#[target_feature(enable = "neon")]
71933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71934#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71935#[cfg_attr(
71936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71937    assert_instr(sub)
71938)]
71939#[cfg_attr(
71940    not(target_arch = "arm"),
71941    stable(feature = "neon_intrinsics", since = "1.59.0")
71942)]
71943#[cfg_attr(
71944    target_arch = "arm",
71945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71946)]
71947pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
71948    unsafe { simd_sub(a, b) }
71949}
71950#[doc = "Subtract"]
71951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
71952#[inline]
71953#[target_feature(enable = "neon")]
71954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71956#[cfg_attr(
71957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71958    assert_instr(sub)
71959)]
71960#[cfg_attr(
71961    not(target_arch = "arm"),
71962    stable(feature = "neon_intrinsics", since = "1.59.0")
71963)]
71964#[cfg_attr(
71965    target_arch = "arm",
71966    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71967)]
71968pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
71969    unsafe { simd_sub(a, b) }
71970}
71971#[doc = "Subtract returning high narrow"]
71972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
71973#[inline]
71974#[target_feature(enable = "neon")]
71975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71977#[cfg_attr(
71978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71979    assert_instr(subhn2)
71980)]
71981#[cfg_attr(
71982    not(target_arch = "arm"),
71983    stable(feature = "neon_intrinsics", since = "1.59.0")
71984)]
71985#[cfg_attr(
71986    target_arch = "arm",
71987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71988)]
71989pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
71990    let d: int8x8_t = vsubhn_s16(b, c);
71991    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71992}
71993#[doc = "Subtract returning high narrow"]
71994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
71995#[inline]
71996#[target_feature(enable = "neon")]
71997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71999#[cfg_attr(
72000    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72001    assert_instr(subhn2)
72002)]
72003#[cfg_attr(
72004    not(target_arch = "arm"),
72005    stable(feature = "neon_intrinsics", since = "1.59.0")
72006)]
72007#[cfg_attr(
72008    target_arch = "arm",
72009    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72010)]
72011pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
72012    let d: int16x4_t = vsubhn_s32(b, c);
72013    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
72014}
72015#[doc = "Subtract returning high narrow"]
72016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
72017#[inline]
72018#[target_feature(enable = "neon")]
72019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72021#[cfg_attr(
72022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72023    assert_instr(subhn2)
72024)]
72025#[cfg_attr(
72026    not(target_arch = "arm"),
72027    stable(feature = "neon_intrinsics", since = "1.59.0")
72028)]
72029#[cfg_attr(
72030    target_arch = "arm",
72031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72032)]
72033pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
72034    let d: int32x2_t = vsubhn_s64(b, c);
72035    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
72036}
72037#[doc = "Subtract returning high narrow"]
72038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
72039#[inline]
72040#[target_feature(enable = "neon")]
72041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72043#[cfg_attr(
72044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72045    assert_instr(subhn2)
72046)]
72047#[cfg_attr(
72048    not(target_arch = "arm"),
72049    stable(feature = "neon_intrinsics", since = "1.59.0")
72050)]
72051#[cfg_attr(
72052    target_arch = "arm",
72053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72054)]
72055pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
72056    let d: uint8x8_t = vsubhn_u16(b, c);
72057    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
72058}
72059#[doc = "Subtract returning high narrow"]
72060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
72061#[inline]
72062#[target_feature(enable = "neon")]
72063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72065#[cfg_attr(
72066    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72067    assert_instr(subhn2)
72068)]
72069#[cfg_attr(
72070    not(target_arch = "arm"),
72071    stable(feature = "neon_intrinsics", since = "1.59.0")
72072)]
72073#[cfg_attr(
72074    target_arch = "arm",
72075    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72076)]
72077pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
72078    let d: uint16x4_t = vsubhn_u32(b, c);
72079    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
72080}
72081#[doc = "Subtract returning high narrow"]
72082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
72083#[inline]
72084#[target_feature(enable = "neon")]
72085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72087#[cfg_attr(
72088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72089    assert_instr(subhn2)
72090)]
72091#[cfg_attr(
72092    not(target_arch = "arm"),
72093    stable(feature = "neon_intrinsics", since = "1.59.0")
72094)]
72095#[cfg_attr(
72096    target_arch = "arm",
72097    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72098)]
72099pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
72100    let d: uint32x2_t = vsubhn_u64(b, c);
72101    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
72102}
72103#[doc = "Subtract returning high narrow"]
72104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
72105#[inline]
72106#[target_feature(enable = "neon")]
72107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72109#[cfg_attr(
72110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72111    assert_instr(subhn)
72112)]
72113#[cfg_attr(
72114    not(target_arch = "arm"),
72115    stable(feature = "neon_intrinsics", since = "1.59.0")
72116)]
72117#[cfg_attr(
72118    target_arch = "arm",
72119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72120)]
72121pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
72122    let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72123    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72124}
72125#[doc = "Subtract returning high narrow"]
72126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
72127#[inline]
72128#[target_feature(enable = "neon")]
72129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72131#[cfg_attr(
72132    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72133    assert_instr(subhn)
72134)]
72135#[cfg_attr(
72136    not(target_arch = "arm"),
72137    stable(feature = "neon_intrinsics", since = "1.59.0")
72138)]
72139#[cfg_attr(
72140    target_arch = "arm",
72141    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72142)]
72143pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
72144    let c: i32x4 = i32x4::new(16, 16, 16, 16);
72145    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72146}
72147#[doc = "Subtract returning high narrow"]
72148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
72149#[inline]
72150#[target_feature(enable = "neon")]
72151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72153#[cfg_attr(
72154    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72155    assert_instr(subhn)
72156)]
72157#[cfg_attr(
72158    not(target_arch = "arm"),
72159    stable(feature = "neon_intrinsics", since = "1.59.0")
72160)]
72161#[cfg_attr(
72162    target_arch = "arm",
72163    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72164)]
72165pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
72166    let c: i64x2 = i64x2::new(32, 32);
72167    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72168}
72169#[doc = "Subtract returning high narrow"]
72170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
72171#[inline]
72172#[target_feature(enable = "neon")]
72173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72175#[cfg_attr(
72176    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72177    assert_instr(subhn)
72178)]
72179#[cfg_attr(
72180    not(target_arch = "arm"),
72181    stable(feature = "neon_intrinsics", since = "1.59.0")
72182)]
72183#[cfg_attr(
72184    target_arch = "arm",
72185    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72186)]
72187pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
72188    let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72189    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72190}
72191#[doc = "Subtract returning high narrow"]
72192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
72193#[inline]
72194#[target_feature(enable = "neon")]
72195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72197#[cfg_attr(
72198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72199    assert_instr(subhn)
72200)]
72201#[cfg_attr(
72202    not(target_arch = "arm"),
72203    stable(feature = "neon_intrinsics", since = "1.59.0")
72204)]
72205#[cfg_attr(
72206    target_arch = "arm",
72207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72208)]
72209pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
72210    let c: u32x4 = u32x4::new(16, 16, 16, 16);
72211    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72212}
72213#[doc = "Subtract returning high narrow"]
72214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
72215#[inline]
72216#[target_feature(enable = "neon")]
72217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72219#[cfg_attr(
72220    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72221    assert_instr(subhn)
72222)]
72223#[cfg_attr(
72224    not(target_arch = "arm"),
72225    stable(feature = "neon_intrinsics", since = "1.59.0")
72226)]
72227#[cfg_attr(
72228    target_arch = "arm",
72229    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72230)]
72231pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
72232    let c: u64x2 = u64x2::new(32, 32);
72233    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72234}
72235#[doc = "Signed Subtract Long"]
72236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
72237#[inline]
72238#[target_feature(enable = "neon")]
72239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72241#[cfg_attr(
72242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72243    assert_instr(ssubl)
72244)]
72245#[cfg_attr(
72246    not(target_arch = "arm"),
72247    stable(feature = "neon_intrinsics", since = "1.59.0")
72248)]
72249#[cfg_attr(
72250    target_arch = "arm",
72251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72252)]
72253pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
72254    unsafe {
72255        let c: int16x8_t = simd_cast(a);
72256        let d: int16x8_t = simd_cast(b);
72257        simd_sub(c, d)
72258    }
72259}
72260#[doc = "Signed Subtract Long"]
72261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
72262#[inline]
72263#[target_feature(enable = "neon")]
72264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72266#[cfg_attr(
72267    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72268    assert_instr(ssubl)
72269)]
72270#[cfg_attr(
72271    not(target_arch = "arm"),
72272    stable(feature = "neon_intrinsics", since = "1.59.0")
72273)]
72274#[cfg_attr(
72275    target_arch = "arm",
72276    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72277)]
72278pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
72279    unsafe {
72280        let c: int32x4_t = simd_cast(a);
72281        let d: int32x4_t = simd_cast(b);
72282        simd_sub(c, d)
72283    }
72284}
72285#[doc = "Signed Subtract Long"]
72286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
72287#[inline]
72288#[target_feature(enable = "neon")]
72289#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72290#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72291#[cfg_attr(
72292    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72293    assert_instr(ssubl)
72294)]
72295#[cfg_attr(
72296    not(target_arch = "arm"),
72297    stable(feature = "neon_intrinsics", since = "1.59.0")
72298)]
72299#[cfg_attr(
72300    target_arch = "arm",
72301    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72302)]
72303pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
72304    unsafe {
72305        let c: int64x2_t = simd_cast(a);
72306        let d: int64x2_t = simd_cast(b);
72307        simd_sub(c, d)
72308    }
72309}
72310#[doc = "Unsigned Subtract Long"]
72311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
72312#[inline]
72313#[target_feature(enable = "neon")]
72314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72316#[cfg_attr(
72317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72318    assert_instr(usubl)
72319)]
72320#[cfg_attr(
72321    not(target_arch = "arm"),
72322    stable(feature = "neon_intrinsics", since = "1.59.0")
72323)]
72324#[cfg_attr(
72325    target_arch = "arm",
72326    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72327)]
72328pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
72329    unsafe {
72330        let c: uint16x8_t = simd_cast(a);
72331        let d: uint16x8_t = simd_cast(b);
72332        simd_sub(c, d)
72333    }
72334}
72335#[doc = "Unsigned Subtract Long"]
72336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
72337#[inline]
72338#[target_feature(enable = "neon")]
72339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72341#[cfg_attr(
72342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72343    assert_instr(usubl)
72344)]
72345#[cfg_attr(
72346    not(target_arch = "arm"),
72347    stable(feature = "neon_intrinsics", since = "1.59.0")
72348)]
72349#[cfg_attr(
72350    target_arch = "arm",
72351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72352)]
72353pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
72354    unsafe {
72355        let c: uint32x4_t = simd_cast(a);
72356        let d: uint32x4_t = simd_cast(b);
72357        simd_sub(c, d)
72358    }
72359}
72360#[doc = "Unsigned Subtract Long"]
72361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
72362#[inline]
72363#[target_feature(enable = "neon")]
72364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72366#[cfg_attr(
72367    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72368    assert_instr(usubl)
72369)]
72370#[cfg_attr(
72371    not(target_arch = "arm"),
72372    stable(feature = "neon_intrinsics", since = "1.59.0")
72373)]
72374#[cfg_attr(
72375    target_arch = "arm",
72376    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72377)]
72378pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
72379    unsafe {
72380        let c: uint64x2_t = simd_cast(a);
72381        let d: uint64x2_t = simd_cast(b);
72382        simd_sub(c, d)
72383    }
72384}
72385#[doc = "Signed Subtract Wide"]
72386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
72387#[inline]
72388#[target_feature(enable = "neon")]
72389#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72391#[cfg_attr(
72392    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72393    assert_instr(ssubw)
72394)]
72395#[cfg_attr(
72396    not(target_arch = "arm"),
72397    stable(feature = "neon_intrinsics", since = "1.59.0")
72398)]
72399#[cfg_attr(
72400    target_arch = "arm",
72401    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72402)]
72403pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
72404    unsafe { simd_sub(a, simd_cast(b)) }
72405}
72406#[doc = "Signed Subtract Wide"]
72407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
72408#[inline]
72409#[target_feature(enable = "neon")]
72410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72412#[cfg_attr(
72413    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72414    assert_instr(ssubw)
72415)]
72416#[cfg_attr(
72417    not(target_arch = "arm"),
72418    stable(feature = "neon_intrinsics", since = "1.59.0")
72419)]
72420#[cfg_attr(
72421    target_arch = "arm",
72422    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72423)]
72424pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
72425    unsafe { simd_sub(a, simd_cast(b)) }
72426}
72427#[doc = "Signed Subtract Wide"]
72428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
72429#[inline]
72430#[target_feature(enable = "neon")]
72431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72433#[cfg_attr(
72434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72435    assert_instr(ssubw)
72436)]
72437#[cfg_attr(
72438    not(target_arch = "arm"),
72439    stable(feature = "neon_intrinsics", since = "1.59.0")
72440)]
72441#[cfg_attr(
72442    target_arch = "arm",
72443    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72444)]
72445pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
72446    unsafe { simd_sub(a, simd_cast(b)) }
72447}
72448#[doc = "Unsigned Subtract Wide"]
72449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
72450#[inline]
72451#[target_feature(enable = "neon")]
72452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72454#[cfg_attr(
72455    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72456    assert_instr(usubw)
72457)]
72458#[cfg_attr(
72459    not(target_arch = "arm"),
72460    stable(feature = "neon_intrinsics", since = "1.59.0")
72461)]
72462#[cfg_attr(
72463    target_arch = "arm",
72464    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72465)]
72466pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
72467    unsafe { simd_sub(a, simd_cast(b)) }
72468}
72469#[doc = "Unsigned Subtract Wide"]
72470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
72471#[inline]
72472#[target_feature(enable = "neon")]
72473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72475#[cfg_attr(
72476    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72477    assert_instr(usubw)
72478)]
72479#[cfg_attr(
72480    not(target_arch = "arm"),
72481    stable(feature = "neon_intrinsics", since = "1.59.0")
72482)]
72483#[cfg_attr(
72484    target_arch = "arm",
72485    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72486)]
72487pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
72488    unsafe { simd_sub(a, simd_cast(b)) }
72489}
72490#[doc = "Unsigned Subtract Wide"]
72491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
72492#[inline]
72493#[target_feature(enable = "neon")]
72494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72496#[cfg_attr(
72497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72498    assert_instr(usubw)
72499)]
72500#[cfg_attr(
72501    not(target_arch = "arm"),
72502    stable(feature = "neon_intrinsics", since = "1.59.0")
72503)]
72504#[cfg_attr(
72505    target_arch = "arm",
72506    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72507)]
72508pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
72509    unsafe { simd_sub(a, simd_cast(b)) }
72510}
72511#[doc = "Dot product index form with signed and unsigned integers"]
72512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
72513#[inline]
72514#[target_feature(enable = "neon,i8mm")]
72515#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72517#[cfg_attr(
72518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72519    assert_instr(sudot, LANE = 0)
72520)]
72521#[rustc_legacy_const_generics(3)]
72522#[cfg_attr(
72523    not(target_arch = "arm"),
72524    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72525)]
72526#[cfg_attr(
72527    target_arch = "arm",
72528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72529)]
72530pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
72531    static_assert_uimm_bits!(LANE, 1);
72532    unsafe {
72533        let c: uint32x2_t = transmute(c);
72534        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
72535        vusdot_s32(a, transmute(c), b)
72536    }
72537}
72538#[doc = "Dot product index form with signed and unsigned integers"]
72539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
72540#[inline]
72541#[target_feature(enable = "neon,i8mm")]
72542#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72544#[cfg_attr(
72545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72546    assert_instr(sudot, LANE = 0)
72547)]
72548#[rustc_legacy_const_generics(3)]
72549#[cfg_attr(
72550    not(target_arch = "arm"),
72551    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72552)]
72553#[cfg_attr(
72554    target_arch = "arm",
72555    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72556)]
72557pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
72558    static_assert_uimm_bits!(LANE, 1);
72559    unsafe {
72560        let c: uint32x2_t = transmute(c);
72561        let c: uint32x4_t =
72562            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
72563        vusdotq_s32(a, transmute(c), b)
72564    }
72565}
72566#[doc = "Table look-up"]
72567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
72568#[inline]
72569#[target_feature(enable = "neon")]
72570#[cfg(target_arch = "arm")]
72571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72572#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72573#[cfg_attr(test, assert_instr(vtbl))]
72574fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72575    unsafe extern "unadjusted" {
72576        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")]
72577        fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
72578    }
72579    unsafe { _vtbl1(a, b) }
72580}
72581#[doc = "Table look-up"]
72582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
72583#[inline]
72584#[target_feature(enable = "neon")]
72585#[cfg(target_arch = "arm")]
72586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72587#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72588#[cfg_attr(test, assert_instr(vtbl))]
72589pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72590    vtbl1(a, b)
72591}
72592#[doc = "Table look-up"]
72593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72594#[inline]
72595#[cfg(target_endian = "little")]
72596#[target_feature(enable = "neon")]
72597#[cfg(target_arch = "arm")]
72598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72599#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72600#[cfg_attr(test, assert_instr(vtbl))]
72601pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72602    unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72603}
72604#[doc = "Table look-up"]
72605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72606#[inline]
72607#[cfg(target_endian = "big")]
72608#[target_feature(enable = "neon")]
72609#[cfg(target_arch = "arm")]
72610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72611#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72612#[cfg_attr(test, assert_instr(vtbl))]
72613pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72614    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72615    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72616    unsafe {
72617        let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72618        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72619    }
72620}
72621#[doc = "Table look-up"]
72622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72623#[inline]
72624#[cfg(target_endian = "little")]
72625#[target_feature(enable = "neon")]
72626#[cfg(target_arch = "arm")]
72627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72628#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72629#[cfg_attr(test, assert_instr(vtbl))]
72630pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72631    unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72632}
72633#[doc = "Table look-up"]
72634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72635#[inline]
72636#[cfg(target_endian = "big")]
72637#[target_feature(enable = "neon")]
72638#[cfg(target_arch = "arm")]
72639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72640#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72641#[cfg_attr(test, assert_instr(vtbl))]
72642pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72643    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72644    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72645    unsafe {
72646        let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72647        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72648    }
72649}
72650#[doc = "Table look-up"]
72651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
72652#[inline]
72653#[target_feature(enable = "neon")]
72654#[cfg(target_arch = "arm")]
72655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72656#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72657#[cfg_attr(test, assert_instr(vtbl))]
72658fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72659    unsafe extern "unadjusted" {
72660        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")]
72661        fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72662    }
72663    unsafe { _vtbl2(a, b, c) }
72664}
72665#[doc = "Table look-up"]
72666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
72667#[inline]
72668#[target_feature(enable = "neon")]
72669#[cfg(target_arch = "arm")]
72670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72671#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72672#[cfg_attr(test, assert_instr(vtbl))]
72673pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
72674    vtbl2(a.0, a.1, b)
72675}
72676#[doc = "Table look-up"]
72677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72678#[inline]
72679#[cfg(target_endian = "little")]
72680#[target_feature(enable = "neon")]
72681#[cfg(target_arch = "arm")]
72682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72683#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72684#[cfg_attr(test, assert_instr(vtbl))]
72685pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72686    unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72687}
72688#[doc = "Table look-up"]
72689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72690#[inline]
72691#[cfg(target_endian = "big")]
72692#[target_feature(enable = "neon")]
72693#[cfg(target_arch = "arm")]
72694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72695#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72696#[cfg_attr(test, assert_instr(vtbl))]
72697pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72698    let mut a: uint8x8x2_t = a;
72699    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72700    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72701    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72702    unsafe {
72703        let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72704        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72705    }
72706}
72707#[doc = "Table look-up"]
72708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72709#[inline]
72710#[cfg(target_endian = "little")]
72711#[target_feature(enable = "neon")]
72712#[cfg(target_arch = "arm")]
72713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72714#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72715#[cfg_attr(test, assert_instr(vtbl))]
72716pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72717    unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72718}
72719#[doc = "Table look-up"]
72720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72721#[inline]
72722#[cfg(target_endian = "big")]
72723#[target_feature(enable = "neon")]
72724#[cfg(target_arch = "arm")]
72725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72726#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72727#[cfg_attr(test, assert_instr(vtbl))]
72728pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72729    let mut a: poly8x8x2_t = a;
72730    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72731    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72732    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72733    unsafe {
72734        let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72735        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72736    }
72737}
72738#[doc = "Table look-up"]
72739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
72740#[inline]
72741#[target_feature(enable = "neon")]
72742#[cfg(target_arch = "arm")]
72743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72744#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72745#[cfg_attr(test, assert_instr(vtbl))]
72746fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72747    unsafe extern "unadjusted" {
72748        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")]
72749        fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72750    }
72751    unsafe { _vtbl3(a, b, c, d) }
72752}
72753#[doc = "Table look-up"]
72754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
72755#[inline]
72756#[target_feature(enable = "neon")]
72757#[cfg(target_arch = "arm")]
72758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72759#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72760#[cfg_attr(test, assert_instr(vtbl))]
72761pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
72762    vtbl3(a.0, a.1, a.2, b)
72763}
72764#[doc = "Table look-up"]
72765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72766#[inline]
72767#[cfg(target_endian = "little")]
72768#[target_feature(enable = "neon")]
72769#[cfg(target_arch = "arm")]
72770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72771#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72772#[cfg_attr(test, assert_instr(vtbl))]
72773pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72774    unsafe {
72775        transmute(vtbl3(
72776            transmute(a.0),
72777            transmute(a.1),
72778            transmute(a.2),
72779            transmute(b),
72780        ))
72781    }
72782}
72783#[doc = "Table look-up"]
72784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72785#[inline]
72786#[cfg(target_endian = "big")]
72787#[target_feature(enable = "neon")]
72788#[cfg(target_arch = "arm")]
72789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72790#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72791#[cfg_attr(test, assert_instr(vtbl))]
72792pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72793    let mut a: uint8x8x3_t = a;
72794    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72795    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72796    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72797    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72798    unsafe {
72799        let ret_val: uint8x8_t = transmute(vtbl3(
72800            transmute(a.0),
72801            transmute(a.1),
72802            transmute(a.2),
72803            transmute(b),
72804        ));
72805        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72806    }
72807}
72808#[doc = "Table look-up"]
72809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72810#[inline]
72811#[cfg(target_endian = "little")]
72812#[target_feature(enable = "neon")]
72813#[cfg(target_arch = "arm")]
72814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72815#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72816#[cfg_attr(test, assert_instr(vtbl))]
72817pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72818    unsafe {
72819        transmute(vtbl3(
72820            transmute(a.0),
72821            transmute(a.1),
72822            transmute(a.2),
72823            transmute(b),
72824        ))
72825    }
72826}
72827#[doc = "Table look-up"]
72828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72829#[inline]
72830#[cfg(target_endian = "big")]
72831#[target_feature(enable = "neon")]
72832#[cfg(target_arch = "arm")]
72833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72834#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72835#[cfg_attr(test, assert_instr(vtbl))]
72836pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72837    let mut a: poly8x8x3_t = a;
72838    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72839    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72840    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72841    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72842    unsafe {
72843        let ret_val: poly8x8_t = transmute(vtbl3(
72844            transmute(a.0),
72845            transmute(a.1),
72846            transmute(a.2),
72847            transmute(b),
72848        ));
72849        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72850    }
72851}
72852#[doc = "Table look-up"]
72853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
72854#[inline]
72855#[target_feature(enable = "neon")]
72856#[cfg(target_arch = "arm")]
72857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72858#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72859#[cfg_attr(test, assert_instr(vtbl))]
72860fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
72861    unsafe extern "unadjusted" {
72862        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")]
72863        fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
72864    }
72865    unsafe { _vtbl4(a, b, c, d, e) }
72866}
72867#[doc = "Table look-up"]
72868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
72869#[inline]
72870#[target_feature(enable = "neon")]
72871#[cfg(target_arch = "arm")]
72872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72873#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72874#[cfg_attr(test, assert_instr(vtbl))]
72875pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
72876    vtbl4(a.0, a.1, a.2, a.3, b)
72877}
72878#[doc = "Table look-up"]
72879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72880#[inline]
72881#[cfg(target_endian = "little")]
72882#[target_feature(enable = "neon")]
72883#[cfg(target_arch = "arm")]
72884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72885#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72886#[cfg_attr(test, assert_instr(vtbl))]
72887pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72888    unsafe {
72889        transmute(vtbl4(
72890            transmute(a.0),
72891            transmute(a.1),
72892            transmute(a.2),
72893            transmute(a.3),
72894            transmute(b),
72895        ))
72896    }
72897}
72898#[doc = "Table look-up"]
72899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72900#[inline]
72901#[cfg(target_endian = "big")]
72902#[target_feature(enable = "neon")]
72903#[cfg(target_arch = "arm")]
72904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72905#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72906#[cfg_attr(test, assert_instr(vtbl))]
72907pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72908    let mut a: uint8x8x4_t = a;
72909    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72910    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72911    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72912    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72913    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72914    unsafe {
72915        let ret_val: uint8x8_t = transmute(vtbl4(
72916            transmute(a.0),
72917            transmute(a.1),
72918            transmute(a.2),
72919            transmute(a.3),
72920            transmute(b),
72921        ));
72922        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72923    }
72924}
72925#[doc = "Table look-up"]
72926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72927#[inline]
72928#[cfg(target_endian = "little")]
72929#[target_feature(enable = "neon")]
72930#[cfg(target_arch = "arm")]
72931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72932#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72933#[cfg_attr(test, assert_instr(vtbl))]
72934pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72935    unsafe {
72936        transmute(vtbl4(
72937            transmute(a.0),
72938            transmute(a.1),
72939            transmute(a.2),
72940            transmute(a.3),
72941            transmute(b),
72942        ))
72943    }
72944}
72945#[doc = "Table look-up"]
72946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72947#[inline]
72948#[cfg(target_endian = "big")]
72949#[target_feature(enable = "neon")]
72950#[cfg(target_arch = "arm")]
72951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72952#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72953#[cfg_attr(test, assert_instr(vtbl))]
72954pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72955    let mut a: poly8x8x4_t = a;
72956    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72957    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72958    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72959    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72960    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72961    unsafe {
72962        let ret_val: poly8x8_t = transmute(vtbl4(
72963            transmute(a.0),
72964            transmute(a.1),
72965            transmute(a.2),
72966            transmute(a.3),
72967            transmute(b),
72968        ));
72969        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72970    }
72971}
72972#[doc = "Extended table look-up"]
72973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
72974#[inline]
72975#[target_feature(enable = "neon,v7")]
72976#[cfg(target_arch = "arm")]
72977#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72978#[cfg_attr(test, assert_instr(vtbx))]
72979fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72980    unsafe extern "unadjusted" {
72981        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")]
72982        fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72983    }
72984    unsafe { _vtbx1(a, b, c) }
72985}
72986#[doc = "Extended table look-up"]
72987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
72988#[inline]
72989#[target_feature(enable = "neon,v7")]
72990#[cfg(target_arch = "arm")]
72991#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72992#[cfg_attr(test, assert_instr(vtbx))]
72993pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72994    vtbx1(a, b, c)
72995}
72996#[doc = "Extended table look-up"]
72997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72998#[inline]
72999#[cfg(target_endian = "little")]
73000#[target_feature(enable = "neon,v7")]
73001#[cfg(target_arch = "arm")]
73002#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73003#[cfg_attr(test, assert_instr(vtbx))]
73004pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
73005    unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
73006}
73007#[doc = "Extended table look-up"]
73008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
73009#[inline]
73010#[cfg(target_endian = "big")]
73011#[target_feature(enable = "neon,v7")]
73012#[cfg(target_arch = "arm")]
73013#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73014#[cfg_attr(test, assert_instr(vtbx))]
73015pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
73016    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73017    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
73018    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73019    unsafe {
73020        let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
73021        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73022    }
73023}
73024#[doc = "Extended table look-up"]
73025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
73026#[inline]
73027#[cfg(target_endian = "little")]
73028#[target_feature(enable = "neon,v7")]
73029#[cfg(target_arch = "arm")]
73030#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73031#[cfg_attr(test, assert_instr(vtbx))]
73032pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
73033    unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
73034}
73035#[doc = "Extended table look-up"]
73036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
73037#[inline]
73038#[cfg(target_endian = "big")]
73039#[target_feature(enable = "neon,v7")]
73040#[cfg(target_arch = "arm")]
73041#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73042#[cfg_attr(test, assert_instr(vtbx))]
73043pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
73044    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73045    let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
73046    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73047    unsafe {
73048        let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
73049        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73050    }
73051}
73052#[doc = "Extended table look-up"]
73053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
73054#[inline]
73055#[target_feature(enable = "neon,v7")]
73056#[cfg(target_arch = "arm")]
73057#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73058#[cfg_attr(test, assert_instr(vtbx))]
73059fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
73060    unsafe extern "unadjusted" {
73061        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")]
73062        fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
73063    }
73064    unsafe { _vtbx2(a, b, c, d) }
73065}
73066#[doc = "Extended table look-up"]
73067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
73068#[inline]
73069#[target_feature(enable = "neon,v7")]
73070#[cfg(target_arch = "arm")]
73071#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73072#[cfg_attr(test, assert_instr(vtbx))]
73073pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
73074    vtbx2(a, b.0, b.1, c)
73075}
73076#[doc = "Extended table look-up"]
73077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73078#[inline]
73079#[cfg(target_endian = "little")]
73080#[target_feature(enable = "neon,v7")]
73081#[cfg(target_arch = "arm")]
73082#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73083#[cfg_attr(test, assert_instr(vtbx))]
73084pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73085    unsafe {
73086        transmute(vtbx2(
73087            transmute(a),
73088            transmute(b.0),
73089            transmute(b.1),
73090            transmute(c),
73091        ))
73092    }
73093}
73094#[doc = "Extended table look-up"]
73095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73096#[inline]
73097#[cfg(target_endian = "big")]
73098#[target_feature(enable = "neon,v7")]
73099#[cfg(target_arch = "arm")]
73100#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73101#[cfg_attr(test, assert_instr(vtbx))]
73102pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73103    let mut b: uint8x8x2_t = b;
73104    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73105    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73106    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73107    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73108    unsafe {
73109        let ret_val: uint8x8_t = transmute(vtbx2(
73110            transmute(a),
73111            transmute(b.0),
73112            transmute(b.1),
73113            transmute(c),
73114        ));
73115        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73116    }
73117}
73118#[doc = "Extended table look-up"]
73119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73120#[inline]
73121#[cfg(target_endian = "little")]
73122#[target_feature(enable = "neon,v7")]
73123#[cfg(target_arch = "arm")]
73124#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73125#[cfg_attr(test, assert_instr(vtbx))]
73126pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73127    unsafe {
73128        transmute(vtbx2(
73129            transmute(a),
73130            transmute(b.0),
73131            transmute(b.1),
73132            transmute(c),
73133        ))
73134    }
73135}
73136#[doc = "Extended table look-up"]
73137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73138#[inline]
73139#[cfg(target_endian = "big")]
73140#[target_feature(enable = "neon,v7")]
73141#[cfg(target_arch = "arm")]
73142#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73143#[cfg_attr(test, assert_instr(vtbx))]
73144pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73145    let mut b: poly8x8x2_t = b;
73146    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73147    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73148    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73149    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73150    unsafe {
73151        let ret_val: poly8x8_t = transmute(vtbx2(
73152            transmute(a),
73153            transmute(b.0),
73154            transmute(b.1),
73155            transmute(c),
73156        ));
73157        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73158    }
73159}
73160#[doc = "Extended table look-up"]
73161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
73162#[inline]
73163#[target_feature(enable = "neon,v7")]
73164#[cfg(target_arch = "arm")]
73165#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73166#[cfg_attr(test, assert_instr(vtbx))]
73167fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
73168    unsafe extern "unadjusted" {
73169        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")]
73170        fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
73171    }
73172    unsafe { _vtbx3(a, b, c, d, e) }
73173}
73174#[doc = "Extended table look-up"]
73175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
73176#[inline]
73177#[target_feature(enable = "neon,v7")]
73178#[cfg(target_arch = "arm")]
73179#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73180#[cfg_attr(test, assert_instr(vtbx))]
73181pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
73182    vtbx3(a, b.0, b.1, b.2, c)
73183}
73184#[doc = "Extended table look-up"]
73185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73186#[inline]
73187#[cfg(target_endian = "little")]
73188#[target_feature(enable = "neon,v7")]
73189#[cfg(target_arch = "arm")]
73190#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73191#[cfg_attr(test, assert_instr(vtbx))]
73192pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73193    unsafe {
73194        transmute(vtbx3(
73195            transmute(a),
73196            transmute(b.0),
73197            transmute(b.1),
73198            transmute(b.2),
73199            transmute(c),
73200        ))
73201    }
73202}
73203#[doc = "Extended table look-up"]
73204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73205#[inline]
73206#[cfg(target_endian = "big")]
73207#[target_feature(enable = "neon,v7")]
73208#[cfg(target_arch = "arm")]
73209#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73210#[cfg_attr(test, assert_instr(vtbx))]
73211pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73212    let mut b: uint8x8x3_t = b;
73213    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73214    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73215    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73216    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73217    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73218    unsafe {
73219        let ret_val: uint8x8_t = transmute(vtbx3(
73220            transmute(a),
73221            transmute(b.0),
73222            transmute(b.1),
73223            transmute(b.2),
73224            transmute(c),
73225        ));
73226        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73227    }
73228}
73229#[doc = "Extended table look-up"]
73230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73231#[inline]
73232#[cfg(target_endian = "little")]
73233#[target_feature(enable = "neon,v7")]
73234#[cfg(target_arch = "arm")]
73235#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73236#[cfg_attr(test, assert_instr(vtbx))]
73237pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73238    unsafe {
73239        transmute(vtbx3(
73240            transmute(a),
73241            transmute(b.0),
73242            transmute(b.1),
73243            transmute(b.2),
73244            transmute(c),
73245        ))
73246    }
73247}
73248#[doc = "Extended table look-up"]
73249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73250#[inline]
73251#[cfg(target_endian = "big")]
73252#[target_feature(enable = "neon,v7")]
73253#[cfg(target_arch = "arm")]
73254#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73255#[cfg_attr(test, assert_instr(vtbx))]
73256pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73257    let mut b: poly8x8x3_t = b;
73258    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73259    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73260    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73261    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73262    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73263    unsafe {
73264        let ret_val: poly8x8_t = transmute(vtbx3(
73265            transmute(a),
73266            transmute(b.0),
73267            transmute(b.1),
73268            transmute(b.2),
73269            transmute(c),
73270        ));
73271        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73272    }
73273}
73274#[doc = "Extended table look-up"]
73275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
73276#[inline]
73277#[target_feature(enable = "neon,v7")]
73278#[cfg(target_arch = "arm")]
73279#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73280#[cfg_attr(test, assert_instr(vtbx))]
73281fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t {
73282    unsafe extern "unadjusted" {
73283        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")]
73284        fn _vtbx4(
73285            a: int8x8_t,
73286            b: int8x8_t,
73287            c: int8x8_t,
73288            d: int8x8_t,
73289            e: int8x8_t,
73290            f: int8x8_t,
73291        ) -> int8x8_t;
73292    }
73293    unsafe { _vtbx4(a, b, c, d, e, f) }
73294}
73295#[doc = "Extended table look-up"]
73296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73297#[inline]
73298#[cfg(target_endian = "little")]
73299#[target_feature(enable = "neon,v7")]
73300#[cfg(target_arch = "arm")]
73301#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73302#[cfg_attr(test, assert_instr(vtbx))]
73303pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73304    unsafe {
73305        vtbx4(
73306            a,
73307            transmute(b.0),
73308            transmute(b.1),
73309            transmute(b.2),
73310            transmute(b.3),
73311            c,
73312        )
73313    }
73314}
73315#[doc = "Extended table look-up"]
73316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73317#[inline]
73318#[cfg(target_endian = "big")]
73319#[target_feature(enable = "neon,v7")]
73320#[cfg(target_arch = "arm")]
73321#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73322#[cfg_attr(test, assert_instr(vtbx))]
73323pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73324    let mut b: int8x8x4_t = b;
73325    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73326    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73327    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73328    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73329    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73330    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73331    unsafe {
73332        let ret_val: int8x8_t = vtbx4(
73333            a,
73334            transmute(b.0),
73335            transmute(b.1),
73336            transmute(b.2),
73337            transmute(b.3),
73338            c,
73339        );
73340        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73341    }
73342}
73343#[doc = "Extended table look-up"]
73344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73345#[inline]
73346#[cfg(target_endian = "little")]
73347#[target_feature(enable = "neon,v7")]
73348#[cfg(target_arch = "arm")]
73349#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73350#[cfg_attr(test, assert_instr(vtbx))]
73351pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73352    unsafe {
73353        transmute(vtbx4(
73354            transmute(a),
73355            transmute(b.0),
73356            transmute(b.1),
73357            transmute(b.2),
73358            transmute(b.3),
73359            transmute(c),
73360        ))
73361    }
73362}
73363#[doc = "Extended table look-up"]
73364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73365#[inline]
73366#[cfg(target_endian = "big")]
73367#[target_feature(enable = "neon,v7")]
73368#[cfg(target_arch = "arm")]
73369#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73370#[cfg_attr(test, assert_instr(vtbx))]
73371pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73372    let mut b: uint8x8x4_t = b;
73373    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73374    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73375    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73376    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73377    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73378    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73379    unsafe {
73380        let ret_val: uint8x8_t = transmute(vtbx4(
73381            transmute(a),
73382            transmute(b.0),
73383            transmute(b.1),
73384            transmute(b.2),
73385            transmute(b.3),
73386            transmute(c),
73387        ));
73388        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73389    }
73390}
73391#[doc = "Extended table look-up"]
73392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73393#[inline]
73394#[cfg(target_endian = "little")]
73395#[target_feature(enable = "neon,v7")]
73396#[cfg(target_arch = "arm")]
73397#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73398#[cfg_attr(test, assert_instr(vtbx))]
73399pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73400    unsafe {
73401        transmute(vtbx4(
73402            transmute(a),
73403            transmute(b.0),
73404            transmute(b.1),
73405            transmute(b.2),
73406            transmute(b.3),
73407            transmute(c),
73408        ))
73409    }
73410}
73411#[doc = "Extended table look-up"]
73412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73413#[inline]
73414#[cfg(target_endian = "big")]
73415#[target_feature(enable = "neon,v7")]
73416#[cfg(target_arch = "arm")]
73417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73418#[cfg_attr(test, assert_instr(vtbx))]
73419pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73420    let mut b: poly8x8x4_t = b;
73421    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73422    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73423    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73424    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73425    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73426    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73427    unsafe {
73428        let ret_val: poly8x8_t = transmute(vtbx4(
73429            transmute(a),
73430            transmute(b.0),
73431            transmute(b.1),
73432            transmute(b.2),
73433            transmute(b.3),
73434            transmute(c),
73435        ));
73436        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73437    }
73438}
73439#[doc = "Transpose elements"]
73440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
73441#[inline]
73442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73444#[cfg_attr(
73445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73446    assert_instr(trn)
73447)]
73448#[target_feature(enable = "neon,fp16")]
73449#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73450pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
73451    unsafe {
73452        let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73453        let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73454        transmute((a1, b1))
73455    }
73456}
73457#[doc = "Transpose elements"]
73458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
73459#[inline]
73460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73462#[cfg_attr(
73463    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73464    assert_instr(trn)
73465)]
73466#[target_feature(enable = "neon,fp16")]
73467#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73468pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
73469    unsafe {
73470        let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73471        let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73472        transmute((a1, b1))
73473    }
73474}
73475#[doc = "Transpose elements"]
73476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
73477#[inline]
73478#[target_feature(enable = "neon")]
73479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73481#[cfg_attr(
73482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73483    assert_instr(zip)
73484)]
73485#[cfg_attr(
73486    not(target_arch = "arm"),
73487    stable(feature = "neon_intrinsics", since = "1.59.0")
73488)]
73489#[cfg_attr(
73490    target_arch = "arm",
73491    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73492)]
73493pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
73494    unsafe {
73495        let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]);
73496        let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]);
73497        transmute((a1, b1))
73498    }
73499}
73500#[doc = "Transpose elements"]
73501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
73502#[inline]
73503#[target_feature(enable = "neon")]
73504#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73506#[cfg_attr(
73507    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73508    assert_instr(zip)
73509)]
73510#[cfg_attr(
73511    not(target_arch = "arm"),
73512    stable(feature = "neon_intrinsics", since = "1.59.0")
73513)]
73514#[cfg_attr(
73515    target_arch = "arm",
73516    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73517)]
73518pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
73519    unsafe {
73520        let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]);
73521        let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]);
73522        transmute((a1, b1))
73523    }
73524}
73525#[doc = "Transpose elements"]
73526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
73527#[inline]
73528#[target_feature(enable = "neon")]
73529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73531#[cfg_attr(
73532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73533    assert_instr(zip)
73534)]
73535#[cfg_attr(
73536    not(target_arch = "arm"),
73537    stable(feature = "neon_intrinsics", since = "1.59.0")
73538)]
73539#[cfg_attr(
73540    target_arch = "arm",
73541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73542)]
73543pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
73544    unsafe {
73545        let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
73546        let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
73547        transmute((a1, b1))
73548    }
73549}
73550#[doc = "Transpose elements"]
73551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
73552#[inline]
73553#[target_feature(enable = "neon")]
73554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73556#[cfg_attr(
73557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73558    assert_instr(trn)
73559)]
73560#[cfg_attr(
73561    not(target_arch = "arm"),
73562    stable(feature = "neon_intrinsics", since = "1.59.0")
73563)]
73564#[cfg_attr(
73565    target_arch = "arm",
73566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73567)]
73568pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
73569    unsafe {
73570        let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73571        let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73572        transmute((a1, b1))
73573    }
73574}
73575#[doc = "Transpose elements"]
73576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
73577#[inline]
73578#[target_feature(enable = "neon")]
73579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73581#[cfg_attr(
73582    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73583    assert_instr(trn)
73584)]
73585#[cfg_attr(
73586    not(target_arch = "arm"),
73587    stable(feature = "neon_intrinsics", since = "1.59.0")
73588)]
73589#[cfg_attr(
73590    target_arch = "arm",
73591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73592)]
73593pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
73594    unsafe {
73595        let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73596        let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73597        transmute((a1, b1))
73598    }
73599}
73600#[doc = "Transpose elements"]
73601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
73602#[inline]
73603#[target_feature(enable = "neon")]
73604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73606#[cfg_attr(
73607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73608    assert_instr(trn)
73609)]
73610#[cfg_attr(
73611    not(target_arch = "arm"),
73612    stable(feature = "neon_intrinsics", since = "1.59.0")
73613)]
73614#[cfg_attr(
73615    target_arch = "arm",
73616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73617)]
73618pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
73619    unsafe {
73620        let a1: int8x16_t = simd_shuffle!(
73621            a,
73622            b,
73623            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73624        );
73625        let b1: int8x16_t = simd_shuffle!(
73626            a,
73627            b,
73628            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73629        );
73630        transmute((a1, b1))
73631    }
73632}
73633#[doc = "Transpose elements"]
73634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
73635#[inline]
73636#[target_feature(enable = "neon")]
73637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73639#[cfg_attr(
73640    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73641    assert_instr(trn)
73642)]
73643#[cfg_attr(
73644    not(target_arch = "arm"),
73645    stable(feature = "neon_intrinsics", since = "1.59.0")
73646)]
73647#[cfg_attr(
73648    target_arch = "arm",
73649    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73650)]
73651pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
73652    unsafe {
73653        let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73654        let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73655        transmute((a1, b1))
73656    }
73657}
73658#[doc = "Transpose elements"]
73659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
73660#[inline]
73661#[target_feature(enable = "neon")]
73662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73664#[cfg_attr(
73665    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73666    assert_instr(trn)
73667)]
73668#[cfg_attr(
73669    not(target_arch = "arm"),
73670    stable(feature = "neon_intrinsics", since = "1.59.0")
73671)]
73672#[cfg_attr(
73673    target_arch = "arm",
73674    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73675)]
73676pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
73677    unsafe {
73678        let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73679        let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73680        transmute((a1, b1))
73681    }
73682}
73683#[doc = "Transpose elements"]
73684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
73685#[inline]
73686#[target_feature(enable = "neon")]
73687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73689#[cfg_attr(
73690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73691    assert_instr(trn)
73692)]
73693#[cfg_attr(
73694    not(target_arch = "arm"),
73695    stable(feature = "neon_intrinsics", since = "1.59.0")
73696)]
73697#[cfg_attr(
73698    target_arch = "arm",
73699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73700)]
73701pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
73702    unsafe {
73703        let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73704        let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73705        transmute((a1, b1))
73706    }
73707}
73708#[doc = "Transpose elements"]
73709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
73710#[inline]
73711#[target_feature(enable = "neon")]
73712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73714#[cfg_attr(
73715    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73716    assert_instr(trn)
73717)]
73718#[cfg_attr(
73719    not(target_arch = "arm"),
73720    stable(feature = "neon_intrinsics", since = "1.59.0")
73721)]
73722#[cfg_attr(
73723    target_arch = "arm",
73724    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73725)]
73726pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
73727    unsafe {
73728        let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73729        let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73730        transmute((a1, b1))
73731    }
73732}
73733#[doc = "Transpose elements"]
73734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
73735#[inline]
73736#[target_feature(enable = "neon")]
73737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73739#[cfg_attr(
73740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73741    assert_instr(trn)
73742)]
73743#[cfg_attr(
73744    not(target_arch = "arm"),
73745    stable(feature = "neon_intrinsics", since = "1.59.0")
73746)]
73747#[cfg_attr(
73748    target_arch = "arm",
73749    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73750)]
73751pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
73752    unsafe {
73753        let a1: uint8x16_t = simd_shuffle!(
73754            a,
73755            b,
73756            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73757        );
73758        let b1: uint8x16_t = simd_shuffle!(
73759            a,
73760            b,
73761            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73762        );
73763        transmute((a1, b1))
73764    }
73765}
73766#[doc = "Transpose elements"]
73767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
73768#[inline]
73769#[target_feature(enable = "neon")]
73770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73772#[cfg_attr(
73773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73774    assert_instr(trn)
73775)]
73776#[cfg_attr(
73777    not(target_arch = "arm"),
73778    stable(feature = "neon_intrinsics", since = "1.59.0")
73779)]
73780#[cfg_attr(
73781    target_arch = "arm",
73782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73783)]
73784pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
73785    unsafe {
73786        let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73787        let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73788        transmute((a1, b1))
73789    }
73790}
73791#[doc = "Transpose elements"]
73792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
73793#[inline]
73794#[target_feature(enable = "neon")]
73795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73797#[cfg_attr(
73798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73799    assert_instr(trn)
73800)]
73801#[cfg_attr(
73802    not(target_arch = "arm"),
73803    stable(feature = "neon_intrinsics", since = "1.59.0")
73804)]
73805#[cfg_attr(
73806    target_arch = "arm",
73807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73808)]
73809pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
73810    unsafe {
73811        let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73812        let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73813        transmute((a1, b1))
73814    }
73815}
73816#[doc = "Transpose elements"]
73817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
73818#[inline]
73819#[target_feature(enable = "neon")]
73820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73822#[cfg_attr(
73823    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73824    assert_instr(trn)
73825)]
73826#[cfg_attr(
73827    not(target_arch = "arm"),
73828    stable(feature = "neon_intrinsics", since = "1.59.0")
73829)]
73830#[cfg_attr(
73831    target_arch = "arm",
73832    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73833)]
73834pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
73835    unsafe {
73836        let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73837        let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73838        transmute((a1, b1))
73839    }
73840}
73841#[doc = "Transpose elements"]
73842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
73843#[inline]
73844#[target_feature(enable = "neon")]
73845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73846#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73847#[cfg_attr(
73848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73849    assert_instr(trn)
73850)]
73851#[cfg_attr(
73852    not(target_arch = "arm"),
73853    stable(feature = "neon_intrinsics", since = "1.59.0")
73854)]
73855#[cfg_attr(
73856    target_arch = "arm",
73857    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73858)]
73859pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
73860    unsafe {
73861        let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73862        let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73863        transmute((a1, b1))
73864    }
73865}
73866#[doc = "Transpose elements"]
73867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
73868#[inline]
73869#[target_feature(enable = "neon")]
73870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73872#[cfg_attr(
73873    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73874    assert_instr(trn)
73875)]
73876#[cfg_attr(
73877    not(target_arch = "arm"),
73878    stable(feature = "neon_intrinsics", since = "1.59.0")
73879)]
73880#[cfg_attr(
73881    target_arch = "arm",
73882    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73883)]
73884pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
73885    unsafe {
73886        let a1: poly8x16_t = simd_shuffle!(
73887            a,
73888            b,
73889            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73890        );
73891        let b1: poly8x16_t = simd_shuffle!(
73892            a,
73893            b,
73894            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73895        );
73896        transmute((a1, b1))
73897    }
73898}
73899#[doc = "Transpose elements"]
73900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
73901#[inline]
73902#[target_feature(enable = "neon")]
73903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73905#[cfg_attr(
73906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73907    assert_instr(trn)
73908)]
73909#[cfg_attr(
73910    not(target_arch = "arm"),
73911    stable(feature = "neon_intrinsics", since = "1.59.0")
73912)]
73913#[cfg_attr(
73914    target_arch = "arm",
73915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73916)]
73917pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
73918    unsafe {
73919        let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73920        let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73921        transmute((a1, b1))
73922    }
73923}
73924#[doc = "Transpose elements"]
73925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
73926#[inline]
73927#[target_feature(enable = "neon")]
73928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73930#[cfg_attr(
73931    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73932    assert_instr(trn)
73933)]
73934#[cfg_attr(
73935    not(target_arch = "arm"),
73936    stable(feature = "neon_intrinsics", since = "1.59.0")
73937)]
73938#[cfg_attr(
73939    target_arch = "arm",
73940    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73941)]
73942pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
73943    unsafe {
73944        let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73945        let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73946        transmute((a1, b1))
73947    }
73948}
73949#[doc = "Signed compare bitwise Test bits nonzero"]
73950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
73951#[inline]
73952#[target_feature(enable = "neon")]
73953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73955#[cfg_attr(
73956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73957    assert_instr(cmtst)
73958)]
73959#[cfg_attr(
73960    not(target_arch = "arm"),
73961    stable(feature = "neon_intrinsics", since = "1.59.0")
73962)]
73963#[cfg_attr(
73964    target_arch = "arm",
73965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73966)]
73967pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
73968    unsafe {
73969        let c: int8x8_t = simd_and(a, b);
73970        let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73971        simd_ne(c, transmute(d))
73972    }
73973}
73974#[doc = "Signed compare bitwise Test bits nonzero"]
73975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
73976#[inline]
73977#[target_feature(enable = "neon")]
73978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73980#[cfg_attr(
73981    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73982    assert_instr(cmtst)
73983)]
73984#[cfg_attr(
73985    not(target_arch = "arm"),
73986    stable(feature = "neon_intrinsics", since = "1.59.0")
73987)]
73988#[cfg_attr(
73989    target_arch = "arm",
73990    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73991)]
73992pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
73993    unsafe {
73994        let c: int8x16_t = simd_and(a, b);
73995        let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73996        simd_ne(c, transmute(d))
73997    }
73998}
73999#[doc = "Signed compare bitwise Test bits nonzero"]
74000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
74001#[inline]
74002#[target_feature(enable = "neon")]
74003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74005#[cfg_attr(
74006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74007    assert_instr(cmtst)
74008)]
74009#[cfg_attr(
74010    not(target_arch = "arm"),
74011    stable(feature = "neon_intrinsics", since = "1.59.0")
74012)]
74013#[cfg_attr(
74014    target_arch = "arm",
74015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74016)]
74017pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
74018    unsafe {
74019        let c: int16x4_t = simd_and(a, b);
74020        let d: i16x4 = i16x4::new(0, 0, 0, 0);
74021        simd_ne(c, transmute(d))
74022    }
74023}
74024#[doc = "Signed compare bitwise Test bits nonzero"]
74025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
74026#[inline]
74027#[target_feature(enable = "neon")]
74028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74030#[cfg_attr(
74031    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74032    assert_instr(cmtst)
74033)]
74034#[cfg_attr(
74035    not(target_arch = "arm"),
74036    stable(feature = "neon_intrinsics", since = "1.59.0")
74037)]
74038#[cfg_attr(
74039    target_arch = "arm",
74040    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74041)]
74042pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
74043    unsafe {
74044        let c: int16x8_t = simd_and(a, b);
74045        let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74046        simd_ne(c, transmute(d))
74047    }
74048}
74049#[doc = "Signed compare bitwise Test bits nonzero"]
74050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
74051#[inline]
74052#[target_feature(enable = "neon")]
74053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74055#[cfg_attr(
74056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74057    assert_instr(cmtst)
74058)]
74059#[cfg_attr(
74060    not(target_arch = "arm"),
74061    stable(feature = "neon_intrinsics", since = "1.59.0")
74062)]
74063#[cfg_attr(
74064    target_arch = "arm",
74065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74066)]
74067pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
74068    unsafe {
74069        let c: int32x2_t = simd_and(a, b);
74070        let d: i32x2 = i32x2::new(0, 0);
74071        simd_ne(c, transmute(d))
74072    }
74073}
74074#[doc = "Signed compare bitwise Test bits nonzero"]
74075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
74076#[inline]
74077#[target_feature(enable = "neon")]
74078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74080#[cfg_attr(
74081    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74082    assert_instr(cmtst)
74083)]
74084#[cfg_attr(
74085    not(target_arch = "arm"),
74086    stable(feature = "neon_intrinsics", since = "1.59.0")
74087)]
74088#[cfg_attr(
74089    target_arch = "arm",
74090    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74091)]
74092pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
74093    unsafe {
74094        let c: int32x4_t = simd_and(a, b);
74095        let d: i32x4 = i32x4::new(0, 0, 0, 0);
74096        simd_ne(c, transmute(d))
74097    }
74098}
74099#[doc = "Signed compare bitwise Test bits nonzero"]
74100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
74101#[inline]
74102#[target_feature(enable = "neon")]
74103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74105#[cfg_attr(
74106    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74107    assert_instr(cmtst)
74108)]
74109#[cfg_attr(
74110    not(target_arch = "arm"),
74111    stable(feature = "neon_intrinsics", since = "1.59.0")
74112)]
74113#[cfg_attr(
74114    target_arch = "arm",
74115    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74116)]
74117pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
74118    unsafe {
74119        let c: poly8x8_t = simd_and(a, b);
74120        let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74121        simd_ne(c, transmute(d))
74122    }
74123}
74124#[doc = "Signed compare bitwise Test bits nonzero"]
74125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
74126#[inline]
74127#[target_feature(enable = "neon")]
74128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74130#[cfg_attr(
74131    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74132    assert_instr(cmtst)
74133)]
74134#[cfg_attr(
74135    not(target_arch = "arm"),
74136    stable(feature = "neon_intrinsics", since = "1.59.0")
74137)]
74138#[cfg_attr(
74139    target_arch = "arm",
74140    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74141)]
74142pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
74143    unsafe {
74144        let c: poly8x16_t = simd_and(a, b);
74145        let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74146        simd_ne(c, transmute(d))
74147    }
74148}
74149#[doc = "Signed compare bitwise Test bits nonzero"]
74150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
74151#[inline]
74152#[target_feature(enable = "neon")]
74153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74155#[cfg_attr(
74156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74157    assert_instr(cmtst)
74158)]
74159#[cfg_attr(
74160    not(target_arch = "arm"),
74161    stable(feature = "neon_intrinsics", since = "1.59.0")
74162)]
74163#[cfg_attr(
74164    target_arch = "arm",
74165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74166)]
74167pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
74168    unsafe {
74169        let c: poly16x4_t = simd_and(a, b);
74170        let d: i16x4 = i16x4::new(0, 0, 0, 0);
74171        simd_ne(c, transmute(d))
74172    }
74173}
74174#[doc = "Signed compare bitwise Test bits nonzero"]
74175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
74176#[inline]
74177#[target_feature(enable = "neon")]
74178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74180#[cfg_attr(
74181    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74182    assert_instr(cmtst)
74183)]
74184#[cfg_attr(
74185    not(target_arch = "arm"),
74186    stable(feature = "neon_intrinsics", since = "1.59.0")
74187)]
74188#[cfg_attr(
74189    target_arch = "arm",
74190    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74191)]
74192pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
74193    unsafe {
74194        let c: poly16x8_t = simd_and(a, b);
74195        let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74196        simd_ne(c, transmute(d))
74197    }
74198}
74199#[doc = "Unsigned compare bitwise Test bits nonzero"]
74200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
74201#[inline]
74202#[target_feature(enable = "neon")]
74203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74205#[cfg_attr(
74206    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74207    assert_instr(cmtst)
74208)]
74209#[cfg_attr(
74210    not(target_arch = "arm"),
74211    stable(feature = "neon_intrinsics", since = "1.59.0")
74212)]
74213#[cfg_attr(
74214    target_arch = "arm",
74215    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74216)]
74217pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
74218    unsafe {
74219        let c: uint8x8_t = simd_and(a, b);
74220        let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74221        simd_ne(c, transmute(d))
74222    }
74223}
74224#[doc = "Unsigned compare bitwise Test bits nonzero"]
74225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
74226#[inline]
74227#[target_feature(enable = "neon")]
74228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74230#[cfg_attr(
74231    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74232    assert_instr(cmtst)
74233)]
74234#[cfg_attr(
74235    not(target_arch = "arm"),
74236    stable(feature = "neon_intrinsics", since = "1.59.0")
74237)]
74238#[cfg_attr(
74239    target_arch = "arm",
74240    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74241)]
74242pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
74243    unsafe {
74244        let c: uint8x16_t = simd_and(a, b);
74245        let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74246        simd_ne(c, transmute(d))
74247    }
74248}
74249#[doc = "Unsigned compare bitwise Test bits nonzero"]
74250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
74251#[inline]
74252#[target_feature(enable = "neon")]
74253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74255#[cfg_attr(
74256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74257    assert_instr(cmtst)
74258)]
74259#[cfg_attr(
74260    not(target_arch = "arm"),
74261    stable(feature = "neon_intrinsics", since = "1.59.0")
74262)]
74263#[cfg_attr(
74264    target_arch = "arm",
74265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74266)]
74267pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
74268    unsafe {
74269        let c: uint16x4_t = simd_and(a, b);
74270        let d: u16x4 = u16x4::new(0, 0, 0, 0);
74271        simd_ne(c, transmute(d))
74272    }
74273}
74274#[doc = "Unsigned compare bitwise Test bits nonzero"]
74275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
74276#[inline]
74277#[target_feature(enable = "neon")]
74278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74280#[cfg_attr(
74281    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74282    assert_instr(cmtst)
74283)]
74284#[cfg_attr(
74285    not(target_arch = "arm"),
74286    stable(feature = "neon_intrinsics", since = "1.59.0")
74287)]
74288#[cfg_attr(
74289    target_arch = "arm",
74290    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74291)]
74292pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
74293    unsafe {
74294        let c: uint16x8_t = simd_and(a, b);
74295        let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74296        simd_ne(c, transmute(d))
74297    }
74298}
74299#[doc = "Unsigned compare bitwise Test bits nonzero"]
74300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
74301#[inline]
74302#[target_feature(enable = "neon")]
74303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74305#[cfg_attr(
74306    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74307    assert_instr(cmtst)
74308)]
74309#[cfg_attr(
74310    not(target_arch = "arm"),
74311    stable(feature = "neon_intrinsics", since = "1.59.0")
74312)]
74313#[cfg_attr(
74314    target_arch = "arm",
74315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74316)]
74317pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
74318    unsafe {
74319        let c: uint32x2_t = simd_and(a, b);
74320        let d: u32x2 = u32x2::new(0, 0);
74321        simd_ne(c, transmute(d))
74322    }
74323}
74324#[doc = "Unsigned compare bitwise Test bits nonzero"]
74325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
74326#[inline]
74327#[target_feature(enable = "neon")]
74328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74330#[cfg_attr(
74331    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74332    assert_instr(cmtst)
74333)]
74334#[cfg_attr(
74335    not(target_arch = "arm"),
74336    stable(feature = "neon_intrinsics", since = "1.59.0")
74337)]
74338#[cfg_attr(
74339    target_arch = "arm",
74340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74341)]
74342pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
74343    unsafe {
74344        let c: uint32x4_t = simd_and(a, b);
74345        let d: u32x4 = u32x4::new(0, 0, 0, 0);
74346        simd_ne(c, transmute(d))
74347    }
74348}
74349#[doc = "Dot product index form with unsigned and signed integers"]
74350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
74351#[inline]
74352#[target_feature(enable = "neon,i8mm")]
74353#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74355#[cfg_attr(
74356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74357    assert_instr(usdot, LANE = 0)
74358)]
74359#[rustc_legacy_const_generics(3)]
74360#[cfg_attr(
74361    not(target_arch = "arm"),
74362    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74363)]
74364#[cfg_attr(
74365    target_arch = "arm",
74366    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74367)]
74368pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74369    static_assert_uimm_bits!(LANE, 1);
74370    unsafe {
74371        let c: int32x2_t = transmute(c);
74372        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
74373        vusdot_s32(a, b, transmute(c))
74374    }
74375}
74376#[doc = "Dot product index form with unsigned and signed integers"]
74377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
74378#[inline]
74379#[target_feature(enable = "neon,i8mm")]
74380#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74382#[cfg_attr(
74383    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74384    assert_instr(usdot, LANE = 0)
74385)]
74386#[rustc_legacy_const_generics(3)]
74387#[cfg_attr(
74388    not(target_arch = "arm"),
74389    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74390)]
74391#[cfg_attr(
74392    target_arch = "arm",
74393    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74394)]
74395pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
74396    static_assert_uimm_bits!(LANE, 1);
74397    unsafe {
74398        let c: int32x2_t = transmute(c);
74399        let c: int32x4_t =
74400            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
74401        vusdotq_s32(a, b, transmute(c))
74402    }
74403}
74404#[doc = "Dot product vector form with unsigned and signed integers"]
74405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
74406#[inline]
74407#[target_feature(enable = "neon,i8mm")]
74408#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74410#[cfg_attr(
74411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74412    assert_instr(usdot)
74413)]
74414#[cfg_attr(
74415    not(target_arch = "arm"),
74416    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74417)]
74418#[cfg_attr(
74419    target_arch = "arm",
74420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74421)]
74422pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74423    unsafe extern "unadjusted" {
74424        #[cfg_attr(
74425            any(target_arch = "aarch64", target_arch = "arm64ec"),
74426            link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8"
74427        )]
74428        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")]
74429        fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t;
74430    }
74431    unsafe { _vusdot_s32(a, b, c) }
74432}
74433#[doc = "Dot product vector form with unsigned and signed integers"]
74434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
74435#[inline]
74436#[target_feature(enable = "neon,i8mm")]
74437#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74439#[cfg_attr(
74440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74441    assert_instr(usdot)
74442)]
74443#[cfg_attr(
74444    not(target_arch = "arm"),
74445    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74446)]
74447#[cfg_attr(
74448    target_arch = "arm",
74449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74450)]
74451pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74452    unsafe extern "unadjusted" {
74453        #[cfg_attr(
74454            any(target_arch = "aarch64", target_arch = "arm64ec"),
74455            link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8"
74456        )]
74457        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")]
74458        fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74459    }
74460    unsafe { _vusdotq_s32(a, b, c) }
74461}
74462#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
74463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
74464#[inline]
74465#[target_feature(enable = "neon,i8mm")]
74466#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
74468#[cfg_attr(
74469    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74470    assert_instr(usmmla)
74471)]
74472#[cfg_attr(
74473    not(target_arch = "arm"),
74474    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74475)]
74476#[cfg_attr(
74477    target_arch = "arm",
74478    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74479)]
74480pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74481    unsafe extern "unadjusted" {
74482        #[cfg_attr(
74483            any(target_arch = "aarch64", target_arch = "arm64ec"),
74484            link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8"
74485        )]
74486        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")]
74487        fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74488    }
74489    unsafe { _vusmmlaq_s32(a, b, c) }
74490}
74491#[doc = "Unzip vectors"]
74492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
74493#[inline]
74494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74496#[cfg_attr(
74497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74498    assert_instr(uzp)
74499)]
74500#[target_feature(enable = "neon,fp16")]
74501#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74502pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74503    unsafe {
74504        let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74505        let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74506        transmute((a0, b0))
74507    }
74508}
74509#[doc = "Unzip vectors"]
74510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
74511#[inline]
74512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74514#[cfg_attr(
74515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74516    assert_instr(uzp)
74517)]
74518#[target_feature(enable = "neon,fp16")]
74519#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74520pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74521    unsafe {
74522        let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74523        let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74524        transmute((a0, b0))
74525    }
74526}
74527#[doc = "Unzip vectors"]
74528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
74529#[inline]
74530#[target_feature(enable = "neon")]
74531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74533#[cfg_attr(
74534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74535    assert_instr(zip)
74536)]
74537#[cfg_attr(
74538    not(target_arch = "arm"),
74539    stable(feature = "neon_intrinsics", since = "1.59.0")
74540)]
74541#[cfg_attr(
74542    target_arch = "arm",
74543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74544)]
74545pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74546    unsafe {
74547        let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74548        let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74549        transmute((a0, b0))
74550    }
74551}
74552#[doc = "Unzip vectors"]
74553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
74554#[inline]
74555#[target_feature(enable = "neon")]
74556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74558#[cfg_attr(
74559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74560    assert_instr(zip)
74561)]
74562#[cfg_attr(
74563    not(target_arch = "arm"),
74564    stable(feature = "neon_intrinsics", since = "1.59.0")
74565)]
74566#[cfg_attr(
74567    target_arch = "arm",
74568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74569)]
74570pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
74571    unsafe {
74572        let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
74573        let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
74574        transmute((a0, b0))
74575    }
74576}
74577#[doc = "Unzip vectors"]
74578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
74579#[inline]
74580#[target_feature(enable = "neon")]
74581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74583#[cfg_attr(
74584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74585    assert_instr(zip)
74586)]
74587#[cfg_attr(
74588    not(target_arch = "arm"),
74589    stable(feature = "neon_intrinsics", since = "1.59.0")
74590)]
74591#[cfg_attr(
74592    target_arch = "arm",
74593    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74594)]
74595pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
74596    unsafe {
74597        let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
74598        let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
74599        transmute((a0, b0))
74600    }
74601}
74602#[doc = "Unzip vectors"]
74603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
74604#[inline]
74605#[target_feature(enable = "neon")]
74606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74608#[cfg_attr(
74609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74610    assert_instr(uzp)
74611)]
74612#[cfg_attr(
74613    not(target_arch = "arm"),
74614    stable(feature = "neon_intrinsics", since = "1.59.0")
74615)]
74616#[cfg_attr(
74617    target_arch = "arm",
74618    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74619)]
74620pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
74621    unsafe {
74622        let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74623        let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74624        transmute((a0, b0))
74625    }
74626}
74627#[doc = "Unzip vectors"]
74628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
74629#[inline]
74630#[target_feature(enable = "neon")]
74631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74633#[cfg_attr(
74634    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74635    assert_instr(uzp)
74636)]
74637#[cfg_attr(
74638    not(target_arch = "arm"),
74639    stable(feature = "neon_intrinsics", since = "1.59.0")
74640)]
74641#[cfg_attr(
74642    target_arch = "arm",
74643    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74644)]
74645pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
74646    unsafe {
74647        let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74648        let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74649        transmute((a0, b0))
74650    }
74651}
74652#[doc = "Unzip vectors"]
74653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
74654#[inline]
74655#[target_feature(enable = "neon")]
74656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74658#[cfg_attr(
74659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74660    assert_instr(uzp)
74661)]
74662#[cfg_attr(
74663    not(target_arch = "arm"),
74664    stable(feature = "neon_intrinsics", since = "1.59.0")
74665)]
74666#[cfg_attr(
74667    target_arch = "arm",
74668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74669)]
74670pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
74671    unsafe {
74672        let a0: int8x16_t = simd_shuffle!(
74673            a,
74674            b,
74675            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74676        );
74677        let b0: int8x16_t = simd_shuffle!(
74678            a,
74679            b,
74680            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74681        );
74682        transmute((a0, b0))
74683    }
74684}
74685#[doc = "Unzip vectors"]
74686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
74687#[inline]
74688#[target_feature(enable = "neon")]
74689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74691#[cfg_attr(
74692    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74693    assert_instr(uzp)
74694)]
74695#[cfg_attr(
74696    not(target_arch = "arm"),
74697    stable(feature = "neon_intrinsics", since = "1.59.0")
74698)]
74699#[cfg_attr(
74700    target_arch = "arm",
74701    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74702)]
74703pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
74704    unsafe {
74705        let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74706        let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74707        transmute((a0, b0))
74708    }
74709}
74710#[doc = "Unzip vectors"]
74711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
74712#[inline]
74713#[target_feature(enable = "neon")]
74714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74716#[cfg_attr(
74717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74718    assert_instr(uzp)
74719)]
74720#[cfg_attr(
74721    not(target_arch = "arm"),
74722    stable(feature = "neon_intrinsics", since = "1.59.0")
74723)]
74724#[cfg_attr(
74725    target_arch = "arm",
74726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74727)]
74728pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
74729    unsafe {
74730        let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74731        let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74732        transmute((a0, b0))
74733    }
74734}
74735#[doc = "Unzip vectors"]
74736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
74737#[inline]
74738#[target_feature(enable = "neon")]
74739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74741#[cfg_attr(
74742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74743    assert_instr(uzp)
74744)]
74745#[cfg_attr(
74746    not(target_arch = "arm"),
74747    stable(feature = "neon_intrinsics", since = "1.59.0")
74748)]
74749#[cfg_attr(
74750    target_arch = "arm",
74751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74752)]
74753pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
74754    unsafe {
74755        let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74756        let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74757        transmute((a0, b0))
74758    }
74759}
74760#[doc = "Unzip vectors"]
74761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
74762#[inline]
74763#[target_feature(enable = "neon")]
74764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74766#[cfg_attr(
74767    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74768    assert_instr(uzp)
74769)]
74770#[cfg_attr(
74771    not(target_arch = "arm"),
74772    stable(feature = "neon_intrinsics", since = "1.59.0")
74773)]
74774#[cfg_attr(
74775    target_arch = "arm",
74776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74777)]
74778pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
74779    unsafe {
74780        let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74781        let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74782        transmute((a0, b0))
74783    }
74784}
74785#[doc = "Unzip vectors"]
74786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
74787#[inline]
74788#[target_feature(enable = "neon")]
74789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74791#[cfg_attr(
74792    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74793    assert_instr(uzp)
74794)]
74795#[cfg_attr(
74796    not(target_arch = "arm"),
74797    stable(feature = "neon_intrinsics", since = "1.59.0")
74798)]
74799#[cfg_attr(
74800    target_arch = "arm",
74801    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74802)]
74803pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
74804    unsafe {
74805        let a0: uint8x16_t = simd_shuffle!(
74806            a,
74807            b,
74808            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74809        );
74810        let b0: uint8x16_t = simd_shuffle!(
74811            a,
74812            b,
74813            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74814        );
74815        transmute((a0, b0))
74816    }
74817}
74818#[doc = "Unzip vectors"]
74819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
74820#[inline]
74821#[target_feature(enable = "neon")]
74822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74824#[cfg_attr(
74825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74826    assert_instr(uzp)
74827)]
74828#[cfg_attr(
74829    not(target_arch = "arm"),
74830    stable(feature = "neon_intrinsics", since = "1.59.0")
74831)]
74832#[cfg_attr(
74833    target_arch = "arm",
74834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74835)]
74836pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
74837    unsafe {
74838        let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74839        let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74840        transmute((a0, b0))
74841    }
74842}
74843#[doc = "Unzip vectors"]
74844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
74845#[inline]
74846#[target_feature(enable = "neon")]
74847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74849#[cfg_attr(
74850    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74851    assert_instr(uzp)
74852)]
74853#[cfg_attr(
74854    not(target_arch = "arm"),
74855    stable(feature = "neon_intrinsics", since = "1.59.0")
74856)]
74857#[cfg_attr(
74858    target_arch = "arm",
74859    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74860)]
74861pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
74862    unsafe {
74863        let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74864        let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74865        transmute((a0, b0))
74866    }
74867}
74868#[doc = "Unzip vectors"]
74869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
74870#[inline]
74871#[target_feature(enable = "neon")]
74872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74874#[cfg_attr(
74875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74876    assert_instr(uzp)
74877)]
74878#[cfg_attr(
74879    not(target_arch = "arm"),
74880    stable(feature = "neon_intrinsics", since = "1.59.0")
74881)]
74882#[cfg_attr(
74883    target_arch = "arm",
74884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74885)]
74886pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
74887    unsafe {
74888        let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74889        let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74890        transmute((a0, b0))
74891    }
74892}
74893#[doc = "Unzip vectors"]
74894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
74895#[inline]
74896#[target_feature(enable = "neon")]
74897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74899#[cfg_attr(
74900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74901    assert_instr(uzp)
74902)]
74903#[cfg_attr(
74904    not(target_arch = "arm"),
74905    stable(feature = "neon_intrinsics", since = "1.59.0")
74906)]
74907#[cfg_attr(
74908    target_arch = "arm",
74909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74910)]
74911pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
74912    unsafe {
74913        let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74914        let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74915        transmute((a0, b0))
74916    }
74917}
74918#[doc = "Unzip vectors"]
74919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
74920#[inline]
74921#[target_feature(enable = "neon")]
74922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74924#[cfg_attr(
74925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74926    assert_instr(uzp)
74927)]
74928#[cfg_attr(
74929    not(target_arch = "arm"),
74930    stable(feature = "neon_intrinsics", since = "1.59.0")
74931)]
74932#[cfg_attr(
74933    target_arch = "arm",
74934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74935)]
74936pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
74937    unsafe {
74938        let a0: poly8x16_t = simd_shuffle!(
74939            a,
74940            b,
74941            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74942        );
74943        let b0: poly8x16_t = simd_shuffle!(
74944            a,
74945            b,
74946            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74947        );
74948        transmute((a0, b0))
74949    }
74950}
74951#[doc = "Unzip vectors"]
74952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
74953#[inline]
74954#[target_feature(enable = "neon")]
74955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74957#[cfg_attr(
74958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74959    assert_instr(uzp)
74960)]
74961#[cfg_attr(
74962    not(target_arch = "arm"),
74963    stable(feature = "neon_intrinsics", since = "1.59.0")
74964)]
74965#[cfg_attr(
74966    target_arch = "arm",
74967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74968)]
74969pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
74970    unsafe {
74971        let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74972        let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74973        transmute((a0, b0))
74974    }
74975}
74976#[doc = "Unzip vectors"]
74977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
74978#[inline]
74979#[target_feature(enable = "neon")]
74980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74982#[cfg_attr(
74983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74984    assert_instr(uzp)
74985)]
74986#[cfg_attr(
74987    not(target_arch = "arm"),
74988    stable(feature = "neon_intrinsics", since = "1.59.0")
74989)]
74990#[cfg_attr(
74991    target_arch = "arm",
74992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74993)]
74994pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
74995    unsafe {
74996        let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74997        let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74998        transmute((a0, b0))
74999    }
75000}
75001#[doc = "Zip vectors"]
75002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
75003#[inline]
75004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75005#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
75006#[cfg_attr(
75007    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75008    assert_instr(zip)
75009)]
75010#[target_feature(enable = "neon,fp16")]
75011#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
75012pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
75013    unsafe {
75014        let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75015        let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75016        transmute((a0, b0))
75017    }
75018}
75019#[doc = "Zip vectors"]
75020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
75021#[inline]
75022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
75024#[cfg_attr(
75025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75026    assert_instr(zip)
75027)]
75028#[target_feature(enable = "neon,fp16")]
75029#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
75030pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
75031    unsafe {
75032        let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75033        let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75034        transmute((a0, b0))
75035    }
75036}
75037#[doc = "Zip vectors"]
75038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
75039#[inline]
75040#[target_feature(enable = "neon")]
75041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75043#[cfg_attr(
75044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75045    assert_instr(zip)
75046)]
75047#[cfg_attr(
75048    not(target_arch = "arm"),
75049    stable(feature = "neon_intrinsics", since = "1.59.0")
75050)]
75051#[cfg_attr(
75052    target_arch = "arm",
75053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75054)]
75055pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
75056    unsafe {
75057        let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
75058        let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
75059        transmute((a0, b0))
75060    }
75061}
75062#[doc = "Zip vectors"]
75063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
75064#[inline]
75065#[target_feature(enable = "neon")]
75066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75068#[cfg_attr(
75069    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75070    assert_instr(zip)
75071)]
75072#[cfg_attr(
75073    not(target_arch = "arm"),
75074    stable(feature = "neon_intrinsics", since = "1.59.0")
75075)]
75076#[cfg_attr(
75077    target_arch = "arm",
75078    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75079)]
75080pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
75081    unsafe {
75082        let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
75083        let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
75084        transmute((a0, b0))
75085    }
75086}
75087#[doc = "Zip vectors"]
75088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
75089#[inline]
75090#[target_feature(enable = "neon")]
75091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75093#[cfg_attr(
75094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75095    assert_instr(zip)
75096)]
75097#[cfg_attr(
75098    not(target_arch = "arm"),
75099    stable(feature = "neon_intrinsics", since = "1.59.0")
75100)]
75101#[cfg_attr(
75102    target_arch = "arm",
75103    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75104)]
75105pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
75106    unsafe {
75107        let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
75108        let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
75109        transmute((a0, b0))
75110    }
75111}
75112#[doc = "Zip vectors"]
75113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
75114#[inline]
75115#[target_feature(enable = "neon")]
75116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75118#[cfg_attr(
75119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75120    assert_instr(zip)
75121)]
75122#[cfg_attr(
75123    not(target_arch = "arm"),
75124    stable(feature = "neon_intrinsics", since = "1.59.0")
75125)]
75126#[cfg_attr(
75127    target_arch = "arm",
75128    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75129)]
75130pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
75131    unsafe {
75132        let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75133        let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75134        transmute((a0, b0))
75135    }
75136}
75137#[doc = "Zip vectors"]
75138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
75139#[inline]
75140#[target_feature(enable = "neon")]
75141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75143#[cfg_attr(
75144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75145    assert_instr(zip)
75146)]
75147#[cfg_attr(
75148    not(target_arch = "arm"),
75149    stable(feature = "neon_intrinsics", since = "1.59.0")
75150)]
75151#[cfg_attr(
75152    target_arch = "arm",
75153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75154)]
75155pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
75156    unsafe {
75157        let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75158        let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75159        transmute((a0, b0))
75160    }
75161}
75162#[doc = "Zip vectors"]
75163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
75164#[inline]
75165#[target_feature(enable = "neon")]
75166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75168#[cfg_attr(
75169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75170    assert_instr(zip)
75171)]
75172#[cfg_attr(
75173    not(target_arch = "arm"),
75174    stable(feature = "neon_intrinsics", since = "1.59.0")
75175)]
75176#[cfg_attr(
75177    target_arch = "arm",
75178    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75179)]
75180pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
75181    unsafe {
75182        let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75183        let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75184        transmute((a0, b0))
75185    }
75186}
75187#[doc = "Zip vectors"]
75188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
75189#[inline]
75190#[target_feature(enable = "neon")]
75191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75193#[cfg_attr(
75194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75195    assert_instr(zip)
75196)]
75197#[cfg_attr(
75198    not(target_arch = "arm"),
75199    stable(feature = "neon_intrinsics", since = "1.59.0")
75200)]
75201#[cfg_attr(
75202    target_arch = "arm",
75203    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75204)]
75205pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
75206    unsafe {
75207        let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75208        let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75209        transmute((a0, b0))
75210    }
75211}
75212#[doc = "Zip vectors"]
75213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
75214#[inline]
75215#[target_feature(enable = "neon")]
75216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75218#[cfg_attr(
75219    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75220    assert_instr(zip)
75221)]
75222#[cfg_attr(
75223    not(target_arch = "arm"),
75224    stable(feature = "neon_intrinsics", since = "1.59.0")
75225)]
75226#[cfg_attr(
75227    target_arch = "arm",
75228    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75229)]
75230pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
75231    unsafe {
75232        let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75233        let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75234        transmute((a0, b0))
75235    }
75236}
75237#[doc = "Zip vectors"]
75238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
75239#[inline]
75240#[target_feature(enable = "neon")]
75241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75243#[cfg_attr(
75244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75245    assert_instr(zip)
75246)]
75247#[cfg_attr(
75248    not(target_arch = "arm"),
75249    stable(feature = "neon_intrinsics", since = "1.59.0")
75250)]
75251#[cfg_attr(
75252    target_arch = "arm",
75253    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75254)]
75255pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
75256    unsafe {
75257        let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75258        let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75259        transmute((a0, b0))
75260    }
75261}
75262#[doc = "Zip vectors"]
75263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
75264#[inline]
75265#[target_feature(enable = "neon")]
75266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75268#[cfg_attr(
75269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75270    assert_instr(zip)
75271)]
75272#[cfg_attr(
75273    not(target_arch = "arm"),
75274    stable(feature = "neon_intrinsics", since = "1.59.0")
75275)]
75276#[cfg_attr(
75277    target_arch = "arm",
75278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75279)]
75280pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
75281    unsafe {
75282        let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75283        let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75284        transmute((a0, b0))
75285    }
75286}
75287#[doc = "Zip vectors"]
75288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
75289#[inline]
75290#[target_feature(enable = "neon")]
75291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75293#[cfg_attr(
75294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75295    assert_instr(zip)
75296)]
75297#[cfg_attr(
75298    not(target_arch = "arm"),
75299    stable(feature = "neon_intrinsics", since = "1.59.0")
75300)]
75301#[cfg_attr(
75302    target_arch = "arm",
75303    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75304)]
75305pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
75306    unsafe {
75307        let a0: int8x16_t = simd_shuffle!(
75308            a,
75309            b,
75310            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75311        );
75312        let b0: int8x16_t = simd_shuffle!(
75313            a,
75314            b,
75315            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75316        );
75317        transmute((a0, b0))
75318    }
75319}
75320#[doc = "Zip vectors"]
75321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
75322#[inline]
75323#[target_feature(enable = "neon")]
75324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75326#[cfg_attr(
75327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75328    assert_instr(zip)
75329)]
75330#[cfg_attr(
75331    not(target_arch = "arm"),
75332    stable(feature = "neon_intrinsics", since = "1.59.0")
75333)]
75334#[cfg_attr(
75335    target_arch = "arm",
75336    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75337)]
75338pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
75339    unsafe {
75340        let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75341        let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75342        transmute((a0, b0))
75343    }
75344}
75345#[doc = "Zip vectors"]
75346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
75347#[inline]
75348#[target_feature(enable = "neon")]
75349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75351#[cfg_attr(
75352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75353    assert_instr(zip)
75354)]
75355#[cfg_attr(
75356    not(target_arch = "arm"),
75357    stable(feature = "neon_intrinsics", since = "1.59.0")
75358)]
75359#[cfg_attr(
75360    target_arch = "arm",
75361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75362)]
75363pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
75364    unsafe {
75365        let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75366        let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75367        transmute((a0, b0))
75368    }
75369}
75370#[doc = "Zip vectors"]
75371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
75372#[inline]
75373#[target_feature(enable = "neon")]
75374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75376#[cfg_attr(
75377    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75378    assert_instr(zip)
75379)]
75380#[cfg_attr(
75381    not(target_arch = "arm"),
75382    stable(feature = "neon_intrinsics", since = "1.59.0")
75383)]
75384#[cfg_attr(
75385    target_arch = "arm",
75386    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75387)]
75388pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
75389    unsafe {
75390        let a0: uint8x16_t = simd_shuffle!(
75391            a,
75392            b,
75393            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75394        );
75395        let b0: uint8x16_t = simd_shuffle!(
75396            a,
75397            b,
75398            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75399        );
75400        transmute((a0, b0))
75401    }
75402}
75403#[doc = "Zip vectors"]
75404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
75405#[inline]
75406#[target_feature(enable = "neon")]
75407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75409#[cfg_attr(
75410    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75411    assert_instr(zip)
75412)]
75413#[cfg_attr(
75414    not(target_arch = "arm"),
75415    stable(feature = "neon_intrinsics", since = "1.59.0")
75416)]
75417#[cfg_attr(
75418    target_arch = "arm",
75419    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75420)]
75421pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
75422    unsafe {
75423        let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75424        let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75425        transmute((a0, b0))
75426    }
75427}
75428#[doc = "Zip vectors"]
75429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
75430#[inline]
75431#[target_feature(enable = "neon")]
75432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75434#[cfg_attr(
75435    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75436    assert_instr(zip)
75437)]
75438#[cfg_attr(
75439    not(target_arch = "arm"),
75440    stable(feature = "neon_intrinsics", since = "1.59.0")
75441)]
75442#[cfg_attr(
75443    target_arch = "arm",
75444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75445)]
75446pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
75447    unsafe {
75448        let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75449        let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75450        transmute((a0, b0))
75451    }
75452}
75453#[doc = "Zip vectors"]
75454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
75455#[inline]
75456#[target_feature(enable = "neon")]
75457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75459#[cfg_attr(
75460    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75461    assert_instr(zip)
75462)]
75463#[cfg_attr(
75464    not(target_arch = "arm"),
75465    stable(feature = "neon_intrinsics", since = "1.59.0")
75466)]
75467#[cfg_attr(
75468    target_arch = "arm",
75469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75470)]
75471pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
75472    unsafe {
75473        let a0: poly8x16_t = simd_shuffle!(
75474            a,
75475            b,
75476            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75477        );
75478        let b0: poly8x16_t = simd_shuffle!(
75479            a,
75480            b,
75481            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75482        );
75483        transmute((a0, b0))
75484    }
75485}
75486#[doc = "Zip vectors"]
75487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
75488#[inline]
75489#[target_feature(enable = "neon")]
75490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75492#[cfg_attr(
75493    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75494    assert_instr(zip)
75495)]
75496#[cfg_attr(
75497    not(target_arch = "arm"),
75498    stable(feature = "neon_intrinsics", since = "1.59.0")
75499)]
75500#[cfg_attr(
75501    target_arch = "arm",
75502    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75503)]
75504pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
75505    unsafe {
75506        let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75507        let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75508        transmute((a0, b0))
75509    }
75510}